Silicon carbide field effect transistor with deep trapezoidal P-type junction and preparation method of silicon carbide field effect transistor
By etching on the Drift layer of the SiC MOSFET device to form a trapezoidal structure and forming a deeper P-type junction, the problem of failure risk of device gate oxide layer and insufficient short-circuit tolerance is solved, and better protection and tolerance are achieved.
Patent Information
- Application Number
- CN202411899258.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-23
- Publication Date
- 2025-03-11
AI Technical Summary
The gate oxide layer of SiC MOSFET devices has a large interface density and many defects, which poses a risk of failure. At the same time, its short-circuit tolerance is poor, making it prone to breakdown failure.
The trapezoidal structure is formed by etching at the top corner of the Drift layer and forming a deeper P-type junction on the trench surface by ion implantation, which enhances the protection of the gate oxide layer and improves the device's short-circuit tolerance in the saturation region.
It realizes better protection of the gate oxide layer of SiC MOSFET device, reduces the risk of failure, and improves the device's short-circuit tolerance in the saturated region.
Smart Images
Figure CN119603988A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a silicon carbide field effect transistor with a deep trapezoidal P-type junction and a preparation method thereof. Background Art
[0002] In the field of power electronics technology, voltage-controlled power switching devices are used in various system scenarios and are the most important power components. Voltage-controlled switching devices have always been based on Si-based devices, such as Si MOSFET, SiIGBT, and Si FET. This is due to the high reserves and easy access of Si raw materials, as well as the stable and mature process manufacturing and performance of Si devices. However, with the continuous development of society, Si-based devices are increasingly unable to meet the needs of the rapidly developing power electronics field. Therefore, researchers have begun to develop a new generation of raw materials to prepare higher-performance devices. Among them, the third-generation wide-bandgap semiconductor power devices represented by SiCMOSFET are considered to be key products in the future in the fields of high voltage, high temperature, and high frequency due to their excellent performance.
[0003] SiC MOSFET has good performance in both static and dynamic aspects due to its unipolar structure advantages and SiC's high physical performance advantages, and can achieve higher efficiency gains in the system. Although it seems that SiC MOSFET has more advantages than Si-based devices, the interface state density and defects of the SiC MOSFET gate oxide layer are large, so there is a risk of failure during use. At the same time, the poor short-circuit tolerance of SiC MOSFET also easily causes short-circuit failure of the tube. It can be seen that SiC MOSFET has significant long-term use problems, and the device still needs to be deeply optimized and improved. Summary of the invention
[0004] In view of the above problems, the present invention provides a method for improving the gate oxide layer protection of SiC MOSFET devices, reducing the failure risk of the gate oxide layer of the device, and improving the short-circuit tolerance of the device when the device operates in the saturation region.
[0005] The technical solution of the present invention is: A method for preparing a silicon carbide field effect transistor with a deep trapezoidal P-type junction comprises the following steps: S100, forming a Drift layer on the top surface of the Sub layer by epitaxial deposition, and etching the top corner of the Drift layer so that the top cross-section of the Drift layer has a trapezoidal structure; S200, forming a P-body region, a NP region and a PP region on the top surface of the Drift layer by ion implantation in sequence, and then activating all implanted regions by high temperature annealing; S300, forming a gate oxide layer and a Poly layer on top surfaces of the Drift layer, the P-body region, and the NP region in sequence; S400, forming an isolation dielectric layer on the top surface of the NP region and the Poly layer by oxide deposition; S500, forming an ohmic contact alloy layer on the top surface of the NP region and the PP region by Ni metal sputtering or deposition followed by thermal annealing; S600 , forming a front electrode metal layer on the top surfaces of the isolation dielectric layer and the ohmic contact alloy layer by sputtering Ti and AlCu metals.
[0006] Specifically, in step S100, the conductivity type of the Sub layer is N-type, the thickness is 100um-450um, and the doping concentration is 1E19-3E19cm -2 The conductivity type of the Drift layer is N-type, the thickness is 5um-15um, and the doping concentration is 5E15-5E16cm -2 .
[0007] Specifically, in step S100 , the etching depth vertically downward from the top surface of the Drift layer is 2 um-6 um.
[0008] Specifically, in step S200, the depth of the P-body region (the distance translated inward from the corresponding outer surface) is 0.6um-2um, and the doping concentration is 1E17-3E18cm -2 .
[0009] Specifically, in step S200, the depth of the NP region is 0.3um-1.2um, and the doping concentration is 1E18-3E19cm -2 .
[0010] Specifically, in step S200, the depth of the PP region (the distance translated inward from the corresponding outer surface) is 0.3um-1.5um, and the doping concentration is 1E18-3E19cm -2 .
[0011] Specifically, in step S300 , the thickness of the gate oxide layer is 40 nm-60 um.
[0012] Specifically, the Ni metal thickness in step S500 is 0.3um-1um.
[0013] Specifically, in step S600 , the thickness of the Ti metal is 0.1 um-0.6 um, and the thickness of the AlCu metal is 2 um-5 um.
[0014] A deep trapezoidal P-type junction silicon carbide field effect transistor, comprising: Sub layer; The Drift layer has a pair of right-angle trapezoidal etched portions at the top corners, which makes the top two sides of the Drift layer be inclined; A pair of P-body regions are provided, extending inwardly from the top outer side of the Drift layer; a spacing is provided between the tops of the pair of P-body regions; An NP region extending downward from a top surface of the P-body region; A PP region extends inward from a side surface of the P-body region and is spaced apart from an inner side surface of the P-body region; the PP region is connected to the NP region; A gate oxide layer is disposed on the top surfaces of the Drift layer, the P-body region and the NP region; A Poly layer, disposed on the top surface of the gate oxide layer; An isolation dielectric layer, disposed on the top surface of the Poly layer, with a side portion extending downward to connect with the NP region; An ohmic contact alloy layer, disposed on the outer side of the PP region, and connected to the isolation dielectric layer on the top; Front electrode metal layer, set on the top of the device.
[0015] The present invention is directed to a planar SiC MOSFET device. By etching at the top corner of the Drift layer so that its top cross-section is in a trapezoidal structure, a P-type junction is then formed on the surface of the inverted trapezoidal groove by ion implantation, thereby achieving a deeper P-type junction structure. The deeper P-type junction can better protect the gate oxide layer of the SiC MOSFET device, thereby reducing the failure risk of the gate oxide layer of the device. At the same time, when the device operates in a saturation region, the depletion layer generated by the deeper P-type junction and the Drift layer can also hinder the current, thereby improving the short-circuit tolerance of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 is a structural schematic diagram of step S100 of the present invention; Figure 2 is a schematic structural diagram of step S200 of the present invention; Figure 3 is a schematic structural diagram of step S300 of the present invention; Figure 4 is a structural schematic diagram of step S400 of the present invention; Figure 5 is a schematic structural diagram of step S500 of the present invention; Figure 6 is a schematic structural diagram of step S600 of the present invention; Figure 7 is a schematic structural diagram of step S700 of the present invention; Figure 8 is a structural schematic diagram of step S800 of the present invention; Fig. 9 is a structural schematic diagram of step S900 of the present invention; Fig.10 is a structural schematic diagram of step S1000 of the present invention; In the figure, 1 is the Sub layer, 2 is the Drift layer, 3 is the P-body region, 4 is the NP region, 5 is the PP region, 6 is the gate oxide layer, 7 is the Poly layer, 8 is the isolation dielectric layer, 9 is the Ohmic contact alloy layer, and 10 is the front electrode metal layer. DETAILED DESCRIPTION
[0017] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.
[0018] A deep trapezoidal P-type junction silicon carbide field effect transistor comprises the following steps: S100, forming a Drift layer 2 on the top surface of the Sub layer 1 by epitaxial deposition; The conductivity type of Sub layer 1 in step S100 is N type, the thickness is 100um-450um, and the doping concentration is 1E19-3E19cm -2 , Drift layer 2 conductivity type is N type, thickness is 5um-15um, doping concentration is 5E15-5E16cm -2 .
[0019] S200, etching downward on the top surface of the Drift layer 2 to form a trapezoidal structure on the top of the Drift layer 2; In step S200 , the etching depth vertically downward from the top surface of the Drift layer 2 is 2 um-6 um.
[0020] S300, forming a P-body region 3 on the top of the Drift layer 2 by Al ion implantation; In step S300, the implantation depth of P-body region 3 is 0.6um-2um, and the doping concentration is 1E17-3E18cm -2 .
[0021] S400, forming an NP region 4 on the top surface of the P-body region 3 by N ion implantation; The implantation depth of NP region 4 in step S400 is 0.3um-1.2um, and the doping concentration is 1E18-3E19cm -2 .
[0022] S500, forming a PP region 5 on the P-body region 3 by Al ion implantation, and then activating all implanted regions by high temperature annealing; The PP region in step S500 is implanted with a depth of 0.3um-1.5um and a doping concentration of 1E18-3E19cm -2 .
[0023] S600, forming a gate oxide layer 6 on the top surfaces of the Drift layer 2, the P-body region 3 and the NP region 4 by dry oxygen oxidation growth; The thickness of the gate oxide layer 6 in step S600 is 40nm-60um.
[0024] S700, forming a Poly layer 7 on the top surface of the gate oxide layer 6 by polysilicon deposition; S800, forming an isolation dielectric layer 8 on the top surfaces of the NP region 4 and the Poly layer 7 by oxide deposition; S900, forming an ohmic contact alloy layer 9 on the top surfaces of the NP region 4 and the PP region 5 by sputtering or depositing Ni metal followed by thermal annealing; The Ni metal thickness in step S900 is 0.3um-1um.
[0025] S1000, forming a front electrode metal layer 10 on the top surface of the isolation dielectric layer 8 and the ohmic contact alloy layer 9 by sputtering Ti and AlCu metals; The thickness of the Ti metal in step S1000 is 0.1um-0.6um, and the thickness of the AlCu metal is 2um-5um.
[0026] A deep trapezoidal P-type junction silicon carbide field effect transistor, comprising: Sub layer 1; The Drift layer 2 has a pair of right-angle trapezoidal etched portions at the top corners, which makes the top two sides of the Drift layer 2 form an inclined surface; A pair of P-body regions 3 are provided, extending inward from the top outer side of the Drift layer 2; a spacing is provided between the tops of the pair of P-body regions 3; NP region 4, extending downward from the top surface of the P-body region 3; The PP region 5 extends inward from the side surface of the P-body region 3 and is spaced apart from the inner side surface of the P-body region 3; the PP region 5 is connected to the NP region 4; A gate oxide layer 6 is disposed on the top surfaces of the Drift layer 2, the P-body region 3 and the NP region 4; A Poly layer 7, disposed on the top surface of the gate oxide layer 6; An isolation dielectric layer 8 is disposed on the top surface of the Poly layer 7, and its side portion extends downward to connect with the NP region 4; An ohmic contact alloy layer 9 is disposed on the outer side of the PP region 5 and connected to the isolation dielectric layer 8 on the top; The front electrode metal layer 10 is arranged on the top of the device.
[0027] The bottom of the front electrode metal layer 10 is connected to the ohmic contact alloy layer 9 and the isolation dielectric layer 8 respectively.
[0028] Since SiC contains C elements, the interface state density in the gate oxide layer is large and there are many defects, which can easily cause breakdown failure during use, thus affecting safe use. At the same time, the short-circuit tolerance of SiC MOSFET is also poor, only about 3us. If the system is improperly designed during use, it is also very easy to cause breakdown failure due to short-circuit problems. The present invention is directed to a planar SiC MOSFET device, and a groove with a right-angle trapezoidal structure is etched on the Drift layer, and then a P-type junction is formed on the surface of the groove by ion implantation, thereby achieving a deeper P-type junction structure. The advantage of this design is that the deeper P-type junction can better protect the gate oxide layer of the SiC MOSFET device, which can reduce the failure risk of the device gate oxide layer to a certain extent, and at the same time, when the device is working in the saturation region, the deeper P-type junction and the depletion layer generated by the Drift layer will also hinder the current, thereby improving the short-circuit tolerance of the device.
Claims
1. A method for preparing a deep trapezoidal P-type junction silicon carbide field effect transistor, characterized in that: The steps include: S100, forming a Drift layer (2) on the top surface of the Sub layer (1) by epitaxial deposition, and etching the top corner of the Drift layer (2) so that the top cross-section of the Drift layer (2) has a trapezoidal structure; S200, forming a P-body region (3), a NP region (4) and a PP region (5) on the top surface of the Drift layer (2) by ion implantation in sequence, and then activating all the implanted regions by high temperature annealing; S300, forming a gate oxide layer (6) and a Poly layer (7) on the top surfaces of the Drift layer (2), the P-body region (3) and the NP region (4) in sequence; S400, forming an isolation dielectric layer (8) on the top surface of the NP region (4) and the Poly layer (7) by oxide deposition; S500, forming an ohmic contact alloy layer (9) on the top surface of the NP region (4) and the PP region (5) by Ni metal sputtering or deposition followed by thermal annealing; S600, forming a front electrode metal layer (10) on the top surfaces of the isolation dielectric layer (8) and the ohmic contact alloy layer (9) by sputtering Ti and AlCu metals.
2. The method for preparing a deep trapezoidal P-type junction silicon carbide field effect transistor according to claim 1, characterized in that: In step S100, the conductivity type of the Sub layer (1) is N-type, the thickness is 100um-450um, and the doping concentration is 1E19-3E19cm -2 , the conductivity type of the drift layer (2) is N-type, the thickness is 5um-15um, and the doping concentration is 5E15-5E16cm -2 .
3. The method for preparing a deep trapezoidal P-type junction silicon carbide field effect transistor according to claim 1, characterized in that: In step S100, the etching depth vertically downward from the top surface of the Drift layer (2) is 2um-6um.
4. The method for preparing a deep trapezoidal P-type junction silicon carbide field effect transistor according to claim 1, characterized in that: In step S200, the depth of the P-body region (3) is 0.6um-2um, and the doping concentration is 1E17-3E18cm -2 .
5. The method for preparing a deep trapezoidal P-type junction silicon carbide field effect transistor according to claim 1, characterized in that: In step S200, the depth of the NP region (4) is 0.3um-1.2um, and the doping concentration is 1E18-3E19cm -2 .
6. The method for preparing a deep trapezoidal P-type junction silicon carbide field effect transistor according to claim 1, characterized in that: In step S200, the depth of the PP region (5) is 0.3um-1.5um, and the doping concentration is 1E18-3E19cm -2 .
7. The method for preparing a deep trapezoidal P-type junction silicon carbide field effect transistor according to claim 1, characterized in that: In step S300, the thickness of the gate oxide layer (6) is 40nm-60um.
8. The method for preparing a deep trapezoidal P-type junction silicon carbide field effect transistor according to claim 1, characterized in that: The thickness of the Ni metal in step S500 is 0.3um-1um.
9. The method for preparing a deep trapezoidal P-type junction silicon carbide field effect transistor according to claim 1, characterized in that: In step S600 , the thickness of the Ti metal is 0.1 um-0.6 um, and the thickness of the AlCu metal is 2 um-5 um.
10. A silicon carbide field effect transistor with a deep trapezoidal P-type junction, prepared by the method for preparing a silicon carbide field effect transistor with a deep trapezoidal P-type junction according to any one of claims 1 to 9, characterized in that: include: Sub layer (1); The Drift layer (2) has a pair of right-angled trapezoidal etched portions at its top corners, so that the top two sides of the Drift layer (2) are inclined; A pair of P-body regions (3) are provided, extending inward from the top outer surface of the Drift layer (2); a spacing is provided between the tops of the pair of P-body regions (3); An NP region (4) extending downward from the top surface of the P-body region (3); a PP region (5), extending inward from a side surface of the P-body region (3), and having a spacing therebetween from an inner side surface of the P-body region (3); the PP region (5) is connected to the NP region (4); A gate oxide layer (6) is arranged on the top surfaces of the Drift layer (2), the P-body region (3) and the NP region (4); A Poly layer (7) disposed on the top surface of the gate oxide layer (6); An isolation dielectric layer (8) is disposed on the top surface of the Poly layer (7), with a side portion extending downward to connect with the NP region (4); An ohmic contact alloy layer (9), arranged on the outer side of the PP region (5), and connected to the isolation dielectric layer (8) at the top; A front electrode metal layer (10) is arranged on the top of the device.