Display panel, manufacturing method thereof and display device

Abstract

The invention provides a display panel, a manufacturing method thereof and a display device. The display panel comprises: a substrate; the first electrode layer is positioned on one side of the substrate and comprises a plurality of first electrodes which are arranged at intervals; the pixel definition layer is located on one side of the substrate, and at least part of the top surface of each first electrode is exposed out of the pixel definition layer; the second electrode layer covers the pixel definition layer and the first electrode in a planar graph; wherein the pixel definition layer is provided with a barrier groove between at least two adjacent first electrodes; and the second electrode layer is disconnected at the groove wall of one side of the barrier groove. According to the display panel, the current path is prolonged, the problem of power supply voltage drop caused by voltage loss during current flowing is solved, and the in-plane uniformity and the electrical performance of the display panel are improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] With the continuous advancement of display technology and changes in consumer demand, medium-sized display products are becoming increasingly popular and in demand in the current market due to their cost-effectiveness, wide application scenarios, and continuous optimization of manufacturing processes.

[0003] Medium-sized display products usually have a large active display area (AA). In the current display panel manufacturing process, when the active display area is large, it is easy to produce display effect problems caused by uneven pixel voltage distribution and supply voltage drop caused by voltage loss when current flows, which leads to poor in-plane uniformity and has an adverse effect on the performance and stability of the display panel.

[0004] Therefore, how to maintain good in-plane uniformity and electrical performance of the display panel is a problem that needs to be solved urgently.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the invention

[0006] Based on this, the embodiments of the present application provide a display panel and a manufacturing method thereof, and a display device, which improve the problem of power supply voltage drop caused by voltage loss when current flows by extending the current path, thereby improving the in-plane uniformity and electrical performance of the display panel.

[0007] According to some embodiments, the present application provides a display panel, including:

[0008] substrate substrate;

[0009] A first electrode layer, located on one side of the substrate, comprises a plurality of first electrodes arranged at intervals;

[0010] A pixel definition layer, located on one side of the base substrate and exposing at least a portion of the top surface of each of the first electrodes;

[0011] a second electrode layer, the second electrode layer covering the pixel definition layer and the first electrode in a plan view;

[0012] The pixel definition layer has a blocking groove between at least two adjacent first electrodes; and the second electrode layer is disconnected at a groove wall on one side of the blocking groove.

[0013] In some embodiments, the pixel definition layer includes: a pixel defining portion and a raised portion;

[0014] The protrusion is arranged on a side of the pixel defining portion away from the base substrate, and is formed on both sides of the same first electrode together with the blocking groove.

[0015] In some embodiments, a groove wall of the blocking groove is an inclined surface shrinking toward the base substrate.

[0016] In some embodiments, one of the groove walls of the blocking groove is a concave structure; and the second electrode layer is disconnected at the concave structure.

[0017] In some embodiments, the protrusion includes an organic film layer.

[0018] In some embodiments, a depth of the blocking groove is greater than or equal to 1 / 2 of a thickness of the pixel defining portion.

[0019] In some embodiments, the height of the protrusion is greater than or equal to 1 / 2 of the thickness of the pixel defining portion.

[0020] In some embodiments, the display panel includes a plurality of light emitting elements distributed at intervals, and the light emitting elements include an anode and a cathode;

[0021] The anodes of the plurality of light-emitting elements are connected to the plurality of first electrodes correspondingly, and the cathodes of the plurality of light-emitting elements are connected to the second electrode layer.

[0022] In some embodiments, among the plurality of light-emitting elements, at least two of the light-emitting elements are stacked and disposed between the first electrode layer and the second electrode layer.

[0023] According to some embodiments, the present application provides, on the other hand, a method for manufacturing a display panel, including:

[0024] providing a substrate base plate;

[0025] Forming a first electrode layer on one side of the base substrate, wherein the first electrode layer includes a plurality of first electrodes arranged at intervals;

[0026] forming a pixel definition layer on one side of the base substrate, wherein the pixel definition layer exposes at least a portion of the top surface of each of the first electrodes, and a blocking groove is formed between at least two adjacent first electrodes;

[0027] A second electrode layer is formed, wherein the second electrode layer covers the pixel definition layer and the exposed first electrode in a plan view and is disconnected at a groove wall on one side of the blocking groove.

[0028] In some embodiments, forming a pixel definition layer on one side of the base substrate includes:

[0029] forming a pixel defining portion on one side of the base substrate;

[0030] forming a protrusion on a side of the pixel defining portion away from the base substrate;

[0031] The protruding portion and the blocking groove are respectively formed on two sides of the same first electrode, and the pixel defining portion and the protruding portion together constitute the pixel definition layer.

[0032] In some embodiments, forming the barrier groove between at least two adjacent first electrodes comprises:

[0033] forming a sacrificial portion on a side of the pixel defining portion away from the base substrate, wherein the sacrificial portion and the protruding portion are respectively formed on two sides of the same first electrode;

[0034] A passivation layer is covered on the side of the pixel defining portion and the protruding portion away from the base substrate, wherein the passivation layer exposes the sacrificial portion and the blocking groove area;

[0035] The blocking groove region and the sacrificial portion are etched to form the blocking groove.

[0036] In some embodiments, the second electrode layer covers the passivation layer and the exposed pixel defining portion, and is disconnected at a groove wall on one side of the blocking groove.

[0037] According to some embodiments, the present application provides a display device on another aspect, wherein the display device includes the display panel provided in the aforementioned embodiments; or, the display device includes a display panel manufactured using the manufacturing method provided in the aforementioned embodiments.

[0038] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application.

[0039] The embodiments of the present application may or at least have the following advantages:

[0040] In an embodiment of the present application, the pixel definition layer has a blocking groove between at least two adjacent first electrodes, and the second electrode layer is isolated by the blocking groove, so as to achieve effective control of current flow and reduce leakage current. The second electrode layer is disconnected at the groove wall on one side of the blocking groove, so that the blocking groove can effectively separate the current path formed by the power line (PVEE), while the other side remains connected, extending the current path of PVEE, improving the power supply voltage drop (IR Drop) problem caused by voltage loss when current flows, and providing a stable channel for current flow. The embodiment of the present application adopts different settings on both sides of the blocking groove, so that the entire second electrode layer is more stable in design, which helps to improve the in-plane uniformity and electrical performance of the display panel.

[0041] In some embodiments, the pixel definition layer includes a pixel defining portion and a protrusion disposed on a side of the pixel defining portion away from the substrate, and the protrusion and the blocking groove are respectively formed on both sides of the same first electrode. By providing the protrusion on the pixel defining portion, the current path of the PVEE is further extended, and the IR Drop when the current flows is reduced, thereby significantly improving the in-plane uniformity and electrical performance of the display panel.

[0042] Other advantages, objectives and features of the present application will be described in the following description to some extent, and will be apparent to those skilled in the art based on the following examination and study, or can be taught from the practice of the present application to some extent. The objectives and other advantages of the present application can be achieved and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings.

[0044] Figure 1 A schematic diagram of a cross-sectional structure of a display panel in some embodiments of the present application;

[0045] Figure 2 A partial top view of a display panel in some embodiments of the present application;

[0046] Figure 3 A schematic diagram of a process for manufacturing a display panel in some embodiments of the present application;

[0047] Figure 4 A schematic diagram of a process of forming a pixel definition layer on one side of a substrate in some embodiments of the present application;

[0048] Figure 5 A schematic diagram of a process of forming a blocking groove between at least two adjacent first electrodes in some embodiments of the present application;

[0049] Figure 6 A schematic cross-sectional view of a structure obtained after a protrusion is formed in a method for manufacturing a display panel provided in some embodiments of the present application;

[0050] Figure 7 A schematic diagram of a cross-sectional structure of a structure obtained after a passivation layer is formed in a method for manufacturing a display panel provided in some embodiments of the present application;

[0051] Figure 8 A schematic cross-sectional view of a structure obtained after forming a barrier groove in a method for manufacturing a display panel provided in some embodiments of the present application;

[0052] Fig. 9 This is a schematic diagram of the structure of a display device in some embodiments of the present application.

[0053] Description of reference numerals:

[0054] 10, substrate; 101, thin film transistor array layer; 101', via hole; 102, planarization layer;

[0055] 20, first electrode; 20r, first color first electrode; 20g, second color first electrode; 20b, third color first electrode;

[0056] 30, pixel definition layer; 30a, blocking groove; 30a', blocking groove area; 301, pixel definition part; 302, protrusion; 303, sacrificial part; 304, passivation layer;

[0057] 40. a second electrode layer;

[0058] 1. Display device; 100. Display panel. DETAILED DESCRIPTION

[0059] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0061] It should be noted that when an element is considered to be "connected" to another element, it may be directly connected to the other element or there may be an intermediate element at the same time. For example, when a layer, region, element, etc. is described as being connected or electrically connected, the layer, region, element, etc. may not only be directly connected or electrically connected, but also be connected or electrically connected through another layer, region, element, etc. placed therebetween.

[0062] The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only. In the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity. It is understood that when a layer or element is referred to as being "on" another layer or substrate, the layer or element may be directly on the other layer or substrate, or there may be an intermediate layer. In addition, it is also understood that when a layer is referred to as being "between" two layers, the layer may be the only layer between the two layers, or there may be one or more intermediate layers. In addition, the same reference numerals always represent the same elements.

[0063] Hereinafter, although terms such as "first", "second", etc. may be used to describe various components, these components are not necessarily limited to the above terms. The above terms are only used to distinguish one component from another. It will also be understood that expressions used in the singular include plural expressions unless the expression in the singular has an obviously different meaning in the context.

[0064] It should be understood that the terms "include / comprises" or "having" and the like specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0065] In the current manufacturing process of display panels, when the effective display area is large, it is easy to produce display effect problems caused by uneven pixel voltage distribution, and the supply voltage drops caused by voltage loss when current flows, which in turn leads to poor in-plane uniformity and has an adverse effect on the performance and stability of the display panel.

[0066] Based on this, the present application hopes to provide a solution that can solve the above technical problems and can be used to maintain good in-plane uniformity and electrical performance of the display panel. The details will be described in the subsequent embodiments.

[0067] See also Figure 1 The present application provides a display panel, which may include a base substrate 10 , a first electrode layer, a pixel definition layer 30 and a second electrode layer 40 .

[0068] The first electrode layer is located on one side of the base substrate 10, and includes a plurality of first electrodes 20 arranged at intervals; the pixel definition layer 30 is located on one side of the base substrate 10, and exposes at least a portion of the top surface of each first electrode 20; the second electrode layer 40 is located on a plane view (e.g. Figure 1 As shown in the figure), the pixel definition layer 30 and the first electrode 20 are covered.

[0069] The pixel definition layer 30 has a blocking groove 30a between at least two adjacent first electrodes 20, and the second electrode layer 40 is formed at a groove wall on one side of the blocking groove 30a (eg Figure 1 Disconnect at point A where the arrow points.

[0070] In the display panel provided in the present application, the pixel definition layer 30 has a blocking groove 30a between at least two adjacent first electrodes 20, and the second electrode layer 40 is isolated by the blocking groove 30a, thereby achieving effective control of current flow and reducing leakage current. The second electrode layer 40 is located at the groove wall on one side of the blocking groove 30a (such as Figure 1 The isolation groove 30a is disconnected at point A indicated by the middle arrow, so that the blocking groove 30a can effectively separate the current path formed by the power line (PVEE), while the other side remains connected, extending the current path of the PVEE, improving the power supply voltage drop (IR Drop) problem caused by voltage loss when the current flows, and providing a stable channel for current flow.

[0071] The display panel provided in the present application adopts different configurations on both sides of the blocking groove 30 a , so that the entire second electrode layer 40 is more stable in design, which helps to improve the in-plane uniformity and electrical performance of the display panel.

[0072] As an example, Figure 1 As shown, the substrate 10 may include a substrate and a thin film transistor array layer 101 disposed on the substrate. The thin film transistor array layer 101 includes a plurality of thin film transistors, and the thin film transistor array layer 101 may be used as a part of a pixel circuit structure to drive a light emitting element for display.

[0073] Exemplarily, the substrate 10 may further include a planarization layer 102. The planarization layer 102 is disposed on a surface of the thin film transistor array layer 101 away from the substrate, and is used to provide a planarized surface for the subsequent production of the first electrode layer, the pixel definition layer 30, and the second electrode layer 40. The planarization layer 102 is provided with via holes 101', and each first electrode 20 in the first electrode layer can be electrically connected to the thin film transistor array layer 101 via the via holes 101'.

[0074] In some embodiments, please refer to Figure 1The groove wall of the blocking groove 30 a is an inclined surface shrinking toward the base substrate 10 , that is, the distance between the two side walls of the blocking groove 30 a gradually decreases in the direction toward the base substrate 10 .

[0075] In some embodiments, please refer to Figure 1 , one of the groove walls (such as Figure 1 The area A indicated by the middle arrow is a concave structure. The second electrode layer 40 is disconnected at the concave structure.

[0076] The embodiment of the present application does not specifically limit the thickness of the pixel defining portion 301. As an example, the thickness t1 of the pixel defining portion 301 may range from 1.5 μm to 2.5 μm. For example, the thickness t1 of the pixel defining portion 301 may be 1.5 μm, 1.75 μm, 2 μm, 2.25 μm, or 2.5 μm, etc.

[0077] The present embodiment of the application does not specifically limit the depth of the blocking groove 30a. In some embodiments, the depth of the blocking groove 30a is greater than or equal to 1 / 2 of the thickness t1 of the pixel defining portion 301. In this way, the blocking groove 30a can have a sufficient depth, thereby further improving the isolation effect of current separation of the path formed by the PVEE.

[0078] For example, when the thickness t1 of the pixel defining portion 301 is 2 μm, the depth of the blocking groove 30 a may be, for example, 1 μm.

[0079] In some embodiments, please refer to Figure 1 The pixel definition layer 30 may specifically include a pixel defining portion 301 and a protruding portion 302 .

[0080] The protrusion 302 is disposed on a side of the pixel defining portion 301 away from the base substrate 10 , and is formed on two sides of the same first electrode 20 together with the blocking groove 30 a .

[0081] In the above embodiment, the pixel definition layer 30 includes a pixel defining portion 301 and a protruding portion 302 disposed on a side of the pixel defining portion 301 away from the base substrate 10, and the protruding portion 302 and the blocking groove 30a are respectively formed on both sides of the same first electrode 20. By providing the protruding portion 302 on the pixel defining portion 301, while ensuring isolation, the current path of the PVEE is further extended, and the IR Drop when the current flows is reduced, thereby significantly improving the in-plane uniformity and electrical performance of the display panel.

[0082] like Figure 1As shown, a protrusion 302 is provided above the pixel defining portion 301 for padding, and the side of the blocking groove 30 close to the protrusion 302 is kept connected (not disconnected at the groove wall), and the other side is not padded. In this way, while ensuring isolation, the PVEE path can be extended and IR dr op can be reduced.

[0083] The embodiment of the present application does not specifically limit the height of the protrusion 302. In some embodiments, the height t2 of the protrusion 302 is greater than or equal to 1 / 2 of the thickness t1 of the pixel defining portion 301. A higher protrusion 302 can extend the current path of the PVEE more, thereby further reducing the IR Drop when the current flows, and improving the in-plane uniformity and electrical performance of the display panel.

[0084] For example, when the thickness t1 of the pixel defining portion 301 is 2 μm, the height t2 of the protrusion 302 may be, for example, 1 μm.

[0085] The embodiment of the present application does not specifically limit the material of the raised portion 302. In some embodiments, the raised portion 302 may include an organic film layer, but is not limited thereto. The organic film layer has good processability and is easy to coat and pattern. Therefore, the material of the raised portion 302 made of an organic film layer helps to simplify the manufacturing process, reduce the production steps, and thus improve the production efficiency of the display panel.

[0086] The material of the organic film layer can be, for example, polyimide (PI). The polyimide material has good chemical corrosion resistance and can remain stable in subsequent deposition and etching processes, reducing the risk of defects. In addition, the polyimide material still has good performance in a high temperature environment and is suitable for display panel manufacturing processes involving high temperature processing.

[0087] Please continue reading Figure 1 In some embodiments, the display panel may further include a passivation layer 304 . The passivation layer 304 is located on a side of the pixel definition layer 30 away from the base substrate 10 , and covers the protrusion 302 and a portion of the pixel definition portion 301 .

[0088] In the above embodiment, the passivation layer 304 can not only effectively protect the pixel defining portion 301 and the protruding portion 302, prevent external environmental factors (such as moisture, oxygen, etc.) from corroding or damaging these areas, and improve the reliability and life of the display panel, but also further extend the current path of the PVEE, reduce the IR Drop when the current flows, and thus improve the in-plane uniformity and electrical performance of the display panel.

[0089] In some embodiments, the display panel may further include a plurality of light emitting elements distributed at intervals, and the light emitting elements may include an anode and a cathode.

[0090] Specifically, the anodes of the plurality of light emitting elements may be connected to the plurality of first electrodes 20 correspondingly, and the cathodes of the plurality of light emitting elements may be connected to the second electrode layer 40 .

[0091] The plurality of light emitting elements may specifically include a red light emitting element, a green light emitting element and a blue light emitting element. The first electrode connected to the anode of the red light emitting element is Figure 2 The first color first electrode 20r shown in FIG. 1 is connected to the anode of the green light emitting element. Figure 2 The second color first electrode 20g shown in FIG. 1 is connected to the anode of the blue light emitting element. Figure 2 The third color first electrode 20b is shown in FIG.

[0092] See also Figure 2 understand, Figure 2 FIG. 3 shows the passivation layer 304 and the first color first electrode 20r, the second color first electrode 20g and the third color first electrode 20b. Figure 1 understand, Figure 2 The area between the adjacent first electrodes 20 and outside the passivation layer 304, for example Figure 2 The area shown in boxes B and C in the figure indicates Figure 1 The area not covered by the passivation layer 304, that is, Figure 1 The region between the two first electrodes 20 in which the blocking grooves 30 are formed is not covered by the passivation layer 304. However, the region not covered by the passivation layer 304 is not limited thereto.

[0093] For example, please refer to Figure 2 The blocking groove 30 can be arranged between the first color first electrode 20r (corresponding to the red light emitting element) and the second color first electrode 20g (corresponding to the green light emitting element), and between the third color first electrode 20b (corresponding to the blue light emitting element) and the second color first electrode 20g.

[0094] The selective arrangement of the barrier grooves 30 reduces the number of required barrier grooves 30 and avoids the need to form barrier grooves 30 between all adjacent first electrodes 20, thereby simplifying the processing of the pixel definition layer 30, helping to improve the manufacturing efficiency of the display panel and reduce production costs.

[0095] It can be understood that the red light emitting element, the green light emitting element and the blue light emitting element have different luminous efficiency and current density requirements. By selectively setting the blocking groove 30, the characteristics of different light emitting elements can be optimized, thereby further improving the luminous uniformity and performance of the display panel. For example, the green light emitting element generally has a higher luminous efficiency. By selectively setting the blocking groove 30 between the green light emitting element and the light emitting elements of other colors, the light intensity distribution of different colors can be better managed, and the overall luminous uniformity can be optimized.

[0096] The display panel provided in the embodiment of the present application may include various structures, such as a stacked structure. In some embodiments, among the multiple light-emitting elements of the display panel, at least two light-emitting elements are stacked between the first electrode layer and the second electrode layer 40 to form a tandem device structure.

[0097] For example, the above-mentioned Tandem structure may be a structure in which a red light-emitting element, a green light-emitting element and a blue light-emitting element are stacked in series.

[0098] As an example, the display panel provided in the embodiments of the present application may include an organic light emitting diode display panel (Organic Light Emitting Diode, OLED for short), a quantum dot electroluminescent display panel (Quantum Dot Light Emitting Diodes, QLED for short), a sub-millimeter light emitting diode display (Mini Light Emitting Diode Display, Mini LED for short) or a micro light emitting diode display (Micro Light Emitting Diode Display, Micro LED for short), etc., but is not limited to these.

[0099] Based on the same inventive concept, the present application provides a method for manufacturing a display panel, which is used to prepare the display panel provided in the above-mentioned embodiment. Figure 3 The manufacturing method may specifically include the following steps S100 to S400:

[0100] S100: providing a substrate.

[0101] S200: forming a first electrode layer on one side of the base substrate, wherein the first electrode layer includes a plurality of first electrodes arranged at intervals.

[0102] S300: forming a pixel definition layer on one side of the base substrate, wherein the pixel definition layer exposes at least a portion of the top surface of each first electrode, and a blocking groove is formed between at least two adjacent first electrodes.

[0103] S400: forming a second electrode layer, wherein the second electrode layer covers the pixel definition layer and the exposed first electrode in a plan view and is disconnected at a groove wall on one side of the blocking groove.

[0104] It can be understood that the implementation scheme for solving the problem provided by the above manufacturing method is similar to the implementation scheme of the display panel recorded in the above embodiment. Therefore, the technical effects that can be achieved by the above display panel can also be achieved by the above manufacturing method, which will not be repeated here.

[0105] In some embodiments, see Figure 4 The process of forming a pixel definition layer on one side of the substrate may include the following steps S311-S312:

[0106] S311: forming a pixel defining portion on one side of the base substrate.

[0107] S312: forming a protruding portion on a side of the pixel defining portion away from the base substrate; wherein the protruding portion and the blocking groove are respectively formed on two sides of the same first electrode, and the pixel defining portion and the protruding portion together constitute a pixel definition layer.

[0108] In some embodiments, see Figure 5 The process of forming a blocking groove between at least two adjacent first electrodes may include the following steps S321 to S323:

[0109] S321: forming a sacrificial portion on a side of the pixel defining portion away from the base substrate, wherein the sacrificial portion and the protruding portion are respectively formed on two sides of the same first electrode.

[0110] S322: Covering the pixel defining portion and the protruding portion on a side away from the base substrate with a passivation layer, wherein the passivation layer exposes the sacrificial portion and the blocking groove region.

[0111] S323: etching the blocking groove region and the sacrificial portion to form a blocking groove.

[0112] In order to more clearly illustrate the preparation methods in some of the above embodiments, Figures 6 to 8 Understand some embodiments of the present application.

[0113] In step S100 , a base substrate 10 is provided.

[0114] As an example, Figure 6 As shown, the substrate 10 may include a substrate and a thin film transistor array layer 101 disposed on the substrate. For the specific method of forming arrayed thin film transistors (TFTs) on the substrate, reference may be made to the existing method of manufacturing a TFT array, which is not limited in the present embodiment of the application.

[0115] In step S200, please continue to refer to Figure 6 A first electrode layer is formed on one side of the base substrate 10 , and the first electrode layer includes a plurality of first electrodes 20 arranged at intervals.

[0116] In step S300, refer to Figures 6 to 8 A pixel definition layer 30 is formed on one side of the base substrate 10 , the pixel definition layer 30 exposes at least a portion of the top surface of each first electrode 20 , and a blocking groove 30 a is formed between at least two adjacent first electrodes 20 .

[0117] Please combine Figure 4 It is understood that, in some embodiments, the process of forming the pixel definition layer 30 on one side of the base substrate 10 may specifically include the following steps S311 - S312 .

[0118] In step S311, please continue to refer to Figure 6 , a pixel defining portion 301 is formed on one side of the base substrate 10 .

[0119] In step S312, please continue to refer to Figure 6 A protrusion 302 is formed on the side of the pixel defining portion 301 away from the base substrate 10. Figure 6 As shown, the protrusion 302 and the blocking groove 30 a are respectively formed on two sides of the same first electrode 20 , and the pixel defining portion 301 and the protrusion 302 together constitute the pixel definition layer 30 .

[0120] As an example, step S311 may include: forming a pixel defining portion 301 on one side of the base substrate 10 by using a half-tone mask process.

[0121] The half-tone mask process uses a half-tone mask (HTM), which uses a film with a certain optical transmittance to achieve a partial light-transmitting function. When used, traditional masks only show two effects: light-transmitting and light-impermeable for light of a specific wavelength. As an advanced mask material, the half-tone mask (HTM) is formed on a glass substrate through multiple sputtering depositions to form two film layers, a semi-transmitting film and a light-shielding film, and then through two photolithography processes to form a graphic structure that includes full light-transmitting, completely light-impermeable, and partially light-transmitting effects. All indicators of its graphic accuracy are higher than those of traditional masks.

[0122] In some embodiments, the process of forming the barrier groove 30a between at least two adjacent first electrodes 20 may specifically include the following steps S321 to S323:

[0123] In step S321, please continue to refer to Figure 6 A sacrificial portion 303 is formed on a side of the pixel defining portion 301 away from the base substrate 10. Figure 6 As shown, the sacrificial portion 303 and the protruding portion 302 are respectively formed on two sides of the same first electrode 20 .

[0124] In step S322, refer to Figure 7 , the pixel defining portion 301 and the protruding portion 302 are covered with a passivation layer 304 on the side away from the base substrate 10. Figure 7 As shown, the passivation layer 304 exposes the sacrificial portion 303 and the blocking groove area, which can ensure that the sacrificial portion 303 can be accurately removed in subsequent steps and that the blocking groove 30a can be etched into a predetermined shape.

[0125] In step S323, please continue to refer to Figure 8 , etching the blocking groove region and the sacrificial portion 303 to form a blocking groove 30a.

[0126] By adopting the steps provided in the above embodiment, it is possible to add as few additional photomasks (PV Masks) as possible in the process of forming the pixel definition layer 30. For example, only one PV Mask is needed to form the blocking groove 30a. In this way, multiple mask and exposure steps are reduced, which helps to simplify the overall manufacturing process, shorten the manufacturing cycle, and thus improve the production efficiency of the display panel, which is particularly suitable for rapid batch manufacturing in large-scale production.

[0127] It should be noted that there is no order restriction between the step of forming the sacrificial portion 303 and the step of forming the protruding portion 302 in the above embodiment, that is, either of them can be performed first or simultaneously.

[0128] For example, Figure 6 As shown, the protrusion 302 and the sacrificial portion 303 can be formed simultaneously. Performing the steps of forming the protrusion 302 and the sacrificial portion 303 simultaneously can reduce process links and mask design, thereby simplifying the overall production process of the display panel and facilitating shortening the manufacturing cycle of the display panel.

[0129] In step S400, please continue to refer to Figure 1 , forming a second electrode layer 40, the second electrode layer 40 covers the pixel definition layer 30 and the exposed first electrode 20 in a plan view, and at the groove wall on one side of the isolation groove 30a (such as Figure 1 Disconnect at point A where the arrow points.

[0130] In some embodiments, the second electrode layer 40 also covers the passivation layer 304 and the exposed pixel defining portion 301, and is formed at a groove wall on one side of the blocking groove 30a (eg, Figure 1 Disconnect at point A where the arrow points.

[0131] Before forming the second electrode layer 40 in step S400, a light-emitting material may be deposited to form a light-emitting layer, so that the first electrode layer, the light-emitting layer, and the second electrode layer 40 are sequentially stacked on the base substrate 10. The specific process of depositing the light-emitting material to form the light-emitting layer is not the focus of this application, and the process can also refer to the relevant technology, and will not be further described here.

[0132] It should be noted that the manufacturing methods of the display panels in the embodiments of the present application can be used to manufacture corresponding display panels. Therefore, the technical features between the method embodiments and the structural embodiments can be replaced and supplemented with each other without causing conflicts, so that technical personnel in this field can understand the technical content of the present application.

[0133] Based on the same inventive concept, the present application also provides a display device. Fig. 9 The display device 1 may include the display panel 100 provided in the aforementioned embodiment; or, it may also include the display panel 100 manufactured by the manufacturing method provided in the aforementioned embodiment.

[0134] It can be understood that the implementation scheme for solving the problem provided by the above display device is similar to the implementation scheme of the display panel or the implementation scheme of the manufacturing method recorded in the above embodiments. Therefore, the technical effects that can be achieved by the above display panel or its manufacturing method can also be achieved by the above display device, which will not be repeated here.

[0135] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0136] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: include: substrate substrate; A first electrode layer, located on one side of the substrate, comprises a plurality of first electrodes arranged at intervals; A pixel definition layer, located on one side of the base substrate and exposing at least a portion of the top surface of each of the first electrodes; a second electrode layer, the second electrode layer covering the pixel definition layer and the first electrode in a plan view; The pixel definition layer has a blocking groove between at least two adjacent first electrodes; and the second electrode layer is disconnected at a groove wall on one side of the blocking groove.

2. The display panel according to claim 1, characterized in that: The pixel definition layer comprises: a pixel defining portion and a convex portion; The protrusion is arranged on a side of the pixel defining portion away from the base substrate, and is formed on both sides of the same first electrode together with the blocking groove.

3. The display panel according to claim 1, characterized in that: The groove wall of the blocking groove is an inclined surface shrinking toward the base substrate.

4. The display panel according to claim 1, characterized in that: One of the groove walls of the blocking groove is a concave structure; the second electrode layer is disconnected at the concave structure.

5. The display panel according to claim 2, characterized in that: The protrusion includes an organic film layer.

6. The display panel according to claim 2, characterized in that: The depth of the blocking groove is greater than or equal to 1 / 2 of the thickness of the pixel defining portion.

7. The display panel according to claim 6, characterized in that: The height of the protrusion is greater than or equal to 1 / 2 of the thickness of the pixel defining portion.

8. The display panel according to any one of claims 1 to 7, characterized in that: The invention comprises a plurality of light emitting elements which are distributed at intervals, wherein the light emitting elements comprise an anode and a cathode; The anodes of the plurality of light-emitting elements are connected to the plurality of first electrodes correspondingly, and the cathodes of the plurality of light-emitting elements are connected to the second electrode layer.

9. The display panel according to claim 8, characterized in that: Among the plurality of light emitting elements, at least two of the light emitting elements are stacked between the first electrode layer and the second electrode layer.

10. A method for manufacturing a display panel, characterized in that: include: providing a substrate base plate; Forming a first electrode layer on one side of the base substrate, wherein the first electrode layer includes a plurality of first electrodes arranged at intervals; forming a pixel definition layer on one side of the base substrate, wherein the pixel definition layer exposes at least a portion of the top surface of each of the first electrodes, and a blocking groove is formed between at least two adjacent first electrodes; A second electrode layer is formed, wherein the second electrode layer covers the pixel definition layer and the exposed first electrode in a plan view and is disconnected at a groove wall on one side of the blocking groove.

11. The method for manufacturing a display panel according to claim 10, wherein: The step of forming a pixel definition layer on one side of the base substrate comprises: forming a pixel defining portion on one side of the base substrate; forming a protrusion on a side of the pixel defining portion away from the base substrate; The protruding portion and the blocking groove are respectively formed on two sides of the same first electrode, and the pixel defining portion and the protruding portion together constitute the pixel definition layer.

12. The method for manufacturing a display panel according to claim 11, characterized in that: Forming the barrier groove between at least two adjacent first electrodes comprises: forming a sacrificial portion on a side of the pixel defining portion away from the base substrate, wherein the sacrificial portion and the protruding portion are respectively formed on two sides of the same first electrode; A passivation layer is covered on the side of the pixel defining portion and the protruding portion away from the base substrate, wherein the passivation layer exposes the sacrificial portion and the blocking groove area; The blocking groove region and the sacrificial portion are etched to form the blocking groove.

13. The method for manufacturing a display panel according to claim 12, characterized in that: The second electrode layer covers the passivation layer and the exposed pixel defining portion, and is disconnected at a groove wall on one side of the blocking groove.

14. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 9; or, the display device comprises a display panel manufactured by the manufacturing method according to any one of claims 10 to 13.

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