Double-sided polishing device and double-sided polishing method

Abstract

The invention provides a double-sided polishing device and a double-sided polishing method.The double-sided polishing method comprises the steps that firstly, a mechanical grinding process is executed, so that the face, away from a buried oxide layer, of a device wafer is thinned to the preset thickness, and the edge thickness difference of the device wafer meets the first preset threshold value; then executing a double-sided chemical mechanical polishing process to enable the edge thickness difference of the bonded wafer to meet a second preset threshold value; the carrier for executing the double-sided chemical mechanical polishing process comprises a lining and a substrate, the thickness difference between the lining and the substrate is 5-10 [mu] m, and the thickness of the lining is 770-780 [mu] m. By controlling the thickness of the lining and the thickness difference between the lining and the substrate of the carrier for the double-sided chemical mechanical polishing process, the edge thickness difference of the SOI wafer after the double-sided chemical mechanical polishing process meets the second preset threshold value, the edge thickness difference range of top silicon of the SOI wafer is improved, and the edge thickness uniformity of the SOI wafer is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a double-sided polishing device and a double-sided polishing method. Background Art

[0002] Silicon on insulator (SOI) technology has become one of the mainstream products in most electronic materials fields. SOI is an integrated circuit manufacturing technology that achieves insulation between the silicon layer and the substrate by growing a thin silicon layer on an insulating substrate. SOI technology can improve the performance and reliability of integrated circuits, reduce power consumption and noise, and achieve a smaller device size. With the rapid development of new energy vehicles, the integration of automotive-grade SOI material on-board chips has gradually increased. Therefore, the market demand for high-uniformity SOI is getting higher and higher. How to further improve the uniformity of SOI materials has become an important trend in current development.

[0003] The SOI double-sided polishing process is one of the main processes in wafer manufacturing. Its main function is to eliminate stress damage caused by cutting and thinning, improve wafer uniformity, and obtain wafers with high flatness and low roughness. As one of the key components in the double-sided polishing process, the selection of the carrier planetary wheel is crucial. The planetary wheel consists of a stainless steel bushing and a DLC (diamond film) substrate. The thickness and uniformity of the bushing and substrate have an important impact on the uniformity of the top silicon of SOI after double-sided polishing.

[0004] Currently, SOI wafers of target thickness are generally obtained through chemical mechanical grinding and polishing processes. The chemical mechanical grinding and polishing process needs to consider the thinness of the silicon layer and the surface flatness. The uneven thickness of the dome-shaped top silicon layer may cause unstable device performance, which in turn leads to inconsistent current density in local electron channels, uneven thermal effects and even line width changes. Summary of the invention

[0005] The object of the present invention is to provide a double-sided polishing device and a double-sided polishing method to improve the uniformity of wafers after the double-sided polishing process of silicon on insulator.

[0006] In order to solve the above technical problems, the present invention provides a double-sided polishing method, comprising:

[0007] Providing a bonding wafer, the bonding wafer comprising a device wafer, a support wafer, and a buried oxide layer located between the support wafer and the device wafer;

[0008] Performing a mechanical grinding process so that a side of the device wafer away from the buried oxide layer is thinned to a preset thickness and an edge thickness difference of the device wafer meets a first preset threshold;

[0009] Performing a double-sided chemical mechanical polishing process so that the edge thickness difference of the bonded wafer meets a second preset threshold, and the bonded wafer after double-sided polishing constitutes an SOI wafer;

[0010] The carrier used to perform the double-sided chemical mechanical polishing process includes a bushing and a substrate, the difference in thickness between the bushing and the substrate is 5 μm to 10 μm, and the thickness of the bushing is 770 μm to 780 μm.

[0011] Optionally, the first preset threshold is less than 0.8 μm, and the second preset threshold is less than 0.2 μm.

[0012] Optionally, the thickness difference range of the bushing is less than 8 μm, and the thickness difference range of the substrate is less than 2 μm.

[0013] Optionally, after performing the mechanical grinding process, the preset thickness of the device wafer is greater than 12 μm.

[0014] Optionally, the solution of the double-sided chemical mechanical polishing process is an alkaline polishing solution.

[0015] Optionally, the solution pH value of the double-sided chemical mechanical polishing process is 10-12, the polishing pressure of the double-sided chemical mechanical polishing process is 500kg to 1500kg, and the disk temperature of the carrier of the double-sided chemical mechanical polishing process is 20°C to 30°C.

[0016] Optionally, the step of forming the bonded wafer includes:

[0017] Provide support wafers and device wafers;

[0018] performing a thermal oxidation process to form a buried oxide layer on the support wafer and / or the device wafer;

[0019] A bonding process is performed to bond the support wafer and the device wafer, wherein the buried oxide layer is located between the support wafer and the device wafer.

[0020] Optionally, the buried oxide layer has a thickness of 0.2 μm to 2 μm.

[0021] Optionally, after the bonded wafer is formed, a heat treatment strengthening process, a chamfering process and an edge corrosion process are sequentially performed on the bonded wafer.

[0022] Based on the same inventive concept, the present invention also provides a double-sided polishing device for executing any of the double-sided polishing methods described above, comprising a plurality of planetary wheels, wherein the planetary wheels comprise a bushing and a base, the thickness difference between the bushing and the base is 5 μm to 10 μm and the thickness of the bushing is 770 μm to 780 μm.

[0023] In the double-sided polishing method provided by the present invention, a bonded wafer is provided, the bonded wafer includes a device wafer, a support wafer, and a buried oxide layer located between the support wafer and the device wafer; a mechanical grinding process is performed to thin the back side of the device wafer to a preset thickness and the edge thickness difference of the device wafer meets a first preset threshold; a double-sided chemical mechanical polishing process is performed to make the edge thickness difference of the bonded wafer meet a second preset threshold; wherein, the carrier used to perform the double-sided chemical mechanical polishing process includes a bushing and a substrate, the thickness difference between the bushing and the substrate is 5μm to 10μm and the thickness of the bushing is 770μm to 780μm. By controlling the bushing thickness of the carrier of the double-sided chemical mechanical polishing process and the thickness difference between the bushing and the substrate, so that the edge thickness difference of the SOI wafer after the double-sided chemical mechanical polishing process meets the second preset threshold, the edge thickness difference range of the top silicon of the SOI wafer is improved, and the edge thickness uniformity of the SOI wafer is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0025] Figure 1 4 is a relationship diagram between the sleeve thickness, the base thickness and the edge thickness difference of the wafer after polishing of the planetary wheel according to the embodiment of the present invention.

[0026] Figure 2 It is a flow chart of the double-sided polishing method according to an embodiment of the present invention.

[0027] Figures 3 to 5 It is a schematic diagram of the structures corresponding to the steps of the double-sided polishing method according to an embodiment of the present invention.

[0028] Figure 6 1 is a schematic structural diagram of a planetary wheel according to an embodiment of the present invention.

[0029] In the attached figure:

[0030] 10-support wafer; 11-first buried oxide layer; 20-device wafer; 21-second buried oxide layer; 30-planetary wheel; 31-substrate; 32-bushing. DETAILED DESCRIPTION

[0031] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0032] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second" and "third" can explicitly or implicitly include one or at least two of the features. In addition, as used in the present invention, an element is arranged on another element, which usually only indicates that there is a connection, coupling, matching or transmission relationship between the two elements, and the connection, coupling, matching or transmission between the two elements can be direct or indirect through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, an element can be in any orientation such as inside, outside, above, below or on one side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0033] The inventors have found that the edge thickness difference of the SOI wafer in the traditional double-sided polishing process is uncontrollable, which affects the overall uniformity of the top silicon of the SOI wafer, thereby causing unstable device performance, inconsistent current density of local electron channels, uneven thermal effects and even line width changes.

[0034] In the double-sided polishing process, the factors that affect the edge thickness difference of the SOI wafer are usually process factors and equipment accessories, especially equipment accessories that are in direct contact with the wafer. The thickness of the sleeve of the carrier and the thickness of the base of the carrier in the equipment accessories have a significant impact on the edge thickness difference of the SOI wafer. In the traditional process, the uniformity of the sleeve thickness of the carrier and the thickness of the base of the carrier will have a significant impact on the thickness uniformity of the top silicon of the SOI wafer, so the current strategy is to have higher and higher specifications for the carrier. However, even if the thickness of the carrier sleeve and the thickness of the base are controlled, the edge uniformity of SOI still cannot meet the requirements. This is because compared with silicon wafers, the edge of the SOI wafer will have a circle of obvious steps due to the influence of the chamfering process. The inventor analyzed that it is due to the existence of the edge step that if the thickness difference between the carrier sleeve and the base is too large or too small, it will affect the distribution of the polishing liquid in the edge area. Too large will cause too much polishing liquid to remain here and remove too much, and too small will also affect the discharge circulation process of the polishing liquid, and some positions will be uneven. Therefore, the inventor speculates that the edge thickness difference of the SOI wafer can only be controlled if there is a matching process window between the carrier sleeve and the carrier substrate. The inventor designed a DOE experiment for the two influencing factors of the carrier sleeve and the carrier substrate, and obtained a large amount of experimental data. The experimental data show that the edge thickness difference range (Range) of the SOI wafer after polishing is significantly correlated with the carrier sleeve thickness and the substrate thickness. The carrier sleeve thickness is controlled at 770μm~780μm. When the carrier sleeve thickness X and the substrate thickness Y meet the conditions of 5μm≤YX≤10μm, the edge thickness difference range (Range) of the SOI wafer after double-sided polishing can be controlled within 0.2μm. In this experiment, the carrier is a planetary wheel. Specifically, Figure 1 : is a graph showing the relationship between the sleeve thickness, substrate thickness and edge thickness difference of the polished wafer of the embodiment of the present invention. When the sleeve thickness of the carrier's carrier for the double-sided chemical mechanical polishing process is between 770μm and 780μm, we tested the edge thickness difference range of SOI wafers after polishing with carriers of different substrate thicknesses. The results are as follows: Figure 1 shown. Figure 1The horizontal axis is the bushing thickness, in micrometers (μm), and the vertical axis is the substrate thickness or base thickness, in micrometers (μm). The edge thickness difference range (Range) of the SOI wafer represented by the green data points is less than or equal to 0.2μm, and the edge thickness difference range (Range) of the SOI wafer represented by the red data points is greater than 0.2μm. The test results show that the edge thickness difference range (Range) of the polished SOI wafer is significantly correlated with the thickness of the planetary bushing and the thickness of the substrate. The thickness of the planetary bushing is controlled at 770μm to 780μm. When the planetary bushing thickness X and the base thickness Y meet the conditions of 5μm≤YX≤10μm, the edge thickness difference range (Range) of the SOI wafer after double-sided polishing can be controlled within 0.2μm.

[0035] The inventors also conducted experimental research and designed 6 groups of experiments. The thickness of the support wafer 10 in each group of experiments was the same, all 775 μm. The thickness difference range of the edge after chemical mechanical polishing in each group of experiments was also the same, all 0.5 μm. The thickness of the device wafer 20 after chemical mechanical polishing in each group of experiments was also the same, all 15 μm. That is, the thickness of the top silicon of the SOI wafer before the double-sided chemical mechanical polishing process was the same, 15 μm. However, the thickness of the bushing of the carrier planetary wheel in the double-sided chemical mechanical polishing process is different from the thickness of the substrate, so the edge thickness difference range of the SOI wafer after the double-sided chemical mechanical polishing process is also different. The bushing thickness of the first group is 770 μm, the substrate thickness is 784 μm, and the thickness difference between the bushing and the substrate is 14 μm. The bushing thickness of the second group is 775 μm, the substrate thickness is 783 μm, and the thickness difference between the bushing and the substrate is 8 μm. The thickness of the sleeve of the third group is 777μm, the thickness of the substrate is 783μm, and the thickness difference between the sleeve and the substrate is 6μm. The thickness of the sleeve of the fourth group is 778μm, the thickness of the substrate is 790μm, and the thickness difference between the sleeve and the substrate is 12μm. The thickness of the sleeve of the fifth group is 778.5μm, the thickness of the substrate is 788μm, and the thickness difference between the sleeve and the substrate is 9.5μm. The thickness of the sleeve of the sixth group is 780μm, the thickness of the substrate is 784μm, and the thickness difference between the sleeve and the substrate is 4μm. Specifically, two silicon wafers are provided as the device wafer 20 and the support wafer 10 respectively, and the thickness of the support wafer 10 is 775μm; the two silicon wafers or one of the silicon wafers are thermally oxidized to obtain an SOI buried oxide layer; the device wafer 20 and the support wafer 10 are bonded, and after bonding, a heat treatment reinforcement process, a chamfering process, an edge corrosion process and a mechanical grinding process are performed. After the mechanical grinding process, the overall thickness distribution of the SOI wafer is concave, and the thickness of the top silicon is 15μm, that is, the thickness of the device wafer 20 is 15μm; a double-sided chemical mechanical polishing process is performed, and the polishing removal amount is 8μm. When a buried oxide layer is formed on the support wafer 10, a buried oxide layer will also be formed on the side of the support wafer 10 away from the device wafer 20. At this time, the side of the support wafer 10 away from the device wafer 20 will not be polished, and only the side of the device wafer 20 away from the support wafer 10 will be polished. When no buried oxide layer is formed on the support wafer 10, and the side of the support wafer 10 away from the device wafer 20 is bare silicon, the side of the support wafer 10 away from the device wafer 20 is polished at the same time, that is, double-sided polishing.

[0036] Table 1 Effect of different bushing thickness and substrate thickness on the edge thickness difference of polished wafer

[0037]

[0038] As described in Table 1, the sleeve thickness of the first group is 770μm, the substrate thickness is 784μm, the thickness difference between the sleeve and the substrate is 14μm, and the edge thickness difference range of the SOI wafer after polishing is 0.35μm. The sleeve thickness of the second group is 775μm, the substrate thickness is 783μm, the thickness difference between the sleeve and the substrate is 8μm, and the edge thickness difference range of the SOI wafer after polishing is 0.15μm. The sleeve thickness of the third group is 777μm, the substrate thickness is 783μm, the thickness difference between the sleeve and the substrate is 6μm, and the edge thickness difference range of the SOI wafer after polishing is 0.18μm. The sleeve thickness of the fourth group is 778μm, the substrate thickness is 790μm, the thickness difference between the sleeve and the substrate is 12μm, and the edge thickness difference range of the SOI wafer after polishing is 0.35μm. The thickness of the bushing of the fifth group is 778.5μm, the thickness of the substrate is 788μm, the thickness difference between the bushing and the substrate is 9.5μm, and the edge thickness difference of the polished SOI wafer is 0.15μm. The thickness of the bushing of the sixth group is 780μm, the thickness of the substrate is 784μm, the thickness difference between the bushing and the substrate is 4μm, and the edge thickness difference of the polished SOI wafer is 0.39μm. It can be seen that only the edge thickness difference of the polished SOI wafer of the second, third and fifth groups is controlled within 0.2μm, and only the thickness difference between the bushing and the substrate of the second, third and fifth groups is between 5μm and 10μm. And whether it is the first and fourth groups whose thickness difference between the bushing and the substrate is greater than 10μm, or the sixth group whose thickness difference between the bushing and the substrate is less than 5μm, the edge thickness difference of the polished SOI wafer is greater than 0.2μm.

[0039] Therefore, when the difference between the sleeve and the base thickness of the planetary wheel is stable within a certain range, the edge thickness difference range of the polished SOI wafer is better controlled. When the sleeve thickness and base thickness of the planetary wheel meet 5μm≤YX≤10μm, where the sleeve thickness X of the planetary wheel is between 770μm and 780μm, the edge thickness difference range of the SOI wafer after double-sided polishing is controllable, and the edge thickness difference of the SOI wafer is less than 0.2μm.

[0040] Based on this, the core idea of ​​the present invention is to provide a bonded wafer, wherein the bonded wafer includes a device wafer, a support wafer, and a buried oxide layer between the support wafer and the device wafer; perform a mechanical grinding process so that the back side of the device wafer is thinned to a preset thickness and the edge thickness difference of the device wafer meets a first preset threshold; perform a double-sided chemical mechanical polishing process so that the edge thickness difference of the bonded wafer meets a second preset threshold; wherein the carrier used to perform the double-sided chemical mechanical polishing process includes a bushing and a substrate, the thickness difference between the bushing and the substrate is 5μm to 10μm and the thickness of the bushing is 770μm to 780μm. By controlling the bushing thickness of the carrier of the double-sided chemical mechanical polishing process and the thickness difference between the bushing and the substrate so that the edge thickness difference of the SOI wafer after the double-sided chemical mechanical polishing process meets the second preset threshold, the edge thickness difference range of the top silicon of the SOI wafer is improved, and the edge thickness uniformity of the SOI wafer is improved.

[0041] Specifically, Figure 2 1 is a flow chart of the double-sided polishing method according to an embodiment of the present invention. Figure 2 As shown, this embodiment provides a double-sided polishing method, comprising:

[0042] Step S10, providing a bonding wafer, wherein the bonding wafer includes a device wafer, a support wafer, and a buried oxide layer located between the support wafer and the device wafer;

[0043] Step S20, performing a mechanical grinding process to thin the side of the device wafer away from the buried oxide layer to a preset thickness and an edge thickness difference of the device wafer meets a first preset threshold;

[0044] Step S30, performing a double-sided chemical mechanical polishing process so that the edge thickness difference of the bonded wafer meets a second preset threshold, and the bonded wafer after double-sided polishing constitutes an SOI wafer; wherein, the carrier used to perform the double-sided chemical mechanical polishing process includes a sleeve and a substrate, the thickness difference between the sleeve and the substrate is 5μm to 10μm and the thickness of the sleeve is 770μm to 780μm.

[0045] Figures 3 to 5 1 is a schematic diagram of the double-sided polishing method according to the embodiment of the present invention. Figures 3 to 5 The specific embodiments of the present invention are described in detail.

[0046] like Figure 3 As shown, a bonding wafer is provided, wherein the bonding wafer includes a device wafer 20 , a support wafer 10 , and a buried oxide layer located between the support wafer 10 and the device wafer 20 .

[0047] In detail, the step of forming the bonded wafer includes: providing a support wafer 10 and a device wafer 20; the support wafer 10 is used to support the device wafer 20 when the device wafer 20 is thinned. The thickness of the support wafer 10 is, for example, 772 μm to 777 μm. The TTV (Total Thickness Variation) of the support wafer 10 and the device wafer 20 is less than 0.4 μm. The diameter of the support wafer 10 and the device wafer 20 is 200 mm or 300 mm. The device wafer 20 provides an operating platform for subsequent processes, which can be any substrate for carrying semiconductor integrated circuit components known to those skilled in the art, can be a bare chip, or can be a wafer processed by an epitaxial growth process. In detail, the substrate of the device wafer 20 is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate. In this embodiment, the device wafer 20 is a silicon wafer. A thermal oxidation process is performed to form a buried oxide layer on the support wafer 10 and / or the device wafer 20; specifically, the buried oxide layer can be formed by performing a thermal oxidation process only on one of the support wafer 10 or the device wafer 20, or by performing a thermal oxidation process on both of the support wafer 10 and the device wafer 20. A person skilled in the art can select according to the thickness of the buried oxide layer. In this embodiment, the thickness of the buried oxide layer is, for example, 0.2 μm to 2 μm. A buried oxide layer is formed on both the support wafer 10 and the device wafer 20, that is, a first buried oxide layer 11 is formed on the support wafer 10, and a second buried oxide layer 21 is formed on the device wafer 20. A bonding process is performed to bond the support wafer 10 and the device wafer 20, and the buried oxide layer is located between the support wafer 10 and the device wafer 20. That is, the first buried oxide layer 11 and the second buried oxide layer 21 are located between the support wafer 10 and the device wafer 20. In other words, the first buried oxide layer 11 and the second buried oxide layer 21 are in contact. After forming the bonded wafer, the bonded wafer is sequentially subjected to a heat treatment strengthening process, a chamfering process and an edge etching process.

[0048] like Figure 4As shown, a mechanical grinding process is performed to thin the side of the device wafer 20 away from the second buried oxide layer 21 to a preset thickness and the edge thickness difference of the device wafer 20 meets a first preset threshold. A dual-axis grinder is used for the mechanical grinding process. After performing the mechanical grinding process, the preset thickness of the device wafer 20 is greater than 12μm, and the thickness of the device wafer 20 is, for example, 15μm. It is worth noting that the thickness of the device wafer 20 refers to the average thickness of the device wafer 20. The first preset threshold is less than 0.8μm, that is, the range (Range) of the edge thickness difference of the device wafer 20 after the mechanical grinding process is controlled within 0.8μm. The edge thickness difference of the device wafer 20 here refers to the difference between the maximum and minimum values ​​of the edge thickness.

[0049] like Figure 5 As shown, a double-sided chemical mechanical polishing process is performed so that the edge thickness difference of the bonded wafer meets a second preset threshold value, and the bonded wafer after double-sided polishing constitutes an SOI wafer; the second preset threshold value is less than 0.2μm, that is, the edge thickness difference range of the SOI wafer after double-sided polishing can be controlled within 0.2μm. The edge thickness difference of the SOI wafer in the traditional double-sided polishing process is uncontrollable, which affects the overall uniformity of the top silicon of the SOI wafer, thereby causing unstable device performance, inconsistent current density of local electron channels, uneven thermal effects and even line width changes. In this implementation, the edge thickness difference range of the SOI wafer after double-sided polishing can be controlled within 0.2μm, which improves the edge thickness difference range of the top silicon of the SOI wafer, improves the uniformity of the top silicon of the SOI wafer, and thus improves the stability of the device of the SOI wafer.

[0050] Figure 6 Schematic diagram of the structure of the planetary wheel in the embodiment of the present invention. Figure 6As shown, the double-sided chemical mechanical polishing process in this embodiment can control the edge thickness difference range of the SOI wafer within 0.2μm because the carrier of the double-sided chemical mechanical polishing process meets specific conditions. The carrier of the double-sided chemical mechanical polishing process is, for example, a planetary wheel. The planetary wheel 30 includes a substrate 31 and a bushing 32. The carrier of the double-sided chemical mechanical polishing process meets specific conditions that the thickness difference between the bushing 32 and the substrate 31 is 5μm to 10μm and the thickness of the bushing 32 is 770μm to 780μm. In detail, the thickness of the bushing 32 is X, where the thickness of the bushing 32 refers to the average thickness, and the thickness difference range (Range) of the bushing 32 is less than 8μm. The thickness of the substrate 31 is Y, where the thickness of the substrate 31 refers to the average thickness, and the thickness difference range (Range) of the substrate 31 is less than 2μm. During the double-sided polishing process, the bushing 32 and base 31 of the carrier planetary wheel 30 control the position of the SOI wafer by contacting the edge of the SOI wafer, thereby determining the final thickness and thickness difference range (Range) of the SOI wafer. Therefore, when the thickness difference between the bushing 32 and base 31 of the planetary wheel 30 is stable within a certain range, the thickness difference range (Range) of the edge of the SOI wafer after double-sided polishing is better controlled. Specifically, when the thickness X of the bushing 32 of the planetary wheel 30 and the thickness Y of the base 31 satisfy 5μm≤YX≤10μm, wherein the thickness X of the bushing 32 is between 770μm and 780μm, the thickness difference range (Range) of the edge of the SOI wafer after the double-sided chemical mechanical polishing process is controllable, and the thickness difference range (Range) of the edge of the SOI wafer is less than 0.2μm.

[0051] In this embodiment, the solution of the double-sided chemical mechanical polishing process is an alkaline polishing solution. The pH value of the solution of the double-sided chemical mechanical polishing process is 10-12, the polishing pressure of the double-sided chemical mechanical polishing process is, for example, 500kg to 1500kg, and the disc temperature of the carrier of the double-sided chemical mechanical polishing process is, for example, 20°C to 30°C.

[0052] Figure 6: is a schematic diagram of the structure of the planetary wheel of an embodiment of the present invention. This embodiment also provides a double-sided polishing device for performing any of the double-sided polishing methods described above. The double-sided polishing device includes a plurality of planetary wheels (only one planetary wheel is shown in the figure), the planetary wheel 30 includes a base 31 and a bushing 32, the thickness of the bushing 32 is X, the thickness of the bushing 32 here refers to the average thickness, the thickness difference range (Range) of the bushing 32 is less than 8μm, the thickness of the base 31 is Y, the thickness of the base 31 here refers to the average thickness, and the thickness difference range (Range) of the base 31 is less than 2μm. When the thickness of the bushing 32 of the planetary wheel 30 and the thickness of the base 31 meet 5μm≤YX≤10μm, wherein the thickness X of the bushing 32 is between 770μm and 780μm, the thickness difference range (Range) of the edge of the SOI wafer after the double-sided chemical mechanical polishing process is controllable, and the thickness difference range (Range) of the edge of the SOI wafer is less than 0.2μm.

[0053] In summary, in the double-sided polishing method provided in the embodiment of the present invention, a bonded wafer is provided, the bonded wafer includes a device wafer, a support wafer, and a buried oxide layer located between the support wafer and the device wafer; a mechanical grinding process is performed to thin the back side of the device wafer to a preset thickness and the edge thickness difference of the device wafer meets a first preset threshold; a double-sided chemical mechanical polishing process is performed to make the edge thickness difference of the bonded wafer meet a second preset threshold; wherein, the carrier used to perform the double-sided chemical mechanical polishing process includes a bushing and a substrate, the thickness difference between the bushing and the substrate is 5μm to 10μm and the thickness of the bushing is 770μm to 780μm. By controlling the bushing thickness of the carrier of the double-sided chemical mechanical polishing process and the thickness difference between the bushing and the substrate, so that the edge thickness difference of the bonded wafer after the double-sided chemical mechanical polishing process meets the second preset threshold, the top silicon edge thickness difference range of the SOI wafer is improved, the edge thickness uniformity of the SOI wafer is improved, and the performance of the device wafer is improved.

[0054] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A double-sided polishing method, characterized in that: include: Providing a bonding wafer, the bonding wafer comprising a device wafer, a support wafer, and a buried oxide layer located between the support wafer and the device wafer; Performing a mechanical grinding process so that a side of the device wafer away from the buried oxide layer is thinned to a preset thickness and an edge thickness difference of the device wafer meets a first preset threshold; Performing a double-sided chemical mechanical polishing process so that the edge thickness difference of the bonded wafer meets a second preset threshold, and the bonded wafer after double-sided polishing constitutes an SOI wafer; The carrier used to perform the double-sided chemical mechanical polishing process includes a bushing and a substrate, the difference in thickness between the bushing and the substrate is 5 μm to 10 μm, and the thickness of the bushing is 770 μm to 780 μm.

2. The double-sided polishing method according to claim 1, characterized in that: The first preset threshold is less than 0.8 μm, and the second preset threshold is less than 0.2 μm.

3. The double-sided polishing method according to claim 1, characterized in that: The thickness difference range of the bushing is less than 8 μm, and the thickness difference range of the substrate is less than 2 μm.

4. The double-sided polishing method according to claim 1, characterized in that: After performing the mechanical grinding process, the preset thickness of the device wafer is greater than 12 μm.

5. The double-sided polishing method according to claim 1, characterized in that: The solution of the double-sided chemical mechanical polishing process is an alkaline polishing solution.

6. The double-sided polishing method according to claim 1, characterized in that: The solution pH value of the double-sided chemical mechanical polishing process is 10 to 12, the polishing pressure of the double-sided chemical mechanical polishing process is 500kg to 1500kg, and the disk temperature of the carrier of the double-sided chemical mechanical polishing process is 20°C to 30°C.

7. The double-sided polishing method according to claim 1, characterized in that: The steps of forming the bonded wafer include: Provide support wafers and device wafers; performing a thermal oxidation process to form a buried oxide layer on the support wafer and / or the device wafer; A bonding process is performed to bond the support wafer and the device wafer, wherein the buried oxide layer is located between the support wafer and the device wafer.

8. The double-sided polishing method according to claim 1 or 7, characterized in that: The buried oxide layer has a thickness of 0.2 μm to 2 μm.

9. The double-sided polishing method according to claim 1 or 7, characterized in that: After the bonded wafer is formed, a heat treatment strengthening process, a chamfering process and an edge corrosion process are sequentially performed on the bonded wafer.

10. A double-sided polishing device, characterized in that: A double-sided polishing method for performing any one of claims 1 to 9, comprising a plurality of planetary wheels, wherein the planetary wheels comprise a bushing and a base, the thickness difference between the bushing and the base is 5 μm to 10 μm and the thickness of the bushing is 770 μm to 780 μm.

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