Method for testing single-particle fault transmission in SiP microsystem chip

Abstract

The invention discloses an internal single-particle fault transmission testing method for a SiP microsystem chip, and belongs to the technical field of integrated circuit single-particle effect testing. According to the method disclosed by the invention, the influence of single-particle faults generated by the FPGA in different working modes on the working state of the SiP device is obtained by analyzing each key node of the SiP core processing chip FPGA and a SiP single-particle soft error transmission path and performing single-particle detection on an FPGA sensitive module through simulation; the single-particle cross section of each sensitive module of the FPGA is calculated according to the test data of the single-particle upset and the single-particle function interruption of each sensitive module of the FPGA chip, so that the problems that the SiP single-particle effect ground test is inaccurate and the fault transmission path and the data are difficult to obtain are solved, and a basis is provided for the SiP single-particle ground simulation test.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit single particle effect testing, and in particular to a single particle fault transmission testing method inside a SiP microsystem chip. Background Art

[0002] System-in-Package (SiP) uses three-dimensional stacking packaging technology to package multiple bare chips of electronic components with different functions into a microsystem, and assemble them into an integrated chip that can realize multiple computing functions. It mainly includes field programmable gate array (FPGA), configuration chip, memory chip, digital signal processor (DSP), etc. Due to its high performance, miniaturization, lightweight, and rapid iteration, it is widely used in the aerospace field.

[0003] However, affected by the space radiation environment, when a single high-energy particle is incident on the SiP chip, a certain number of electron-hole pairs are generated in the chip due to energy deposition. The charges are collected at sensitive nodes during the movement, resulting in instantaneous changes in the current. The transient current propagates in the circuit, causing the SiP core chip FPGA to produce single-particle effects, which in turn leads to SiP data calculation errors, program runaway, and even device burnout. In order to study the single-particle fault transmission characteristics of the core computing chip (FPGA) inside the SiP device and to design radiation-resistant reinforcement for the sensitive modules inside the SiP, a ground-based simulated irradiation test is required.

[0004] At present, in the field of single-particle effect testing of integrated circuit chips, the single-particle test method for monolithic integrated circuit chips is relatively mature, but due to the diversity of chips packaged in SiP devices and the particularity of their work, there is no test method for the transmission of single-particle faults within SiP devices. When SiP is working normally, its core chip needs to exchange data with other component-level chips, resulting in intermittent signal working voltage, which is equivalent to intermittent radiation bias. Therefore, the single-particle effect sensitivity of the chip working in SiP is different from the static bias conditions of a single device, and because the transmission of the single-particle fault of its core chip in the SiP device will cause other chips to work abnormally, the traditional independent chip single-particle test method cannot be used to evaluate the single-particle resistance of SiP devices.

[0005] Based on this, it is necessary to further study the single-particle fault transmission test method inside the SiP microsystem chip, test the single-particle lock (SEL), single-particle functional interrupt (SEFI), and single-particle upset (SEU) of the FPGA chip inside the SiP device, and perform transmission test on the single-particle soft error of the FPGA chip in the internal fault of the SiP device, to provide a basis for the SiP single-particle ground simulation test. Summary of the invention

[0006] The problem to be solved by the present invention is to provide a method for testing single particle fault transmission inside a SiP microsystem chip, so as to solve the problems of inaccurate SiP single particle effect ground test and difficulty in obtaining fault transmission path and data.

[0007] The present invention adopts the following technical solution: a method for testing single-particle fault transmission inside a SiP microsystem chip, comprising the following steps:

[0008] Step S1, power on and configure the SiP device to put the SiP device in a normal working state, and monitor the working current of the core processing chip FPGA chip inside the SiP device;

[0009] Step S2, analyzing the structural characteristics of the core processing chip FPGA, dividing and combining the single-particle sensitive circuit modules inside the SiP device, configuring four working modes of the core processing chip FPGA, and establishing a single-particle fault transmission model of the core processing chip FPGA in the SiP device;

[0010] Step S3, analyzing the key nodes of the sensitive module of the core processing chip FPGA, and performing single particle detection of the FPGA sensitive module;

[0011] Step S4, single-particle soft error propagation process analysis, analyzing the impact of single-particle faults generated in each working mode of the core processing chip FPGA on the working state of the entire SiP;

[0012] Step S5, simulating injection errors, injecting single-particle soft errors into each submodule inside the core processing chip FPGA by means of simulation, and detecting the fault transmission result by using a test system;

[0013] Step S6, performing single particle irradiation on the core processing chip FPGA to verify the feasibility of the test method, analyzing the single particle fault transmission characteristics of the SiP device core processing chip FPGA, and calculating the single particle cross section of each sensitive module of the FPGA.

[0014] Preferably, in step S1, the SiP device includes components: a core processing chip FPGA, a configuration chip, a storage chip and an auxiliary operation refresh chip; when the SiP device is in normal working state, the core processing chip FPGA interacts with the configuration chip through the BPI configuration mode, interacts with the storage chip through the DDR2 controller, interacts with the auxiliary processing refresh chip and the external controller through the SRIO and EMIF interfaces, and interacts with the host computer through the UART and GPIO ports.

[0015] Preferably, in step S2, the core processing chip FPGA is an SRAM type structure, and the underlying resources include submodules: block memory, programmable logic block, input / output module, operation circuit and digital clock management unit;

[0016] First, the single-particle sensitive circuit module inside the SiP device is divided, and the programmable logic block is configured as a DRAM memory and an FF trigger chain, so that the core processing chip FPGA works in four different working modes: in the first working mode, the block memory, programmable logic block, and operation circuit resources in the FPGA are all in a running state; in the second working mode, the programmable logic block in the FPGA is in a non-working state; in the third working mode, the block memory is in a non-working state, and the programmable logic block is configured as a DRAM memory; in the fourth working mode, the block memory is in a non-working state, and the programmable logic block is configured as an FF trigger chain.

[0017] Then, a single-particle fault transmission model of the core processing chip FPGA in the SiP device is established, including the following sub-steps:

[0018] Step S2.1, analyzing the internal resources of the programmable logic block, each programmable logic block is connected to a switch matrix, each switch matrix includes a pair of slices, namely SliceL and SliceM, the slices connected to each programmable logic block are organized into a column, and each slice in the column has an independent carry chain;

[0019] The switch matrix is ​​used to access the general wiring matrix. The two slices of each switch matrix are not directly connected to each other. Each slice contains four logic function generators, four storage elements, a multi-function multiplexer and carry logic for logic, arithmetic and ROM function operations. The four logic function generators constitute a LUT lookup table. Some slices use distributed RAM to store data and use 32-bit registers to shift data.

[0020] Step S2.2, configuring the programmable logic block into different logic circuits through Verilog programming, including a LUT resource chain, an FF trigger chain and a DRAM memory; the LUT resource chain includes all resources of SliceL and SliceM, the FF trigger chain includes a D trigger in the Slice resource, and the DRAM memory only uses SliceM;

[0021] Step S2.3, configuring the block memory, the operation circuit and the input / output module so that each module can independently complete the sub-circuit function.

[0022] Preferably, in step S3, the key nodes of the sensitive modules of the core processing chip FPGA include: FPGA internal block memory nodes, programmable logic block nodes, FF trigger nodes, DRAM memory nodes, and transmission nodes for data interaction between the FPGA chip and other components; node single-particle soft error detection is set at each key node of the sensitive module to perform node error detection and record error transmission information.

[0023] Preferably, in step S4, the single-particle soft error propagation path of the core processing chip FPGA in each working mode is as follows:

[0024] Path 1: In the first working mode, the single-particle soft error propagation path is: configuration chip → block memory → programmable logic block → operation circuit → input / output module → auxiliary processing refresh chip and host computer;

[0025] The core processing chip FPGA reads the configuration data in the configuration chip through the BPI mode, temporarily stores it in the block memory, transfers the data in the block memory to the programmable logic block and the auxiliary operation refresh chip for operation processing, and transmits the operation result to the storage chip through the GPIO interface, transmits the operation result to the auxiliary operation refresh chip through the EMIF interface, and transmits it to the host computer through the UART interface; real-time detection of single particle errors generated by each node, and the impact of errors generated by each resource on the next level of resources and other chips;

[0026] Path 2: The second working mode, based on the first working mode, controls the programmable logic block in the core processing chip FPGA to not work, and studies the impact of the block storage module failure on other FPGA modules and the entire SiP chip. The single-particle soft error propagation path is: configuration chip → block memory → operation circuit → input / output module → auxiliary processing refresh chip and host computer;

[0027] Path 3: The third working mode, based on the first working mode, controls the block memory in the core processing chip FPGA to stop working, configures the programmable logic block into DRAM, and studies the impact of DRAM module failure on other FPGA modules and the entire SiP chip. The single-particle soft error propagation path is: configuration chip → DRAM → operation circuit → input / output module → auxiliary processing refresh chip and host computer;

[0028] Path 4: The fourth working mode. Based on the third working mode, the programmable logic block is configured into an FF trigger chain to study the impact of the D trigger module failure on other FPGA modules and the entire SiP chip. The single-particle soft error propagation path is: configuration chip → FF trigger chain → operation circuit → input / output module → auxiliary processing refresh chip and host computer.

[0029] Preferably, in step S5, before performing the irradiation test, single-particle soft errors are respectively injected into the BRAM module, FF trigger chain module and DRAM module inside the core processing chip FPGA by simulation means to obtain the number of errors, error addresses and current changes of each sub-module.

[0030] Preferably, in step S6, the core processing chip FPGA is subjected to single-particle irradiation, and single-particle locking, single-particle functional interruption, single-particle flipping and single-particle soft error fault transmission tests of the FPGA chip inside the SiP device are performed, and the number of single-particle flippings of the programmable logic block, FF trigger, and block memory of the FPGA and the number of single-particle functional interruptions of the UART interface circuit in the four working modes are obtained in turn to obtain the single-particle fault transmission characteristic test results.

[0031] Furthermore, after the SiP device completes the heavy ion test, the single-particle fault transmission characteristic test results are uploaded to the host computer, the impact of different working modes of the core processing chip FPGA under irradiation conditions on the SiP operating conditions is analyzed, and the single-particle cross-section of each sensitive module of the FPGA is calculated to provide a basis for the SiP single-particle ground simulation test.

[0032] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0033] 1. The single-particle fault transmission test method inside the SiP microsystem chip proposed in the present invention can simply and effectively implement the single-particle fault transmission test of the SiP device, rather than the independent test of each component-level chip of the SiP device as in the prior art.

[0034] 2. The method of the present invention analyzes the key nodes and transmission paths of the SiP core processing chip FPGA, and obtains the impact of single-particle failures generated by FPGA in different working modes on the working state of the SiP device, as well as the test data of single-particle flips and single-particle functional interruptions of each sensitive module of the FPGA chip, which saves the time of the irradiation beam machine, avoids repeated experiments, and provides a basis for the subsequent radiation resistance reinforcement of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a flow chart of the internal single particle fault transmission test method of the SiP microsystem chip of the present invention;

[0036] Figure 2 This is a functional block diagram of a SiP chip according to an embodiment of the present invention;

[0037] Figure 3 A CLB configuration circuit diagram of an embodiment of the present invention;

[0038] Figure 4The FF trigger chain configuration circuit diagram of the embodiment of the present invention;

[0039] Figure 5 A DRAM configuration circuit diagram according to an embodiment of the present invention;

[0040] Figure 6 This is a block diagram of a SiP fault transmission path according to an embodiment of the present invention;

[0041] Figure 7 This is a fault injection diagram simulated by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the application is further elaborated in detail below in conjunction with the accompanying drawings. The described embodiments are only a part of the embodiments involved in the present invention. All non-innovative embodiments of other researchers in the field on this embodiment belong to the protection scope of the present invention. At the same time, for the step numbering in the embodiment of the present invention, it is only set for the convenience of explanation, and the order between the steps is not limited in any way. The execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0043] In one embodiment of the present invention, Figure 1 As shown, a method for testing single-particle fault transmission inside a SiP microsystem chip has the following main steps:

[0044] S1. Power on and configure the SiP chip, and assign work tasks to the SiP according to the SiP working characteristics.

[0045] The SiP device selected in this embodiment is composed of a core processing chip FPGA, a configuration chip PROM, a storage chip DDR2 and an auxiliary calculation refresh chip DSP.

[0046] Specifically, the workflow of the SiP device in this embodiment is as follows: Figure 2 As shown in the figure, the SiP device uses two LTM4644s to realize power-on control and monitoring of the operating voltage and current of each component-level chip. During the irradiation process, when a large current is detected (when a single-particle lock is detected), the SiP is automatically powered off to prevent the SiP chip from burning out.

[0047] When the SiP device is working normally, its component-level FPGA chip is at the core position. The core processing chip FPGA can exchange data with the configuration chip, storage chip and auxiliary processing refresh chip, and realize the monitoring of the working current of the FPGA chip.

[0048] Preferably, SiP realizes data interaction between FPGA and PROM through BPI configuration mode, realizes data interaction between FPGA and DSP and external controller through SRIO and EMIF interface; realizes data interaction between FPGA and DDR2 through DDR2 controller; realizes data interaction between FPGA and host computer through UART and GPIO port.

[0049] S2. Analyze the structural characteristics of the core processing chip FPGA of the SiP device and divide the sensitive circuit modules.

[0050] In order to establish a single-particle fault transmission model of the SiP core processing chip within the SiP, it is necessary to analyze the internal structure of the FPGA and divide and combine the internal single-particle sensitive circuits.

[0051] It should be noted that the core processing chip FPGA used in the SiP device of the present invention is an SRAM type structure, and its underlying resources are mainly composed of block memory (BRAM), programmable logic block (CLB), input / output module (I / O Block), operation circuit (adder and multiplier) and digital clock management unit (CMT). CLB is the main logic resource for realizing sequential circuits and combinational circuits. The single particle failure of FPGA mainly occurs in BRAM and CLB. Therefore, the focus of studying FPGA fault transmission is to first study the transmission path of CLB. CLB can be configured as DRAM memory and FF trigger chain, so the core processing chip FPGA is configured into four different working modes, and then its fault transmission characteristics are studied.

[0052] Specifically, the core processing chip FPGA has four working modes: Mode 1 makes all resources such as BRAM, CLB, and computing circuits in the FPGA run; Mode 2 makes the CLB in the FPGA non-working; Mode 3 makes the BRAM non-working and configures the CLB as a DRAM memory; Mode 4 makes the BRAM non-working and configures the CLB as an FF trigger chain.

[0053] First, analyze the internal resources of CLB. The CLB configuration circuit diagram of this embodiment is as follows: Figure 3 As shown, each CLB is connected to a switch matrix (GMR) that can access a general routing matrix, including a pair of slices, which are not directly connected to each other. Each slice is organized into a column, and each slice in the column has an independent carry chain.

[0054] For each CLB, the slice at the bottom of the CLB is labeled SLICE(0), and the slice at the top of the CLB is labeled SLICE(1). Each slice contains four logic function generators (i.e., LUT lookup tables), four storage elements, multi-function multiplexers, and carry logic. All slices perform logic, arithmetic, and ROM function operations through these elements. In addition, some slices support two additional functions: storing data with distributed RAM and shifting data with 32-bit registers.

[0055] Secondly, according to the diversity of Slice functions, CLB is configured into different logic circuits through Verilog programming, including LUT resource chain (including all resources in SliceL and SliceM), FF trigger chain (D trigger in Slice resources) and DRAM memory (only using SliceM).

[0056] The FF trigger chain configuration circuit diagram of this embodiment is as follows Figure 4 As shown, the DRAM configuration circuit diagram is as follows Figure 5 shown.

[0057] Finally, in addition to the CLB module, there are also BRAM storage modules, computing modules and IO port output modules. The functions and logic circuits of the three are single, so there is no need to configure multiple circuits like CLB. It is only necessary to ensure that each module is configured as a sub-circuit that can independently complete the function.

[0058] S3. Analysis of key nodes of sensitive modules of SiP core processing chip FPGA.

[0059] According to the division of the FPGA internal circuit in step S2, it is necessary to set a node single-particle soft error detection function in each sub-module to realize single-particle detection of FPGA sensitive modules, including the internal BRAM nodes, CLB nodes, FF trigger nodes, DRAM nodes of the FPGA and the transmission nodes for data exchange between the FPGA chip and other chips.

[0060] By writing a test program, the input and output ports of each sub-circuit in step S2 are checked for node errors, and error transmission information is recorded.

[0061] S4. Analyze the SiP single particle soft error propagation process.

[0062] After configuring the FPGA internal circuits and key nodes, the FPGA is configured in four different working states to analyze the impact of single-particle failures in each mode on the entire SiP working state. Connect the internal and external nodes of the FPGA to put all SiP component-level chips in working conditions. There are four working modes and transmission paths:

[0063] Mode 1: In this working mode, all resources inside the FPGA need to be used, so it is the most complete test path. SiP fault transmission path diagram, such as Figure 6 As shown, PROM→BRAM→CLB→arithmetic circuit→IO interface→DSP and host computer.

[0064] First, the FPGA reads the configuration data in the PROM through the BPI mode and temporarily stores the data in the BRAM; then, the data in the BRAM is transferred to the CLB and DSP operation modules for simple operation processing;

[0065] Secondly, the calculation results are transmitted to DDR2 through the GPIO interface, to DSP through the EMIF interface, and to the host computer through the UART interface;

[0066] Finally, single-particle errors generated by each node are detected in real time, as well as the impact of errors generated by each resource on the next-level resources and other chips.

[0067] Throughout the entire process, all FPGA resources must be utilized, including BRAM, CLB, DSP computing modules, and IO interfaces, and the resource utilization rate must reach 90%.

[0068] Mode 2: In the transmission path of Mode 1, the CLB link is removed so that the CLB in the FPGA does not work, that is, the impact of BRAM errors on computing resources, interface circuits and other chips is studied. The transmission path is: PROM→BRAM→computing circuit→IO interface→DSP and host computer.

[0069] Mode 3: On the transmission path of Mode 1, the FPGA is in an abnormal working state, the CLB of the FPGA is configured as a DRAM resource, and runs simultaneously with the DSP computing resources, and the impact of errors in the DRAM module of the CLB on the computing module, IO interface and other chips is observed. The transmission path is: PROM→DRAM→computing circuit→IO interface→DSP and host computer.

[0070] Mode 4: Based on Mode 3, the CLB resources of the FPGA are configured as FF trigger chains to observe the impact of single-particle errors of the D triggers on the computing module, IO interface and other chips. The transmission path is: PROM → FF trigger chain → computing circuit → IO interface → DSP and host computer.

[0071] S5. Verify the feasibility of the test system by injecting errors through simulation.

[0072] Before conducting the irradiation test, single-particle soft errors are injected into the BRAM module, FF trigger chain module and DRAM module inside the FPGA through simulation means, and the test system is used to detect the fault transmission results to verify whether the designed test system and test method can meet the test requirements. If the simulation test passes, after the heavy ion test, enter step S6, otherwise return to step S3.

[0073] The single event fault injection diagram of the SiP device in mode 1 operation is shown in the figure below. Figure 7 As shown, single-particle soft errors are injected into the BRAM module, FF trigger chain module and DRAM module inside the FPGA through simulation, and the test system is used to detect the fault transmission results.

[0074] It can be seen from the figure that the test system has captured the number of errors, error addresses and current changes of the BRAM module and DRAM (CLB) module. Because no irradiation was performed, the fault did not cause the entire SiP to be in an abnormal working state during the transmission process, which meets the design requirements.

[0075] S6. Perform irradiation test on the core processing chip of SiP device to verify the feasibility of the test method and analyze the single particle fault transmission characteristics of the SiP core processing chip.

[0076] The single-particle flip-flops of the FPGA's CLB, FF trigger, BRAM and other modules and the single-particle function interruptions of the UART interface circuit were tested in turn in the four working modes. The test results are shown in Table 1:

[0077] Table 1 FPGA fault transmission test results

[0078]

[0079] According to the test results, no single-particle lock occurred in all operating modes; under the same LET value, the single-particle soft errors generated in operating mode 1 were the most and had the greatest impact on the operating status of the SiP. The CLB module inside the FPGA generated the most single-particle errors, while the operation module and the POR circuit did not produce single-particle effects.

[0080] Furthermore, after the SiP device completes the heavy ion test, the test data is uploaded to the host computer, and the impact of different working modes of FPGA under irradiation conditions on the operating conditions of SiP is analyzed based on the test results. Finally, the single particle cross section of each sensitive module of FPGA is calculated, and the cross section is shown in Table 2 below:

[0081] Table 2 FPGA single particle cross section

[0082]

[0083] The results in Table 2 show that: in working mode 1, the single-particle cross-section is the largest, and a large number of single-particle soft errors will be generated inside the FPGA. The single-particle soft errors will cause the SiP to be in an abnormal working state during the propagation process; while the single-particle errors generated by modes 2, 3, and 4 have little impact on the SiP. The SiP will process data according to the fault results of the FPGA and are all in normal working conditions.

[0084] In summary, the single-particle fault transmission test method inside the SiP microsystem chip proposed in the present invention solves the problems of inaccurate ground test of SiP single-particle effects and difficulty in obtaining fault transmission paths and data, and realizes single-particle locking (SEL), single-particle functional interruption (SEFI), and single-particle upset (SEU) tests on the core chip FPGA of the SiP device, as well as fault transmission test of single-particle soft errors of FPGA chips inside the SiP device, providing a basis for SiP single-particle ground simulation tests.

[0085] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for testing single-particle fault transmission inside a SiP microsystem chip, characterized in that: The steps include: Step S1, power on and configure the SiP device to put the SiP device in a normal working state, and monitor the working current of the core processing chip FPGA chip inside the SiP device; Step S2, analyzing the structural characteristics of the core processing chip FPGA, dividing and combining the single-particle sensitive circuit modules inside the SiP device, configuring four working modes of the core processing chip FPGA, and establishing a single-particle fault transmission model of the core processing chip FPGA in the SiP device; Step S3, analyzing the key nodes of the sensitive module of the core processing chip FPGA, and performing single particle detection of the FPGA sensitive module; Step S4, single-particle soft error propagation process analysis, analyzing the impact of single-particle faults generated in each working mode of the core processing chip FPGA on the working state of the entire SiP; Step S5, simulating injection errors, injecting single-particle soft errors into each submodule inside the core processing chip FPGA by means of simulation, and detecting the fault transmission result by using a test system; Step S6, performing single particle irradiation on the core processing chip FPGA to verify the feasibility of the test method, analyzing the single particle fault transmission characteristics of the SiP device core processing chip FPGA, and calculating the single particle cross section of each sensitive module of the FPGA.

2. The method for testing single-particle fault transmission inside a SiP microsystem chip according to claim 1, characterized in that: In step S1, the SiP device includes components: a core processing chip FPGA, a configuration chip, a storage chip and an auxiliary operation refresh chip; When the SiP device is in normal working state, the core processing chip FPGA interacts with the configuration chip through the BPI configuration mode, interacts with the storage chip through the DDR2 controller, interacts with the auxiliary processing refresh chip and the external controller through the SRIO and EMIF interfaces, and interacts with the host computer through the UART and GPIO ports.

3. The method for testing single-particle fault transmission inside a SiP microsystem chip according to claim 1, characterized in that: In step S2, the core processing chip FPGA is an SRAM type structure, and the underlying resources include submodules: block memory, programmable logic block, input / output module, operation circuit and digital clock management unit; The single-particle sensitive circuit module inside the SiP device is divided, and the programmable logic block is configured as a DRAM memory and an FF trigger chain, so that the core processing chip FPGA works in four different working modes: in the first working mode, the block memory, programmable logic block, and operation circuit resources in the FPGA are all in a running state; in the second working mode, the programmable logic block in the FPGA is in a non-working state; in the third working mode, the block memory is in a non-working state, and the programmable logic block is configured as a DRAM memory; in the fourth working mode, the block memory is in a non-working state, and the programmable logic block is configured as an FF trigger chain.

4. The method for testing single-particle fault transmission inside a SiP microsystem chip according to claim 3, characterized in that: In step S2, a single-particle fault transmission model of the core processing chip FPGA in the SiP device is established, including the following sub-steps: Step S2.1, analyzing the internal resources of the programmable logic block, each programmable logic block is connected to a switch matrix, each switch matrix includes a pair of slices, namely SliceL and SliceM, the slices connected to each programmable logic block are organized into a column, and each slice in the column has an independent carry chain; Step S2.2, configuring the programmable logic block into different logic circuits through Verilog programming, including a LUT resource chain, an FF trigger chain and a DRAM memory; the LUT resource chain includes all resources of SliceL and SliceM, the FF trigger chain includes a D trigger in the Slice resource, and the DRAM memory only uses SliceM; Step S2.3, configuring the block memory, the operation circuit and the input / output module so that each module can independently complete the sub-circuit function.

5. The method for testing single-particle fault transmission inside a SiP microsystem chip according to claim 4, characterized in that: The switch matrix is ​​used to access the general wiring matrix. The two slices of each switch matrix are not directly connected to each other. Each slice contains four logic function generators, four storage elements, a multi-function multiplexer and carry logic for logic, arithmetic and ROM function operations. The four logic function generators constitute a LUT lookup table; some slices use distributed RAM to store data and use 32-bit registers for data shifting.

6. The method for testing single-particle fault transmission inside a SiP microsystem chip according to claim 4, characterized in that: In step S3, the key nodes of the sensitive modules of the core processing chip FPGA include: FPGA internal block memory nodes, programmable logic block nodes, FF trigger nodes, DRAM memory nodes, and transmission nodes for data interaction between the FPGA chip and other components; node single particle soft error detection is set at each key node of the sensitive module to perform node error detection and record error transmission information.

7. The method for testing single-particle fault transmission inside a SiP microsystem chip according to claim 4, characterized in that: In step S4, the single-particle soft error propagation path of the core processing chip FPGA in each working mode is as follows: Path 1: In the first working mode, the single-particle soft error propagation path is: configuration chip → block memory → programmable logic block → operation circuit → input / output module → auxiliary processing refresh chip and host computer; The core processing chip FPGA reads the configuration data in the configuration chip through the BPI mode, temporarily stores it in the block memory, transfers the data in the block memory to the programmable logic block and the auxiliary operation refresh chip for operation processing, and transmits the operation result to the storage chip through the GPIO interface, transmits the operation result to the auxiliary operation refresh chip through the EMIF interface, and transmits it to the host computer through the UART interface; Real-time detection of single-particle errors generated by each node, as well as the impact of errors generated by each resource on the next-level resources and other chips; Path 2: The second working mode, based on the first working mode, controls the programmable logic block in the core processing chip FPGA to not work, and studies the impact of the block storage module failure on other FPGA modules and the entire SiP chip. The single-particle soft error propagation path is: configuration chip → block memory → operation circuit → input / output module → auxiliary processing refresh chip and host computer; Path 3: The third working mode, based on the first working mode, controls the block memory in the core processing chip FPGA to stop working, configures the programmable logic block into DRAM, and studies the impact of DRAM module failure on other FPGA modules and the entire SiP chip. The single-particle soft error propagation path is: configuration chip → DRAM → operation circuit → input / output module → auxiliary processing refresh chip and host computer; Path 4: The fourth working mode. Based on the third working mode, the programmable logic block is configured into an FF trigger chain to study the impact of the D trigger module failure on other FPGA modules and the entire SiP chip. The single-particle soft error propagation path is: configuration chip → FF trigger chain → operation circuit → input / output module → auxiliary processing refresh chip and host computer.

8. The method for testing single-particle fault transmission inside a SiP microsystem chip according to claim 7, characterized in that: In step S5, before performing the irradiation test, single-particle soft errors are injected into the BRAM module, FF trigger chain module and DRAM module inside the core processing chip FPGA by simulation means to obtain the number of errors, error addresses and current changes of each sub-module.

9. The method for testing single-particle fault transmission inside a SiP microsystem chip according to claim 8, characterized in that: In step S6, the core processing chip FPGA is subjected to single-particle irradiation, and single-particle locking, single-particle functional interruption, single-particle flipping and single-particle soft error fault transmission tests of the FPGA chip are performed inside the SiP device. The number of single-particle flips of the programmable logic block, FF trigger, and block memory of the FPGA and the number of single-particle functional interruptions of the UART interface circuit in the four working modes are obtained in turn to obtain the single-particle fault transmission characteristic test results.

10. The method for testing single-particle fault transmission inside a SiP microsystem chip according to claim 9, characterized in that: After the SiP device completes the heavy ion test, the single-particle fault transmission characteristic test results are uploaded to the host computer, the impact of different working modes of the core processing chip FPGA on the SiP operating conditions under irradiation conditions is analyzed, and the single-particle cross-section of each sensitive module of the FPGA is calculated to provide a basis for the SiP single-particle ground simulation test.

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