Method for reticle enhancement technology and method for manufacturing semiconductor device

Abstract

In one embodiment, a method for reticle enhancement technology (RET) includes inputting a target wafer pattern that spans an entire design area. The proposed mask for the entire design area is iterated until the proposed mask meets the criteria to produce the target wafer pattern. A method for RET of a lithographic imaging system includes representing a target wafer pattern or a predicted wafer pattern as a smoothing function captured as a function sample array (FSA). A continuous tone mask (CTM) is provided, where the CTM is used to generate the predicted wafer pattern, the predicted wafer pattern spanning the entire design area. The predicted wafer pattern is calculated from the CTM. The method for RET of a lithographic imaging system further includes representing the CTM as a second smoothing function captured as a second function sample array (FSA).

Description

[0001] This application is a divisional application of the invention patent application with application number 201880083241.3 filed on December 12, 2018 and invention name “Modeling of Design in Mask Enhancement Technology”.

[0002] Related Applications

[0003] This application claims the benefit of U.S. Non-Provisional Patent Application No. 15 / 853,311, filed on December 22, 2017, and entitled “MODELING OF A DESIGN INRETICLE ENHANCEMENT TECHNOLOGY”; which is incorporated herein by reference for all purposes. Background Art

[0004] Submicron manufacturing uses photolithography to build layers of material on a substrate to form transistors, diodes, light emitting diodes (LEDs), capacitors, resistors, inductors, sensors, wires, fiber optic cables, micro-electromechanical systems (MEMS), and other elements that together produce a device that performs a function. Substrate lithography is a printing process in which a mask (sometimes called a reticle) is used to transfer a pattern to a substrate to form a device. In the production or manufacture of devices such as integrated circuits or flat panel displays, substrate lithography can be used to manufacture the device. When the device to be formed is an integrated circuit, the substrate is typically a silicon wafer. When forming an integrated circuit, the lithography is semiconductor lithography, and for mass production it is typically substrate lithography. Other substrates may include flat panel displays, liquid crystal panel displays, masks for flat panel displays, nanoimprint masters, or other substrates or even other masks.

[0005] In semiconductor lithography, one or more masks may contain circuit patterns corresponding to individual layers or portions of layers in multiple patterning processes of an integrated circuit. This pattern may be imaged onto specific areas of a substrate that have been coated with a layer of radiation-sensitive material known as a photoresist or resist. Once the patterned layer is transferred, the layer may undergo various other processes such as etching, ion implantation (doping), metallization, oxidation, and polishing. These processes are employed to refine individual layers in a substrate. If several layers are required, the entire process or a variation thereof will be repeated to obtain each new layer. Ultimately, a combination of multiple devices that may be integrated circuits will be presented on the substrate. These devices may then be separated from one another by cutting or sawing, and then may be mounted in individual packages.

[0006] Optical lithography can be 193 nm light with or without immersion, or extreme ultraviolet (EUV) or X-ray lithography, or any other frequency of light or any combination thereof.

[0007] Optical lithography using 193nm light waves works with refractive optics and a transmissive light mask or reticle. The mask blocks, partially blocks, or selectively transmits the light waves onto a substrate that is typically coated with resist during the lithography process to partially expose or expose different portions of the substrate or a material on the substrate. The mask is typically 4 times the magnification of the target substrate size.

[0008] Extreme ultraviolet lithography (EUV) uses light with a wavelength of approximately 13.5 nm with reflective optics.Some implementations use an image-changing mask with 8x magnification in one dimension and 4x magnification in another dimension.

[0009] Generally, smaller wavelengths of light are able to resolve finer geometries, finer spacing between geometries, and higher frequencies (densities) of features on a substrate. Also generally, smaller wavelengths of light are more difficult to reliably generate and control. Economically, it is best to use light of the largest wavelength that can resolve the feature size, spacing, and frequency required for the device. Therefore, it is of interest to enhance the resolution achievable on a substrate using one or more light of any given wavelength.

[0010] For any lithography of a particular resolution, additional techniques such as off-axis illumination, phase-shift masks, and multiple patterning extend the resolution capability. When multiple patterning is used, a single substrate layer is exposed multiple times, each exposure using a different mask called a mask layer.

[0011] The mask is formed by an electron beam (eBeam) machine that shoots electrons at the photoresist coating the surface, which is then processed to produce the desired opening in the mask. The amount of energy delivered to the light spot on the mask is called the dose, and by convention, there may be no energy at a dose set to 0.0 and a nominal dose set to 1.0. When the dose exceeds a certain threshold (usually around 0.5 by convention), the pattern will be recorded. The critical dimension (CD) variation is inversely proportional to the slope of the dose curve at the resist threshold, which is called the edge slope or dose margin, among other terms.

[0012] There are multiple technologies used by eBeam machines. Three common types of charged particle beam lithography are variable shaped beam (VSB), character projection (CP), and multi-beam projection (MBP). The most commonly used system for leading edge mask production is VSB. VSB and CP are subcategories of shaped beam charged particle beam lithography, where the electron beam is shaped by a series of apertures and steered to expose a surface coated with resist. MBP uses multiple charged particle beams, while VSB and CP machines typically have a single beam.

[0013] It is difficult to print features that are similar in size to or smaller than the wavelength of light used for lithography. Various techniques have been applied in industry to address the difficulty of reliably printing the desired shape on the substrate. The field of computational lithography has emerged to use computation to enhance substrate lithography, which is also called wafer lithography in semiconductor lithography. Mask enhancement technology (RET) includes computational methods and systems for designing target mask shapes, which can be used to more accurately and reliably project the desired pattern on the substrate across manufacturing changes. RET typically uses computation to enhance the image on the mask to more accurately and reliably print the desired substrate pattern while being resilient to manufacturing changes. Two common techniques in RET are optical proximity correction (OPC) and inverse lithography (ILT). OPC and ILT are typically iterative optimization algorithms that adjust the parameters defining the mask until the predicted pattern on the wafer is within an acceptable tolerance for a set of conditions or a range of conditions. OPC manipulates the mask geometry and simulates the wafer pattern near the target edge. ILT manipulates the mask transmission into pixels, and ILT typically simulates the entire wafer pattern, a process known as dense simulation. An iterative optimization algorithm typically consists of the following steps: (1) Evaluate proposed solutions to assign a cost to attempt to minimize; (2) Stop if the cost is below a cost criterion; (3) Calculate the gradient of each element of the proposed solution that would result in a lower cost; (4) Adjust the proposed solution based on the calculated gradient; (5) Return to (1). Costs are typically defined as positive values, with zero being the best possible score as assumed here. However, alternative cost definitions may be used.

[0014] RET generally means improving the printability of all desired features under nominal (expected) manufacturing conditions and within expected manufacturing variations around nominal manufacturing conditions. Since manufacturing processes are not perfect, the design needs to be resilient to specific expected manufacturing variations. A larger process window means greater resilience to manufacturing variations, specifically pattern differences throughout defocus and dose variations within acceptable tolerances. The goal of RET is to provide sufficient process windows for as many features as possible. The percentage of chips that function as described after manufacturing is usually referred to as yield. Many factors can affect yield. It is generally believed among those skilled in the art that improving the process window is related to improving yield. Summary of the invention

[0015] In some embodiments, a method for reticle enhancement technology includes: representing a target wafer pattern or a predicted wafer pattern as a smooth function captured as a function sample array (FSA). The FSA is an array of function values, such as real numbers, complex numbers, or a collection of numbers. A continuous tone mask (CTM) is provided, wherein the CTM is used to generate a predicted wafer pattern, the predicted wafer pattern spanning an entire design area.

[0016] In some embodiments, a method for a mask enhancement technique includes: inputting a target wafer pattern, wherein the target wafer pattern spans an entire design area. Dividing the entire design area into a plurality of tiles, each tile having a halo region surrounding the tile. Iterating the proposed mask for the entire design area until the proposed mask meets the criteria for generating the target wafer pattern. Each iteration includes calculating the predicted wafer pattern for a subset of the plurality of tiles, the subset having two to all of the plurality of tiles, wherein the calculation is performed for each tile in the subset and its halo region. Each iteration also includes updating the proposed mask for the tile, wherein all tiles in the subset are calculated before the next iteration.

[0017] The present embodiment also includes a system for RET, wherein the system includes: a computer processor configured to receive a target wafer pattern to be used in a reticle enhancement technique; calculate a function sample array (FSA) of the target wafer pattern, wherein the target wafer pattern is a smooth function; calculate a continuous tone mask (CTM), wherein the CTM is represented as a smooth function captured as the function sample array (FSA); and compare the target wafer pattern to a predicted wafer pattern generated by the CTM. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a block diagram of a chip design that is processed into a wafer as is known in the art.

[0019] Figures 2A-2D An example of expressing a pattern by a smoothing function according to an embodiment of the present disclosure is shown.

[0020] Figure 3 Sampling of a band-limited function and reconstruction of the function from the samples as known in the art is shown.

[0021] Figure 4 is a boundary mismatch ripple as known in the art as an example of the Gibbs phenomenon.

[0022] Figure 5 The application of a Gaussian envelope factor to reduce periodic boundary condition mismatch effects according to an embodiment of the present disclosure is shown.

[0023] Figure 6 The use of a filter with a Gaussian envelope factor to reconstruct a sampled band-limited function is shown. Embodiments of the present disclosure capture a smooth function at the sampling points. Figure 6 Demonstrates the capture and subsequent reconstruction of a smooth function. The reconstruction allows the implementation to compute the value of the smooth function at a finer granularity than the sampling rate.

[0024] Figure 7 is an embodiment of a method according to the present disclosure.

[0025] Figures 8A-8B Applying a filter to a target pattern according to an embodiment of the present disclosure is shown.

[0026] Fig. 9A is an embodiment of a method according to the present disclosure.

[0027] Fig. 9B Provide corresponding to Fig. 9A An example illustration of the steps of a flowchart.

[0028] Fig. 10A is an example of distributed computing for RET as is known in the art, where a design is broken down into tiles, the individual tiles then go through optimization cycles, and then the full design is assembled back together from the tiles.

[0029] Fig. 10B An embodiment of distributed computing for reticle enhancement techniques according to the present disclosure, wherein the entire design is iterated within an optimization loop for a period of time.

[0030] Figures 11A-11B An embodiment of a tile having border regions is shown.

[0031] Fig.12 A 1-D example showing Gaussian localized interpolation on overlapping tiles.

[0032] Fig.13 is a block diagram of an embodiment of a computing hardware system that may be used with embodiments of the present disclosure.

[0033] Fig.14 is a block diagram of another embodiment of a computing hardware system, a computational design platform (CDP), that may be used with embodiments of the present disclosure. DETAILED DESCRIPTION

[0034] In the present disclosure, the use of the term wafer lithography shall generally refer to substrate lithography. That is, the embodiments shall be described with respect to semiconductor lithography as an example to simplify understanding, but the embodiments are also applicable to other types of substrate lithography and overall mask enhancement technology. The term "substrate" in the present disclosure may refer to a mask used in lithography, a silicon wafer, a flat panel display, a liquid panel display, a mask for a flat panel display, a nanoimprint master or other substrate, or other mask.

[0035] Conventional techniques

[0036] Figure 1A conventional semiconductor manufacturing process 100 is shown. The chip design is completed by forming a composite material of wafer layers in step 110. In step 120, some of the wafer layers are separated into mask layers. This step also includes a coloring step sometimes referred to as a coloring step, in which each feature on the wafer layer is colored to reflect the assignment of the feature to a specific mask layer. Once the mask layers are separately identified, each mask layer undergoes a RET step 130. A mask data preparation (MDP) step 140 then prepares data for the mask writer. This step may include "splitting" the data into trapezoids, rectangles, or triangles. Mask process correction (MPC) geometrically modifies the shape and / or assigns a dose to the shape so that the resulting shape on the mask is closer to the desired shape. MPC is sometimes performed in step 130, sometimes in step 140, sometimes in step 150, and sometimes in any combination. Pixel level dose correction (PLDC) may also be applied in step 150. The masks are manufactured and verified in step 150, which includes steps such as mask writing, mask inspection, metrology, mask defect handling, mask repair, and wafer plane inspection of the masks. In step 160, a continuous set of masks manufactured in step 150 are used to write a wafer.

[0037] exist Figure 1 In each of the steps, there may or may not be a verification step to thoroughly verify or sanity check the output of the step. Figure 1 Some of the steps of may be performed in a different order or in parallel. An example of pipelining in a semiconductor manufacturing process is when a design is divided into multiple tiles (e.g., an array of equal-sized tiles), then a first step is performed on a tile, and then a second step is performed on the tile without waiting for other tiles to complete the first step. For example, the RET step 130 and the MDP step 140 may be pipelined to reduce turnaround time. In another example, the MPC of step 140 may be pipelined with the mask fabrication of step 150.

[0038] In wafer lithography, if additional features are added to the mask that are too small to print on their own, it is found that the desired features on the substrate (called the main features) can be printed with greater fidelity and an improved process window, but will still favorably affect the way nearby main features are printed. These additional features are called sub-resolution assist features (SRAFs). The additional features are isolated shapes, not attached to the main features, that are small enough not to be printed on the substrate.

[0039] Calculating SRAF and major feature modifications is highly computationally intensive, and the results are brittle. Unwanted extra patterns may be printed, may not match the target pattern well, and the process window may be unnecessarily restricted. Typical RET methods have OPC verification to identify and correct hot spots. Hot spots are areas that require ideal conditions to print properly, and are therefore not resilient to manufacturing variations, or in some cases will not print properly even under ideal conditions. Hot spots lead to poor yield.

[0040] ILT often generates surprising mask patterns, providing excellent results. The ILT algorithm naturally forms curved shapes that include many SRAFs. For variable shaped beam (VSB) mask writing machines using conventional fracturing, these patterns have proven to be impractical because there are too many geometries to handle. The number of mask writes is a key business factor, and VSB writes are proportional to the number of VSB shots that need to be printed. Therefore, the ILT algorithm spends a considerable amount of running time to convert the curved shape into an approximation that is more suitable for VSB writing (commonly known as Manhattanization). Model-based mask data preparation using overlapping shots can significantly reduce the impact of writing time. However, the curved shape still takes longer to write. The recently introduced multi-beam electron beam mask writing system writes the curved shape directly on the mask without spending any additional time. This enables ILT to output the curved shape without Manhattanization. The problem that ILT still has is the huge computational demand for intensive simulation of the full mask layer of the full design (especially the full mask size design), and for semiconductor manufacturing, the wafer size of the full mask size design is typically about 3.0cm×2.5cm.

[0041] Multi-beam writing eliminates the need for Manhattan-shaped curve shapes for VSB writing. However, mask printability and resilience to manufacturing variations remain important considerations for mask shapes output by ILT. For example, shapes that are too small or too close to each other, or have sharp turns in the contours of the shapes, make it difficult to manufacture the mask reliably, especially across manufacturing variations.

[0042] The energy delivered by electrons from an eBeam machine is often approximated as a point spread function (PSF). While there are many effects that affect how the energy spreads, a monotonically continuous PSF is a reasonable representation of the energy distribution in eBeam-based masks that facilitate variable shaped beams or facilitate multi-beam writing. In this disclosure, for ease of understanding, a simple single Gaussian distribution will be used as the PSF, but the embodiments are applicable to any suitable PSF.

[0043] When energy is delivered in a unit dose across a sufficiently large area with a Gaussian distribution, there is enough dose inside the area to reach the unit dose. However, if the area is smaller, the highest dose inside the area will not reach the unit dose. Similarly, if the interval between the areas is large enough, the minimum dose will reach zero. However, if the interval is smaller, the minimum dose will not reach zero. When either the area or the interval between the areas is smaller, the dose distribution is shallower. The mask manufacturing process is designed to provide sufficient dose margin for reasonable areas and intervals, such as a 100nm line separated by a 100nm space, where the unit dose is for a typical front edge for 193i lithography. Smaller areas and intervals have lower dose margins at the contour edges of the area. If the applied dose is a unit dose, the smaller the area, the worse the dose margin.

[0044] Dose margins also deteriorate for typical mask writing processes due to proximity effect correction (PEC). Whether it is VSB, CP or MBP, mask writing with eBeam has a backscattering effect that is well known in the art. Electrons hit the resist surface, and the secondary electrons released by the electrons bounce around to expose the resist in the 10-micron scale area around the exposed position. This has a scattering effect, a long-range effect, and thereby partially exposes the resist in the surrounding 10-micron scale area. The collection of these local exposures from all exposures around a given area is significant enough to require correction. Software-based corrections for backscatter and other long-range effects are called PEC, and are usually applied in concert with the mask writer when writing the mask. PEC essentially reduces the unit dose of the emission (or pixel in terms of MBP) to compensate for the collective pre-injection from the surrounding emission (or pixel). With the PEC in the machine turned on, almost all production masks are written. When the dose density in the 10-micron scale area is high, the amount of PEC applied is also high. This has the effect of reducing the height of the exposed Gaussian (or PSF), and therefore reduces the dose margin at the edges of the contours in the dense areas. Thus, a small shape written in a high dose density area has a worse dose margin than a shape of the same size written in a low dose density area.

[0045] The reason dose margin is important is because a flatter slope means a given percentage dose change results in a larger CD difference. Since dose margin is known to those skilled in the art to be a good proxy for various, if not most, sources of manufacturing variation, measuring CD variation against dose variation is an important measure of resilience to manufacturing variation.

[0046] Mask process corrections, which may be performed off-line, in-line, or with a mask writer, may manipulate the shape or dose applied to the mask in order to correct linearity and enhance critical dimension uniformity (CDU) and line edge roughness (LER), in addition to measures of resilience to manufacturing variations. Improving CDU and LER includes enhancing dose margin, and improving the uniformity of dose margin across features in a mask. Enhancements to dose margin (edge ​​slope) are disclosed in U.S. Patent 8,473,875, entitled "Method and System for Forming High Accuracy Patterns Using Charged Particle Beam Lithography," owned by the assignee of the present application. For masks to be written with a VSB or CP writer, reducing CD splitting also improves CDU. CD splitting is the condition when more than one shot is used to define the opposing edges of a critical dimension feature. An example of CD splitting is disclosed in U.S. Patent 8,745,549, entitled "Method and System for Forming High Precision Patterns Using Charged Particle Beam Lithography," which is owned by the assignee of the present application.

[0047] In a typical semiconductor manufacturing process, Figure 1 The RET of step 130 in produces the target mask shape. When the mask representation does not automatically satisfy all the desired mask constraints and characteristics (such as allowed transmission values, minimum feature size, minimum spacing, or sufficient dose margin, etc.), the evaluation of the suitability of the mask requires the introduction of terms that increase the costs associated with violating these constraints. In the field of inverse problems, the introduction of these terms is called regularization, and is a method of selecting solutions that equally or similarly fit the desired result well from a possible infinite set of solutions but also have other a priori desirable properties. An example of inverse modeling for a mask is Fourier-ILT as disclosed in U.S. Patent No. 7,856,612, entitled "Lithography Mask Design Through Mask Functional Optimization and Spatial Frequency Analysis", which is owned by the assignee of the present disclosure and is incorporated herein by reference. Some aspects of the present disclosure are based on Fourier-ILT and other RET systems and methods.

[0048] Semiconductor manufacturing and submicron manufacturing in general follow Moore's Law, which predicts that manufacturing infrastructure will evolve together to allow resolution to improve at a relatively predictable and stable rate over time. An important aspect of Moore's Law is that the computing power of the infrastructure is proportional to Moore's Law, because effects such as computing bandwidth, computing speed, memory capacity, memory access speed, communication bandwidth, communication speed, long-term storage (whether solid state or hard disk) capabilities and speed relative to power consumption and cost are also proportional to Moore's Law. The introduction of new manufacturing technologies (such as EUV lithography or MBP-based mask writing) will create discontinuities in computing requirements. The introduction of new computing technologies such as graphics processing unit (GPU) acceleration will also create discontinuities in computing power and scalability.

[0049] In terms of design complexity, computational algorithms are generally worse than linear algorithms. This means that the time spent on calculating a tile with 1000 elements will be more than twice the amount of computation required for a tile with 500 elements. Depending on the size of the tile with 1000 elements that takes longer to calculate, it may be faster to divide the tile into two tiles of 500 elements and then splice them back together to form a tile of 1000 elements. Depending on the interaction between the computational task and the tiles, the division and splicing may have complexity. There is a complex trade-off to determine the correct tile size for the most efficient calculation. This effect is exacerbated when the amount of memory required to store sufficient information for the design far exceeds the amount of memory available on an economically feasible computing system. In data processing for chip design or chip manufacturing or generally any device design or sub-micron device manufacturing, full chip design or more generally full-scale devices, most computational steps need to be divided into much smaller tiles. This is because the amount of data and computing power that need to be calculated are proportional to Moore's Law. The results are then stitched back together for use by the next step of processing and for error and data reporting. This is called tile-based calculations. Tiles are typically rectangular, but can be hexagonal or a mix of different shapes and / or sizes. Predicting the wafer pattern in a tile requires including the data surrounding the tile. The surrounding data is called a halo. The halo must be large enough to capture significant effects on the predicted pattern of the tile.

[0050] All conventional computer-aided design (CAD) algorithms for the design or manufacture of devices use tile-based computations. In addition, when iterative optimization algorithms are deployed (usually in NP-complete problems), tile-based computations cause each tile to iterate the optimization loop separately. Tile-based systems cause halo zone data to become stale due to changes made by the optimization process in adjacent tiles. The more optimization iterations in a tile, the more its adjacent tile halos become outdated. When it becomes untenable to resolve data at the boundaries of the tile, a splicing problem occurs. Tiles are usually calculated in a situation where the output will only change the interior of the tile, but the effects of its adjacent objects projected on the tile are seen while calculating, as seen in the halo.

[0051] Details of this embodiment

[0052] Some embodiments of the present disclosure produce continuous tone masks ("CTMs") for large sections of a mask including an entire mask layer at one time. For masks for 193i projection of semiconductor wafers, systems and methods known in the art on today's computing platforms do not allow CTMs with wafer sizes greater than 400-1000 square microns in area to be produced at one time. CTMs of tiles are produced, where each tile and its halo undergo an optimization cycle independently and are then stitched together to form the entire mask layer, requiring additional processing to deal with stitching artifacts. In contrast, some embodiments of the present disclosure enable the production of an entire mask layer with a wafer size of 7.5 square centimeters in area together in one large optimization cycle. The CTM captures the values ​​of a continuously varying amplitude transmission coefficient map, from which the transmitted intensity can be calculated. The present disclosure describes methods and systems for avoiding stitching problems in a correctly constructed manner by iteratively optimizing the entire large section rather than independently iteratively optimizing the tiles of the large section, as known in the art. The large section can be, for example, 5 microns by 5 microns. In embodiments where the large section is the entire mask, the entire mask avoids stitching problems.

[0053] In some embodiments, techniques are applied to identify tiles that do not need to be refined in subsequent iterations until otherwise determined. In these cases, many of the tiles remain unchanged when iterating over the entire proposed mask. These techniques can significantly improve computational performance.

[0054] In some embodiments, by refreshing the halo on each optimization iteration, a smaller halo zone is utilized than is known in the art. Due to inconsistent optimization in adjacent tiles, the prior art requires multiplying the halo width by as many iterations as is likely to occur or suffer stitching errors. Additionally, in some embodiments, larger tile sizes can be achieved by one or two orders of magnitude in area compared to conventional methods and systems. Increasing the tile size reduces the percentage of processed area from the halo zone. The combination of smaller halo width and larger tile size reduces the amount of memory and processing overhead that the halo zone adds to the tile when processing and storing the tile.

[0055] Some embodiments additionally utilize novel, more efficient data representations of CTMs and target wafer patterns. In these embodiments, the sparsity of the grid points is 4 or 5 times that of existing metrics, and the data stored at each data point is minimal, but the representation is accurate within the precision of the optical system being modeled. Taken together, in some embodiments, the CTM and target wafer pattern of the entire mask layer for optical (193i) projection of wafer lithography can be stored in the combined memory of all computing nodes of a current commercially viable computing platform. When EUV lithography requires ILT, then similar commercially viable computing platforms can store the entire mask layer for EUV projection. ILT for EUV requires higher precision, and therefore more memory is required to represent the data. In the present disclosure, for ease of understanding, the discussion uses the 193i mask scenario, where the entire mask layer is stored in the collective memory of the computing platform and iteratively optimized together. Even if the collective memory is not sufficient to store the entire mask layer, the present disclosure is also applicable to processing large sections of the entire mask layer. In these embodiments, the CTMs and target wafer patterns for all tiles of the entire mask layer can remain resident in memory throughout processing the entire mask layer. This avoids time-consuming non-resident memory accesses (whether solid state drives or hard disk drives), thereby enabling rapid updates of halo regions among compute nodes. The memory required to hold large segments is easily calculated as [(X size / grid spacing)*(Y size / grid spacing)*(data size at each grid point). In some embodiments, intermediate results are only held in memory for the duration of the computation within a tile.

[0056] Having the CTM and target wafer function sample arrays for all tiles of the entire mask layer in memory at all times also enables the present embodiment to compute optimization iterations for the entire mask layer at once, rather than optimizing each tile independently of each other as is done in the art. Thus, the present embodiment eliminates the stitching problem in a right-by-construction manner and uses commercially viable computing platforms to efficiently compute CTMs for large sections that include the entire mask layer.

[0057] In some embodiments, certain mask process corrections or enhanced resilience to mask manufacturing variations are performed during RET, where the mask is used in a photolithography process to form a pattern on a wafer.

[0058] In some embodiments, sample values ​​of a smoothing function on a grid are captured in an array, the smoothing function being a continuous differentiable function. In some embodiments, the degree of match of a predicted wafer pattern to a target wafer pattern is represented as a smoothing function. This technique eliminates the need to find contour edges on the predicted wafer pattern and then compare them to contour edges on the target wafer pattern, which is done in most existing ILT implementations.

[0059] In some embodiments, the process may allow the ILT process to proceed until a point where the number of regions remaining that require further optimization is sufficiently small, and the tiles containing such regions are statistically likely to be large enough so that the optimization will not affect those regions within the tile that are adjacent to the halo regions. With the understanding that such regions are present throughout the design, re-blocking of the design at this stage may select tile sizes and regions that include potential non-rectangular regions or even curved boundaries and corresponding halo regions along the perimeter.

[0060] In some embodiments, there may be iterations among different optimization strategies, for example, where the entire design is optimized all together with one strategy, and where tiles are optimized independently of each other with another strategy. Strategies may be preset, such as optimizing the entire design to achieve a preset number of optimization iterations, then optimizing the tiles until each tile meets a "cost criterion" (which may hit the maximum number of iterations allowed, or meet a certain quality criterion, or fail to improve the quality criterion sufficiently), and then iterating the overall design again to achieve another preset number of iterations. In another example, the strategy may be adapted to observe the state of the mask design and a certain set of criteria for the global and local optimization progress, including the rate of change, and utilize the rate of change of the optimization criteria of the various strategies as the ILT process continues with different parameters and potentially different tiles deployed.

[0061] Function Sample Array

[0062] The goal of RET is to form a mask so that the energy in the substrate is below the threshold in any case where the substrate is assumed to be transparent (or dark in a negative resist), above the threshold in any case where the substrate is assumed to be dark (or transparent in a negative resist), and crosses the threshold transition at the desired position. In some embodiments, a smooth function is used to represent transparent areas, dark areas, and transition positions. The smooth function is continuous and differentiable. The smooth function is captured on a sufficiently fine grid to define the function within a tolerance. In the present disclosure, an array representing the value of a smooth function shall be referred to as a function sample array (FSA), which is an array of real or possibly complex values ​​of the underlying function at the sampling position. In some embodiments, the smooth function is implemented as a band-limited function, which is essentially infinitely differentiable. In contrast to the theoretically infinite number of components, a band-limited function is a function that contains only frequency components within a fixed limit. The nature of the band-limited function determines the sampling rate (grid spacing). The present embodiment uniquely recognizes that the light emitted from the mask and the energy absorbed by the substrate are naturally represented by a smooth function. The target wafer pattern, the predicted wafer pattern, and the CTM are modeled as FSAs.

[0063] Utilizing knowledge of optical lithography allows the selection of smoothing functions so that accurate functions can be defined on much coarser grids than those used for existing RET methods. The lithographic imaging resolution is based on the wavelength and numerical aperture of the lithographic imaging system. In this embodiment, the FSA grid has a plurality of grid points, and the grid points are separated by a grid pitch. The grid pitch can be set by selecting a transition distance that is less than the lithographic imaging resolution of the lithographic imaging system, and dividing the transition distance by a value such as 3 to 6; or it can be set based on a predefined edge layout error description. The determining factor of the divisor is the accuracy required when determining where the function crosses the threshold. The key to these embodiments is that the smoothing function is accurately captured by its value at the grid point. This means that the predicted mask pattern grid points can be directly compared to the target mask pattern grid points without calculating the exact position of the mask pattern contour. The ability to accurately represent the pattern with a limited number of samples enables large tiles to be calculated with less memory and higher speed than conventional methods. This enables fast, accurate and distributed calculation of differentiable cost functions that measure the degree of shape matching (which can be, for example, GPU-based).

[0064] Figure 2A A smooth function of (x, y) represented on a grid is shown. The edge of the pattern of such a function f(x, y) occurs where it crosses a threshold shown as plane 230. This plane 230 can be visualized as a level profile z=constant of the surface defined by z=f(x, y). Figure 2AA typical smoothing function 200 and the intersection of the function with a plane 230 are shown. Grid point locations 220 are locations where grid lines 210 intersect each other. In this example, where 0.5 is the shape contour level of plane 230, the smoothing function 200 has values ​​≥ 0.5 inside the target shape and values ​​< 0.5 outside the target shape. This three-dimensional plot shows the smoothing function as a function of height in the z direction, where the height represents the sampled value at the grid point 220. The collection of values ​​at the grid points of the smoothing function 200 can be captured in a function sample array (FSA). Figure 2B The 2-D graph 235 shows y-plane slices cut along grid lines across the L-shaped pattern. The grid spacing 237 is selected so that there are multiple grid points on the transition 239 of the function from z=0 to z=1. The multiple grid points ensure that the position of the function transition across the threshold is within tolerance.

[0065] Figure 2A and Figure 2B The smooth functions demonstrated in can be used to represent the target pattern and the predicted pattern. In some embodiments, due to the smooth nature of the target pattern function and the predicted pattern function, the cost and cost derivatives can be calculated analytically.

[0066] For all stages from CTM to target pattern FSA, the present embodiment forms a grid based on the physics of the lithography imaging system and is able to reliably resample to a finer grid. Because of this, the present embodiment can work on a large area with a single compute node. In addition, the present embodiment decomposes the calculation of extremely large areas, such as the entire mask layer for a 193i mask, into tiles without stitching artifacts. These possibilities are not obvious to the mask enhancement technology industry because there are multiple stumbling blocks to be solved, such as accurate grid-based pattern representation without ultra-fine grids, and reliable interpolation to finer grids on the fly. For example, instead of using a 1-4nm sampling grid for RET of 193i lithography as is typical in the prior art, in the present embodiment, a sampling grid with a scale of 10nm can be used. This amplification of grid sampling saves 5 to 100 times or more in terms of required memory.

[0067] Generates the FSA of the target wafer pattern from the input target geometry. Figure 2C A sample target geometry 240 is shown in three dimensions as it would appear if all entries within the shape had a value of 1 and all entries outside the shape had a value of 0. Since such a representation is not achievable, the present embodiment applies a low pass filter such as a Gaussian blur to the geometry to generate Figure 2D A smooth function 250. For example, by Figure 2D The smoothing function 250 obtains a pattern 260 with Figure 2CThe target geometry 240 is compared to the pattern 260 which is still accurately captured.

[0068] The FSA of the predicted wafer pattern is generated from the CTM using the lithography system model. The predicted wafer pattern FSA is tampered with to have characteristics similar to the target pattern FSA, such as values ​​near 1 inside the shape, values ​​near 0 outside the shape, and smooth transitions between these areas. This tampering prevents the value 0.15 in the predicted pattern from not matching the value 0.0 in the target pattern in the transparent (or dark under negative resist) area. The only critical value is the position where the function crosses the threshold transition. Therefore, when the values ​​at the grid points of the predicted wafer pattern FSA match the values ​​of the target wafer pattern FSA, the mask will accurately form the desired pattern on the substrate. The smooth function representation in the FSA supports the optimized value without having any clear understanding of the edge positions in the target mask pattern.

[0069] Use of Fast Fourier Transform

[0070] The present embodiment is independent of U.S. Pat. No. 7,856,612 based on the following insight: The physics of lithographic imaging systems is highly amenable to a two-dimensional Fourier (plane wave) basis to represent all quantities, thus making the use of the Fast Fourier Transform (FFT) method computationally efficient. There is great value in exploiting the machinery of linear vector space, and the present method exploits this advantage by representing the CTM as a linear combination of a set of fully orthogonal basis functions. The physics of lithographic imaging is particularly well suited to a 2-D Fourier basis, since only components with spatial frequencies f ≤ fcutoff (where fcutoff is the system resolution cutoff) will contribute to the projected image. The cutoff depends on the details of the illumination and projection optics, but for partially coherent imaging using quasi-monochromatic light of wavelength λ and imaging systems using numerical aperture NA, typically fcutoff ≤ 2NA / λ.

[0071] The two main benefits of using a Fourier basis set are that the convolutions required to compute the image are now simple multiplications in Fourier space, and efficient FFT implementations are commonly available. The most computationally intensive optimization work can be performed with low-frequency mask components just within the lithography imaging cutoff. Further inspired by the lithography imaging cutoff, some embodiments of the present Fourier-based method find an optimal mask function that is band-limited to fcutoff captured in a CTM. Once the optimal mask function is found, a manufacturable physical mask can be produced in a separate process using the CTM.

[0072] In some embodiments, efficiency is gained by avoiding excessive oversampling of the grid used to represent the band-limited mask function, which is then interpolated to a finer grid as needed to compute the pattern and cost density. A background review of discrete sampling of band-limited functions and their reconstruction from these samples should first be presented.

[0073] like Figure 3 As shown in (a), consider the band-limited function h(x) and its Fourier transform The double-ended arrows in the figure indicate that the left and right plots are Fourier transform pairs. The former function is sampled by multiplying it with the sampling function Δ(x), which is a series of Dirac delta functions separated by "l", such as Figure 3 (b) is shown. The sampling function and its transformation are Figure 3 (c) is shown. Since the convolved images do not overlap, there is no aliasing in this example, which is the condition for establishing the Nyquist criterion. Now the reconstruction of h(x) from samples of the band-limited function is shown. Figure 3 (d) Multiply the spectrum by an ideal low-pass filter Π(f) to remove all but the baseband spectrum by filtering out higher-order convolution images. This corresponds to convolving the sampled function with sinc(x / l). Figure 3 (e) The result shown matches Figure 3 (a) The initial function.

[0074] The FFT works directly with sample values, but computes the data as periodic outside the interval of the data being analyzed. There is a class of functions for which the FFT and the continuous Fourier transform are identical (within possible proportionality constants) and for which the reconstruction of intermediate values ​​will therefore be exact. In this class of functions, the function h(x) must be periodic, h(x) must be band-limited, the sampling rate must be at least twice the largest frequency component of h(x), and the data interval must be an integer of the period of h(x). The last requirement amounts to the absence of mismatches due to the imposition of periodic boundary conditions (PBC).

[0075] The value mismatch from an imposed PBC is a jump in value from one side of a boundary to the other. There is ringing in the reconstructed function near these boundaries that is equivalent to the Gibbs phenomenon of a step discontinuity. Any mismatch with the PBC will behave exactly like a step discontinuity at the midpoint between the sampling points. Figure 4 A graphical representation is provided showing samples and the results of Fourier interpolation around a sudden jump in the sample values ​​of a square wave pulse. The smooth curve is a band-limited periodic (over the full interval) function consistent with the samples and shows the ringing characteristic of the Gibbs phenomenon.

[0076] To reduce ringing, some implementations utilize envelope factors to localize the Fourier interpolation kernel. This article will describe Gaussian envelope factors, but other factors may also be used. In addition, other interpolation methods such as spline functions, polynomial functions, rational functions, etc. may be used instead of Fourier interpolation. The Gaussian envelope factor exp(-x2 / s 2 ) is applied to the regular sinc(x) kernel to localize the Fourier interpolation kernel, which smoothly and strongly limits its range. Essentially, this is Figure 3 (d) to Figure 5 The modification of the Fourier transform pair shown, where in this embodiment the width parameter has been set to s=4. This width provides a trade-off between interpolation accuracy and the increased halo thickness (i.e., added to the boundary layer of the tile, as shall be described in a later section) required to give a fully converged result. In frequency space, the width adjusts the width of the roll-off of the error function of the low-pass filter. In order to accurately reconstruct the highest frequency components, the function can be band-limited to the monotonic top of the filter. Using this method, the approximation is consistent in that the same range of samples is used for interpolation everywhere, and the values ​​at the original sample points are preserved.

[0077] Figure 6 The operations performed in the present method for reconstructing a function using Gaussian localized interpolation are graphically illustrated. Figure 6 Similar to Figure 3 , except for step (d). Therefore, Figure 3 (a) Figure 3 (b) Figure 3 (c) and Figure 3 The description in (e) applies to Figure 6 (a) Figure 6 (b) Figure 6 (c) and Figure 6 (e) In step (d), the low-pass filter is lpf(x)=exp(-x 2 / s 2 )sinc(x) and in frequency space That is, the method involves a Gaussian localized interpolation Fourier transform pair.

[0078] Figure 7 700 is an exemplary flow chart of a method for a reticle enhancement technique in which a smoothing function is captured in an FSA and used for a target pattern and for a mask to be used to generate a target pattern (e.g., a target wafer pattern). For example, flow chart 700 describes a method for representing a target wafer pattern or a predicted wafer pattern as a smoothing function captured as an FSA, where the FSA is an array of function values, which may be real numbers, complex numbers, or a collection of numbers. In step 710, a target pattern to be used in a reticle enhancement technique is input, such as pattern 711. Target pattern 711 may include, for example, Figure 7 The design shown may be a plurality of patterns (eg, individual rectangular and square patterns in target pattern 711), such as an entire mask layer of a semiconductor chip, or may be a single pattern to be written onto a surface, such as Figure 2C The individual L-shaped patterns shown. Figure 7 In step 720, a target pattern FSA of the target pattern is calculated. In some embodiments, generating the target pattern FSA in step 720 may include applying a low pass filter to the target pattern. The target pattern function is Figure 7 , where function 721 is slightly blurred compared to target pattern 711. Target pattern function 721 is band-limited to the bandwidth of the low-pass filter and is sampled on a pattern grid having a first sampling rate, which may be at least twice the bandwidth of the low-pass filter. The low-pass filter bandwidth may be set to maintain edge position and allow rounding of corners consistent with lithography system characteristics or specifications provided with the target pattern.

[0079] In step 730, a CTM 731 is calculated. The CTM 731 may be initialized using a first guess, such as a constant value, a low pass filter applied to the target pattern, a previously determined CTM (e.g., a preliminary result of a previous calculation), or a low pass filtered mask obtained by other means (e.g., when solving for hot spots in an existing mask design or examining a solution provided by another system).

[0080] In step 740, a predicted pattern FSA (representing the predicted wafer pattern) is calculated from the CTM and the system model.

[0081] In step 750, the target pattern FSA is compared to the predicted pattern FSA calculated for the CTM. The comparison of the target pattern FSA and the predicted pattern FSA uses grid points of the pattern grid. The comparison may include calculating a cost density function using the target pattern function and the predicted pattern function. The predicted pattern function (FSA) may be generated using the CTM, a lithography imaging system model, and a resist process model.

[0082] Figures 8A-8B Details are provided on the smoothing function for generating the FSA (such as the target mask pattern) of the present embodiment. For simplicity, the figure is shown in 1-D, where the x-axis represents the spatial position and the y-axis represents the value of the smoothing function. The smoothing function is generated by convolution with a low-pass filter, which can also be described as applying a blur. Fig. 8AThere are three curves showing a smoothed target pattern representation. Curve 810 is the ideal target pattern, which in this example has edges at spatial locations x=+0.5 and -0.5. Curve 820 is the result after applying a Gaussian blur of (1 / e) width w=1 / 10 to curve 810, and curve 830 is the result after blurring curve 810 with a wider Gaussian of (1 / e) width=1 / 3. It should be noted that all curves 810, 820 and 830 intersect at the ideal edge location of y-value 0.5, which is a result of arbitrarily choosing a value of 1 for y-values ​​indicated within the shape and 0 for y-values ​​outside the shape in this exemplary embodiment. Barring any other considerations, the geometric target shape can therefore be represented as the outline of a smooth curve with a y-value of 0.5. Gaussian blur means that the curve is effectively limited in spatial frequency; in fact, the blur multiplies the spectrum by the Gaussian 1 / e width (1 / πw), in units of frequency. The 20 dB attenuation criterion that defines the Gaussian filter bandwidth corresponds to almost perfectly capturing the smooth curves 820 and 830 using 3 to 4 sampling points with a smooth edge transition from approximately 0 to approximately 1.

[0083] Figure 8B The plot of 820 shows how the pattern is preserved with the smoothest representation (blur width 1 / 3) but then the y values ​​of the blur curve are sharpened to a degree very similar to blur width 1 / 10 (curve 820) by running it through a soft thresholding function. The result is curve 832, which looks almost exactly like Fig. 8A The result of the narrower blur of curve 820 is the same as that of the sharper blur of curve 820 and is monotonic at full value away from the edge. This facilitates comparison without the explicit pursuit of contours used by conventional methods. Using this blurring technique, the present method can take the difference between two curves that are stylistically similar to the blurred 1 / 10 curve (curve 820) or the sharpened blurred 1 / 3 curve (curve 832) to examine the degree of mismatch between the two patterns.

[0084] Optimizing CTM

[0085] The present embodiment utilizes an optimization technique that iterates the proposed solution until the desired result is achieved. The proposed solution is captured as a CTM. A measure of desirability is determined by comparing the FSA of the predicted pattern and the target design pattern. Comparison of the FSA involves comparing values ​​at equivalent grid points representing the two functions, possibly within a certain tolerance. The goal of the described process is to reduce the cost as close to zero as possible. Other techniques may converge using different cost indicators.

[0086] Fig. 9Ais an exemplary flow chart 900 of a method for reticle enhancement technology, wherein FSA is used for all steps involving generating a mask of a target pattern on a wafer. In step 910, a substrate lithography system model such as that used for wafer lithography is input. The substrate lithography system model includes one or more of an optical model, an EUV model or other lithography system model, a resist process model, and any other model required to predict the printed pattern on the substrate resulting from the mask. The models included in the substrate lithography system model may be complex, physically accurate models, simpler empirical models, or any other level of models according to specifications, including null models that remove most or all of their effects on the final result. The substrate imaging system model may include parameters such as wavelength, illumination pattern, numerical aperture, refractive index, etc.

[0087] Step 920 includes inputting a target pattern to be formed on the substrate using a substrate lithography process, the target pattern being within the design area. In some embodiments, the target pattern includes multiple patterns on a wafer, and the design area includes a large section of a mask layer of a semiconductor chip, such as the entire mask layer. In step 920, in some embodiments of the present disclosure, specific geometric manipulations of the target pattern may be performed. For example, edge biases that take into account etching effects during processing of the substrate may be pre-calculated prior to the optimization steps in step 930 and subsequent steps.

[0088] In step 930, a target pattern FSA of a target pattern, such as a target wafer pattern, is calculated. In some embodiments, calculation of the target pattern function includes applying a low pass filter (also referred to as blurring) to the target pattern, such as with respect to Fig. 8A The low pass filter may for example be a Gaussian or any other filter that is well localized in space and frequency.

[0089] In step 940, as described in relation to Figure 7 As explained in step 730 of , the CTM (ie, the proposed mask) is calculated.

[0090] In step 950, the predicted pattern FSA that will be produced by the CTM on the substrate is calculated using the substrate lithography system model. In some embodiments, the calculation of the predicted pattern FSA (e.g., the predicted resist pattern function) may include calculating the projected image function from the CTM using the substrate imaging system model. Next, the projected mask image FSA and the resist process model are used to calculate the predicted pattern FSA produced by the projected image function. The calculation of the projected image function may be transferred to a finer grid using localized Fourier interpolation as required by the calculation method or subsequent use of the projected image.

[0091] In step 960, the cost is calculated using the target mask pattern FSA and the predicted mask pattern FSA, and the function derivative of the cost with respect to the CTM is also calculated. The cost may be, for example, a total cost. The cost may be represented by a smooth function. In some embodiments, the cost may be global cost data, which may include, for example, local partial costs, cost density, and cost gradients. In some embodiments, the calculation of the function derivative takes into account the adjacent pattern information in the boundary region surrounding the design region. In some implementations, the calculation of the cost includes: calculating the cost density function using the target pattern function and the predicted resist pattern function; and integrating the cost density function over the design region. The calculation of the cost density function may include the square difference between the target pattern function and the predicted resist pattern function, the absolute value of these differences, or any formula that produces positive values, which tend to zero when the patterns match and tend to larger numbers when the patterns do not match. These cost density values ​​may also be weighted according to other information provided with or derived from the target pattern. For example, weights may be used to emphasize fitting edges and de-emphasize matching corners.

[0092] In step 970, the cost and the function derivative are compared to a cost criterion. In other words, this comparison determines the mismatch between the predicted pattern and the desired pattern. The cost criterion may include converging the cost to a value near a minimum, or minimizing the magnitude of the function derivative or its components. That is, the cost criterion may be considered to be satisfied when the change between further iterations and the previous solution does not exceed a specific amount. In some embodiments, the cost criterion may include evaluating the distribution of the value of the cost density function over the design area. The cost criterion may also be defined as the amount of mismatch, for example, specifying an acceptable amount, such as a geometric value or a percentage.

[0093] It should be noted that in flow chart 900, variations are possible. For example, steps 910 and 920 may be interchanged sequentially. In some embodiments of the present disclosure, step 930 may be a null step. Steps 940 and 950 may be combined into one step. In steps 960 and 970, calculating derivatives is optional. Other calculations may be performed in steps 960 and 970 to help iterate the CTM.

[0094] In some methods, by applying a soft thresholding function to the target pattern function in step 935 to sharpen the edges of the target pattern function, a target pattern function with more distinct edges can be generated before calculating the cost of step 960. This thresholding is Figure 8BSoft thresholding converts the encoded pattern into higher resolution functions that are indistinguishable from edge transitions, thus giving more weight to contours without directly determining them. This allows the target pattern function to be stored at a lower grid resolution than when used for comparison. After any applied sharpening and predicted resist pattern function, the target pattern FSA is used to calculate a cost, such as a total cost, in step 960.

[0095] In an example of thresholding the target pattern FSA, the target pattern FSA in step 930 is generated by applying a low pass filter to the target pattern so that the target pattern function is band limited to the bandwidth of the low pass filter. The target pattern function is sampled on a first pattern grid having a first sampling rate that may be equal to or higher than the Nyquist rate of the bandwidth, and the thresholded target pattern function generated in step 935 is sampled on a second pattern grid having a second sampling rate that is higher than the first sampling rate. The soft thresholding function may be, for example, an S-shaped function that sharpens the transition between a minimum and a maximum in the target pattern. For example, the slope of the thresholded target pattern function may increase at the transition between a minimum and a maximum in the target pattern, thereby sharpening the edge of the target pattern function.

[0096] Soft thresholding enables the function to more closely conform to the results of the predicted resist pattern function. Soft thresholding can be implemented to map 0 to "0" (soft range), 1 to "1", threshold to threshold (e.g., 1 / 2 to "1 / 2"); and can be implemented as a smooth, monotonically increasing switching function based on a Gaussian error function, a hyperbolic tangent, or any other sigmoid function that one of ordinary skill in the art can design. In some embodiments, this first soft thresholding function can also be applied to the predicted resist pattern function to generate a second predicted resist pattern function for comparison with the target pattern.

[0097] return Fig. 9AIn step 970, if the cost criterion is not met, the method is iterated as indicated by step 980 by: in step 990, the CTM is modified to reduce the cost, using the function derivative of the cost to provide directions on how to modify the mask. This will be calculated using derivatives, and any suitable algorithm (such as conjugate gradient) is used to pick a "direction" to move from the current mask parameters to reduce the cost. The cost or local contribution to the cost can be explicitly used in this process or gradient component or in both. In some embodiments, step 960 includes calculating the printability of the mask shape and the elasticity of the manufacturing variability to be used as part of the optimized cost. The size, spacing and slope of the CTM at a specific threshold value or multiple CTM threshold values ​​of the CTM are examples of components in this cost. Then, as indicated by loop "A", steps 950, 960, 970, 980 and 990 will be repeated until the cost criterion is met. In addition to the function derivative, other factors should be considered in each iteration to modify the CTM, such as historical data of previously calculated solutions. Next, the final CTM is output in step 995. Next, the CTM data can be "legalized" into a more reliably manufacturable mask pattern. In some embodiments, step 995 includes separate steps to produce a more reliably manufacturable mask. An example of such a step is to force all shapes and spacings to "snap" to comply with specified minimum values. By combining these factors as costs during the optimization cycle in step 960, the amount of snap will be negligible, with negligible impact on the resulting quality in the predicted pattern FSA. These mask patterns can also be further processed to incorporate some MPC of mask manufacturing effects, such as mask etch bias. Step 995 can include all MPCs. The output of the legalization step can be in the form of data to drive the eBeam machine, such as generating exposure instructions directly from the CTM.

[0098] Fig. 9BAn example illustration of the steps described in flowchart 900 is provided. Target pattern geometry 921 is an example of the target pattern input in step 920, wherein in this embodiment target pattern geometry 921 includes several rectangular shapes. Target wafer pattern FSA 931 corresponds to the target function generated in step 930. Initial CTM 941 is generated in step 940, and predicted pattern FSA 951A is generated by initial CTM 941 in step 950. Figure 951 shows predicted pattern FSA 951A as an open curve shape, and target wafer pattern FSA 951B is shown as a cross-hatched shape. As shown in 951, the difference between predicted pattern FSA 951A and target wafer pattern FSA 951B is used in step 960 to calculate the cost and the functional derivative of the cost. If the cost criteria are not met in steps 970 and 980, a modified (improved) CTM 991 is calculated in step 990. Next, loop A is iterated, where a modified predicted pattern FSA is calculated using the improved CTM 991 in step 950. Similar to graph 951, graph 952 shows the difference between the modified predicted pattern FSA 952A and the target wafer pattern FSA 952B. No open shapes can be seen, indicating that the modified (and improved) predicted pattern FSA 952A is sufficiently close to the target wafer pattern FSA 952B that the difference is not visible in graph 951. The difference between the improved predicted pattern FSA 952A and the target wafer pattern FSA 952B is used to determine whether the cost criterion is met. Note that in Fig. 9B In , the function is depicted as a conventional profile of a geometric shape, where the profile is shown at a resist exposure threshold level in this example. These profiles show how the pattern shape can be improved using the present method. However, as explained throughout this disclosure, some embodiments of the present method use FSA to perform the calculations rather than working with geometric profiles.

[0099] Distributed processing

[0100] An aspect of the present embodiment is the combination of data representation as FSA as captured on a regular grid, which can efficiently deliver and receive data from each process of the distributed process.

[0101] As stated previously, in some embodiments, the entire CTM and target mask pattern for the entire mask layer are maintained in memory. In order to predict the mask pattern of the CTM and compare the predicted wafer pattern with the target wafer pattern, the present embodiment decomposes the design into tiles. Although the present embodiment of optimizing the entire design through distributed processing shall be described in terms of the CTM, these embodiments may also be applied to the proposed mask types other than the CTM described herein.

[0102] When calculations are performed on specific tiles of the entire pattern, segments of the FSA can be sampled at a higher rate. For example, the pattern can be divided into multiple tiles, and calculations on multiple tiles are performed in a distributed process. Distributed processes operate independently, and many processes can run simultaneously. Multiple tiles are processed in parallel on the nodes of the computing cluster. In any tile of the multiple tiles, the CTM and the target mask pattern FSA are delivered at a designed wide grid interval, but when more detailed calculations are required, the value of the FSA can be calculated at any interval. The results of the distributed process are returned at a designed wide grid interval. That is, when calculations are performed on a specific tile, the sampling rate can be increased to perform higher resolution calculations, but during the calculation of the entire pattern, it is not necessary to store additional values ​​of the FSA (higher sampling rate) in memory. This saves memory and enables the calculation of the entire mask layer in a distributed process. Upsampling can be performed by performing a discrete Fourier transform via an FFT algorithm; extending the transform to higher frequencies corresponding to a higher sampling rate via periodic expansion; multiplying the result by a low-pass filter in frequency space corresponding to an ideal filter in real space multiplied by a local Gaussian; and applying an inverse discrete Fourier transform via an FFT algorithm. The stitching error between tiles can be reduced to a cancellation point by adding more tiles to the boundaries of the tiles so that the mismatch occurs at a specified number of Gaussian widths away from the edge of the tile. The use of a Gaussian localization factor is described above, but other forms of limiting the spatial range may be appropriate, as known to those skilled in the art. The sampling rate is also set to be higher than the Nyquist minimum rate so that the function bandwidth remains within the monotonic portion of the filter in frequency space and achieves a specified accuracy.

[0103] Due to the conventional grid structure calculation, the present method realizes graphics processing unit (GPU) acceleration. Because many grids can be processed simultaneously, FSA is beneficial to GPU computing. The calculation involves single instruction, multiple data (SIMD) operations, in which contours are not pursued. Accurate function resampling is achieved via highly optimized FFT. Due to the reduction of data transfer time, the GPU calculation time is greatly reduced because the amount of grid sample data that needs to be kept in the memory is based on using only the coarsest grid necessary to accurately represent the function. The reason why minimizing data transfer to / from the GPU is important is because the GPU has extremely fast computing speed, but is usually limited by its data transfer rate. Compared with conventional methods, the present method can increase the area of ​​tiles that can fit into a given memory size by 30 to 100 times, wherein the corresponding overhead is reduced by 5 to 10 times, and the seams between tiles are reduced by 5 to 10 times.

[0104] The use of localized Fourier interpolation via FFT and localized functions that constrain the effects of mismatched boundaries to specified distances allows the calculation to operate on any most appropriate resolution grid and only store the quantities retained by the optimization on its smallest grid. Without doing this, the memory requirements of the entire mask layer cannot be met. Another benefit of this method is that the calculation of the cost function and its derivatives are distributed using large tiles that overlap sufficiently to allow for lithographic imaging proximity and localized Fourier interpolation ranges while still optimizing all mask parameters within the entire mask layer rather than stitching tile by tile.

[0105] Using the decomposition into tiles along with the halo, independent evaluation of each tile's contribution to the cost function and derivatives can be performed, and the benefit of the band-limited smooth function allows a single node to hold values ​​for large design regions due to memory efficiency. Tiling also enables computational accelerations such as using a GPU, which can be further enabled by conventional grid-based computations and leverage from FFTs as needed. Independent evaluation of tiles also means that multiple nodes can be used first to handle even larger design regions (this is weakly proportional, which is calculated for larger problem sizes in a similar amount of time), and secondly to achieve more parallel execution of tile evaluations (this is strongly proportional, which occurs when more function units are accommodated for a fixed problem size with a corresponding reduction in computation time).

[0106] Optimize the entire design

[0107] Fig. 10A is an exemplary flow chart 1000 for conventional distributed computing of RET, and Fig. 10B is an exemplary flow chart 1001 for distributed computing of mask enhancement techniques at a possible global level of the present method. Fig. 10B As described, the method iterates on the optimization of a large section of the mask layer (such as the entire mask layer), rather than iterating on the optimization of each tile separately, as in Fig. 10A In the prior art example of Fig. 10A In step 1010 of the conventional method, a design and a mask are represented. In step 1020, the mask is divided into tiles. Each tile is iterated individually with its large halo area in steps 1030a / b...n, where costs and derivatives are calculated in steps 1030a / b...n, and if the cost does not meet the cost criteria in steps 1050a / b...n, the proposed mask for each tile is modified in steps 1060a / b...n. After each tile has been optimized, the mask is assembled from the tiles in step 1070. Therefore, in the conventional method, the design is broken down into tiles, and the individual tiles undergo optimization cycles; then the full design for the large area is assembled back together from the tiles. A well-known problem with all prior art systems is stitching.

[0108] In the present method for mask enhancement technology Fig. 10B In , the entire design is iterated on the optimization loop. In each loop iteration, the data of the halo of each tile is refreshed from the adjacent tiles. Therefore, there will be no difference in the data processed by the adjacent tiles. In step 1011 of flowchart 1001, the entire target wafer pattern is input and a proposed mask such as a continuous tone mask (CTM) is prepared. In some embodiments, the target wafer pattern and the proposed mask can be represented as a function sample array. The design of the entire target wafer pattern can be, for example, the entire mask layer of the chip design. The target wafer pattern spans the entire design area. Step 1011 corresponds to Fig. 9A In step 1021, the entire design area is divided into a plurality of "N" blocks. Fig. 10B As indicated by loop "B" in , the proposed mask such as CTM is iterated over the entire design area, wherein each tile is calculated independently of any other tile in the iteration. The calculation of each tile and its halo area in steps 1031a, 1031b to 1031n includes calculating cost and derivative data for each tile. Steps 1031a / b...n correspond to Fig. 9A Steps 950 and 960. The cost and derivative data are based on comparing the target design to the predicted design that would be produced by the proposed mask (eg, CTM). All tiles are computed in a distributed process.

[0109] Each iteration also includes step 1041: collecting cost and derivative data for all tiles in the plurality of tiles to calculate costs. In some embodiments, the collected costs include costs for reliable manufacturability of the mask as discussed in step 960. If the cost does not meet the cost criteria in step 1051, the cost and derivative data are used to modify the proposed mask in step 1061. Step 1051 corresponds to Fig. 9A Steps 970 and 980, and step 1061 corresponds to Fig. 9A The process is then iterated as indicated by loop B. In step 1091, after it has been determined that the cost satisfies the cost criteria, the proposed mask is converted to the outputted shape. For MPC, further processing of the mask shape to enable reliable manufacture of the mask or to achieve format output as described in step 995 is applicable to step 1091. Fig. 10BVariations of the process depicted in include: (1) not optimizing in some iterations tiles that have met the optimization criteria and whose halo regions are known to have not changed; (2) re-blocking the design and / or proposed mask after the criteria have been met (such as when multiple tiles meet the optimization criteria or multiple iterations have been performed); (3) using different optimization techniques for some of the iterations; and (4) optimizing only tiles that have a high cost for several iterations before continuing to optimize the entire design.

[0110] In an exemplary embodiment, the target wafer pattern or the predicted wafer pattern is represented as a smooth function captured as a function sample array (FSA), wherein the FSA is an array of function values, which can be a set of real numbers, complex numbers or numbers. A CTM is provided, wherein the CTM is used to generate the predicted wafer pattern, and the predicted wafer pattern spans the entire design area. In some embodiments, the entire design is divided into a plurality of tiles, and the CTM of the entire design area is iterated until the CTM meets the criteria for generating the target wafer pattern. Each iteration includes calculating the predicted wafer pattern for at least one subset of the tiles (such as one tile, or two or more tiles that need to be optimized), and all tiles in the subset are calculated before the next iteration. In some embodiments, iteration may include calculating for each tile, wherein all tiles are calculated before the next iteration. In some embodiments, the calculation is performed on a computing platform, and the computing platform has a collective total memory of all computing nodes of the computing platform, wherein the collective total memory maintains the target wafer pattern and the CTM of the entire design area during all iterations. In some embodiments, the calculation of the predicted wafer pattern also includes calculating cost and derivative data, the cost and derivative data being based on comparing the predicted wafer pattern with the target wafer pattern; and using the cost and derivative data to update the CTM of the tile. The cost may also be represented as a smooth function, wherein the smooth function of the cost may be different from the smooth function of the target wafer pattern, the predicted wafer pattern, or the CTM. In the present disclosure, the cost may also be referred to as a cost function. In some embodiments, the CTM is represented as a smooth function captured as a function sample array (FSA), wherein the FSA is an array of function values, which may be a real number, a complex number, or a set of numbers. The FSA of the CTM may be different from the FSA of the target wafer pattern or the predicted wafer pattern. For example, the target wafer pattern may be represented by a first FSA, and the CTM may be represented as a second FSA.

[0111] In some embodiments, each tile has a halo region surrounding the tile; the calculation is calculated for each tile and its halo region; and each iteration further includes: updating the CTM of an individual tile in the subset of tiles after calculating the predicted wafer pattern; and using the updated CTM of the individual tile to update the halo region of tiles adjacent to the individual tile. In a specific embodiment, the halo region of a tile in the plurality of tiles has a thickness surrounding the tile that is as small as 1.5 to 4 times the lithography imaging proximity range cutoff of a substrate lithography system for RET.

[0112] In some embodiments, the computation of each tile is performed on a compute node accelerated by a graphics processing unit. In some embodiments, representing the target wafer pattern as an FSA includes applying a low pass filter to the target wafer pattern. In some embodiments, the FSA of the target wafer pattern is band limited to a spatial frequency cutoff of a substrate lithography system and optionally can be sampled on a grid that satisfies the Nyquist criterion. In some embodiments, the target wafer pattern is a mask layer for a semiconductor chip.

[0113] In other exemplary embodiments, a method for RET includes: inputting a target wafer pattern, the target wafer pattern spanning the entire design area. The entire design area is divided into a plurality of tiles, each tile having a halo area surrounding the tile. The proposed mask (which may be a CTM) of the entire design area is iterated until the proposed mask (e.g., CTM) meets the criteria for generating the target wafer pattern. Each iteration includes calculating the predicted wafer pattern for a subset of the plurality of tiles, the subset having two to all of the plurality of tiles, wherein the calculation is performed for each tile and its halo area in the subset. Each iteration also includes updating the proposed mask of the tile, wherein all calculations for the subset are calculated before the next iteration. The subset may include two or more tiles of the plurality of tiles, such as up to all tiles. For example, tiles that need further optimization or have not yet exceeded a certain number of iterations may be included in the subset for calculation for the iteration. Other tiles that have met the optimization criteria or have been iterated a certain number of times do not need to be included in each iteration.

[0114] In some embodiments, the predicted wafer pattern is a continuous tone mask (CTM), and the CTM is represented as a smooth function captured as a function sample array (FSA), wherein the FSA is an array of function values, such as real values, complex numbers, or a collection of numbers. The function values ​​represent the mask values ​​at the grid points.

[0115] exist Fig. 10BIn some embodiments of the method, the proposed mask can be represented in a manner different from the CTM. For example, the proposed mask can be a modifiable mask with geometric shapes intended to produce a pattern, where the edges of each shape can be decomposed and manipulated near the target pattern edge.

[0116] In some implementations, the target wafer pattern or predicted wafer pattern is represented as a smooth function captured as a function sample array (FSA), where the FSA is an array of real values, complex numbers, or sets of numbers.

[0117] In some embodiments, the target wafer pattern is represented as a smooth function captured as a function sample array (FSA), wherein the FSA is an array of real values, complex numbers, or sets of numbers. The function values ​​characterize the target wafer pattern values ​​at the grid points. Representing the target wafer pattern as an FSA includes applying a low pass filter to the target wafer pattern. The FSA of the target wafer pattern can be band limited to the spatial frequency cutoff of the substrate lithography system and sampled on a grid that meets the Nyquist criterion.

[0118] In some embodiments, the calculation for each tile further comprises calculating a cost and derivative data based on comparing the predicted wafer pattern to the target wafer pattern, wherein the cost is also represented as a smooth function. In some embodiments, each iteration further comprises updating a halo region of a tile adjacent to the individual tile of the plurality of tiles using the updated proposed mask for the individual tile. In some embodiments, the calculation is performed on a computing platform having a collective total memory of all computing nodes of the computing platform, wherein the collective total memory maintains the target wafer pattern and the proposed mask for the entire design area during all iterations.

[0119] Decomposition and boundary conditions

[0120] The FFT implicitly imposes periodic boundary conditions (PBC) which must be resolved to successfully use the FFT. The spatial localization of the substrate projection model means that the PBC can be made almost harmless by adding a halo of adjacent mask regions to the region being worked on, so that the convolution result is correct in the original region. The filter kernels describing the substrate projection model are actually strictly band-limited in frequency, but their effects are also well localized in space, at least when their weights are taken into account. This is consistent with the idea of ​​the "lithography proximity effect". Mask values ​​r outside the lithography proximity range cutoff 截止 ≈5-10λ / NA does not affect what is printed in the region; therefore, most problems with PBC are avoided when it is calculated in the region by adding the vignetting of adjacent mask regions and values.

[0121] In order to correctly calculate the projected image in the region, a mask value is needed in the surrounding halo (boundary layer) at a depth of rcutoff. The value rcutoff is the spatial positioning distance. This is in the image of the tile with halo region 1100 Fig.11A , where the addition of a first boundary layer (halo) 1100 with a thickness r cutoff to block 1120 enables the calculation of the image intensity. Changes in the mask values ​​in the central image calculation area (block 1120) will affect the image on the area plus the first halo area. This is because light energy propagates over an area. Light projected through a specific portion of the mask will transfer energy on a nearby substrate. The distance over which a large amount of energy is projected determines the halo distance. Therefore, in order to obtain a cost change for changing the mask values ​​in the central area (block 1120), the image needs to be corrected to and including the first halo 1110. In the present method, this condition is achieved by adding a second extended halo area 1130 of mask values, such as Fig. 11B As shown. Fig. 11B , adding the second halo region 1130 obtains correct image values ​​in the extended central region (tile 1120 with the first halo 1110), which in turn allows correct calculation of the functional derivative of the mask value within the central region (tile 1120).

[0122] If the boundary of the area being calculated is one of the outer boundaries of the entire layer, then a halo of the new mask area to be optimized should be added, and another should be added is the desired mask boundary value such as full transmission or blocking. The new mask area to be optimized will allow the present pattern representation modeling method to add sub-resolution assist features (SRAFs) to the layout near the edge, and its goal in this area will be to print nothing.

[0123] If everything is represented on the finest grid required, then everything is fine, except for the potentially heavy storage requirements. Standard Fourier interpolation, which can be used to avoid unlimited oversampling, causes new ripple problems due to PBC. For example, Fourier interpolation used to resample from a mask or image grid to a finer cost function grid is still a problem because it is inherently non-local in nature. Any mismatch due to PBC will result in ripples that only decay to 1 / R, where R is the distance from the boundary. Solutions must be found to mitigate the ripple, or the mask must be oversampled to the cost function grid, which increases the amount of memory required to store the mask by one or two orders of magnitude or more. As previously discussed, embodiments of the present disclosure solve this resampling problem by applying a local filter (such as an ideal low-pass filter with a Gaussian envelope factor).

[0124] Decomposition of splicing without solution

[0125] Distributed Computing Strategy There are two main data distribution options to utilize sufficient computing power and memory to handle the construction of band-limited continuous tone masks (CTMs): 1-D strip decomposition or 2-D tile decomposition. The 1-D decomposition enables the 2-D FFT operation itself to be parallelized. The present method achieves 2-D decomposition, but does not incur the splicing problem as conventional methods.

[0126] 1-D decomposition requires a lot of memory, and there may be arithmetic precision issues when computing FFTs on very large arrays. The 1-D decomposition of the entire mask layer across multiple graphics processing units (GPUs), central processing units (CPUs), and compute nodes is intended to allow 2-D FFTs to be parallelized on the mask layer. The "compute unit" of this decomposition is essentially the entire mask layer, because everything will be processed as if at once. Specifically, any temporary quantities required to improve the CTM will be calculated and maintained for the entire mask layer before releasing its storage. The entire mask layer is calculated at once, so there may be no splicing issues.

[0127] A 2-D FFT operation involves performing all 1-D FFTs along one axis, then performing all 1-DFFTs along the other axis. Thus, with strip decomposition, all local 1-DFFTs are first performed (along the length of each strip), a correspondence step is performed to change the decomposition axis, and then all 1-D FFTs along the (now local) second axis are performed.

[0128] In cases where many 2-D FFTs and other calculations are performed, there is an opportunity to build pipelines that use overlapping calculations to hide most of the communication overhead. The main challenges are the storage of intermediate quantities to keep the entire mask layer on a fine grid, and possible precision problems when calculating FFTs on very large arrays. A major advantage of calculating across the entire mask layer is that the strips are not stitched back together, thus completely avoiding the stitching problems that plague the simplest 2-D decomposition methods.

[0129] In the present disclosure, the 2-D block decomposition does not directly process the entire mask layer at once, but achieves the same effect and without any stitching. The 2-D decomposition localizes all calculations to the tile (plus its halo), so this is the unit of calculation. In some embodiments, the contribution to the total cost and the derivative of the cost can be fully calculated for each tile's mask value separately. The number of fine grids like the cost density is temporary, and only enough memory is needed to hold the temporary values ​​for the multiple tiles currently being worked on. When the energies and derivatives of all tiles have been calculated, the net result will be as if the entire mask layer was handled as a unit, but there is no need to store intermediate values ​​as a whole, unless it is desirable to provide checkpoints for error recovery or debugging.

[0130] At this point an optimization step may be performed across the entire mask layer, followed by a communication phase to update the halo data for each neighboring tile for the next iteration. The update may involve exchanging tile data with neighboring tiles through memory sharing, local replication, through message passing in a distributed system, or by other means, and may not be necessary when the memory for the neighboring tiles is a neighboring sub-array of an array containing both tiles.

[0131] In some embodiments, each tile is selected to allow all of its local computations to reside in a single node GPU, while allowing pipelining of GPU computations and data transfers to and from main memory. Computations may be performed in double, single, half, or other floating point precisions, or in various integer formats, depending on the needs of speed, memory, and precision.

[0132] The present method enables seamless optimization over very large domains and effectively eliminates the effects of PBC mismatch when interpolating, thus achieving a feasible method for 2-D parallel decomposition where each tile is a computational unit, where temporary storage requirements are limited to those tiles being processed simultaneously, where entire mask layers are optimized together, and where the ongoing storage requirements while optimizing involve a small number of grids for band-limited masks.

[0133] 1-D instance in Fig.12 , which shows an interpolation, such as a Gaussian localized interpolation, of long-term data treated as four linearly adjacent tiles overlapping in their halo regions. The underlying curve is thirteen cycles of a sinusoid evaluated at 1024 sample points, and the Gaussian width parameter used is s=4 samples. The data is decomposed into four equal-sized tiles with overlapping halos of sixteen samples. Fig.12 Four adjacent tiles are shown in (a), each with their halo, and with conventional Fourier interpolation onto a 10x finer grid. Note the ringing at the end of each curve in the halo region of the tile. The curves reassembled from the central tile region are Fig.12 (b) shows the results for both conventional Fourier interpolation and Gaussian localized Fourier interpolation. The difference between the curves is too small to be seen at this scale. Fig.12 The difference between the reassembled Fourier interpolated curve and the ideal sinusoidal curve is plotted in (c). The difference reaches the 1% level at the tile boundaries and shows a longer range into the center of each tile. In contrast, Fig.12 The difference in the Gaussian localized Fourier interpolation shown in (d) only partially reaches 10 at the tile boundaries. 9 , and then decays rapidly from here.

[0134] Computing System

[0135] A general-purpose computer with appropriate computer software as a computing device can be used to implement the calculations and processing steps described in the present disclosure. Multiple computers or processor cores can also be used in parallel. In some embodiments, a single-use or multiple-use dedicated hardware device can be used to perform the calculation of one or more steps at a faster speed than using a general-purpose computer or processor core. In certain embodiments, the dedicated hardware device can be a graphics processing unit (GPU). In other embodiments, other dedicated hardware devices can also be used as coprocessors, such as digital signal processors (DSPs), tensor processing units (TPUs), field programmable gate arrays (FPGAs), or application-specific integrated circuits (ASICs).

[0136] Fig.13 1 is a block diagram of an example of a computing hardware device 1300 that can be used to perform the calculations described in the present disclosure. The computing hardware device 1300 includes a central processing unit (CPU) 1302 and an attached main memory 1304. The CPU 1302 may include, for example, eight processing cores, thereby enhancing the performance of any part of the multithreading of the computer software. The size of the main memory 1304 may be, for example, 64 Gbytes. The CPU 1302 is connected to a peripheral component interconnect high-speed (PCIe) bus 1320. A graphics processing unit (GPU) 1314 may also be connected to the PCIe bus 1320. In the computing hardware device 1300, the GPU 1314 may or may not be connected to a graphics output device such as a video monitor. If not connected to a graphics output device, the GPU 1314 may be used purely as a high-speed parallel computing engine. By using the GPU 1314 for a portion of the calculation, the computing software can achieve significantly higher performance than using the CPU 1302 for all calculations. The CPU 1302 communicates with the GPU 1314 via the PCIe bus 1320. In other embodiments (not shown), GPU 1314 may be integrated with CPU 1302 instead of being connected to PCIe bus 1320. Disk controller 1308 may also be attached to PCIe bus 1320, with, for example, two disks 1310 connected to disk controller 1308. Finally, local area network (LAN) controller 1312 may also be attached to the PCIe bus and provide a Gigabit Ethernet (GbE) connection to other computers. In some embodiments, computer software and / or design data is stored on disk 1310. In other embodiments, either or both the computer program or design data may be accessed from other computers or file serving hardware via GbE Ethernet or other connection schemes such as Infiniband.

[0137] Fig.14It is another embodiment of the system for performing the calculation of the present embodiment. System 1400 may also be referred to as a computational design platform (CDP), and includes a master node 1410, an optional view node 1420, an optional network file system 1430, and a GPU-enabled node 1440. View node 1420 may not exist or actually have only one node, or may have other numbers of nodes. GPU-enabled node 1440 may include one or more GPU-enabled nodes. Each GPU-enabled node 1440 may be, for example, a GPU, a CPU, a paired GPU and a CPU, a plurality of GPUs for a CPU, or other combinations of GPUs and CPUs. GPU and / or CPU may be on a single chip, such as a GPU chip with a CPU accelerated by a GPU on the chip, or a CPU chip with a GPU that accelerates a CPU. GPU may be replaced by other coprocessors.

[0138] The master node 1410 and the view node 1420 may be connected to the network file system 1430 and the GPU-enabled node 1440 via switches and high-speed networks such as networks 1450, 1452, and 1454. In an exemplary embodiment, network 1450 may be a 56Gbps network, 1452 may be a 1Gbps network, and 1454 may be a management network. In various embodiments, there may be fewer or more of these networks, and there may be various combinations of network types such as high speed and low speed. The master node 1410 controls the CDP 1400. External systems may be connected to the master node 1410 from an external network 1460. In some embodiments, a job is launched from an external system. Before launching a job, the data for the job is loaded onto the network file system 1430, and a program is used to schedule and monitor tasks on the GPU-enabled node 1440. The progress of the job may be seen via a graphical interface such as the view node 1420 or by a user on the master node 1410. Tasks are performed on the CPU using scripts that run appropriate executables on the CPU. The executables connect to the GPU, run various computational tasks, and then disconnect from the GPU. The master node 1410 can also be used to disable any failed GPU-enabled nodes 1440 and then operate as if the nodes did not exist.

[0139] In some embodiments, a system for a reticle enhancement technique includes a computer processor configured to receive a target wafer pattern to be used in a reticle enhancement technique; and calculate a function sample array (FSA) of the target wafer pattern, the FSA of the target wafer pattern being a smooth function. The computer processor is further configured to calculate a continuous tone mask (CTM), wherein the CTM is represented as a smooth function captured by the function sample array (FSA); and compare the target wafer pattern with a predicted wafer pattern generated by the CTM. In other embodiments, the target wafer pattern is divided into a plurality of tiles, and the computer processor is further configured to calculate cost and derivative data for each of the plurality of tiles, the calculations of the plurality of tiles being performed in a distributed process. The cost and derivative data are based on comparing the target wafer pattern with the predicted wafer pattern generated by the CTM.

[0140] In a general embodiment, the system is a computer processor, which in some embodiments may include a graphics processing unit or other coprocessor for performing distributed computing (such as parallel processing). In some embodiments, the graphics processing unit or other coprocessor may be configured to interconnect with each other for fast communication. The computer processor is configured to receive a target pattern to be used in a mask enhancement technique and generate a target pattern function of the target pattern, wherein the target pattern function is an FSA. The computer processor is further configured to generate a CTM and compare the target pattern function with the predicted pattern function generated by the CTM. The CTM is a smoothing function.

[0141] Recognition

[0142] In the present disclosure, a CTM can be converted into a reliably manufacturable mask. The CTM (ie, the proposed mask) can be modified to ensure that the mask is physically realizable.

[0143] In some embodiments, iterative optimization of CTM uses costs related to the reliable manufacturability of mask shapes. In some embodiments, a set of constraints related to the reliable manufacturability of mask shapes prohibits consideration of specific shapes. In some embodiments, after the cost criteria are met, the mask shape can be further modified to match the precise specifications of mask manufacturability. The costs and criteria for mask manufacturability include, but are not limited to, minimum size and spacing, maximum allowed curvature, minimum dose margin, and mask edge error factor (MEEF). Optimization of MEEF and other factors is disclosed in U.S. Patent No. 8,719,739 entitled "Method and System for Forming Patterns Using Charged Particle Beam Lithography", which is owned by the assignee of the present application.

[0144] In addition to incorporating mask manufacturability costs and constraints during ILT, MPC and other mask reliability enhancement and mask data preparation steps are performed during ILT. The combined effect may be referred to as mask-wafer co-optimization. In some embodiments, a technique to accomplish mask-wafer co-optimization is dual simulation, which is disclosed in U.S. Patent No. 9,038,003, “Method and System for Critical Dimension Uniformity Using Charged Particle Beam Lithography,” owned by the assignee of the present application.

[0145] The CTM has a continuous range of values ​​that must be converted into a continuous region of allowed transmission values. The continuous region with fixed transmission values ​​corresponds to the shape on the manufacturable mask. The allowed transmission values ​​depend on the type of mask; for example, they are typically 0 or 1 for a glass-chrome mask, or 1 for a 6% attenuated phase-shift mask. and 1.

[0146] In one embodiment, this conversion is accomplished by regularization that involves adding a term to the cost that favors manufacturable masks.

[0147] The main regularization required is to favor masks that are very close to the allowed transmission values ​​everywhere, with the exception of transitions from one allowed value to another that may contain intermediate values. In one embodiment, a term is introduced that will be referred to as a "value shaping term" that favors the allowed values ​​and favors short transitions between regions of one value to the boundary regions of another value.

[0148] The CTM selected using the value shaping term in the optimization may include shapes that would be difficult to manufacture reliably. In one embodiment, a second term is introduced that favors shapes that will have good dose margins when manufacturing the mask. This term can use the PSF to measure how much the shape has changed and calculate a cost based on the change.

[0149] Reference has been made in detail to the embodiments of the disclosed invention, one or more examples of which have been shown in the accompanying drawings. Each example has been provided by way of explanation of the present technology, rather than as a limitation to the present technology. In fact, although the present specification has been described in detail with reference to specific embodiments of the present invention, it should be understood that those skilled in the art can easily conceive of alternatives, variations and equivalents of these embodiments after obtaining an understanding of the foregoing. For example, a feature shown or described as a part of an embodiment can be used together with another embodiment to produce another embodiment. Therefore, the present subject matter is intended to include all such modifications and variations within the scope of the attached claims and their equivalents. Those of ordinary skill in the art may make these and other modifications and variations to the present invention without departing from the scope of the present invention as more specifically stated in the attached claims. In addition, those of ordinary skill in the art will understand that the foregoing description is only by way of example and is not intended to limit the present invention.

Claims

1. A method for mask enhancement technology RET, comprising: Input a target wafer pattern, wherein the target wafer pattern spans the entire design area; Iterating the proposed mask for the entire design area until the proposed mask meets the criteria for producing the target wafer pattern, wherein each iteration comprises: calculating a predicted wafer pattern based on the proposed mask; wherein the calculating comprises calculating cost and derivative data, the cost and the derivative data being based on comparing the predicted wafer pattern to the target wafer pattern; and The cost also includes specifications for the manufacturability of the mask.

2. The method according to claim 1, wherein: The specification for mask manufacturability includes at least one of a minimum dimension, a minimum spacing, a maximum curvature, or a minimum dose margin.

3. The method according to claim 1, wherein: The proposed mask is a continuous tone mask CTM and wherein the CTM is represented by a continuous range of values.

4. The method according to claim 3, wherein: The continuous range of values ​​is converted into a continuous region of allowed transmission values, wherein the continuous region corresponds to a shape on a manufacturable mask.

5. The method according to claim 1, further comprising dividing the entire design area into a plurality of tiles, each tile having a halo area surrounding the tile, wherein The calculation is performed for each tile and its halo region.

6. The method according to claim 5, wherein: Each iteration further includes updating the proposed mask for an individual tile of the plurality of tiles, and updating halo regions of tiles adjacent to the individual tile using the updated proposed mask for the individual tile of the plurality of tiles, wherein all tiles of the plurality of tiles are calculated prior to a next iteration.

7. The method according to claim 1, wherein: The computation is performed on a computing platform having an aggregate memory of all computing nodes of the computing platform, wherein the aggregate memory holds the target wafer pattern and the proposed masks for the entire design area across all iterations.

8. The method according to claim 1, wherein: The calculation also includes a mask process correction MPC.

9. The method according to claim 8, wherein: The MPC includes one or more of correction linearity, enhanced critical dimension uniformity CDU, and enhanced line edge roughness LER as a measure of resilience to manufacturing variations.

10. A method for manufacturing a semiconductor device, comprising: Iterating a continuous tone mask CTM to optimize the CTM for reliable manufacturability of a mask shape, wherein the CTM is represented by a continuous range of values, and wherein each iteration comprises: calculating a predicted wafer pattern based on the CTM; and Cost and derivative data are calculated, the cost and the derivative data being based on comparing the predicted wafer pattern to a target wafer pattern.

11. The method according to claim 10, wherein: The manufacturability of the mask shape includes at least one of a minimum size, a minimum spacing, a maximum curvature, or a minimum dose margin.

12. A method for a mask enhancement technique (RET) for a lithography imaging system, the method comprising: representing a target wafer pattern or a predicted wafer pattern as a smooth function captured as a function sample array FSA, wherein the FSA is an array of sampled values ​​of the smooth function, the smooth function being a continuously differentiable function; providing a continuous tone mask (CTM), wherein the CTM is used to generate the predicted wafer pattern, the predicted wafer pattern spanning the entire design area; and Calculating the predicted wafer pattern based on the CTM, wherein the calculating comprises: calculating a cost based on comparing the predicted wafer pattern to the target wafer pattern, wherein the cost is represented as a third smooth function; and updating the CTM using the cost.

13. The method according to claim 12, further comprising: The CTM is determined, wherein the CTM captures values ​​of a continuously varying amplitude transmission coefficient map.

14. The method according to claim 12, wherein: The FSA is band-limited to the spatial frequency cutoff of the substrate lithography system and sampled on a grid that satisfies the Nyquist criterion.

15. The method of claim 12, further comprising inputting a target geometry, wherein: The FSA for the target wafer pattern is generated based on the input target geometry.

16. The method according to claim 12, wherein: The calculation also includes: Derivative data is calculated based on comparing the predicted wafer pattern to the target wafer pattern.

17. The method of claim 12, further comprising iterating the CTM for the entire design area until the CTM meets criteria for producing the target wafer pattern.

18. The method according to claim 17, wherein: The computation is performed on a computing platform that includes an aggregate memory of all computing nodes of the computing platform, wherein the aggregate memory maintains the target wafer pattern and the CTM of the entire design area across all iterations.

19. The method according to claim 17, further comprising: Divide the entire design area into a plurality of tiles, wherein the iterating comprises computing the predicted wafer pattern for a subset of the plurality of tiles; Therein, all tiles in the subset are calculated before the next iteration.

20. The method according to claim 19, wherein: Each tile in the subset of the plurality of tiles has a halo region surrounding the tile, wherein the calculation for each tile includes the halo region of the tile, and wherein each iteration further comprises: After calculating the predicted wafer pattern for an individual tile in the subset of tiles, updating the CTM for the individual tile; and The halo regions of tiles adjacent to the individual tile are updated using the updated CTM for the individual tile.

21. The method according to claim 20, wherein: The halo region has a thickness around the tile that is 1.5 to 4 times the lithography imaging proximity range cutoff of a substrate lithography system used for the RET.

22. The method according to claim 19, wherein: The computations for tiles in the subset of the plurality of tiles are performed on a compute node accelerated by a graphics processing unit.

23. A method for a mask enhancement technique (RET) for a lithography imaging system, the method comprising: representing a target wafer pattern or a predicted wafer pattern as a smooth function captured as a function sample array FSA, wherein the FSA is an array of sampled values ​​of the smooth function, the smooth function being a continuously differentiable function; providing a continuous tone mask (CTM), wherein the CTM is used to generate the predicted wafer pattern, the predicted wafer pattern spanning the entire design area; and The CTM is represented as a second smooth function captured as a second function sample array FSA, wherein the second FSA is an array of sampled values ​​of the second smooth function, the second smooth function being a continuously differentiable function.

24. The method of claim 23, further comprising determining the CTM, wherein: The CTM captures the values ​​of a continuously varying amplitude transmission coefficient map.

25. The method according to claim 23, wherein: The FSA is band-limited to the spatial frequency cutoff of the substrate lithography system and sampled on a grid that satisfies the Nyquist criterion.

26. The method of claim 23, further comprising inputting a target geometry, wherein: The FSA for the target wafer pattern is generated based on the input target geometry.

27. A method for a mask enhancement technique (RET) for a lithography imaging system, the method comprising: Representing a target wafer pattern or a predicted wafer pattern as a smooth function captured as a function sample array FSA, wherein the FSA is an array of sampled values ​​of the smooth function, the smooth function being a continuously differentiable function; and providing a continuous tone mask (CTM), wherein the CTM is used to generate the predicted wafer pattern, the predicted wafer pattern spanning the entire design area; Wherein the FSA for the target wafer pattern or the predicted wafer pattern has a plurality of grid points, and the grid points are spaced apart at a grid pitch, wherein the grid pitch is set to a transition distance that is less than a lithographic imaging resolution of the lithographic imaging system.

28. The method of claim 27, further comprising determining the CTM, wherein: The CTM captures the values ​​of a continuously varying amplitude transmission coefficient map.

Images