System and method for optimizing scanning speed of lithographic scanner device and method for increasing yield of lithographic device

Abstract

The present disclosure provides a system and method for optimizing the scanning speed of a lithographic scanner device and a method for increasing the yield of a lithographic device. A method of optimizing a scan speed of a lithographic scanner includes receiving a process design layout corresponding to a plurality of field columns to be formed on an associated wafer and determining a preset machine constant of the lithographic scanner. Each of the plurality of field columns is then identified as corresponding to the received process design layout. A scan speed for each determination type of the column and a preset machine constant for the determination are then determined. The associated wafer is then processed using the determined scan speed for each of the columns according to the process design layout.

Description

Technical Field

[0001] The present disclosure relates to systems and methods for optimizing the scanning speed of a lithography scanner device and methods for increasing the throughput of a lithography device. Background Art

[0002] A lithography apparatus is a machine that utilizes a reticle (i.e., a mask) that applies a desired pattern onto a target portion of a substrate. The reticle may be a reflective mask or a transmissive mask. In the process, ultraviolet light reflects off the surface of the reticle (for a reflective mask) or transmits through the reticle (for a transmissive mask) to transfer the pattern to a photoresist and thereby onto a target portion of a semiconductor wafer. The minimum feature size of the pattern is limited by the wavelength of the light. Deep ultraviolet (UV) lithography uses wavelengths of 193nm or 248nm. Extreme ultraviolet (EUV) light, which spans wavelengths from 124 nanometers (nm) down to 10nm, is currently being used to provide small minimum feature sizes. A lithography scanner is one such type of apparatus, in which each target portion is exposed by scanning the reticle through a projection beam in a given direction while synchronously scanning (i.e., moving) the wafer substrate parallel to or antiparallel to this direction. The scanning speed of the scanner affects not only the quality but also the yield. Summary of the invention

[0003] In some embodiments of the present disclosure, a method for optimizing a scanning speed to increase the throughput of a lithography device includes a scaled-down mask stage assembly and a wafer stage assembly, the method comprising the following steps: receiving a process design layout corresponding to a plurality of fields to be formed on an associated wafer; determining a full-field scanning length based on the received process design layout; determining a preset machine constant including determining a moving speed of the scaled-down mask stage assembly and determining a moving speed of the wafer stage assembly; identifying a type of each of a plurality of field columns corresponding to the received process design layout, wherein the type of field column is selected from a group including a center field column, an edge field column, or a combination of an edge field and a center field column; determining a center field column scanning speed of each of the plurality of field columns identified as a center field column; determining an edge field column scanning speed of each of the plurality of field columns identified as an edge field column; determining a predetermined machine constant including determining a moving speed of the scaled-down mask stage assembly and determining a moving speed of the wafer stage assembly ... An edge field and center field combination row scanning speed for each of the field and center field combination rows, wherein the edge field and center field combination row scanning speed uses the center field row scanning speed for each center field in the edge field and center field combination row and uses the edge field row scanning speed for each edge field in the edge field and center field combination row; and the associated wafer is processed according to the process design layout using the center field row scanning speed, the edge field row scanning speed and the edge field and center field combination scanning speed, wherein each center field is the full field scanning length, and each edge field has a scanning length less than the full field scanning length; wherein the step of determining the center field row scanning speed, the edge field row scanning speed and the edge field and center field combination scanning speed is performed according to the preset machine constant; and wherein the step of determining the center field row scanning speed further includes the following steps: distinguishing a scanning time of the lithography device from an acceleration time of the scaled mask stage assembly.

[0004] In some embodiments disclosed herein, a method for optimizing a scanning speed of a lithography scanner device, the lithography scanner device comprising a scaled mask stage assembly and a wafer stage assembly, the method comprising the following steps: receiving a process design layout corresponding to a plurality of field columns to be formed on an associated wafer; determining a preset machine constant of the lithography scanner device; identifying a type of each of the plurality of field columns corresponding to the received process design layout, wherein the type of field column is selected from a group including a center field column, an edge field column, or a combination of an edge field and a center field column; determining a scanning speed based on the determined column type and the determined preset machine constant; and applying the determined scanning speed to each of the plurality of columns to process the associated wafer based on the process design layout; wherein the step of determining a center field column scanning speed further comprises the following steps: distinguishing a scanning time of the lithography scanner device from an acceleration time of the scaled mask stage assembly.

[0005] In some embodiments of the present disclosure, a system for optimizing the scanning speed of a lithography scanner device includes: a zoom mask stage assembly including a zoom mask and at least one motor for movement in the x-direction and the y-direction; a wafer stage assembly including a wafer stage body and a wafer holding element for holding a wafer thereon; and a controller including a processor in communication with a memory storing a plurality of instructions executed by the processor to perform the following steps: receiving a process design layout , which corresponds to a plurality of fields to be formed on the wafer, each of the fields is identified as a center field or an edge field via a field identification element, an optimal scanning speed of each of the fields is determined according to the identified field type via a scanning speed determination element, wherein the step of determining an optimal scanning speed of the center field includes the following steps: distinguishing a scanning time of the lithography scanner device from an acceleration time of the scaled mask stage assembly, and starting the at least one motor according to the determined optimal scanning speed for each of the fields via a motor control element. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of this disclosure are in the attached Figure 1 The following detailed description is best understood when read together. Please note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a schematic diagram of a lithography system according to some embodiments;

[0008] Figure 2A For use according to some embodiments Figure 1 A side view of a reduced-mask stage assembly in a lithography system;

[0009] Figure 2B For use according to some embodiments Figure 1 A bottom view of a reduced-mask stage assembly in a lithography system;

[0010] Figure 3 For use according to some embodiments Figure 1 A side view of a wafer stage assembly in a lithography system;

[0011] Figure 4 illustrates a block diagram of a controller according to some embodiments;

[0012] Figure 5 is a flow chart illustrating a method for optimizing a scan speed of a lithography scanner according to some embodiments;

[0013] Figure 6 illustrative example of wafer up and down scanning routing according to some embodiments;

[0014] 7A to 7C is a simplified illustrative example of on-wafer fielding according to some embodiments;

[0015] Figure 8 is an illustrative graph of scan speed according to some embodiments;

[0016] FIG. 9A to FIG. 9B Provides a simplified representation of scan time and step time according to some embodiments;

[0017] FIG. 10A to FIG. 10C provides an illustrative view of a scan length difference according to some embodiments;

[0018] Fig.11 is a flow chart illustrating a method for optimizing a scan speed of a lithography scanner according to some embodiments;

[0019] FIG. 12A to FIG. 12B is a comparative example of output performance according to some embodiments.

[0020]

Explanation of symbols

[0021] 100: Lithography System

[0022] 101: Residue

[0023] 102: Shrinking mask

[0024] 104: Lithographic Scanner

[0025] 108: Communication link

[0026] 110:EUV light source

[0027] 112: Radiation source chamber

[0028] 114: Target droplet generator

[0029] 116: Droplets

[0030] 118: Droplet Catcher

[0031] 119: Output port

[0032] 120: Laser source

[0033] 122: Preheating laser pulse

[0034] 124: Main laser pulse

[0035] 125: Plasma

[0036] 130: Illumination stage

[0037] 132: Field small mirror

[0038] 134: Relay mirror

[0039] 142: Process chamber

[0040] 150: Projection optics module

[0041] 152: Mirror

[0042] 154: Mirror

[0043] 160: Substrate / wafer

[0044] 170: Gas port

[0045] 172: Blade

[0046] 174 / 186: Vacuum pump

[0047] 176: Collector mirror

[0048] 180:Sensor

[0049] 182:Sensor

[0050] 184:Sensor

[0051] 190: Controller

[0052] 200: Shrink mask stage assembly

[0053] 202: Shrinking mask stage assembly body

[0054] 204: Motor

[0055] 206: Motor

[0056] 208: Photomask clip

[0057] 300: Wafer stage assembly

[0058] 302: Wafer stage body

[0059] 304: Electrostatic chuck

[0060] 402: Processor

[0061] 404: Memory

[0062] 406: Instruction

[0063] 408: Data / Control Bus

[0064] 412: Communication link

[0065] 414: Link

[0066] 416: Display device

[0067] 418: User input device

[0068] 420: Associated Database

[0069] 424: Interface

[0070] 426: Interface

[0071] 428: Field identification element

[0072] 430: Scanning speed determination element

[0073] 432: Motor control components

[0074] 434: Process Design Layout

[0075] 436: Preset machine constants

[0076] 438: Reduced mask information

[0077] 500:Flowchart

[0078] 502: Steps

[0079] 504: Steps

[0080] 506: Steps

[0081] 508: Steps

[0082] 510: Steps

[0083] 512: Steps

[0084] 514: Steps

[0085] 516: Steps

[0086] 518: Steps

[0087] 520: Steps

[0088] 522: Steps

[0089] 524: Steps

[0090] 602: Field

[0091] 604: Field

[0092] 606: Column

[0093] 700: Wafer

[0094] 702: Column

[0095] 704: Column

[0096] 706: Column

[0097] 708: Field

[0098] 710: Field

[0099] 1100: Method

[0100] 1102: Steps

[0101] 1104: Steps

[0102] 1106: Steps

[0103] 1108: Steps

[0104] 1110: Steps

[0105] 1112: Steps

[0106] 1114: Steps

[0107] 1116: Steps

[0108] 1118: Steps

[0109] 1120: Steps DETAILED DESCRIPTION

[0110] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these components and configurations are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be directly contacted. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simple and clear purposes, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0111] Additionally, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein for ease of description to describe the relationship of one or more elements or features to another or further elements or features as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0112] The numerical values ​​in the specification and patent application range of this application should be understood to include the same numerical values ​​when reduced to the same number of significant figures, and the numerical values ​​that differ from the stated value by less than the experimental error of the conventional measurement technology of the type described in this application to determine the value. All ranges disclosed herein include the stated endpoints.

[0113] The term "about" can be used to include any numerical value that can vary without changing the basic function of the value. When used with a range, "about" also discloses a range defined by the absolute values ​​of the two endpoints, for example, "about 2 to about 4" also discloses a range "from 2 to 4". The term "about" can refer to plus or minus 10% of the indicated number.

[0114] The present disclosure may refer to temperatures for certain method steps. Note that these references are to temperatures at which the heat source is set, and do not specifically refer to temperatures that must be obtained by a particular material exposed to heat.

[0115] In this disclosure, the terms "photolithography mask," "mask," "reticle," and "reduction reticle" are used interchangeably.

[0116] Lithography equipment can be used, for example, in the manufacture of integrated circuits (ICs), flat panel displays, and other devices involving fine structures. In conventional lithography equipment, a mask or reticle can be used to produce a circuit pattern corresponding to individual layers of an IC (or other device), and this pattern can be imaged onto a target portion (e.g., a portion including one or more dies) on a substrate (e.g., a silicon wafer or a glass plate) having a layer of radiation-sensitive material (e.g., a photoresist material).

[0117] In manufacturing using lithography, a key performance metric for reducing production cost is better yield. Improvements in the yield of lithography scanners are typically achieved through hardware upgrades or continuous improvement processes of photoresists. However, both of these projects require additional cost, time, and effort to develop and implement, resulting in small yield gains while suffering the risk of increased poor overlay (OVL) / focal range. Therefore, the systems and methods described herein provide increased yield by varying the scan speed based on the scan length of the field.

[0118] According to some embodiments, systems and methods are described below, providing a system and method for determining an optimal scan speed of a lithography scanner based on a scan length of a wafer layout to increase throughput. As used herein, the term "scan length" corresponds to the length of an exposure field on a wafer, for example, the distance between exposures. For example, after exposure, the wafer stage assembly moves (or the reticle stage assembly moves) a predetermined distance to enable exposure of the next field on the wafer. In some embodiments, the term "scan speed" or "scanner speed" refers to the rate of movement of the wafer (i.e., movement of the reticle stage assembly and / or the wafer stage assembly, as discussed below). For example, the scan speed may correspond to the rate at which the wafer moves from one field to another. According to some embodiments, the term "step time" corresponds to the amount of time required to move from one field to another. For example, the time it takes to move the wafer to enable exposure of a field. The term "scan time" may be defined as the scan length divided by the scan speed. The term "exposure time" may be generally expressed as the sum of the scan time and the step time (ie, exposure time = Σ(scan time + step time)).

[0119] View now Figure 1 , depicts a schematic diagram of an exemplary lithography system 100 according to some embodiments. It should be understood that although Figure 1 Although depicted as an EUV lithography system 100, the systems and methods described herein are suitably configurable for use with a lithography system, and references herein to the EUV lithography system 100 are intended to be illustrative and not limiting of the present application. Figure 1 A schematic diagram, not drawn to scale, is provided to illustrate various elements of an EUV lithography system 100 that utilizes scan speed optimization and throughput improvement in accordance with the systems and methods described herein. Generally speaking, the EUV lithography system 100 includes an EUV light source 110 and a laser source 120 that generate EUV light. Downstream of the EUV light source 110 is an illumination stage 130 that collects the EUV light and focuses the light onto a retracted reticle 102. Downstream of the retracted reticle 102 is a projection optics module 150 that is configured to image the pattern of the retracted reticle 102 (i.e., the mask) onto a substrate 160, such as a semiconductor wafer. The EUV lithography system 100 may include other modules, or be integrated or coupled with other modules. The operation of the EUV lithography system 100 may be controlled by a controller 190 that is communicatively coupled to the various elements and modules described herein. The controller 190 is described below with respect to FIG. Figure 4 Describe in more detail.

[0120] The EUV light source 110 itself includes a radiation source chamber 112, which contains a plasma reaction that produces EUV light. The radiation source chamber 112 includes a target droplet generator 114. The target droplet generator 114 deposits a plurality of target droplets 116 into the radiation source chamber 112. In some embodiments, the target droplets 116 are tin (Sn) droplets. In other embodiments, the target droplets 116 may include alternative types of materials, such as tin-containing liquid materials such as eutectic alloys containing tin or lithium (Li). The tin droplets 116 can be deposited at a rate of, for example, about 50,000 droplets per second.

[0121] A laser source 120 is also present, which emits one or more laser beams into the radiation source chamber 112, which contacts the target droplet 116 to generate EUV light. In some embodiments, the laser source 120 may be a carbon dioxide (CO2) or neodymium-doped yttrium aluminum garnet (Nd:YAG) laser source. The laser source 120 may be a multi-stage laser source having multiple stages that are used to amplify the laser light generated by a previous stage. In some embodiments, the laser source 120 may generate multiple beams. For example, Figure 1 As shown in , a preheating laser pulse 122 may be used to create a low density target plume that is subsequently heated (or reheated) by a main laser pulse 124 that produces EUV light. The laser source 120 also typically includes optics and other focus elements for directing the laser beam in a desired direction.

[0122] The radiation source chamber 112 includes a window or lens that is substantially transparent to the laser wavelength. The generation of the laser beam is synchronized with the target droplet 116. The preheating laser pulse 122 heats the target droplet and expands the target droplet into a low-density target plume. The delay between the preheating laser pulse 122 and the main laser pulse 124 is controlled to allow the target plume to form and expand to an optimal size and geometry. When the main laser pulse 124 heats the target plume, a high-temperature plasma 125 is generated. The plasma 125 emits EUV radiation in all directions. EUV light traveling in the wrong direction (i.e., away from the output port) is collected by the collector mirror 176.

[0123] The collector mirror 176 has a reflective surface that reflects and focuses EUV light. In some embodiments, the collector mirror 176 has an elliptical shape. The collector mirror 176 may be coated with a material similar to the material of the retraction mask 102 used to reflect EUV light. The EUV light is then directed toward an output port 119, through which the EUV light exits the EUV light source 110 to enter the remainder of the EUV lithography system 100. A droplet catcher 118 may be disposed opposite the target droplet generator 114. The droplet catcher 118 is used to capture additional target droplets 116.

[0124] In the EUV light source 110, the plasma 125 caused by the laser application generates EUV light and also generates physical residues, such as ions, gases and atoms of the droplets 116. In order to prevent the accumulation of particles and residues on the collector 176, a buffer gas can be injected along the surface of the collector mirror through the gas port 170. The buffer gas can be H2, He, Ar, N2 or some other inert gas, but is usually hydrogen. Hydrogen has a low EUV absorption profile. Hydrogen will react with metals to form metal hydrides. In detail, hydrogen will react with tin at the temperature of the EUV generation process to form SnH4 as a gaseous product, which can be captured and exhausted. The gaseous SnH4 is then exhausted out of the radiation source chamber 112.

[0125] Other residue collection mechanisms may also exist. For example, to further capture tin particles and other residues 101, the interior of the radiation source chamber 112 may include a plurality of blades 172 disposed around a conical support frame whose diameter narrows from the plasma field to the output port 119. The blades 172 typically extend radially inward from the support frame. The blades 172 may be made of, for example, molybdenum or stainless steel. The temperature of the blades 172 may be controlled to keep the tin in a liquid state but not a gaseous state, or in other words above about 231° C. but below about 1,100° C. (at the operating pressure of the EUV light source). For example, the blades 172 may include channels through which a liquid or gas may flow. The liquid or gas may be appropriately heated or cooled to obtain the desired temperature of the blades 172. The blades 172 may also be shaped to direct the liquid tin to an appropriate exhaust port, for example, via capillary action and / or wicking action. It should be understood that because gas molecules absorb EUV light, the radiation source chamber 112 is typically maintained in a vacuum or low pressure environment to avoid EUV intensity loss. Thus, the EUV lithography system 100 includes one or more vacuum pumps 174 / 186 that are fluidly coupled to the radiation source chamber 112 and operable in conjunction with a controller 190, such as Figure 1 As shown in the figure.

[0126] In some embodiments, the radiation source chamber 112 may be equipped with one or more sensors 180, 182, 184 that communicate with the controller 190, such as Figure 1 . In such embodiments, the one or more sensors 180, 182, and 184 may correspond to temperature sensors (thermocouples), pressure gauges, and / or flow meters, respectively. The operation of the radiation source chamber 112 may be controlled by a controller 190 based on the output of the one or more sensors 180, 182, 184, as will be appreciated by those skilled in the art.

[0127] Figure 1The EUV lithography system 100 depicted in FIG. 1 further includes a process chamber 142 in which a lithography scanner 104 is positioned to transfer a pattern from the reticle 102 to exposure fields 602, 604 (eg, Figure 6 As is usually the case in Figure 1 As shown in FIG. 1 , the lithography scanner 104 includes a reduced mask stage assembly 200 and a wafer stage assembly 300 for processing the wafer 160 .

[0128] 200 folding mask stage assembly Figure 2A and Figure 2B 100. In some embodiments, the reticle stage assembly 200 is used to move the reticle 102 in the x-direction, y-direction, and / or z-direction within the process chamber 142, as discussed below. The lithography scanner 104 may further include a wafer stage assembly 300 that is used to hold the wafer 160 and, in some embodiments, move in the x-direction, y-direction, and / or z-direction within the process chamber 142 during operation of the EUV lithography system 100.

[0129] Wafer stage assembly 300 Figure 3 100. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In illumination stage 130, EUV light may be collected and focused into a beam, for example using field facet mirror 132 that splits the beam into multiple light channels. These light channels may then be directed onto a plane of debulking reticle 102 using one or more relay mirrors 134. Projection optics module 150 may include refractive or reflective optics for carrying an image of the pattern defined by the reticle. Illustrative mirrors 152, 154 are shown. The pattern is then focused onto substrate 160, which may be, for example, a silicon wafer.

[0130] View now FIG. 2A to FIG. 2B , respectively, illustrate a side view and a bottom view of a reticle stage assembly 200 utilized by a lithography scanner 104 of an EUV lithography system 100 according to some embodiments. The reticle stage assembly 200 includes a reticle stage assembly body 202 for supporting the reticle 102 and conducting movement of the reticle 102 according to processing operations of the EUV lithography system 100. Figure 2A In the exemplary illustration of , the reticle stage 200 includes one or more motors 204 coupled to the reticle stage assembly body 202 , the one or more motors 204 being used to move the reticle stage assembly 200 in the x-direction and the y-direction during exposure processing of the EUV lithography system 100 . Figure 2A The reticle stage assembly 200 further illustrates one or more motors 206 coupled to the reticle stage body 202 and configured to move the reticle stage assembly 200 in the z-direction. Figure 2B A bottom view of a reticle stage assembly 200 is provided in accordance with some embodiments. Figure 2B As shown in FIG. 1 , the reticle stage assembly body 202 includes a reticle clamp 208 for holding the reticle 102 during operation of the EUV lithography system 100. In some embodiments, the reticle clamp 208 may be implemented as an electrostatic reticle clamp. Those skilled in the art will appreciate that other fastening members, fasteners, etc. may be utilized according to other embodiments.

[0131] Figure 3 An illustrative view of a wafer stage assembly 300 of a lithography scanner 104 utilized by an EUV lithography system 100 is provided in accordance with some embodiments. Figure 3 , wafer stage assembly 300 includes a wafer stage body 302 equipped with a wafer holding element, such as an electrostatic chuck 304, which is configured to hold wafer 160 for processing within lithography processing chamber 142. According to some embodiments, wafer stage assembly 300 may include one or more sensors (not shown) for sensing the position of wafer 160, the position of wafer stage assembly 300, temperature associated with electrostatic chuck 304 or wafer 160, speed, exposure power, duration, etc., or the like.

[0132] It should be understood that during the exposure process within the processing chamber 142, the reticle stage assembly 200 and the wafer stage assembly 300 may be moving relative to each other. The relative speed of the reticle stage assembly 200 and the wafer stage assembly 300 may be referred to as the scanner speed. In some embodiments, this speed may be the result of the following: movement of the reticle stage assembly 200 and the wafer stage assembly 300 relative to each other, movement of the reticle stage assembly 200 relative to a fixed position of the wafer stage assembly 300, movement of the wafer stage assembly 300 relative to a fixed position of the reticle stage assembly 200, etc. The operation of the EUV lithography system 100 will be described in more detail below in conjunction with the following description of the operation of the reticle stage assembly 200 and the wafer stage assembly 300. Figure 5 to understand using the method described in .

[0133] Now transfer to Figure 4, depicts an illustrative block diagram of a suitable control controller 190 associated with the EUV lithography system 100, the aforementioned reticle stage assembly 200, and the wafer stage 300 according to one embodiment of the present application. Various elements of the controller 190 may be controlled by a data / control bus 408. The processor 402 of the controller 190 communicates with an associated database 420 via a link 414. Suitable communication links 414 may include, for example, a switched telephone network, a wireless radio communication network, infrared, optical, or other suitable wired or wireless data communications. The database 420 can be implemented on an element of the controller 190, such as stored in a local memory 404, i.e., implemented on a hard drive, virtual drive, or the like, or on a remote memory accessible to the controller 190.

[0134] The associative database 420 represents any organized collection of data for one or more purposes (e.g., process tool information, manufacturing information, motor control information, scan speed information, photoresist information, process layout information, design information, material information, etc.). One skilled in the art will appreciate that this information is updated via machine learning during operation of the subject EUV lithography system 100. Implementation of the associative database 420 can occur on any mass storage device, such as a magnetic storage drive, a hard drive, an optical storage device, a flash memory device, or any combination thereof. The associative database 420 may be implemented as an element of the controller 190, such as residing in the memory 404, or the like. In one embodiment, the associative database 420 may include data corresponding to the process design layout 434, preset machine constants 436, reticle information 438, tool information, temperature information, and the like. In other embodiments, for example and without limitation, the database 420 may further include production scheduling, wafer positioning, process chamber information (e.g., type, location, status, etc.), and the like.

[0135] According to one embodiment, the process design layout 434 stored in the database 420 may correspond to a specific process protocol for the production of the wafer (e.g., materials to be used, reticles / reticles to be used, EUV energies to be applied, and the like). In some embodiments, the process design layout 434 may correspond to information related to the fields 602, 604 to be formed on the wafer 160. By way of example and not limitation, the process design layout 434 may include the number of fields, scan speed, exposure dose, recipe to be used, type of wafer 160, temperature constraints / requirements, and the like. The preset machine constants 436 stored in the database 420 may correspond to information related to a preset scan speed for the lithography scanner 104, as discussed in more detail below. The database 420 may further include reticle information 438 corresponding to information about a specific reticle 102, such as steady state temperature, thickness, material, corresponding recipe, and the like.

[0136] The controller 190 may include one or more input / output (I / O) interfaces 424 and 426 for communicating with external devices. The I / O interface 424 may communicate with one or more of the display devices 416 via the communication link 412 for displaying information such as an estimated destination, and with a user input device 418 such as a keyboard or a touch or writable screen for inputting text; and / or with a cursor control device such as a mouse, trackball, or the like for passing user input information and command selections to the processor 402. The I / O interface 422 may communicate with external devices such as the radiation source chamber 112, the process chamber 142, the retracted reticle stage assembly 200 (e.g., motors 204, 206), the retracted reticle clamp 208, the wafer stage assembly 300, the electrostatic chuck 304, and the like via a suitable communication link 108.

[0137] It should be understood that the diagram in Figure 4 The controller 190 in can be implemented using a distributed computing environment, such as a computer network, which represents any distributed communication system capable of exchanging data between two or more electronic devices. It should be further understood that such computer networks include, for example, but not limited to, virtual local area networks, wide area networks, personal area networks, local area networks, the Internet, corporate intranets, or any suitable combination thereof. Therefore, such computer networks include physical layers and transport layers as illustrated by various conventional data transmission structures, such as, for example, but not limited to, token rings, Ethernet networks, or other wireless or wired communication mechanisms. In addition, although in Figure 4 1 and 2. Although depicted as a networked collection of elements, the controller 190 can be implemented on a standalone device adapted to interact with the lithography system 100, the reticle stage assembly 200, and the wafer stage assembly 300 described herein.

[0138] Controller 190 may include one or more of a computer server, a workstation, a personal computer, a cellular phone, a notebook computer, a pager, a combination thereof, or other computing device capable of executing instructions for performing the illustrative methods.

[0139] According to an example embodiment, controller 190 includes hardware, software, and / or any suitable combination thereof for interacting with an associated user, a networked device, a networked storage, a remote device, or the like.

[0140] At Figure 4Memory 404, illustrated as an element of controller 190, may represent any type of non-transitory computer-readable medium, such as random access memory (RAM), read only memory (ROM), magnetic disk or tape, optical disk, flash memory, or holographic memory. In one embodiment, memory 404 includes a combination of random access memory and read only memory. In some embodiments, processor 402 and memory 404 may be combined into a single chip. Network interfaces 424, 426 allow the computer to communicate with other devices via a computer network and may include a modulator / demodulator (MODEM). Memory 404 may store data processed in the method and instructions for executing the exemplary method.

[0141] The digital processor 402 may be embodied in various ways, such as by a single core processor, a dual core processor (or more generally by a plurality of core processors), a digital processor and a cooperating mathematical coprocessor, a digital controller, or the like. The digital processor 402, in addition to controlling the operation of the controller 190, executes instructions 406 stored in the memory 404 for performing the methods described hereinafter.

[0142] like Figure 4 As shown in FIG. 1 , the instructions 406 stored in the memory 404 may include instructions for identifying each field 602, 604 in the process design layout 434 (more fully shown in FIG. 1 ). Figure 6 In some embodiments, the field identification element 428 is further used to identify each field 602, 604 as an edge field or a center field, wherein the edge field corresponds to a local field located on the edge of the wafer 160, and the center field corresponds to a full field formed on the wafer 160, as described below with respect to Figures 5 to 7C According to some embodiments, the determination made by the field identification element 428 regarding the field type may utilize information regarding the reticle 102, the size of the wafer 160, the location of the fields 602, 604 on the wafer 160 (as indicated by the process design layout 434), the exposure time, and the like.

[0143] like Figure 4As shown in FIG. 4 , the instructions 406 stored in the memory 404 may also include a scan speed determination element 430 for determining an optimal scan speed for processing the wafer 160 based on the process design layout 434. In some embodiments, the scan speed determination element 430 may be used to determine a maximum scan speed for each field 602, 604 of the process design layout 434. In such embodiments, the scan speed may be determined for each field 602, 604 based on its corresponding identification, for example, an edge field may have a slower or faster scan speed than a center field or a full field. Additional discussion regarding the determination of the optimal scan speed is provided below with respect to Figures 5 to 8 To present.

[0144] The instructions 406 stored in the memory 404 may further include a motor control element 432 for controlling the operation of the motors 204, 206 during operation of the EUV lithography system 100. According to some embodiments, the motor control element 432 may communicate with the reticle stage assembly 200 and the wafer stage assembly 300 to receive position data from the motor control element 432 and direct movement of the reticle stage assembly 200 and the wafer stage assembly 300 via control signals sent to the motors 204, 206. It should be appreciated that the control signals sent to the reticle stage assembly 200 and / or the wafer stage assembly 300 may direct movement in the x-direction, y-direction, and / or z-direction as desired by the EUV lithography system 100 during processing of the wafer 160. Thus, the motor control element 432 can move the reticle stage assembly 200 and / or the wafer stage assembly 300 to align the reticle 102 with a portion of the wafer 160 for exposure by the EUV lithography system 100. Figures 1 to 4 The various components and hardware described may be used to perform and implement the methods described in more detail below, for example, in Figure 5 The method is illustrated in a flow chart.

[0145] The term "software" as used herein is intended to encompass any collection or set of instructions that are executable by a computer or other digital system in order to configure the computer or other digital system to perform the tasks that are the purpose of the software. The term "software" as used herein is intended to encompass such instructions stored in storage media such as RAM, hard disks, optical disks, etc., and is also intended to encompass so-called "firmware" of software stored in ROM, etc. Such software may be organized in a variety of ways, and may include software elements organized as: libraries, Internet-type programs stored on remote servers, etc., source code, interpreted code, object code, directly executable code, etc. It is contemplated that the software may call system-level code or other software residing on a server or other location to perform certain functions.

[0146] The operation of EUV lithography system 100 will be combined with Figure 5 500 and the flowchart depicted in Figure 6 160. As used herein, downward scanning field 602 corresponds to exposure through the reticle 102 as the reticle stage assembly 200 is moving downward (toward the bottom) along the page (i.e., the y direction), and upward scanning field 604 corresponds to exposure through the reticle 102 as the reticle stage 200 is moving upward (toward the top) along the page (i.e., the y direction). Note that in Figure 6 In the scanning direction D scan is a vertical direction, and the downward scanning field 602 and the upward scanning field 604 are also indicated by different cross-hatching patterns. That is, the optimal scanning speed of the lithography scanner 104 is determined according to the different scanning lengths associated with the specific layout, thereby increasing the throughput of the EUV lithography system 100. It should be understood by those skilled in the art that this determination includes the use of specific details of the lithography scanner 104, such as the maximum / minimum moving speed of the multiplier reticle stage assembly 200 and / or the wafer stage assembly 300, the field size, the field scanning length, the orientation / position of the field on the wafer 160, and the like.

[0147] As depicted, the controller 190 or other suitable element associated with the EUV lithography system 100 receives at 502 a process design layout 434 corresponding to a layout to be used on the associated wafer 160. In some embodiments, the process design layout 434 includes exposure time, exposure power (e.g., dose, duration, etc.), and the like. At 504, a field scan length associated with each field 602, 604 is determined or determined by the controller 190 based on the process design layout 434. At step 506, preset machine constants 436 of the lithography scanner 104, such as acceleration, maximum / minimum scan speed, etc., are determined. In some embodiments, the preset machine constants 436 are retrieved from the database 420. In other embodiments, the preset machine constants 436 are determined based on operating characteristics of the motors 204, 206 that enable movement of the reticle stage assembly 200 and / or the wafer stage assembly 300.

[0148] Operation then proceeds to step 508, after which a type of column 606 of fields 602, 604 is identified by the controller 190 or other suitable element associated with the EUV lithography system 100. It should be appreciated that the process design layout 434 may include a plurality of columns 606, each column 606 containing one or more fields 602, 604. For example, in Figure 6, nine (9) rows 606 of fields 602, 604 are shown overlying wafer 160. One skilled in the art will appreciate that the number of rows 606 may depend on the size of wafer 160, the size of fields 602, 604, and the like. Figure 6 The diagram of is intended as a non-limiting example of the number of columns 606 and fields 602, 604. According to one embodiment, the columns 606 may be identified as center field only columns, edge field only columns, or a combination of edge field and center field columns. Fig. 7A , Figure 7B and Figure 7C Simplified illustrative examples of column types, namely, center field only columns 702, fringe field only columns 704, or a combination fringe field and center field columns 706, are provided respectively.

[0149] Therefore, in Fig. 7A In the figure, a wafer 700 is shown, and a plurality of fields 602 (downward scanning) and 604 (upward scanning) are formed according to the process design layout. (Furthermore, the scanning direction D scan yes Fig. 7A , Figure 7B and Figure 7C In the illustrative example of the vertical direction; in addition, the downward scanning field and the upward scanning field are also used for Figure 6 1 ). A center field row 702 is outlined, which contains only the center field, i.e., the full field 708 exposed / formed on the wafer 160. That is, the center field 708 corresponds to the usable portion of the wafer 160 where semiconductor devices are formed. In other words, the center field represents a portion of the wafer 160 intended for end use, i.e., a microprocessor, MEMS device, sensor, integrated circuit, etc. Figure 7B Only edge field columns 704 of wafer 700 are shown, corresponding to fields 710 located on the top and bottom edges of the wafer. Figure 7B As shown in FIG. 7 , each of the fields 710 located in the edge field row 704 corresponds to an incompletely formed field 710 of the exposure of the self-retracting reticle 102. That is, the portion of the wafer 700 in the edge field row 704 is an unusable portion and is not intended for end-use products. Figure 7C The diagram shows a combination of fringe field and center field array 706 that includes both center field 708 and fringe field 710. Figure 7C As shown in FIG. 7 , edge field 710 is depicted as being applied only to a portion of the edge of wafer 700 , while center field 708 of modular array 706 is fully exposed on wafer 700 . 7A to 7C As shown in FIG. 1 , each center field 708 is depicted as having a full scan length (where the full scan length is along the scan direction D scan ,that is, Fig. 7A , Figure 7B and Figure 7C, and a particular scan may be an upward scan or a downward scan, as indicated by different cross-hatching patterns), and each fringe field 710 has a scan length that is less than the full scan length (where less than the full scan length is again along the scan direction D scan ,that is, 7A to 7C , and further the upward direction or downward direction is indicated by different hatching patterns). Those skilled in the art will appreciate that 7A to 7C The depiction in is intended only to illustrate the contents of columns 702-706, and the wafer 160, 700 includes a plurality of such columns 702-706 depending on the size of the fields 708-710, the size of the wafer 700, and the like.

[0150] Back to Figure 5 , a determination is made at step 510 whether the column 606 has been identified as a center field column 702 only. After a positive determination, operation proceeds to 512, whereupon a determination is made as to the maximum scan speed of the field in this column 702. According to one embodiment, the full size field in the center of the wafer, i.e., the center column 702, may be a boundary condition. The determination of the maximum scan speed may therefore be determined by distinguishing the following two equations:

[0151] (Equation 1):

[0152]

[0153] (Equation 2):

[0154]

[0155] Where RS acceleration time corresponds to the time required to move the reticle stage assembly 200, "sca speed" corresponds to the scan speed, and "acceleration rate" corresponds to the acceleration differential where the acceleration does not reach the preset machine constant 436. Where the change in time in the direction of higher scan speed (acceleration) = the higher scan speed via the time gain, as in Figure 8 In some embodiments, the edge field row scanning speed is less than or equal to the center field row scanning speed, depending on the scan length and the preset machine constant 436. In other embodiments, the edge field row scanning speed is less than or equal to the center field row scanning speed, depending on the size of the fields 708, 710 and the preset machine constant 436. As a non-limiting example, if the scan length of the full fields 708 in the center field row 702 is 12 mm, the maximum scan speed of these full fields 708 will be 300 mm / s to obtain the best yield (e.g., Figure 8 ). Therefore, if the maximum machine scan speed is 500 mm / s and the full field scan length is 12 mm, the amount of time required to accelerate the lithography scanner 104 to the next field will not be equal to the optimal throughput. See, e.g. Fig.9A and Fig. 9B ,in Fig.9A The diagram shows a slow scan speed, a small acceleration time (as indicated by the thin arrow), and Fig. 9B The faster the scan speed, the longer the acceleration time (as indicated by the thick arrow), that is, the longer the acceleration required to achieve the fast scan speed. The operation then proceeds to step 514, after which it is determined whether any other columns 606 remain for identification. After a positive determination, the operation returns to step 508, and then the next column 606 is identified.

[0156] When it is determined at 510 that the identified column 606 is not a center-field-only column 702, operation proceeds to step 516, whereupon a determination is made as to whether the identified column 606 is a side-field-only column 704 (e.g., Figure 7B ). After a positive determination, the operation proceeds to step 518, whereupon the optimal or best scanning speed of the fringe field 710 is determined. In some embodiments, the optimal scanning speed of the fringe field 710 may be determined using the following equation:

[0157] (Equation 3)

[0158]

[0159] in:

[0160] t-exposure time = the time taken to scan the nth exposure;

[0161] v-scanning speed = exposure speed of scanning;

[0162] y-scan length = field size Y determined by layout in wafer area; and

[0163] s-step time = preparation scanning speed / time taken to move to the next field.

[0164] It will be appreciated that using the same scan speed for different scan lengths will not produce the best yield. Therefore, the above fitting method determines the minimum time and so that the single field scan speed for the longest scan field length is greater than or equal to the scan speed (s n ), the scan speed is greater than or equal to the single field scan speed of the shortest scan length field. In addition, using different scan speeds in the entire field (i.e., the center field 708 of the center field row 702) will induce additional movement distance and therefore does not produce optimal throughput. See Fig. 10C , Fig. 10CThe scan speed 1 of the illustrative center field 708 is shown compared to a different scan speed 2 of the illustrative fringe field 710, thus inducing an additional movement distance (and corresponding additional step time) 712. After determining the scan speed of the fringe field column 704, operation proceeds to step 514 to determine which other columns 606 remain for processing. After a positive determination operation returns to step 508, and the next column 606 is then identified.

[0165] When it is determined at 510 that the identified column 606 is not a center field only column 702, the operation proceeds to step 516, where it is then determined whether the identified column 606 is a fringe field only column 704. When it is determined at 516 that the identified column 606 is not a fringe field column 704, the operation proceeds to step 520, where it is then determined whether the identified column 606 is a fringe field and center field combination column 706 (e.g., Figure 7C ). After a positive determination, operation proceeds to step 522, whereupon an optimum or best scan speed for the fringe field 710 is determined. In combined column 706, portions of the center field 708 may utilize the previously determined scan speed (step 512), and portions of the fringe field 710 may utilize the determined scan speed (step 518).

[0166] After determining at 520 that the identified row 606 is not a combined edge field and center field row 706, operation returns to step 514, whereupon a determination is made whether another row 606 remains for processing. After a negative determination at step 514 that no more rows 606 remain for processing, operation proceeds to step 524, whereupon operation of the EUV lithography system 100 begins on the wafer 160, using the determined scan speed for each identified row 606. FIG. 10A to FIG. 10C An illustrative view of the difference in scan length of the fringe field 710 relative to the scan length of the center field 708 is provided according to some embodiments, wherein Fig. 10B Draw on Fig. 10A An enlarged view of the area 720 indicated in FIG. Fig. 10B and Fig. 10C Provide as Fig. 10B 1 and 2, and the wafer stage assembly (WS) 300 during the scanning operation of the lithography scanner 104. FIG. 10A to FIG. 10C As shown in , the scan speed of the lithography scanner 104 may not be limited to reduce the acceleration time loss (ie, step time) due to shortening the scan field length. This situation produces greater throughput than an unlimited scan speed over a relatively small scan length of the fringe field 710.

[0167] Now transfer to Fig.11, a flow chart illustrating another embodiment of a method 1100 for optimizing a scan speed of a lithography scanner 104 is shown. The method 1100 begins at step 1102, after which the controller 190 or other suitable element associated with the EUV lithography system 100 receives a process design layout 434 corresponding to a layout to be used on an associated wafer 160. At 1104, a field scan length (A) associated with each field 708, 710 is determined or determined by the controller 190 based on the process design layout 434. At step 1106, preset machine constants 436, such as acceleration, maximum / minimum scan speed, etc., for the lithography scanner 104 are determined. In some embodiments, the preset machine constants 436 are retrieved from the database 420. In other embodiments, the preset machine constants 436 are determined based on operating characteristics of the motors 204, 206 that enable movement of the reticle stage assembly 200 and / or the wafer stage assembly 300.

[0168] At step 1108, the scan length (B) is determined based on the acceleration time loss and the scanner maximum time gain (i.e., the preset machine constant 436). At 1110, it is determined whether A>B, and the operation then proceeds to step 1112, such that the increased scan speed obtained is greater than the acceleration loss, resulting in the need to limit the scan speed of the lithography scanner 104 at 1114 (i.e., only the center field 708 exists, indicating the full scan length (A)). After determining at 1110 that the edge or center scan length (A) is less than the scan length (B), the operation proceeds to 1116, and then the fields 708-710 apply Equation 1, Equation 2, or Equation 3 (defined above). Therefore, at step 1118, the scanning speed of the lithography scanner 104 is limited to reduce the acceleration time loss of the short scan length field (e.g., the fringe field 710), thereby producing a greater throughput compared to the application of unlimited scanning speed for the relatively small scan length field (i.e., the fringe field 710) at step 1120. Fig. 12A and Fig. 12B A comparative example of output performance according to some embodiments is provided. Fig. 12A The graphical depictions do not use the outputs of the systems and methods described herein, and Fig. 12B Depicts the output of utilizing the systems and methods described above.

[0169] According to a first embodiment, a method for optimizing scan speed for increased throughput in a lithography apparatus is provided. The method includes receiving a process design layout corresponding to a plurality of fields to be formed on an associated wafer; and determining a field scan length based on the received process design layout. The method also includes identifying a type of each field column corresponding to the received process design layout. The type of field column is selected from the group consisting of: a center field column, an edge field column, or an edge field and center field combination column. The method further includes determining a center field column scan speed for a column identified as a center field column, an edge field column scan speed for a column identified as an edge field column, and an edge field and center field combination column scan speed for a column identified as an edge field and center field combination column. In this case, the edge field and center field combination column scan speed uses the center field column scan speed for each center field in the edge field and center field combination column and uses the edge field column scan speed for each edge field in the edge field and center field combination column. Thereafter, the associated wafer is processed using the center field row scanning speed, the edge field row scanning speed, and the edge field and center field combined row scanning speed according to the process design layout. In some embodiments of the present disclosure, the step of determining the edge field row scanning speed further includes determining an exposure time, a scan length, and a step time. In some embodiments of the present disclosure, the lithography device is an extreme ultraviolet lithography device.

[0170] According to a second embodiment, a method for optimizing the scanning speed of a lithography scanner is provided. The method includes receiving a process design layout corresponding to a plurality of field columns to be formed on an associated wafer. The method further includes determining a preset machine constant of the lithography device, and identifying a type of each of the plurality of field columns corresponding to the received process design layout. The method also includes determining a scanning speed based on the determined column type and the determined preset machine constant. The associated wafer is then processed using the determined scanning speed for each of the plurality of field columns according to the process design layout. In some embodiments of the present disclosure, the step of determining the preset machine constant further includes: determining a moving speed of the scaled mask stage assembly; and determining a moving speed of the wafer stage assembly. In some embodiments of the present disclosure, the step of determining a scan speed further includes: determining the center field row scan speed of each of the plurality of field rows identified as a center field row; determining an edge field row scan speed of each of the plurality of field rows identified as an edge field row; and determining an edge field and center field combination row scan speed of each of the plurality of field rows identified as an edge field and center field combination row, wherein the edge field and center field combination row scan speed uses the center field row scan speed for each center field in the edge field and center field combination row and uses the edge field row scan speed for each edge field in the edge field and center field combination row. In some embodiments of the present disclosure, the steps of determining the center field row scan speed, the edge field row scan speed, and the edge field and center field combination row scan speed are performed according to the preset machine constant. In some embodiments of the present disclosure, the determined edge field row scan speed is less than or equal to the center field row scan speed according to a scan length and the preset machine constant. In some embodiments of the present disclosure, each center field is a full scan length, and each edge field has a scan length less than the full scan length. In some embodiments of the present disclosure, the step of determining the fringe field row scanning speed further comprises the following steps: determining an exposure time, a scanning length and a step time. In some embodiments of the present disclosure, the lithography scanner device is an extreme ultraviolet lithography device.

[0171] According to a third embodiment, a system for optimizing the scanning speed of a lithography scanner is provided. The system includes a reticle stage assembly, a wafer stage assembly, and a controller. The reticle stage assembly includes a reticle, and one or more motors for movement in the x-direction and the y-direction. The wafer stage assembly includes a wafer stage body, and a wafer holding element for holding a wafer. The controller includes a processor in communication with a memory. The memory stores instructions that are executed by the processor to receive a process design layout corresponding to a plurality of fields to be formed on the wafer; and identify each of the fields as a center field or an edge field. The memory further stores instructions to determine an optimal scanning speed for each of the fields according to the identified field type via a scanning speed determination element, and to activate the one or more motors based on the determined optimal scanning speed for each via a motor control element. In some embodiments of the present disclosure, the memory further stores instructions to determine a preset machine constant. In some embodiments of the present disclosure, the preset machine constant corresponds to a movement speed of the reticle stage assembly and a movement speed of the wafer stage assembly. In some embodiments of the present disclosure, the memory further stores instructions to further perform the following steps: determining a center field row scanning speed for each of the plurality of rows identified as a center field row; determining a fringe field row scanning speed for each of the plurality of rows identified as an fringe field row; and determining a fringe field and center field combination row scanning speed for each of the plurality of rows identified as a fringe field and center field combination row, wherein the fringe field and center field combination row scanning speed uses the center field row scanning speed for each center field in the fringe field and center field combination row, and uses the fringe field row scanning speed for each fringe field in the fringe field and center field combination row. In some embodiments of the present disclosure, each of the center field row scanning speed, the fringe field row scanning speed, and the fringe field and center field combination row scanning speed is determined according to a preset machine constant. In some embodiments of the present disclosure, the fringe field row scanning speed is determined to be less than or equal to the center field row scanning speed based on a field size and the predetermined machine constant. In some embodiments of the present disclosure, each center field is a full scan length, and each fringe field has a scan length less than the full scan length. In some embodiments of the present disclosure, the step of determining the fringe field row scanning speed further includes the steps of determining an exposure time, a scan length, and a step time. In some embodiments of the present disclosure, the lithography scanner device is an extreme ultraviolet lithography device.

[0172] Some portions of the detailed description herein are presented in terms of algorithms and symbolic representations of operations on data bits, which are performed by conventional computer components including a central processing unit (CPU), memory storage devices of the CPU, and connected display devices. These algorithmic descriptions and representations are used by those skilled in the art of data processing to most effectively convey the essence of their work to those skilled in the art. An algorithm is generally viewed as a self-consistent series of steps leading to a desired result. The steps are those steps requiring physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, or otherwise manipulated. It has proven convenient at times to refer to these signals as bits, values, components, symbols, characters, terms, numbers, or the like, in principle for common reasons.

[0173] It should be understood, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise, as will be apparent from the discussion herein, it should be understood that throughout the description, discussions utilizing terms such as "processing" or "computing" or "verifying" or "determining" or "displaying" or the like refer to the actions and procedures of computer systems or similar electronic computing devices that manipulate data and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage, transmission or display devices.

[0174] The exemplary embodiments also relate to an apparatus for performing the operations discussed herein. This apparatus may be specially constructed for the required purposes, or the apparatus may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions and each coupled to a computer system bus.

[0175] The algorithms and displays presented herein are not inherently about any particular computer or other device. Various general purpose systems are used with the programs according to the teachings herein, or it may prove convenient to build more specialized devices to perform the methods described herein. The structures for a variety of these systems are apparent from the above description. In addition, the exemplary embodiments are not described with reference to any particular programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the exemplary embodiments as described herein.

[0176] Machine-readable media include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, machine-readable media include read-only memory ("ROM"); random access memory ("RAM"); magnetic disk storage media; optical storage media; flash memory devices; and electrical, optical, ultrasonic or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), to name just a few.

[0177] The methods illustrated throughout the specification may be implemented in a computer program product that can be executed on a computer. The computer program product may include a non-transitory computer-readable storage medium such as a disk, hard disk, or the like, where the control program is recorded. Common forms of non-transitory computer-readable media include, for example, a floppy disk, a flexible disk, a hard disk, a tape, or any other magnetic storage medium, a CD-ROM, a DVD, or any other optical medium, a RAM, a PROM, an EPROM, a FLASH-EPROM, or other memory chips or cartridges, or any other tangible medium that a computer can read and use.

[0178] Alternatively, the method may be implemented in a transient medium such as a transmission carrier wave in which the control program is embodied as a data signal using a transmission medium such as ultrasonic or light waves, such as those generated during radio wave and infrared data communications, and the like.

[0179] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for optimizing scanning speed to increase the throughput of a lithography device, the lithography device comprising a double-shrink mask stage assembly and a wafer stage assembly, characterized in that: The method comprises the following steps: receiving a process design layout corresponding to a plurality of fields to be formed on an associated wafer; Determining a full-field scanning length according to the received process design layout; Determining a preset machine constant includes determining a moving speed of the reticle stage assembly and determining a moving speed of the wafer stage assembly; identifying a type of each of a plurality of field rows corresponding to the received process design layout, wherein the type of field row is selected from a group consisting of a center field row, an edge field row, or a combination of edge field and center field row; determining a center field row scanning speed for each of the plurality of field rows identified as a center field row; determining a fringe field row scanning speed for each of the plurality of field rows identified as a fringe field row; determining a fringe field and center field combination column scan speed for each of the plurality of field columns identified as a fringe field and center field combination column, wherein the fringe field and center field combination column scan speed uses the center field column scan speed for each center field in the fringe field and center field combination column and uses the fringe field column scan speed for each fringe field in the fringe field and center field combination column; and Processing the associated wafer using the center field column scanning speed, the edge field column scanning speed, and the edge field and center field combined column scanning speed according to the process design layout, wherein each center field is the full field scan length, and each edge field has a scan length that is less than the full field scan length; wherein the step of determining the center field row scanning speed, the edge field row scanning speed, and the edge field and center field combined row scanning speed is performed according to the preset machine constant; and The step of determining the center field row scanning speed further includes the following steps: distinguishing a scanning time of the lithography device from an acceleration time of the multiplied photomask stage assembly.

2. The method according to claim 1, characterized in that The step of determining the fringe field row scanning speed further includes the following steps: determining an exposure time, a scanning length and a step time.

3. The method according to claim 1, characterized in that The lithography device is an extreme ultraviolet lithography device.

4. A method for optimizing the scanning speed of a lithography scanner device, the lithography scanner device comprising a reduced mask stage assembly and a wafer stage assembly, characterized in that: The method comprises the following steps: receiving a process design layout corresponding to a plurality of field columns to be formed on an associated wafer; determining a predetermined machine constant of the lithography scanner device; identifying a type of each of the plurality of field rows corresponding to the received process design layout, wherein the type of field row is selected from a group consisting of a center field row, an edge field row, or a combination of edge field and center field row; Determining a scanning speed according to the determined type of field sequence and the determined preset machine constant; and using the determined scan speed for each of the plurality of field columns to process the associated wafer according to the process design layout; The step of determining a center field row scanning speed further includes the following steps: distinguishing a scanning time of the lithography scanner device from an acceleration time of the multiplied mask stage assembly.

5. The method according to claim 4, characterized in that The step of determining the preset machine constant further comprises the following steps: Determining a moving speed of the reticle stage assembly; and A moving speed of the wafer stage assembly is determined.

6. The method according to claim 4, characterized in that The step of determining a scanning speed further comprises the following steps: determining a center field row scan speed for each of the plurality of field rows identified as a center field row; determining a fringe field row scanning speed for each of the plurality of field rows identified as a fringe field row; and Determine an edge field and center field combination column scanning speed for each of the multiple field columns identified as an edge field and center field combination column, wherein the edge field and center field combination column scanning speed uses the center field column scanning speed for each center field in the edge field and center field combination column and uses the edge field column scanning speed for each edge field in the edge field and center field combination column.

7. The method according to claim 6, characterized in that The steps of determining the center field column scanning speed, the fringe field column scanning speed, and the fringe field and center field combined column scanning speed are performed according to the preset machine constants.

8. The method according to claim 7, characterized in that The edge field row scanning speed is determined to be less than or equal to the center field row scanning speed according to a scanning length and the preset machine constant.

9. The method according to claim 4, characterized in that Each center field is a full scan length, and each edge field has a scan length that is less than the full scan length.

10. A system for optimizing the scanning speed of a lithography scanner device, characterized in that: The system includes: A one-fold reduction mask stage assembly, which includes a one-fold reduction mask and at least one motor for movement in the x-direction and the y-direction; A wafer stage assembly, comprising a wafer stage body and a wafer holding element, the wafer holding element being used to hold a wafer thereon; and A controller includes a processor in communication with a memory storing a plurality of instructions executed by the processor to perform the following steps: receiving a process design layout corresponding to a plurality of fields to be formed on the wafer, identifying each of the fields as a center field or a peripheral field via a field identification element, Determining an optimal scanning speed of each of the fields according to the identified field type via a scanning speed determination element, wherein the step of determining an optimal scanning speed of the center field comprises the following steps: distinguishing a scanning time of the lithography scanner device from an acceleration time of the multiplied reticle stage assembly, and The at least one motor is activated via a motor control element according to the optimal scanning speed determined for each of the fields.

Images