Hardware accelerator based on Montgomery and Barrett and implementation method thereof

Abstract

The invention relates to the technical field of hardware acceleration, and discloses a hardware accelerator based on Montgomery and Barrett and an implementation method of the hardware accelerator based on Montgomery and Barrett. The control module is used for forming a Montgomery modular multiplication operation mode when the mode signal is a first signal and forming a Barrett modular multiplication operation mode when the mode signal is a second signal; and a modular multiplication module for performing a Montgomery modular multiplication operation on the operational data in a Montgomery modular multiplication operation mode, and for performing a Barrett modular multiplication operation on the operational data in a Barrett modular multiplication operation mode. The modular multiplication operation module is switched between the Montgomery modular multiplication operation mode and the Barrett modular multiplication operation mode through the control module according to the mode signal, so that the hardware accelerator supports the Montgomery modular multiplication operation and also supports the Barrett modular multiplication operation, different scenes can be selected and flexibly adapted according to requirements, and the applicability of the hardware accelerator is improved.

Description

Technical Field

[0001] The present invention relates to the field of privacy computing hardware acceleration technology, and in particular to a hardware accelerator based on Montgomery and Barrett, a method for implementing a hardware accelerator based on Montgomery and Barrett, and a security chip. Background Art

[0002] Modular multiplication of large numbers is widely used in the field of privacy computing and is in high demand. However, this type of calculation involves division when performing modular operations. The internal processing is relatively complex and extremely computationally intensive. Therefore, when designing hardware acceleration for privacy computing, the modular operations in modular multiplication are converted into other simple operations. Based on this idea, the Montgomery modular multiplication algorithm and the Barrett modular multiplication algorithm were proposed. Their essence is to convert all modular multiplications into multiplication, shift, addition, and comparison and selection operations, avoiding division operations, and combining the acceleration effect of customized hardware design to improve computing performance.

[0003] For different application scenarios, the Montgomery modular multiplication algorithm and the Barrett modular multiplication algorithm each have their own advantages and disadvantages. Specifically, the Montgomery modular multiplication can normalize the number in Montgomery form and avoid division in modular operations, but it may require additional storage space, and the modulus N and the parameter R need to be relatively prime; the Barrett modular multiplication calculation process is relatively simple, and the calculation speed may be faster than the Montgomery modular multiplication when the processing is relatively not complicated, but for some large moduli, there is a problem of inefficient calculation.

[0004] However, the hardware design solutions in the prior art usually only support one modular multiplication algorithm, which is not compatible, flexible enough, and cannot adapt to various scenarios.

[0005] Therefore, providing a modular multiplication algorithm hardware accelerator that can adapt to a variety of computing scenarios has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0006] The present invention provides a hardware accelerator based on Montgomery and Barrett, a method for implementing a hardware accelerator based on Montgomery and Barrett, and a security chip, so as to solve the problems existing in the related art that the hardware accelerators often only support one modular multiplication algorithm, are not compatible, are not flexible enough, and cannot adapt to multiple scenarios.

[0007] As a first aspect of the present invention, a hardware accelerator based on Montgomery and Barrett is provided, comprising: a signal acquisition module, a control module and a modular multiplication operation module;

[0008] The modular multiplication operation module is electrically connected to the signal acquisition module and the control module respectively, and the signal acquisition module is also electrically connected to the control module;

[0009] The signal acquisition module is used to acquire the mode signal and operation data input by the user, wherein the operation data at least includes the number to be operated, the modulus and the fusion parameter;

[0010] The control module is used to form a Montgomery modular multiplication operation mode according to the first signal when the mode signal is the first signal; and is used to form a Barrett modular multiplication operation mode according to the second signal when the mode signal is the second signal;

[0011] The modular multiplication operation module is used to perform Montgomery modular multiplication operation on the operation data in the Montgomery modular multiplication operation mode, and is used to perform Barrett modular multiplication operation on the operation data in the Barrett modular multiplication operation mode.

[0012] Further, the modular multiplication operation module includes a Montgomery modular multiplication operation dedicated submodule, a Barrett modular multiplication operation dedicated submodule and a modular multiplication operation shared submodule;

[0013] The Montgomery modular multiplication operation dedicated submodule and the Barrett modular multiplication operation dedicated submodule are electrically connected to the modular multiplication operation shared submodule respectively, the Montgomery modular multiplication operation dedicated submodule and the Barrett modular multiplication operation dedicated submodule are also electrically connected to the control module respectively, and the modular multiplication operation shared submodule is also electrically connected to the signal acquisition module;

[0014] The modular multiplication operation common submodule is used to perform the operation operations commonly required by the Montgomery modular multiplication operation and the Barrett modular multiplication operation, wherein the commonly required operation operations include multiplication operation, shift operation, subtraction operation, comparison operation and selection operation;

[0015] The Montgomery modular multiplication operation dedicated submodule is used to perform the addition operation dedicated to the Montgomery modular multiplication operation;

[0016] The Barrett modular multiplication operation dedicated submodule is used to perform subtraction operations dedicated to the Barrett modular multiplication operation.

[0017] Further, the modular multiplication operation shared submodule includes: a first multiplication unit, a second multiplication unit, a third multiplication unit, a first shift unit, a second shift unit, a third shift unit, a first subtraction unit, a first comparison unit and a first selection unit;

[0018] The first shift unit is electrically connected to the first multiplication unit and the second multiplication unit, respectively; the second shift unit is electrically connected to the second multiplication unit and the third multiplication unit, respectively; the third shift unit is electrically connected to the third multiplication unit, the first selection unit is electrically connected to the first subtraction unit and the first comparison unit, respectively; the first shift unit, the third shift unit, the first subtraction unit, the first comparison unit and the first selection unit are all electrically connected to the Montgomery modular multiplication operation dedicated submodule; the first shift unit, the third shift unit, the first subtraction unit, the first comparison unit and the first selection unit are all electrically connected to the Barrett modular multiplication operation dedicated submodule;

[0019] In Montgomery modular multiplication mode:

[0020] The first multiplication unit is used to calculate the product of the operands to be operated;

[0021] The first shift unit is used to shift the operation result of the first multiplication unit to the right and output it to the Montgomery modular multiplication operation dedicated submodule, and is used to shift the operation result of the first multiplication unit to the left and output it to the second multiplication unit;

[0022] The second multiplication unit is used to calculate the product of the left shift result of the first shift unit and the fusion parameter;

[0023] The second shift unit is used for shifting the operation result of the second multiplication unit to the left;

[0024] The third multiplication unit is used to calculate the product of the shift result of the second shift unit and the modulus;

[0025] The third shift unit is used for shifting the operation result of the third multiplication unit to the right and outputting it to the Montgomery modular multiplication operation dedicated submodule;

[0026] The first comparison unit is used to compare the operation result of the Montgomery modular multiplication operation dedicated submodule with the size of the modulus;

[0027] The first subtraction unit is used to calculate the difference between the operation result of the Montgomery modular multiplication operation dedicated submodule and the modulus;

[0028] The first selection unit is used to output the operation result of the first subtraction unit when the operation result of the Montgomery modular multiplication operation dedicated submodule is greater than the modulus, and is used to output the operation result of the Montgomery modular multiplication operation dedicated submodule when the operation result of the Montgomery modular multiplication operation dedicated submodule is less than the modulus;

[0029] In Barrett modular multiplication mode:

[0030] The first multiplication unit is used to calculate the product of the operands to be operated;

[0031] The first shift unit is used to output the operation result of the first multiplication unit to the Barrett modular multiplication operation dedicated submodule, and is used to shift the operation result of the first multiplication unit and output the shift result to the second multiplication unit;

[0032] The second multiplication unit is used to calculate the product of the shift result of the first shift unit and the fusion parameter;

[0033] The second shift unit is used to shift the operation result of the second multiplication unit;

[0034] The third multiplication unit is used to calculate the product of the shift result of the second shift unit and the modulus;

[0035] The third shift unit is used to output the operation result of the third multiplication unit to the Barrett modular multiplication operation dedicated submodule;

[0036] The first comparison unit is used to compare the operation result of the Barrett modular multiplication operation dedicated submodule with the size of the modulus;

[0037] The first subtraction unit is used to calculate the difference between the operation result of the Barrett modular multiplication operation dedicated submodule and the modulus;

[0038] The first selection unit is used to output the operation result of the first subtraction unit when the operation result of the Barrett modular multiplication operation dedicated submodule is greater than the modulus, and is used to output the operation result of the Barrett modular multiplication operation dedicated submodule when the operation result of the Barrett modular multiplication operation dedicated submodule is less than the modulus.

[0039] Further, the Montgomery modular multiplication operation dedicated submodule includes: a first adding unit;

[0040] The first adding unit is electrically connected to the first shifting unit, the third shifting unit, the first subtracting unit, the first comparing unit and the first selecting unit respectively;

[0041] The first adding unit is used to calculate the sum of a result of the right shift by the first shift unit and a result of the right shift by the third shift unit.

[0042] Further, the Barrett modular multiplication operation dedicated submodule includes: a second subtraction unit;

[0043] The second subtraction unit is electrically connected to the first shift unit, the third shift unit, the first subtraction unit, the first comparison unit and the first selection unit respectively;

[0044] The second subtraction unit is used to calculate a difference between the operation result of the first multiplication unit and the result of subtracting the third shift unit.

[0045] Further, the control module includes: a second selection unit and a third selection unit;

[0046] The second selection unit is electrically connected to the third selection unit, the second selection unit is also electrically connected to the first addition unit, the second subtraction unit, the first comparison unit and the first subtraction unit, and the third selection unit is also electrically connected to the first selection unit and the first shift unit;

[0047] The second selection unit is used to select the operation result of the Montgomery modular multiplication operation dedicated submodule according to the first signal to form a Montgomery modular multiplication operation mode, and is used to select the operation result of the Barrett modular multiplication operation dedicated submodule according to the second signal to form a Barrett modular multiplication operation mode;

[0048] The third selection unit is used to output the operation result of the second selection unit and send it to the first selection unit.

[0049] Furthermore, in the Barrett modular multiplication operation mode, the bit widths of the multiplier and the multiplicand are both twice the bit width of the modulus.

[0050] As another aspect of the present invention, a method for implementing a hardware accelerator based on Montgomery and Barrett is provided, comprising: obtaining a mode signal and operation data input by a user, wherein the operation data at least includes a to-be-operated number, a modulus, and a fusion parameter;

[0051] When the mode signal is the first signal, a Montgomery modular multiplication operation mode is formed according to the first signal; when the mode signal is the second signal, a Barrett modular multiplication operation mode is formed according to the second signal;

[0052] In the Montgomery modular multiplication operation mode, a Montgomery modular multiplication operation is performed on the operation data, and in the Barrett modular multiplication operation mode, a Barrett modular multiplication operation is performed on the operation data.

[0053] As another aspect of the present invention, a security chip is provided, including a chip carrier and the above-mentioned Montgomery and Barrett-based hardware accelerator arranged on the chip carrier.

[0054] Furthermore, the chip carrier includes FPGA or ASIC.

[0055] The present invention switches the modular multiplication operation module between the Montgomery modular multiplication operation mode and the Barrett modular multiplication operation mode according to the mode signal through the control module, so that the hardware accelerator supports both the Montgomery modular multiplication operation and the Barrett modular multiplication operation, which can be selected according to the needs, flexibly adapt to different scenarios, and improve the applicability of the hardware accelerator. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention, but do not constitute a limitation of the present invention.

[0057] Figure 1 It is a brief structural diagram of the hardware accelerator based on Montgomery and Barrett provided by the present invention.

[0058] Figure 2 It is a brief structural diagram of the modular multiplication operation module provided by the present invention.

[0059] Figure 3 It is a brief structural diagram of the modular multiplication operation shared submodule provided by the present invention.

[0060] Figure 4 The figure is a brief structural diagram of the Montgomery modular multiplication operation dedicated submodule provided by the present invention.

[0061] Figure 5 It is a schematic diagram of the Montgomery modular multiplication operation mode provided by the present invention.

[0062] Figure 6 It is a brief structural diagram of the Barrett modular multiplication operation dedicated submodule provided by the present invention.

[0063] Figure 7 It is a schematic diagram of the Barrett modular multiplication operation mode provided by the present invention.

[0064] Figure 8 It is a brief structural diagram of the control module provided by the present invention.

[0065] Fig. 9 It is a schematic diagram of a hardware accelerator based on Montgomery and Barrett provided for the present invention.

[0066] Fig.10 It is a flow chart of a method for implementing a hardware accelerator based on Montgomery and Barrett provided by the present invention. DETAILED DESCRIPTION

[0067] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0068] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of the present invention.

[0069] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0070] The embodiment of the present invention provides a hardware accelerator 100 based on Montgomery and Barrett, such as Figure 1As shown, it includes: a signal acquisition module 110, a control module 120 and a modular multiplication operation module 130;

[0071] The modular multiplication operation module 130 is electrically connected to the signal acquisition module 110 and the control module 120 respectively, and the signal acquisition module 110 is also electrically connected to the control module 120;

[0072] The signal acquisition module 110 is used to acquire the mode signal and operation data input by the user, wherein the operation data at least includes a number to be operated, a modulus and a fusion parameter;

[0073] Specifically, the mode signal is the mode signal, and the operands include a multiplier and a multiplicand. In an embodiment of the present invention, op1 and op2 are used to represent the multiplier and the multiplicand respectively, q is used to represent the modulus, and the fusion parameters include the fusion parameters in the Montgomery modular multiplication operation and the fusion parameters in the Barrett modular multiplication operation. The fusion parameters in the Montgomery modular multiplication operation are represented by N', and the fusion parameters in the Barrett modular multiplication operation are represented by H.

[0074] The control module 120 is used to form a Montgomery modular multiplication operation mode according to the first signal when the mode signal is the first signal; and to form a Barrett modular multiplication operation mode according to the second signal when the mode signal is the second signal;

[0075] When the mode signal is the first signal, specifically when the mode signal is 0, the control module 120 controls the modular multiplication operation module 130 to form the Montgomery modular multiplication operation mode according to the first signal; when the mode signal is the second signal, specifically when the mode signal is 1, the control module 120 controls the model operation module 130 to form the Barrett modular multiplication operation mode according to the second signal.

[0076] The modular multiplication operation module 130 is used to perform a Montgomery modular multiplication operation on the operation data in a Montgomery modular multiplication operation mode, and is used to perform a Barrett modular multiplication operation on the operation data in a Barrett modular multiplication operation mode.

[0077] In the embodiment of the present invention, the control module 120 switches the modular multiplication operation module 130 between the Montgomery modular multiplication operation mode and the Barrett modular multiplication operation mode according to the mode signal obtained by the signal acquisition module 110, so that the hardware accelerator can support both Montgomery modular multiplication operation and Barrett modular multiplication operation, can select the appropriate algorithm according to the needs, and flexibly adapt to different application scenarios, thereby improving the applicability and flexibility of the hardware accelerator.

[0078] Furthermore, if Figure 2 As shown, the modular multiplication operation module 130 includes a Montgomery modular multiplication operation dedicated submodule 131, a Barrett modular multiplication operation dedicated submodule 132 and a modular multiplication operation shared submodule 133;

[0079] The Montgomery modular multiplication operation dedicated submodule 131 and the Barrett modular multiplication operation dedicated submodule 132 are respectively electrically connected to the modular multiplication operation shared submodule 133, the Montgomery modular multiplication operation dedicated submodule 131 and the Barrett modular multiplication operation dedicated submodule 132 are also respectively electrically connected to the control module 120, and the modular multiplication operation shared submodule 133 is also electrically connected to the signal acquisition module 110;

[0080] The modular multiplication operation sharing submodule 133 is used to perform the operation operations required by the Montgomery modular multiplication operation and the Barrett modular multiplication operation, wherein the required operation operations include multiplication operation, shift operation, subtraction operation, comparison operation and selection operation;

[0081] Specifically, Figure 3 As shown, in the embodiment of the present invention, the modular multiplication operation shared submodule 133 includes: a first multiplication unit 133-1, a second multiplication unit 133-2, a third multiplication unit 133-3, a first shift unit 133-4, a second shift unit 133-5, a third shift unit 133-6, a first subtraction unit 133-7, a first comparison unit 133-8 and a first selection unit 133-9;

[0082] The first shift unit 133-4 is electrically connected to the first multiplication unit 133-1 and the second multiplication unit 133-2, respectively; the second shift unit 133-5 is electrically connected to the second multiplication unit 133-2 and the third multiplication unit 133-3, respectively; the third shift unit 133-6 is electrically connected to the third multiplication unit 133-3, the first selection unit 133-9 is electrically connected to the first subtraction unit 133-7 and the first comparison unit 133-8, respectively; the first shift unit 133-4, the third shift unit 133-6, the first subtraction unit 133-7, the first comparison unit 133-8 and the first selection unit 133-9 are all electrically connected to the Montgomery modular multiplication operation dedicated submodule 131; the first shift unit 133-4, the third shift unit 133-6, the first subtraction unit 133-7, the first comparison unit 133-8 and the first selection unit 133-9 are all electrically connected to the Barrett modular multiplication operation dedicated submodule 132;

[0083] In Montgomery modular multiplication mode:

[0084] The first multiplication unit 133-1 is used to calculate the product of the operands to be operated;

[0085] The first shift unit 133-4 is used to shift the operation result of the first multiplication unit 133-1 to the right and output it to the Montgomery modular multiplication operation dedicated submodule 131, and to shift the operation result of the first multiplication unit 133-1 to the left and output it to the second multiplication unit 133-2;

[0086] The second multiplication unit 133-2 is used to calculate the product of the left shift result of the first shift unit 133-4 and the fusion parameter;

[0087] The second shift unit 133-5 is used to shift the operation result of the second multiplication unit 133-2 to the left;

[0088] The third multiplication unit 133-3 is used to calculate the product of the shift result of the second shift unit 133-5 and the modulus;

[0089] The third shift unit 133-6 is used to shift the operation result of the third multiplication unit 133-3 to the right and output it to the Montgomery modular multiplication operation dedicated submodule 131;

[0090] The first comparison unit 133-8 is used to compare the operation result of the Montgomery modular multiplication operation dedicated submodule 131 with the size of the modulus;

[0091] The first subtraction unit 133-7 is used to calculate the difference between the operation result of the Montgomery modular multiplication operation dedicated submodule 131 and the modulus;

[0092] The first selection unit 133-9 is used to output the operation result of the first subtraction unit 133-7 when the operation result of the Montgomery modular multiplication operation dedicated submodule 131 is greater than the modulus, and is used to output the operation result of the Montgomery modular multiplication operation dedicated submodule 131 when the operation result of the Montgomery modular multiplication operation dedicated submodule 131 is less than the modulus;

[0093] In Barrett modular multiplication mode:

[0094] The first multiplication unit 133-1 is used to calculate the product of the operands to be operated;

[0095] The first shift unit 133-4 is used to output the operation result of the first multiplication unit 133-1 to the Barrett modular multiplication operation dedicated submodule 132, and is used to shift the operation result of the first multiplication unit 133-1 and output the shifted result to the second multiplication unit 133-2;

[0096] The second multiplication unit 133-2 is used to calculate the product of the shift result of the first shift unit 133-4 and the fusion parameter;

[0097] The second shift unit 133-5 is used to shift the operation result of the second multiplication unit 133-2;

[0098] The third multiplication unit 133-3 is used to calculate the product of the shift result of the second shift unit 133-5 and the modulus;

[0099] The third shift unit 133-6 is used to output the operation result of the third multiplication unit 133-3 to the Barrett modular multiplication operation dedicated submodule 132;

[0100] The first comparison unit 133-8 is used to compare the operation result of the Barrett modular multiplication operation dedicated submodule 132 with the size of the modulus;

[0101] The first subtraction unit 133-7 is used to calculate the difference between the operation result of the Barrett modular multiplication operation dedicated submodule 132 and the modulus;

[0102] The first selection unit 133-9 is used to output the operation result of the first subtraction unit 133-7 when the operation result of the Barrett modular multiplication operation dedicated submodule 132 is greater than the modulus, and is used to output the operation result of the Barrett modular multiplication operation dedicated submodule 132 when the operation result of the Barrett modular multiplication operation dedicated submodule 132 is less than the modulus.

[0103] The modular multiplication operation shared submodule 133 in the embodiment of the present invention can cooperate with the Montgomery modular multiplication operation dedicated submodule 131 in the Montgomery modular multiplication operation mode to perform Montgomery modular multiplication operation on the operands; similarly, the modular multiplication operation shared submodule 133 can cooperate with the Barrett modular multiplication operation dedicated submodule 132 in the Barrett modular multiplication operation mode to perform Barrett modular multiplication operation on the operands. This embodiment can effectively reduce the size of the hardware accelerator 100 based on Montgomery and Barrett by integrating the operation units required for the Montgomery modular multiplication operation and the Barrett modular multiplication operation in a modular multiplication operation shared submodule 133, and also greatly reduce the cost of the hardware accelerator 100 based on Montgomery and Barrett.

[0104] The Montgomery modular multiplication operation dedicated submodule 131 is used to perform the addition operation dedicated to the Montgomery modular multiplication operation;

[0105] like Figure 4 As shown, the Montgomery modular multiplication operation dedicated submodule 131 includes: a first adding unit 131-1;

[0106] The first adding unit 131-1 is electrically connected to the first shifting unit 133-4, the third shifting unit 133-6, the first subtracting unit 133-7, the first comparing unit 133-8 and the first selecting unit 133-9 respectively;

[0107] The first adding unit 131 - 1 is used to calculate the sum of a result of the right shift by the first shift unit 133 - 4 and a result of the right shift by the third shift unit 133 - 6 .

[0108] Specifically, Figure 5As shown, when the mode signal is 0, the control module 120 controls a path to be formed between the dedicated sub-module 131 for Montgomery modular multiplication and the shared sub-module 133 for modular multiplication to perform the Montgomery modular multiplication mode.

[0109] First, the multiplier op1 and the multiplicand op2 pass through the first multiplication unit 133-1 to obtain the product T of the multiplier op1 and the multiplicand op2. The first multiplication unit 133-1 outputs T to the first shift unit 133-4.

[0110] The first shift unit 133-4 shifts T to the right by k bits to obtain T / R and outputs T / R to the first addition unit 131-1. The first shift unit 133-4 also shifts T to the left by k bits to obtain q1, where q1 = T mod R. Then the first shift unit 133-4 outputs q1 to the second multiplication unit 133-2. Here, the value of R and the following fusion parameter N' are calculated in advance according to the following principle: for any integer T, and T < R×N, RR'≡1 (mod N), RR'–NN' = 1, RR'–NN'≡1 (mod N). Based on the above conditions, it is deduced that and t < 2N, so if t≥N, T mod N = t - N; otherwise, T mod N = t;

[0111] After obtaining q1, the second multiplication unit 133-2 calculates the product of q1 and the fusion parameter N' to get q2 and outputs q2 to the second shift unit 133-5, where q2 = (T mod R)N';

[0112] Then the second shift unit 133-5 shifts q2 to the left by k bits to obtain q3, where q3 = ((T mod R)N') mod R and outputs q3 to the third multiplication unit 133-3;

[0113] After obtaining q3, the third multiplication unit 133-3 multiplies q3 by the modulus q. Here, the value of q is set to N, so ((T mod R)N') mod R)N is obtained;

[0114] The third shift unit 133-6 shifts the calculation result of the third multiplication unit 133-3 to the right by k bits to obtain ((((T mod R)N') mod R)N) / R and outputs it to the first addition unit 131-1;

[0115] The first addition unit 131-1 adds the shift result of the third shift unit 133-6 and T / R to get t, where t = (T + (((T mod R)N') mod R)N) / R, and outputs t to the first comparison unit 133-8, the first subtraction unit 133-7, and the first selection unit 133-9. The first selection unit 133-9 is Figure 5In MUX1, the first comparison unit 133-8 is Figure 5 CMP in;

[0116] The first comparison unit 133-8 compares t and q, and outputs the comparison result to the first selection unit 133-9;

[0117] While the first comparison unit 133-8 is performing the operation, the first subtraction unit 133-7 calculates the value of tq and outputs the value of tq to the first selection unit 133-9;

[0118] The first selection unit 133 - 9 selects the final output result according to the comparison result of t and q. When t>q, the first selection unit outputs t−q. When t>q, the first selection unit outputs t.

[0119] The Barrett modular multiplication operation dedicated submodule 132 is used to perform a subtraction operation dedicated to the Barrett modular multiplication operation.

[0120] like Figure 6 As shown, the Barrett modular multiplication operation dedicated submodule 132 includes: a second subtraction unit 132-1;

[0121] The second subtraction unit 132-1 is electrically connected to the first shift unit 133-4 and the third shift unit 133-6, the first subtraction unit 133-7, the first comparison unit 133-8 and the first selection unit 133-9 respectively;

[0122] The second subtracting unit 132 - 1 is used to calculate a difference between the operation result of the first multiplying unit 133 - 1 and the result of the third shifting unit 133 - 6 .

[0123] Specifically, Figure 7 As shown, when the mode signal is 1, the control module 120 controls the Barrett modular multiplication operation dedicated submodule 132 and the modular multiplication operation shared submodule 133 to form a path to execute the Barrett modular multiplication operation mode.

[0124] First, the multiplier op1 and the multiplicand op2 pass through the first multiplication unit 133-1 to obtain the product A of the multiplier op1 and the multiplicand op2, and the first multiplication unit 133-1 outputs A to the first shift unit 133-4;

[0125] The first shift unit 133-4 outputs A to the second subtraction unit 132-1, shifts A to obtain q1, and then outputs q1 to the second multiplication unit 133-2;

[0126] The second multiplication unit 133-2 multiplies q1 and the fusion parameter H to obtain q2 and outputs q2 to the second shift unit 133-5;

[0127] After the second shift unit 133-5 shifts q2, it obtains q3 and outputs q3 to the third multiplication unit 133-3;

[0128] The third multiplication unit 133-3 multiplies q3 and the modulus q, and outputs the multiplication result q3×q to the third shift unit 133-6;

[0129] The third shift unit 133-6 outputs q3×q to the second subtraction unit 132-1;

[0130] The second subtraction unit 132-1 calculates A-q3×q and outputs it to the first comparison unit 133-8, the first subtraction unit 133-7 and the first selection unit 133-9. The first comparison unit 133-8 is Figure 7 The first selection unit 133-9 in MUX1 is Figure 7 CMP in;

[0131] The first comparison unit 133-8 compares A-q3×q with q, and outputs the comparison result to the first selection unit 133-9, and the comparison result serves as a selection signal of the first selection unit 133-9;

[0132] The first subtraction unit 133-7 calculates A-q3×q-q and outputs the calculation result to the first selection unit 133-9;

[0133] When A-q3×q>q, the first selection unit 133-9 outputs A-q3×q-q as the final modular multiplication calculation result; when A-q3×q<q, the first selection unit 133-9 outputs A-q3×q as the final modular multiplication calculation result.

[0134] Furthermore, if Figure 8 As shown, the control module 120 includes: a second selection unit 121 and a third selection unit 122;

[0135] The second selection unit 121 is electrically connected to the third selection unit 122, the second selection unit 121 is also electrically connected to the first addition unit 131-1, the second subtraction unit 132-1, the first comparison unit 133-8 and the first subtraction unit 133-7, and the third selection unit 122 is also electrically connected to the first selection unit 133-9 and the first shift unit 133-4.

[0136] The second selection unit 121 is used to select the operation result of the Montgomery modular multiplication operation dedicated submodule 131 according to the first signal to form a Montgomery modular multiplication operation mode, and is used to select the operation result of the Barrett modular multiplication operation dedicated submodule 132 according to the second signal to form a Barrett modular multiplication operation mode;

[0137] The third selection unit 122 is used to output the operation result of the second selection unit 121 and send it to the first selection unit 133 - 9 .

[0138] Specifically, Fig. 9 As shown, MUX1 is the first selection unit 133-9, MUX2 is the second selection unit 121, and MUX3 is the third selection unit 122. The control module 120 of the embodiment of the present invention realizes the switching between the Montgomery modular multiplication operation mode and the Barrett modular multiplication operation mode through the second selection unit 121 and the third selection unit 122, which is convenient and low-cost.

[0139] Furthermore, in the Barrett modular multiplication operation mode, the bit widths of the multiplier and the multiplicand are both twice the bit width of the modulus.

[0140] Specifically, in the embodiment of the present invention, the bit widths of the multiplier op1 and the multiplicand op2 are both 2k bits, and the bit width of the modulus q is k bits. This design enables the modular multiplication operation module 130 to perform only one interval judgment when taking the modulus during the Barrett modular multiplication operation, as follows:

[0141] After the first shift unit 133-4 shifts A, q1 is obtained. Where k represents the bit width of the modulus q. The second multiplication unit 133-2 calculates the product of q1 and the fusion parameter H to obtain q2, q2=q1×H, where By deducing in, Therefore, Amod q = (A-q3×q)mod q. Since (A-q3×q) is between A-2q and A, to take the modulus of q, we only need to determine which interval of [0,q) or [q,2q). If (A-q3×q) falls in the interval [q,2q), then: Amod q = (A-q3×q)-q, otherwise, Amod q = A-q3×q.

[0142] This is consistent with the number of interval judgments in the Montgomery operation process, and can effectively improve the integration of the hardware design of Barrett modular multiplication operation and Montgomery modular multiplication operation.

[0143] Another embodiment of the present invention provides a method for implementing a hardware accelerator based on Montgomery and Barrett, such as Fig.10 As shown, including:

[0144] S100, obtaining a mode signal and operation data input by a user, wherein the operation data at least includes a number to be operated, a modulus, and a fusion parameter;

[0145] Specifically, the mode signal is the mode signal, and the operands include a multiplier and a multiplicand. In an embodiment of the present invention, op1 and op2 are used to represent the multiplier and the multiplicand respectively, q is used to represent the modulus, and the fusion parameters include the fusion parameters in the Montgomery modular multiplication operation and the fusion parameters in the Barrett modular multiplication operation. The fusion parameters in the Montgomery modular multiplication operation are represented by N', and the fusion parameters in the Barrett modular multiplication operation are represented by H.

[0146] S200, when the mode signal is the first signal, forming a Montgomery modular multiplication operation mode according to the first signal; when the mode signal is the second signal, forming a Barrett modular multiplication operation mode according to the second signal;

[0147] When the mode signal is the first signal, specifically when the mode signal is 0, a Montgomery modular multiplication operation mode is formed according to the first signal; when the mode signal is the second signal, specifically when the mode signal is 1, a Barrett modular multiplication operation mode is formed according to the second signal.

[0148] S300. In a Montgomery modular multiplication operation mode, perform a Montgomery modular multiplication operation on the operation data; and in a Barrett modular multiplication operation mode, perform a Barrett modular multiplication operation on the operation data.

[0149] The embodiment of the present invention enables a hardware accelerator based on Montgomery and Barrett to switch between Montgomery modular multiplication operation mode and Barrett modular multiplication operation mode according to a mode signal, so that the hardware accelerator can support both Montgomery modular multiplication operation and Barrett modular multiplication operation, can select a suitable algorithm according to requirements, and flexibly adapt to different application scenarios, thereby improving the applicability and flexibility of the hardware accelerator.

[0150] Regarding the specific principles of the implementation method of the hardware accelerator based on Montgomery and Barrett provided in the embodiment of the present invention, reference can be made to the principles of the hardware accelerator based on Montgomery and Barrett described above, and will not be elaborated here.

[0151] Yet another embodiment of the present invention provides a security chip, including a chip carrier and the above-mentioned Montgomery and Barrett-based hardware accelerator disposed on the chip carrier.

[0152] Furthermore, the chip carrier includes FPGA or ASIC.

[0153] The specific principle of the security chip provided by the embodiment of the present invention can refer to the principle of the hardware accelerator based on Montgomery and Barrett mentioned above, which will not be elaborated here.

[0154] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A hardware accelerator based on Montgomery and Barrett, characterized in that, include: Signal acquisition module, control module and modular multiplication operation module; The modular multiplication operation module is electrically connected to the signal acquisition module and the control module respectively, and the signal acquisition module is also electrically connected to the control module; The signal acquisition module is used to acquire the mode signal and operation data input by the user, wherein the operation data at least includes a number to be operated, a modulus and a fusion parameter; The control module is used for forming a Montgomery modular multiplication operation mode according to the first signal when the mode signal is a first signal; and for forming a Barrett modular multiplication operation mode according to the second signal when the mode signal is a second signal; The modular multiplication operation module is used to perform a Montgomery modular multiplication operation on the operation data in a Montgomery modular multiplication operation mode, and is used to perform a Barrett modular multiplication operation on the operation data in a Barrett modular multiplication operation mode.

2. The Montgomery and Barrett based hardware accelerator according to claim 1, characterized in that: The modular multiplication operation module includes a Montgomery modular multiplication operation dedicated submodule, a Barrett modular multiplication operation dedicated submodule and a modular multiplication operation shared submodule; The Montgomery modular multiplication operation dedicated submodule and the Barrett modular multiplication operation dedicated submodule are electrically connected to the modular multiplication operation shared submodule respectively, the Montgomery modular multiplication operation dedicated submodule and the Barrett modular multiplication operation dedicated submodule are also electrically connected to the control module respectively, and the modular multiplication operation shared submodule is also electrically connected to the signal acquisition module; The modular multiplication operation shared submodule is used to perform the operation operations commonly required by the Montgomery modular multiplication operation and the Barrett modular multiplication operation, wherein the commonly required operation operations include multiplication operation, shift operation, subtraction operation, comparison operation and selection operation; The Montgomery modular multiplication operation dedicated submodule is used to perform the addition operation dedicated to the Montgomery modular multiplication operation; The Barrett modular multiplication operation-specific submodule is used to perform a subtraction operation dedicated to the Barrett modular multiplication operation.

3. The Montgomery and Barrett based hardware accelerator according to claim 2, characterized in that: The modular multiplication operation shared submodule includes: a first multiplication unit, a second multiplication unit, a third multiplication unit, a first shift unit, a second shift unit, a third shift unit, a first subtraction unit, a first comparison unit and a first selection unit; The first shift unit is electrically connected to the first multiplication unit and the second multiplication unit, respectively; the second shift unit is electrically connected to the second multiplication unit and the third multiplication unit, respectively; the third shift unit is electrically connected to the third multiplication unit, and the first selection unit is electrically connected to the first subtraction unit and the first comparison unit, respectively; the first shift unit, the third shift unit, the first subtraction unit, the first comparison unit, and the first selection unit are all electrically connected to the Montgomery modular multiplication operation dedicated submodule; the first shift unit, the third shift unit, the first subtraction unit, the first comparison unit, and the first selection unit are all electrically connected to the Barrett modular multiplication operation dedicated submodule; In Montgomery modular multiplication mode: The first multiplication unit is used to calculate the product of the operands; The first shift unit is used to shift the operation result of the first multiplication unit to the right and output it to the Montgomery modular multiplication operation dedicated submodule, and is used to shift the operation result of the first multiplication unit to the left and output it to the second multiplication unit; The second multiplication unit is used to calculate the product of the left shift result of the first shift unit and the fusion parameter; The second shift unit is used to shift the operation result of the second multiplication unit to the left; The third multiplication unit is used to calculate the product of the shift result of the second shift unit and the modulus; The third shift unit is used for shifting the operation result of the third multiplication unit to the right and outputting it to the Montgomery modular multiplication operation dedicated submodule; The first comparison unit is used to compare the operation result of the Montgomery modular multiplication operation dedicated submodule with the size of the modulus; The first subtraction unit is used to calculate the difference between the operation result of the Montgomery modular multiplication operation dedicated submodule and the modulus; The first selection unit is used to output the operation result of the first subtraction unit when the operation result of the Montgomery modular multiplication operation dedicated submodule is greater than the modulus, and is used to output the operation result of the Montgomery modular multiplication operation dedicated submodule when the operation result of the Montgomery modular multiplication operation dedicated submodule is less than the modulus; In Barrett modular multiplication mode: The first multiplication unit is used to calculate the product of the operands; The first shift unit is used to output the operation result of the first multiplication unit to the Barrett modular multiplication operation dedicated submodule, and is used to shift the operation result of the first multiplication unit and output the shifted result to the second multiplication unit; The second multiplication unit is used to calculate the product of the shift result of the first shift unit and the fusion parameter; The second shift unit is used to shift the operation result of the second multiplication unit; The third multiplication unit is used to calculate the product of the shift result of the second shift unit and the modulus; The third shift unit is used to output the operation result of the third multiplication unit to the Barrett modular multiplication operation dedicated submodule; The first comparison unit is used to compare the operation result of the Barrett modular multiplication operation dedicated submodule with the size of the modulus; The first subtraction unit is used to calculate the difference between the operation result of the Barrett modular multiplication operation dedicated submodule and the modulus; The first selection unit is used to output the operation result of the first subtraction unit when the operation result of the Barrett modular multiplication operation dedicated submodule is greater than the modulus, and is used to output the operation result of the Barrett modular multiplication operation dedicated submodule when the operation result of the Barrett modular multiplication operation dedicated submodule is less than the modulus.

4. The Montgomery and Barrett based hardware accelerator according to claim 3, characterized in that: The Montgomery modular multiplication operation dedicated submodule includes: a first addition unit; The first adding unit is electrically connected to the first shifting unit, the third shifting unit, the first subtracting unit, the first comparing unit and the first selecting unit respectively; The first adding unit is used to calculate the sum of a result of the first shift unit shifting to the right and a result of the third shift unit shifting to the right.

5. The Montgomery and Barrett based hardware accelerator according to claim 3, characterized in that: The Barrett modular multiplication operation dedicated submodule includes: a second subtraction unit; The second subtraction unit is electrically connected to the first shift unit, the third shift unit, the first subtraction unit, the first comparison unit and the first selection unit respectively; The second subtraction unit is used to calculate a difference between an operation result of the first multiplication unit and an operation result of the third shift unit.

6. The Montgomery and Barrett based hardware accelerator according to claim 3, characterized in that: The control module includes: a second selection unit and a third selection unit; The second selection unit is electrically connected to the third selection unit, the second selection unit is also electrically connected to the first addition unit, the second subtraction unit, the first comparison unit and the first subtraction unit, respectively, and the third selection unit is also electrically connected to the first selection unit and the first shift unit, respectively; The second selection unit is used to select the operation result of the Montgomery modular multiplication operation dedicated submodule according to the first signal to form a Montgomery modular multiplication operation mode, and is used to select the operation result of the Barrett modular multiplication operation dedicated submodule according to the second signal to form a Barrett modular multiplication operation mode; The third selection unit is used to output the calculation result of the second selection unit and send it to the first selection unit.

7. The Montgomery and Barrett based hardware accelerator according to claim 1, characterized in that: In the Barrett modular multiplication operation mode, the bit widths of the multiplier and the multiplicand are both twice the bit width of the modulus.

8. A method for implementing a hardware accelerator based on Montgomery and Barrett, applied to a hardware accelerator based on Montgomery and Barrett as claimed in any one of claims 1 to 7, characterized in that: include: Acquire a mode signal and operation data input by a user, wherein the operation data at least includes a number to be operated, a modulus, and a fusion parameter; When the mode signal is a first signal, a Montgomery modular multiplication operation mode is formed according to the first signal; when the mode signal is a second signal, a Barrett modular multiplication operation mode is formed according to the second signal; In the Montgomery modular multiplication operation mode, a Montgomery modular multiplication operation is performed on the operation data, and in the Barrett modular multiplication operation mode, a Barrett modular multiplication operation is performed on the operation data.

9. A security chip, characterized in that: The invention comprises a chip carrier and a hardware accelerator based on Montgomery and Barrett as claimed in any one of claims 1 to 7 arranged on the chip carrier.

10. The security chip according to claim 9, characterized in that: The chip carrier includes FPGA or ASIC.

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