Chip verification test method, chip test device, electronic equipment and storage medium
By building multiple test branches and performing synchronous testing, the problems of low efficiency and long time in traditional fault injection testing methods in large batches of chips are solved, and more efficient chip failure detection is achieved.
Patent Information
- Application Number
- CN202411438964.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-15
- Publication Date
- 2025-03-14
AI Technical Summary
The traditional fault injection test method is inefficient for the testing of large batches of chips to be tested and the test time is too long.
By building multiple test branches, synchronous testing of multiple chips to be tested, preliminary tests determine the target test time, fault tests are performed, and fault chips are determined based on the test results.
It improves the efficiency and speed of chip testing, reduces test time, and can more accurately identify faulty chips.
Smart Images
Figure CN119621446A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip testing technology, and in particular to a chip verification test method, a chip testing device, an electronic device and a storage medium. Background Art
[0002] With the development of chip and information technology, integrated circuit chips are increasingly widely used, and they play a pivotal role in information security. Many manufacturers also carry out security testing and security protection measures on the chips they produce. Information leakage security attacks against chips are mainly divided into two types: side channel attacks and fault injection attacks. Currently, there are many fault injection attack testing methods. However, the traditional fault injection test method can provide high accuracy for a single chip, but for a large number of chips to be tested, if each chip needs to be tested one by one, there will be serious problems such as low test efficiency and long test time. Summary of the invention
[0003] In view of this, the purpose of the present application is to propose a chip verification test method, a chip testing device, an electronic device and a storage medium to solve the problems of low test efficiency and long test time in traditional fault injection testing methods.
[0004] Based on the above purpose, the present application provides a chip verification test method, including:
[0005] Constructing multiple test branches according to multiple chips to be tested and chip testing devices;
[0006] Performing preliminary tests on the multiple test branches to determine target test times for the multiple chips to be tested;
[0007] At the target test time, performing a fault test on the multiple test branches to obtain a test result of each chip to be tested;
[0008] The faulty chip is determined according to the test results of each chip to be tested.
[0009] Optionally, the step of constructing a plurality of test branches according to a plurality of chips to be tested and chip testing devices includes:
[0010] Insert multiple chips to be tested into the chip testing device in rows.
[0011] The chips to be tested in each row are used as a test branch to form multiple test branches.
[0012] Optionally, performing preliminary testing on the multiple test branches to determine target test times for the multiple chips to be tested includes:
[0013] Initializing the plurality of chips to be tested, inputting a first preset voltage to each of the chips to be tested, and collecting preliminary test results of each of the chips to be tested;
[0014] The preset time after the initial test result acquisition time is used as the target test time of the plurality of chips to be tested.
[0015] Optionally, at the target test time, performing fault tests on the multiple test branches to obtain test results of each chip to be tested includes:
[0016] At the target test time, a second preset voltage is injected into each chip to be tested, and test results of each chip to be tested are collected; wherein the second preset voltage is greater than the first preset voltage.
[0017] Optionally, determining a faulty chip according to the test results of each chip to be tested includes:
[0018] The test results of the chips to be tested are grouped, and the chips to be tested in each group are subjected to an XOR operation to obtain an XOR operation result of each group;
[0019] In response to the chipset under test whose XOR operation result is 1, iterative testing is performed on each chip under test in the chipset under test. In response to the number of iterations reaching a preset number of rounds, the iterative testing is stopped, and the chips under test in the chipset under test whose XOR operation result is 1 are regarded as faulty chips.
[0020] Optionally, the iterative testing of each chip to be tested in the chipset to be tested includes:
[0021] Each round of iterative testing of each chip under test in the chipset under test is as follows:
[0022] A third preset voltage is injected into each chip to be tested, and test results of each chip to be tested are collected; wherein, the third preset voltage described in the first round of testing is less than the second preset voltage, and the third preset voltage of each round of iterative testing is the third preset voltage of the previous round gradually reduced by a preset step size.
[0023] Based on the agreed inventive concept, the present application also provides a chip testing device, which is applicable to any of the above chip verification test methods, including: a circuit board and a signal input port, a signal output port and a plurality of mounting seats arranged on the circuit board;
[0024] The plurality of mounting seats are arranged in an array on the circuit board, and the plurality of mounting seats are respectively connected to the signal output port and the signal output port;
[0025] The mounting seat is provided with a chip to be tested, and the mounting seats in each row or column provided with the chip to be tested form a test branch.
[0026] Optionally, the signal input port and the signal output port are connected to the controller via lines respectively.
[0027] Based on the same inventive concept, the present application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the above-described methods when executing the program.
[0028] Based on the same inventive concept, the present application also provides a non-transitory computer-readable storage medium, which stores computer instructions, and the computer instructions are used to enable a computer to execute any of the above-mentioned methods.
[0029] From the above, it can be seen that the present application provides a chip verification test method, a chip testing device, an electronic device and a storage medium. The method constructs multiple test branches according to multiple chips to be tested and a chip testing device; that is, multiple chips to be tested are inserted into the chip device to construct multiple test branches. In this way, multiple test branches can be tested synchronously, thereby improving test efficiency and test speed and reducing test time. During the test process, the multiple test branches are firstly preliminarily tested to determine the target test time of the multiple chips to be tested; at the target test time, the multiple test branches are fault tested to obtain the test results of each chip to be tested; and then the faulty chip is determined according to the test results of each chip to be tested. In this way, by analyzing the test results of each chip to be tested, the faulty chip in each chip to be tested can be determined, thereby improving the chip testing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0031] Figure 1 A schematic diagram of a chip verification test method flow in an embodiment of the present application;
[0032] Figure 2 A schematic diagram of the structure of a chip testing device according to an embodiment of the present application;
[0033] Figure 3 A schematic diagram of the hardware structure of an electronic device according to an embodiment of the present application.
[0034] In the attached figure:
[0035] 1. Circuit board; 2. Mounting seat; 3. Chip to be tested; 4. Signal input port; 5. Signal output port. DETAILED DESCRIPTION
[0036] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.
[0037] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0038] Based on the background technology, fault injection is an invasive attack. The fault injection attack first injects faults into the chip in normal operation, affecting the output level of the micro-unit MOS tube in the circuit, thereby causing unexpected changes in the program flow or data flow composed of the MOS tube, resulting in an error in the output of the calculation result of the chip operation, achieving the effect of affecting the normal operation of the chip function, and then using mathematical statistics to analyze the chip input information and the output information under abnormal working conditions, so as to obtain key information inside the chip. There are many commonly used fault injection methods, including voltage glitch attack, local light attack, electromagnetic manipulation, temperature change attack, etc. Among them, voltage glitch attack is easier to operate and more efficient than its attack methods. Voltage glitch attack is divided into undervoltage glitch fault injection technology that implements a voltage lower than the normal working voltage and overvoltage voltage glitch attack that implements a voltage higher than the normal working voltage. The existing undervoltage glitch fault injection technology cannot achieve fault injection at a specified position, and the results of multiple experiments under the same conditions are mostly different. In addition, undervoltage glitch is difficult to stably inject faults, which easily causes the encryption result of the chip to output slowly instead of failing. During the long-term fault injection experiment, it was found that overvoltage glitches are more likely to cause chip failures and are more suitable as a means of voltage glitch attack.
[0039] The traditional fault injection test method can provide high accuracy for a single chip, but for a large number of chips to be tested, if they need to be tested one by one, there will be serious problems such as low test efficiency and long test time.
[0040] In order to solve the above technical problems, Figure 1 As shown, the present application provides a chip verification test method, comprising the following steps:
[0041] Step 102: construct multiple test branches according to multiple chips to be tested and chip testing devices.
[0042] In this step, the multiple chips to be tested are of the same batch and model. The chip testing device is provided with multiple test stations (such as Figure 2 As shown in FIG. 1 ), a plurality of chips to be tested are exemplarily inserted into the test stations of the chip testing device, thereby forming a plurality of test branches.
[0043] In this step, before testing multiple chips, each chip needs to be tested step by step to perform quality consistency inspection to determine whether it meets the specified chip requirements (for example, there are national standard requirements for different types of chips). In this way, the chip must be inspected before testing to ensure the accuracy of the chip test.
[0044] Step 104: Perform preliminary testing on the multiple test branches to determine target test times for the multiple chips to be tested.
[0045] In this step, a plurality of chips to be tested on a plurality of test branches are preliminarily tested, and while obtaining the preliminary test results of the chips to be tested, the fault test time of the plurality of chips to be tested (that is, the target test time of the chips) is determined. This can be understood as performing a fault test on the chips to be tested after the preliminary test to ensure the accuracy of the test of the chips to be tested.
[0046] Step 106: At the target test time, perform a fault test on the multiple test branches to obtain a test result of each chip to be tested.
[0047] In this step, that is, at the target test time determined after the preliminary test, a fault test is performed on the multiple chips to be tested to obtain the test results of the chips to be tested, so as to ensure the accuracy of the tests of the multiple chips to be tested.
[0048] Step 108: Determine the faulty chip according to the test results of each chip to be tested.
[0049] In this step, the faulty chip is determined according to the test results of each chip to be tested, that is, whether the test result of each chip to be tested is correct is detected, and the chip to be tested with incorrect test result is considered as a faulty chip.
[0050] Through steps 102-108, multiple test branches are constructed according to multiple chips to be tested and chip test devices; that is, multiple chips to be tested are inserted into the chip device to construct multiple test branches. In this way, multiple test branches can be tested synchronously, improving test efficiency and test speed, and reducing test time. During the test process, the multiple test branches are firstly preliminarily tested to determine the target test time of the multiple chips to be tested; at the target test time, the multiple test branches are fault tested to obtain the test results of each chip to be tested; then, the faulty chip is determined according to the test results of each chip to be tested. In this way, by analyzing the test results of each chip to be tested, the faulty chip in each chip to be tested can be determined, thereby improving chip testing efficiency.
[0051] In some embodiments, the step of constructing multiple test branches based on multiple chips to be tested and chip testing devices includes:
[0052] Insert multiple chips to be tested into the chip testing device in rows.
[0053] The chips to be tested in each row are used as a test branch to form multiple test branches.
[0054] Specifically, multiple chips to be tested may be exemplified as: AEC-Q100 and ISO 26262 and other standards for automobiles and GB / T 18336 and GM / T 0028 for cryptographic chips. Each chip to be tested is of the same batch and model, so that the speed of chip testing can be improved. The chip testing device is connected to a tester, and a plurality of test stations (i.e., mounting seats) are provided on the chip testing device. The chips to be tested are inserted into the test stations in rows. The best is to ensure that the number of chips to be tested in each row is equal. In this way, after obtaining the test results of each chip to be tested, group inspection is performed according to the test results, which can improve the test speed. That is, the chips to be tested in each row are used as a test branch to form multiple test branches, and multiple test branches are tested synchronously to improve the test speed.
[0055] In some embodiments, the performing preliminary testing on the plurality of test branches to determine target test times for the plurality of chips to be tested includes:
[0056] Initializing the plurality of chips to be tested, inputting a first preset voltage to each of the chips to be tested, and collecting preliminary test results of each of the chips to be tested;
[0057] The preset time after the initial test result acquisition time is used as the target test time of the plurality of chips to be tested.
[0058] Specifically, multiple chips to be tested are initialized to ensure the consistency of the subsequent multiple chips to be tested, and then a first preset voltage is input to each chip to be tested. It can also be understood that in the preliminary test process, the first preset voltage input to each chip to be tested is a normal voltage chip that can run with the chip model. After collecting the preliminary test results of each chip to be tested, they are recorded to determine whether the initial test results of each chip to be tested are correct. To ensure that multiple chips to be tested can output correct test results, that is, to perform preliminary tests on multiple chips to be tested, to ensure the accuracy of subsequent fault tests, and to avoid incorrect test results due to chip damage. And the preset time after the preliminary test result collection time is used as the target test time of multiple chips to be tested. In this way, the fault target test time of multiple chips to be tested is staggered with the preliminary test, so that the staff can pick out the bad chips and ensure the accuracy of subsequent fault tests of each chip.
[0059] In some embodiments, at the target test time, performing fault tests on the multiple test branches to obtain test results of each chip to be tested includes:
[0060] At the target test time, a second preset voltage is injected into each chip to be tested, and test results of each chip to be tested are collected; wherein the second preset voltage is greater than the first preset voltage.
[0061] Specifically, at the target test time, that is, after the preliminary test of each chip to be tested is completed, each chip to be tested can output the correct test result. Then, a second preset voltage of overvoltage is injected into each chip to be tested. The first preset voltage is the normal voltage at which the chip can operate, and the second preset voltage is greater than the first preset voltage. Therefore, the second preset voltage contains an excitation voltage of the overvoltage glitch. Exemplarily, the amplitude of the second preset voltage can be 3≤k≤p, where p is the maximum number of chips that the test system can accommodate. The output results of each chip to be tested after the overvoltage voltage are collected to obtain the test results, and the fault test is completed. When performing fault analysis, the results can be analyzed to determine the faulty chip.
[0062] In some embodiments, determining a faulty chip according to the test results of each chip to be tested includes:
[0063] The test results of the chips to be tested are grouped, and the chips to be tested in each group are subjected to an XOR operation to obtain an XOR operation result of each group;
[0064] In response to the chipset under test whose XOR operation result is 1, iterative testing is performed on each chip under test in the chipset under test. In response to the number of iterations reaching a preset number of rounds, the iterative testing is stopped, and the chips under test in the chipset under test whose XOR operation result is 1 are regarded as faulty chips.
[0065] Specifically, when determining the faulty chip, the test results of each chip to be tested are grouped, and the chips to be tested in each group are subjected to XOR operation to obtain the XOR operation result of each group; exemplarily, each group may include the test results of multiple chips to be tested, and exemplarily each group includes the test results of six chips to be tested, and the test results of the six chips to be tested are subjected to XOR processing. If the XOR result in the group is 1, it means that there is a faulty chip in the group, then the group is confirmed as a faulty chip group, and the final faulty chip needs to be determined in the faulty chip group later. If the XOR result in the group is 0, it means that there is no faulty chip in the group, and the output results are consistent, then the group is marked, and the group of chips to be tested is not tested later. The group of chips to be tested with an XOR operation result of 1 is iteratively tested again until the preset number of iterations is reached, and then the chips to be tested in the group of chips to be tested with an XOR operation result of 1 are confirmed as faulty chips. Among them, the preset number of iterations can be the number of iterations that have been tested in advance to ensure that all faulty chips can be found.
[0066] In some embodiments, the iterative testing of each chip under test in the chipset under test includes:
[0067] Each round of iterative testing of each chip under test in the chip group under test is as follows:
[0068] A third preset voltage is injected into each chip to be tested, and test results of each chip to be tested are collected; wherein, the third preset voltage described in the first round of testing is less than the second preset voltage, and the third preset voltage of each round of iterative testing is the third preset voltage of the previous round gradually reduced by a preset step size.
[0069] Specifically, when the chips to be tested in the fault group are iteratively tested, the third preset voltage is input to each chip to be tested in each round, wherein the third preset voltage injected in the first round is less than the second preset voltage, and then the third preset voltage in each iteration is reduced by a preset step length (an exemplary preset step length may be 1V) from the third preset voltage in the previous round, so that the test is gradually performed with a reduced overvoltage voltage, which is equivalent to using a binary method to continuously reduce the test range of the faulty chip until the faulty chip is found, making the test result more accurate.
[0070] It should be noted that the method of the embodiment of the present application can be performed by a single device, such as a computer or server. The method of this embodiment can also be applied to a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of the embodiment of the present application, and the multiple devices will interact with each other to complete the described method.
[0071] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0072] Based on the same inventive concept, corresponding to any of the above-mentioned embodiment methods, the present application also provides a chip testing device.
[0073] refer to Figure 2 , the chip testing device comprises: a circuit board 1 and a signal input port 4, a signal output port 5 and a plurality of mounting seats 2 arranged on the circuit board 1;
[0074] The plurality of mounting seats 2 are arranged in an array on the circuit board 1, and the plurality of mounting seats 2 are respectively connected to the signal output port 5 and the signal output port 5;
[0075] The mounting seat 2 is provided with a chip to be tested 3, and each row or column of mounting seats 2 provided with the chip to be tested 3 forms a test branch.
[0076] Specifically, the chip testing device includes a circuit board 1 and a signal input port 4, a signal input port 4 and a plurality of mounting seats 2 arranged on the circuit board 1. The plurality of mounting seats 2 are welded in an array on the circuit. The signal input port 4 and the signal input port 4 can be symmetrically arranged on both sides of the circuit board 1. In this way, during the test, the plug-in ports are far away to avoid the signal influence between the two interfaces. The signal input port 4 and the signal output port 5 are respectively connected to the controller through lines. The signal input port 4 is used to input the voltage signal sent by the controller to each chip to be tested 3 on each test branch, and the signal output port 5 is used to output the output result of each chip to be tested 3 to the controller, so that the controller determines the faulty chip according to the output result. By arranging a plurality of mounting seats 2 on the chip testing device, it is possible to achieve synchronous testing of a large number of chips to be tested 3, saving test time and improving test efficiency.
[0077] For the convenience of description, the above device is described in terms of functions divided into various modules. Of course, when implementing the present application, the functions of each module can be implemented in the same or multiple software and / or hardware.
[0078] The device of the above embodiment is used to implement a corresponding chip verification test method in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.
[0079] Based on the same inventive concept, corresponding to any of the above-mentioned embodiment methods, the present application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, a chip verification test method described in any of the above embodiments is implemented.
[0080] Figure 3 A more specific schematic diagram of the hardware structure of an electronic device provided in this embodiment is shown, and the device may include: a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040 are connected to each other through the bus 1050 in the device.
[0081] The processor 1010 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.
[0082] The memory 1020 may be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 may store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program codes are stored in the memory 1020 and are called and executed by the processor 1010.
[0083] The input / output interface 1030 is used to connect the input / output module to realize information input and output. The input / output module can be configured in the device as a component (not shown in the figure), or it can be externally connected to the device to provide corresponding functions. The input device may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device may include a display, a speaker, a vibrator, an indicator light, etc.
[0084] The communication interface 1040 is used to connect a communication module (not shown) to realize communication interaction between the device and other devices. The communication module can realize communication through a wired mode (such as USB, network cable, etc.) or a wireless mode (such as mobile network, WIFI, Bluetooth, etc.).
[0085] The bus 1050 includes a path that transmits information between the various components of the device (eg, the processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040).
[0086] It should be noted that, although the above device only shows the processor 1010, the memory 1020, the input / output interface 1030, the communication interface 1040 and the bus 1050, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above device may also only include the components necessary for implementing the embodiments of the present specification, and does not necessarily include all the components shown in the figure.
[0087] The electronic device of the above embodiment is used to implement a corresponding chip verification test method in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.
[0088] Based on the same inventive concept, corresponding to any of the above-mentioned embodiment methods, the present application also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute a chip verification test method as described in any of the above embodiments.
[0089] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.
[0090] The computer instructions stored in the storage medium of the above embodiment are used to enable the computer to execute a chip verification test method as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.
[0091] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.
[0092] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present application difficult to understand, the known power supply / ground connection with the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform to be implemented in the embodiments of the present application (that is, these details should be fully within the scope of understanding of those skilled in the art). In the case of elaborating specific details (e.g., circuits) to describe exemplary embodiments of the present application, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details or when these specific details are changed. Therefore, these descriptions should be considered to be illustrative rather than restrictive.
[0093] Although the present application has been described in conjunction with specific embodiments of the present application, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.
[0094] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.
Claims
1. A chip verification test method, characterized in that: include: Constructing multiple test branches according to multiple chips to be tested and chip testing devices; Performing preliminary tests on the multiple test branches to determine target test times for the multiple chips to be tested; At the target test time, performing a fault test on the multiple test branches to obtain a test result of each chip to be tested; The faulty chip is determined according to the test results of each chip to be tested.
2. The method according to claim 1, characterized in that The method of constructing a plurality of test branches according to a plurality of chips to be tested and a chip testing device comprises: Insert multiple chips to be tested into the chip testing device in rows. The chips to be tested in each row are used as a test branch to form multiple test branches.
3. The method according to claim 2, characterized in that The performing preliminary testing on the plurality of test branches to determine target test times for the plurality of chips to be tested includes: Initializing the plurality of chips to be tested, inputting a first preset voltage to each of the chips to be tested, and collecting preliminary test results of each of the chips to be tested; The preset time after the initial test result acquisition time is used as the target test time of the plurality of chips to be tested.
4. The method according to claim 3, characterized in that The method of performing a fault test on the plurality of test branches at the target test time to obtain a test result of each chip to be tested includes: At the target test time, a second preset voltage is injected into each chip to be tested, and test results of each chip to be tested are collected; wherein the second preset voltage is greater than the first preset voltage.
5. The method according to claim 4, characterized in that Determining the faulty chip according to the test results of each of the chips to be tested includes: The test results of the chips to be tested are grouped, and the chips to be tested in each group are subjected to an XOR operation to obtain an XOR operation result of each group; In response to the chipset under test whose XOR operation result is 1, iterative testing is performed on each chip under test in the chipset under test. In response to the number of iterations reaching a preset number of rounds, the iterative testing is stopped, and the chips under test in the chipset under test whose XOR operation result is 1 are regarded as faulty chips.
6. The method according to claim 5, characterized in that The iterative testing of each chip under test in the chipset under test comprises: Each round of iterative testing of each chip under test in the chipset under test is as follows: A third preset voltage is injected into each chip to be tested, and test results of each chip to be tested are collected; wherein, the third preset voltage described in the first round of testing is less than the second preset voltage, and the third preset voltage of each round of iterative testing is the third preset voltage of the previous round gradually reduced by a preset step size.
7. A chip testing device, applicable to a chip verification test method according to any one of claims 1 to 6, characterized in that: include: A circuit board (1), and a signal input port (4), a signal output port (5), and a plurality of mounting seats (2) arranged on the circuit board (1); The plurality of mounting seats (2) are arranged in an array on the circuit board (1), and the plurality of mounting seats (2) are respectively connected to the signal output port (5) and the signal output port (5); The mounting seat (2) is provided with a chip to be tested (3), and each row or column of mounting seats (2) provided with the chip to be tested (3) forms a test branch.
8. The chip testing device according to claim 7, characterized in that: The signal input port (4) and the signal output port (5) are respectively connected to the controller via lines.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the method according to any one of claims 1 to 6 is implemented.
10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to enable a computer to execute the method according to any one of claims 1 to 6.