Chip internal signal sampling method, controller, device and system

Abstract

The embodiment of the invention provides a chip internal signal sampling method, a controller, equipment and a system. The chip internal signal sampling method has the following beneficial effects that a chip internal signal sequence is received; if the idle identifier is received, outputting a first level according to a time length T0; if the logic coding signal bearing the logic information 0 is received, the second level is output according to the time length T1, and the first level is output according to the time length T2; if the logic coding signal bearing the logic information 1 is received, the second level is output according to the time length T2, and the first level is output according to the time length T1; the first level and / or the second level are / is output to off-chip acquisition equipment through a single pin so as to acquire internal signals of the chip according to the time length T3. According to the invention, serial output and acquisition of signals are realized by using a single pin, a large number of pins are not required to be used for connecting an on-chip memory, pin resources are saved, dependence on internal storage is eliminated, and the integrity of the acquired signals is improved.

Description

Technical Field

[0001] The present invention relates to the field of chip debugging, and in particular to a sampling method, controller, device and system for internal signals of a chip. Background Art

[0002] During the development and debugging phase of a chip, it is usually necessary to send a large number of signals inside the chip to the outside for data analysis. The internal signal sequence of the chip can be temporarily stored in the on-chip memory, and then the on-chip data can be read through the off-chip sampling device using a memory access bus with multiple pins. This method will occupy multiple pins of the chip and is dependent on the on-chip storage. The number of chip pins is a valuable resource, and the fewer the number of pins occupied, the better. In addition, the internal storage capacity of the chip is limited and cannot save all the information.

[0003] From the above description, it can be seen that the current sampling method of internal chip signals occupies a lot of pin resources and is limited by the internal storage capacity. How to reduce the pin resources occupied by internal chip signal sampling and improve the integrity of chip signal sampling is a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0004] In order to overcome the shortcomings of existing chip internal signal sampling methods that occupy many pins and rely on internal storage, the present invention proposes a chip internal signal sampling method, controller, device and system.

[0005] In order to achieve the above object, according to a first aspect of the present invention, an embodiment of the present invention provides a method for sampling a chip internal signal, which is applied to a signal output controller. The method comprises the following steps: Receive a chip internal signal sequence, where the chip internal signal sequence includes an idle identifier that does not carry information, a logic coded signal that carries logic information 0, and a logic coded signal that carries logic information 1; If an idle flag is received, a first level is output according to the time length T0; If a logic coded signal carrying logic information 0 is received, the second level is output according to the time length T1 and the first level is output according to the time length T2; If a logic coded signal carrying logic information 1 is received, the second level is output according to the time length T2 and the first level is output according to the time length T1; The first level and / or the second level is output to an off-chip acquisition device through a preset single pin, so that the off-chip acquisition device acquires the chip internal signal according to the time length T3; Among them, T0>T1>T2>T3, the first level and the second level are different level signals.

[0006] Optionally, when the first level is a high level, the second level is a low level.

[0007] Optionally, when the first level is a low level, the second level is a high level.

[0008] According to a second aspect of the present invention, an embodiment of the present invention provides a method for sampling a chip internal signal, which is applied to an off-chip acquisition device. The method comprises the following steps: The first level and / or the second level output by the signal output controller is received by a preset single pin; wherein the first level and / or the second level output by the signal output controller includes: the signal output controller receives a chip internal signal sequence, wherein the chip internal signal sequence includes an idle flag that does not carry information, a logic coding signal that carries logic information 0, and a logic coding signal that carries logic information 1; if the idle flag is received, the first level is output according to the time length T0; if the logic coding signal that carries logic information 0 is received, the second level is output according to the time length T1, and the first level is output according to the time length T2; if the logic coding signal that carries logic information 1 is received, the second level is output according to the time length T2, and the first level is output according to the time length T1; and T0>T1>T2>T3, the first level and the second level are different level signals; If P first levels are sampled, there is no need to extract information, where P is an integer obtained by rounding down T0 / T3; If a combination of 1 first level and M second levels is sampled, logic information 0 is extracted, where M is an integer obtained by rounding down T1 / T3; If a combination of 1 first level, N or N+1 second levels, and 1 first level is sampled, logic information 1 is extracted, where N is an integer obtained by rounding down T2 / T3; Among them, P>M+1, and M>N+1.

[0009] Optionally, when the first level is a high level, the second level is a low level.

[0010] Optionally, when the first level is a low level, the second level is a high level.

[0011] According to a third aspect of the present invention, an embodiment of the present invention further provides a signal output controller, comprising: A receiving module, used to receive a chip internal signal sequence, wherein the chip internal signal sequence includes an idle identifier that does not carry information, a logical coding signal that carries logical information 0, and a logical coding signal that carries logical information 1; The coding module is configured to output a first level according to a time length T0 if an idle flag is received; output a second level according to a time length T1 and a first level according to a time length T2 if a logic coding signal carrying logic information 0 is received; and output a second level according to a time length T2 and a first level according to a time length T1 if a logic coding signal carrying logic information 1 is received; An output module is used to output the first level and / or the second level to an off-chip acquisition device through a preset single pin, so that the off-chip acquisition device collects the internal signal of the chip according to the time length T3; wherein T0>T1>T2>T3, and the first level and the second level are different level signals.

[0012] Optionally, when the first level is a high level, the second level is a low level; or, when the first level is a low level, the second level is a high level.

[0013] According to a fourth aspect of the present invention, an embodiment of the present invention further provides an off-chip acquisition device, including: An acquisition module, used for receiving a first level and / or a second level output by a signal output controller through a preset single pin; wherein the first level and / or the second level output by the signal output controller comprises: the signal output controller receives a chip internal signal sequence, wherein the chip internal signal sequence comprises an idle flag that carries no information, a logic coding signal that carries logic information 0, and a logic coding signal that carries logic information 1; if an idle flag is received, a first level is output according to a time length T0; if a logic coding signal that carries logic information 0 is received, a second level is output according to a time length T1, and a first level is output according to a time length T2; if a logic coding signal that carries logic information 1 is received, a second level is output according to a time length T2, and a first level is output according to a time length T1; and T0>T1>T2>T3, the first level and the second level are different level signals; A decoding module, for extracting logic information 0 if P first levels are sampled, where P is an integer rounded down from T0 / T3; extracting logic information 1 if a combination of 1 first level and M second levels is sampled, where N is an integer rounded down from T2 / T3; and extracting logic information 1 if a combination of 1 first level, N or N+1 second levels, and 1 first level is sampled, where N is an integer rounded down from T2 / T3; wherein P>M+1, and M>N+1; When the first level is a high level, the second level is a low level; or, when the first level is a low level, the second level is a high level.

[0014] According to the fifth aspect of the present invention, an embodiment of the present invention also provides a sampling system for chip internal signals, the system comprising the signal output controller of the above embodiment, and the off-chip acquisition device of the above embodiment, the signal output controller being communicatively connected to the off-chip acquisition device via a preset single pin.

[0015] As described above, a sampling method, controller, device and system for internal chip signals provided by an embodiment of the present invention have the following beneficial effects: by receiving an internal chip signal sequence, the internal chip signal sequence includes an idle flag that does not carry information, a logic coding signal that carries logic information 0, and a logic coding signal that carries logic information 1; if an idle flag is received, a first level is output according to a time length T0; if a logic coding signal that carries logic information 0 is received, a second level is output according to a time length T1, and a first level is output according to a time length T2; if a logic coding signal that carries logic information 1 is received, a second level is output according to a time length T2, and a first level is output according to a time length T1; the first level and / or the second level is output to an off-chip acquisition device through a preset single pin, so that the off-chip acquisition device acquires the internal chip signal according to a time length T3; wherein T0>T1>T2>T3. The present invention uses a single pin to realize serial output and acquisition of signals, does not need to occupy a large number of pins to connect the on-chip memory, saves pin resources, and gets rid of the dependence on internal storage, thereby improving the integrity of the acquired signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a flow chart of a method for sampling a chip internal signal executed by a signal output controller provided by an embodiment of the present invention; Figure 2 is a schematic diagram of the structure of a chip internal signal sequence provided by an embodiment of the present invention; Figure 3 is a schematic diagram of a logic 0 level provided by an embodiment of the present invention; Figure 4 is a schematic diagram of a logic 1 level provided by an embodiment of the present invention; Figure 5 is a schematic diagram of the level of a converted chip internal signal sequence provided by an embodiment of the present invention; Figure 6 It is a flow chart of another method for sampling chip internal signals executed by a signal output controller provided by an embodiment of the present invention; Figure 7 It is a flow chart of a method for sampling chip internal signals by an off-chip acquisition device provided by an embodiment of the present invention; Figure 8 is a schematic diagram of a sampling process provided by an embodiment of the present invention; Fig. 9 It is a flow chart of another method for sampling chip internal signals by an off-chip acquisition device provided by an embodiment of the present invention; Fig.10 is a structural schematic diagram of a signal output controller provided by an embodiment of the present invention; Fig.11 It is a structural schematic diagram of an off-chip acquisition device provided by an embodiment of the present invention; Fig.12 The present invention provides a schematic diagram of the structure of a chip internal signal sampling system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0018] See also Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0019] See also Figure 1 , is a flow chart of a method for sampling a chip internal signal by a signal output controller provided by an embodiment of the present invention, such as Figure 1 As shown, the embodiment of the present invention shows the process of the signal output controller executing the method.

[0020] In the specific implementation, the design, model, and package of the chip to be sampled are not the same. From the design perspective, the signal output controller can be an integrated circuit unit integrated inside the chip, or the signal output controller can be an integrated circuit unit independent of the chip core, or the signal output controller can also be a controller outside the chip that is linked to the chip for communication; in terms of form, the signal output controller can be a unit circuit with an MCU, or a circuit with other processing units. However, during use, the signal output controller is packaged as a whole with the chip core and provides pins to the outside. The packaging structure and form of the signal output controller are not limited in the embodiments of the present invention. The signal output controller can be provided with a storage unit, or a storage unit inside the chip can be used to store firmware or burn programs to execute the corresponding signal output control logic. In this way, the internal signal sequence of the chip can be sent to the signal output controller for further processing by the signal output controller.

[0021] In the first implementation, the signal output controller encodes the chip internal signal sequence, the first level used in the encoding is a high level, and the second level is a low level, the detailed process is as follows:

[0022] Step S101: receiving a chip internal signal sequence, wherein the chip internal signal sequence includes an idle signal that carries no information, a logic signal that carries logic information 0, and a logic signal that carries logic information 1.

[0023] The signal output controller receives a chip internal signal sequence emitted by the chip, where the chip internal signal sequence is a signal sequence generated by chip internal control or calculation. Specifically, the chip internal signal sequence includes an idle marker that carries no information, a logic coding signal that carries logic information 0, and a logic coding signal that carries logic information 1.

[0024] See also Figure 2 , is a structural schematic diagram of a chip internal signal sequence provided by an embodiment of the present invention. As shown in the figure, the chip internal signal sequence includes multiple signal sequences of different bit widths, each signal sequence (such as signal sequence 1, signal sequence 2...signal sequence N, etc.) further includes a logic coding signal (carrying logic information 0 or logic information 1) and an idle marker. The entire chip internal signal sequence starts with an idle marker and ends with an idle marker, and is output to the signal output controller through a single pin.

[0025] Step S102: if an idle flag is received, a high level is output according to the time length T0.

[0026] When the signal output controller receives the idle flag, it outputs a continuous high level for a period of time T0. The idle flag does not carry any information.

[0027] Step S103: if a logic coded signal carrying logic information 0 is received, a low level is output for a time length T1 and a high level is output for a time length T2.

[0028] The logic coding signal is a coding signal of a signal sequence that needs to be transmitted inside the chip, which is encoded with 0 and 1. Therefore, the logic coding signal includes a logic coding signal carrying logic information 0 and a logic coding signal carrying logic information 1.

[0029] When the signal output controller receives the logic coded signal carrying the logic information 0, it outputs a low level for a time length T1 and a high level for a time length T2. Figure 3 , is a schematic diagram of a logic 0 level provided by an embodiment of the present invention. As shown in the figure, the logic 0 consists of a low level at time T1 and a high level at time T2.

[0030] Step S104: if a logic coded signal carrying logic information 1 is received, a low level is output for a time length T2 and a high level is output for a time length T1.

[0031] When the signal output controller receives the logic coded signal carrying logic information 1, it outputs a low level for a time length of T2 and a high level for a time length of T1. Figure 4 , is a schematic diagram of a logic 1 level provided by an embodiment of the present invention. As shown in the figure, the logic 1 consists of a low level at time T2 and a high level at time T1.

[0032] Step S105: the high level and / or the low level is output to an off-chip acquisition device through a preset single pin, so that the off-chip acquisition device acquires the chip internal signal according to the time length T3.

[0033] The signal output controller converts the chip internal signal sequence into a combination of high level and low level through the above implementation, see Figure 5 , is a schematic diagram of the level of a converted chip internal signal sequence provided by an embodiment of the present invention. As shown in the figure, taking the chip internal signal sequence of idle marker, 1010, idle marker as an example, after the signal output controller converts the level, the serial output is a high level (idle marker) of time length T0, a low level of time length T2, a high level (logic 1) of time length T1, a low level of time length T1, a high level (logic 0) of time length T2, a low level of time length T2, a high level (logic 1) of time length T1, a low level of time length T1, a high level (logic 0) of time length T2, and a high level (idle marker) of time length T0.

[0034] The high level or low level is output to the off-chip acquisition device through a preset single pin. The preset single pin can be a pin led out by the signal output controller, so that the signal output controller can communicate with the off-chip acquisition device through a pin. The off-chip acquisition device decodes the high level and / or low level output by the signal output controller according to the time length T3, and finally completes the acquisition of the chip internal signal.

[0035] In a specific implementation, in order to ensure the accuracy of signal sampling, T0>T1>T2>T3. In an exemplary embodiment, T0 can be configured as 35ns, T1 can be configured as 20ns, T2 can be configured as 10ns, and T3 can be configured as 6ns.

[0036] As can be seen from the description of the above embodiments, the embodiment of the present invention provides a method for sampling internal signals of a chip, by receiving an internal signal sequence of the chip, wherein the internal signal sequence of the chip includes an idle flag that does not carry information, a logic coding signal that carries logic information 0, and a logic coding signal that carries logic information 1; if the idle flag is received, a high level is output according to the time length T0; if the logic coding signal that carries logic information 0 is received, a low level is output according to the time length T1, and a high level is output according to the time length T2; if the logic coding signal that carries logic information 1 is received, a low level is output according to the time length T2, and a high level is output according to the time length T1; the high level and / or the low level is output to an off-chip acquisition device through a preset single pin, so that the off-chip acquisition device acquires the internal signal of the chip according to the time length T3; wherein T0>T1>T2>T3. The present invention uses a single pin to realize the serial output and acquisition of the internal signal of the chip, does not need to occupy a large number of pins to connect the on-chip memory, saves pin resources, and gets rid of the dependence on internal storage, thereby improving the integrity of the acquired signal.

[0037] In the second implementation, the signal output controller encodes the chip internal signal sequence, the first level used in the encoding is a low level, and the second level is a high level, the detailed process is as follows:

[0038] See also Figure 6 , is a flow chart of another method for sampling chip internal signals by a signal output controller provided by an embodiment of the present invention, such as Figure 6 As shown, the embodiment of the present invention shows the process of the signal output controller executing the method.

[0039] Step S201: receiving a chip internal signal sequence, wherein the chip internal signal sequence includes an idle identifier that carries no information, a logic coded signal that carries logic information 0, and a logic coded signal that carries logic information 1.

[0040] Step S202: if an idle flag is received, a low level is output according to the time length T0.

[0041] Step S203: if a logic coded signal carrying logic information 0 is received, a high level is output for a time length T1 and a low level is output for a time length T2.

[0042] Step S204: if a logic coded signal carrying logic information 1 is received, a high level is output for a time length T2 and a low level is output for a time length T1.

[0043] Step S205: The high level and / or the low level is output to an off-chip acquisition device through a preset single pin, so that the off-chip acquisition device acquires the chip internal signal according to the time length T3; wherein T0>T1>T2>T3.

[0044] The difference between the embodiment of the present invention and the aforementioned embodiment is that the signal output controller has a different way of outputting the level of the chip internal signal. The embodiment of the present invention reverses the level relative to the aforementioned embodiment, which also achieves the effect of converting the internal chip signal sequence into a level output. However, since the low level occupies a longer time, it can save power consumption. For other similarities with the aforementioned embodiment, please refer to the description of the above embodiment and will not be repeated here.

[0045] See also Figure 7 , is a flow chart of a method for sampling a chip internal signal by an off-chip acquisition device according to an embodiment of the present invention, such as Figure 7 As shown, the embodiment of the present invention shows the process of the off-chip acquisition device executing the method. Figure 1 The signal output controller shown decodes the level output after executing the chip internal signal sampling method, which corresponds to the first implementation situation in the above-mentioned signal output controller side embodiment, that is, when the first level is a high level and the second level is a low level.

[0046] Step S301: receiving a high level and / or a low level output by a signal output controller via a preset single pin.

[0047] The high level and / or low level output by the signal output controller includes: the signal output controller receives a chip internal signal sequence, wherein the chip internal signal sequence includes an idle flag that carries no information, a logic coding signal that carries logic information 0, and a logic coding signal that carries logic information 1; if an idle flag is received, a high level is output according to a time length T0; if a logic coding signal that carries logic information 0 is received, a low level is output according to a time length T1, and a high level is output according to a time length T2; if a logic coding signal that carries logic information 1 is received, a low level is output according to a time length T2, and a high level is output according to a time length T1; and T0>T1>T2>T3.

[0048] Step S302: If P high levels are sampled, there is no need to extract information, where P is an integer obtained by rounding down T0 / T3.

[0049] After receiving the level output by the signal output controller, the off-chip acquisition device samples the level signal with a time length T3. The time length T3 can be understood as the period of the acquisition clock of the off-chip acquisition device, that is, the off-chip acquisition device samples the received level signal with a clock with a period of T3. Specifically, the level signal of the signal output controller is sampled at the rising edge of the acquisition clock, and information is decoded and extracted.

[0050] For the sake of convenience, in an exemplary embodiment, if the signal sequence in the chip is a 4-bit data sequence generated every 1us, according to the relationship between T0, T1, T2, and T3, the values ​​are as follows:

[0051] The values ​​of P, M, and N can be calculated as follows:

[0052] Among them, P is T0 / T3=35 / 6=5.8, which is rounded down to 5; M is T1 / T3=20 / 6=3.3, which is rounded down to 3; N is T2 / T3=10 / 6=1.7, which is rounded down to 1. Moreover, P, M, and N satisfy: P>M+1, M>N+1. The purpose of this is to prevent logical confusion in the subsequent decoding process, thereby further ensuring sampling accuracy.

[0053] According to the above calculation results, if P high levels are sampled, that is, corresponding to 5 high levels in the above example, it corresponds to an idle marker that does not carry information in the chip's internal signal sequence, and there is no need to extract information.

[0054] In the specific sampling process, see Figure 8 , is a schematic diagram of a sampling process provided by an embodiment of the present invention. As shown in the figure, in an exemplary embodiment, two 4-bit data 1010 and 0101 (not shown, output after the last idle marker) inside the chip are output at an interval of 1us, and the signal output controller outputs the level to the off-chip sampling device. The off-chip sampling device samples the level according to the above-mentioned sampling clock (cycle is T3), and samples the rising edge of each clock. If a high level is sampled, it is recorded as 1, and if a low level is sampled, it is recorded as 0, thereby obtaining collected data; the collected data is further parsed to obtain decoded data, and the decoded data corresponds to the internal signal sequence of the chip.

[0055] In this step, we can also see that P=5 high levels are collected, corresponding to the collected data 11111 (5 1s), which is decoded as idle, indicating that the internal signal of the chip corresponds to the idle flag.

[0056] Step S303: If a combination of 1 high level and M low levels is sampled, extract logic information 0, where M is an integer obtained by rounding down T1 / T3.

[0057] According to the description of the above embodiment, combined with Figure 8 , when a combination of 1 high level and M low levels is sampled, the logic information 0 is extracted. Specifically, in the corresponding figure, logic 0 corresponds to the collection of 1 high level, and M=3 low levels are continuously collected. The collected data is 1000 (1 1, 3 0s). The collected data is analyzed to obtain decoded data, which corresponds to the logic coding signal carrying the logic information 0 (i.e., logic 0) in the chip internal signal sequence.

[0058] Step S304: If a combination of 1 high level, N or N+1 low levels, and 1 high level is sampled, logic information 1 is extracted.

[0059] Likewise, combining Figure 8 , when a combination of 1 high level, N or N+1 low levels, and 1 high level is sampled, the logic information 1 is extracted. Specifically, in the corresponding figure, logic 1 corresponds to 1 high level, 1 low level (N=1), and 1 high level, and the collected data is 101 (1 1, 1 0, 1 1). The collected data is parsed to obtain decoded data, which corresponds to the logic coding signal carrying logic information 1 (i.e. logic 1) in the chip internal signal sequence.

[0060] According to the description of the above embodiment, the corresponding relationship between the state of the signal sequence inside the sampling chip and the collected data is summarized as shown in the following table:

[0061] It should be noted that, in the sampling process, in order to avoid repeated counting and resulting decoding errors, in the embodiments of the present invention, the decoding sequences all start from 1, and corresponding to the sampling level, the judgment starts from the high level. In this way, for logical 0, such as the collected data of 10001, if 1000 and 0001 can both be logical 0, the embodiment of the present invention adopts the method of starting the judgment from the high level, that is, 1000 is confirmed as logical 0, and 0001 is not considered as logical 0, thereby avoiding repeated counting, improving the decoding accuracy, and further ensuring the sampling accuracy.

[0062] See also Fig. 9, is a flow chart of another method for sampling chip internal signals by an off-chip acquisition device provided by an embodiment of the present invention, such as Fig. 9 As shown, the embodiment of the present invention shows the process of the off-chip acquisition device executing the method. Figure 6 The signal output controller shown decodes the level output after executing the chip internal signal sampling method, which corresponds to the second implementation of the above-mentioned signal output controller side embodiment, that is, when the first level is a low level and the second level is a high level.

[0063] Step S401: receiving a high level and / or a low level output by a signal output controller via a preset single pin.

[0064] The high level and / or low level output by the signal output controller includes: receiving a chip internal signal sequence, wherein the chip internal signal sequence includes an idle flag that carries no information, a logic coding signal that carries logic information 0, and a logic coding signal that carries logic information 1; if an idle flag is received, a low level is output according to a time length T0; if a logic coding signal that carries logic information 0 is received, a high level is output according to a time length T1 and a low level is output for a time length T2; if a logic coding signal that carries logic information 1 is received, a high level is output according to a time length T2 and a low level is output for a time length T1; and T0>T1>T2>T3.

[0065] Step S402: If P low levels are sampled, there is no need to extract information, where P is an integer obtained by rounding down T0 / T3.

[0066] Step S403: If a combination of 1 low level and M high levels is sampled, extract logic information 0, where M is an integer obtained by rounding down T1 / T3.

[0067] Step S404: If a combination of 1 low level, N or N+1 high levels, and 1 low level is sampled, extract logic information 1, where N is an integer rounded down from T2 / T3; where P>M+1, and M>N+1.

[0068] The embodiment of the present invention is different from the above-mentioned embodiment in that it is suitable for Figure 6 The level output by the signal output controller shown in the figure, the acquisition and decoding of the level by the off-chip acquisition device are also inversely related to the aforementioned implementation, and the sampling of the internal signal of the chip can also be realized, and the effect of low power consumption is also achieved. The same points between the embodiment of the present invention and the aforementioned embodiment can be referred to the description of the aforementioned embodiment, which will not be repeated here.

[0069] Through the description of the above method embodiments, the technicians in the relevant field can clearly understand that the present invention can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk.

[0070] Corresponding to the embodiment of the chip internal signal sampling method provided by the present invention, the present invention also provides a signal output controller.

[0071] See also Fig.10 , is a schematic diagram of the structure of a signal output controller provided by an embodiment of the present invention. As shown in the figure, the controller includes: The receiving module 11 is used to receive a chip internal signal sequence, wherein the chip internal signal sequence includes an idle identifier that does not carry information, a logic coded signal that carries logic information 0, and a logic coded signal that carries logic information 1; The coding module 12 is configured to output a first level according to a time length T0 if an idle flag is received; output a second level according to a time length T1 and a first level according to a time length T2 if a logic coding signal carrying logic information 0 is received; and output a second level according to a time length T2 and a first level according to a time length T1 if a logic coding signal carrying logic information 1 is received; The output module 13 is used to output the first level and / or the second level to an off-chip acquisition device through a preset single pin, so that the off-chip acquisition device collects the internal signal of the chip according to the time length T3; wherein T0>T1>T2>T3, the first level and the second level are different level signals.

[0072] In a first implementation case, when the first level is a high level, the second level is a low level.

[0073] In a second implementation, when the first level is a low level, the second level is a high level.

[0074] See also Fig.11, is a schematic diagram of the structure of an off-chip acquisition device provided by an embodiment of the present invention. As shown in the figure, the device cooperates with the signal output controller in the above embodiment to perform corresponding decoding according to the encoding logic of the first level and the second level, specifically including: The acquisition module 21 is used to receive the high level and / or low level output by the signal output controller through a preset single pin; wherein the high level and / or low level output by the signal output controller includes: the signal output controller receives a chip internal signal sequence, and the chip internal signal sequence includes an idle identifier that does not carry information, a logic coding signal that carries logic information 0, and a logic coding signal that carries logic information 1; if the idle identifier is received, the first level is output according to the time length T0; if the logic coding signal that carries logic information 0 is received, the second level is output according to the time length T1, and the first level is output according to the time length T2; if the logic coding signal that carries logic information 1 is received, the second level is output according to the time length T2, and the first level is output according to the time length T1; and T0>T1>T2>T3, the first level and the second level are different level signals; The decoding module 22 is used for: if P first levels are sampled, there is no need to extract information, where P is an integer rounded down from T0 / T3; if a combination of 1 first level and M second levels is sampled, extracting logic information 0, where M is an integer rounded down from T1 / T3; if a combination of 1 first level, N or N+1 second levels, and 1 first level is sampled, extracting logic information 1, where N is an integer rounded down from T2 / T3; wherein P>M+1, and M>N+1; When the first level is a high level, the second level is a low level; or, when the first level is a low level, the second level is a high level.

[0075] See also Fig.12 , is a structural schematic diagram of a chip internal signal sampling system provided by an embodiment of the present invention. As shown in the figure, the system includes a signal output controller 31 and an off-chip acquisition device 32. The signal output controller 31 and the off-chip acquisition device 32 are communicatively connected via a preset single pin (not marked), so that the chip internal signal sequence is received by the signal output controller 31 and encoded according to the method described in the above embodiment, and then sent to the off-chip acquisition device 32 for decoding via a single pin, thereby completing the sampling of the chip internal signal sequence.

[0076] Specifically, the signal output controller 31 includes Fig.10 The receiving module 11, encoding module 12 and output module 13 shown in the figure; the off-chip acquisition device 32 includes Fig.11 The acquisition module 21 and the decoding module 22 are shown. The output module 13 is connected to the acquisition module 21 through a preset single pin.

[0077] The above product can execute the method provided by the embodiment of the present invention, and has the functional modules and beneficial effects corresponding to the execution method. For technical details not described in detail in this embodiment, please refer to the method provided by the embodiment of the present invention.

[0078] The electronic device of the embodiment of the present invention exists in various forms, including but not limited to: (1) Mobile communication devices: These devices are characterized by their mobile communication functions and their main purpose is to provide voice and data communications. These terminals include: smart phones (such as iPhone), multimedia phones, functional phones, and low-end phones.

[0079] (2) Ultra-mobile personal computer devices: These devices fall into the category of personal computers, have computing and processing capabilities, and generally also have mobile Internet access features. These terminals include: PDA, MID and UMPC devices, such as iPad.

[0080] (3) Portable entertainment devices: These devices can display and play multimedia content. They include audio and video players (such as iPods), handheld game consoles, e-books, smart toys, and portable car navigation devices.

[0081] (4) Server: A device that provides computing services. The server consists of a processor, hard disk, memory, system bus, etc. The server is similar to a general computer architecture, but because it needs to provide highly reliable services, it has higher requirements in terms of processing power, stability, reliability, security, scalability, and manageability.

[0082] (5) Other electronic devices with data interaction functions.

[0083] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0084] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. The device and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0085] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0086] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for sampling a chip internal signal, characterized in that: Applicable to signal output controllers, including: Receive a chip internal signal sequence, where the chip internal signal sequence includes an idle identifier that does not carry information, a logic coded signal that carries logic information 0, and a logic coded signal that carries logic information 1; If an idle flag is received, a first level is output according to the time length T0; If a logic coded signal carrying logic information 0 is received, the second level is output according to the time length T1 and the first level is output according to the time length T2; If a logic coded signal carrying logic information 1 is received, the second level is output according to the time length T2 and the first level is output according to the time length T1; The first level and / or the second level is output to an off-chip acquisition device through a preset single pin, so that the off-chip acquisition device acquires the chip internal signal according to the time length T3; Among them, T0>T1>T2>T3, the first level and the second level are different level signals.

2. The chip internal signal sampling method according to claim 1, characterized in that: Applicable to signal output controllers, including: When the first level is a high level, the second level is a low level.

3. The chip internal signal sampling method according to claim 1, characterized in that: Applicable to signal output controllers, including: When the first level is a low level, the second level is a high level.

4. A method for sampling a chip internal signal, characterized in that: Applied to off-chip acquisition equipment, including: The first level and / or the second level output by the signal output controller is received by a preset single pin; wherein the first level and / or the second level output by the signal output controller includes: the signal output controller receives a chip internal signal sequence, wherein the chip internal signal sequence includes an idle flag that does not carry information, a logic coding signal that carries logic information 0, and a logic coding signal that carries logic information 1; if the idle flag is received, the first level is output according to the time length T0; if the logic coding signal that carries logic information 0 is received, the second level is output according to the time length T1, and the first level is output according to the time length T2; if the logic coding signal that carries logic information 1 is received, the second level is output according to the time length T2, and the first level is output according to the time length T1; and T0>T1>T2>T3, the first level and the second level are different level signals; If P first levels are sampled, there is no need to extract information, where P is an integer obtained by rounding down T0 / T3; If a combination of 1 first level and M second levels is sampled, logic information 0 is extracted, where M is an integer obtained by rounding down T1 / T3; If a combination of 1 first level, N or N+1 second levels, and 1 first level is sampled, logic information 1 is extracted, where N is an integer obtained by rounding down T2 / T3; Among them, P>M+1, and M>N+1.

5. The method for sampling chip internal signals according to claim 4, characterized in that: Applied to off-chip acquisition equipment, including: When the first level is a high level, the second level is a low level.

6. The method for sampling chip internal signals according to claim 4, characterized in that: Applied to off-chip acquisition equipment, including: When the first level is a low level, the second level is a high level.

7. A signal output controller, characterized in that: include: A receiving module, used to receive a chip internal signal sequence, wherein the chip internal signal sequence includes an idle identifier that does not carry information, a logical coding signal that carries logical information 0, and a logical coding signal that carries logical information 1; The encoding module is configured to output a first level according to a time length T0 if an idle flag is received; If a logic coded signal carrying logic information 0 is received, the second level is output according to the time length T1 and the first level is output according to the time length T2; If a logic coded signal carrying logic information 1 is received, the second level is output according to the time length T2 and the first level is output according to the time length T1; An output module is used to output the first level and / or the second level to an off-chip acquisition device through a preset single pin, so that the off-chip acquisition device collects the internal signal of the chip according to the time length T3; wherein T0>T1>T2>T3, and the first level and the second level are different level signals.

8. The signal output controller according to claim 7, characterized in that: include: When the first level is a high level, the second level is a low level; or, When the first level is a low level, the second level is a high level.

9. An off-chip acquisition device, characterized in that: include: An acquisition module, used for receiving a first level and / or a second level output by a signal output controller through a preset single pin; wherein the first level and / or the second level output by the signal output controller comprises: the signal output controller receives a chip internal signal sequence, wherein the chip internal signal sequence comprises an idle flag that carries no information, a logic coding signal that carries logic information 0, and a logic coding signal that carries logic information 1; if an idle flag is received, a first level is output according to a time length T0; if a logic coding signal that carries logic information 0 is received, a second level is output according to a time length T1, and a first level is output according to a time length T2; if a logic coding signal that carries logic information 1 is received, a second level is output according to a time length T2, and a first level is output according to a time length T1; and T0>T1>T2>T3, the first level and the second level are different level signals; A decoding module, for extracting logic information 0 if P first levels are sampled, where P is an integer rounded down from T0 / T3; extracting logic information 1 if a combination of 1 first level and M second levels is sampled, where N is an integer rounded down from T2 / T3; and extracting logic information 1 if a combination of 1 first level, N or N+1 second levels, and 1 first level is sampled, where N is an integer rounded down from T2 / T3; wherein P>M+1, and M>N+1; When the first level is a high level, the second level is a low level; or, when the first level is a low level, the second level is a high level.

10. A chip internal signal sampling system, characterized in that: It comprises the signal output controller as claimed in claim 7 or 8, and the off-chip acquisition device as claimed in claim 9, wherein the signal output controller is communicatively connected to the off-chip acquisition device via a preset single pin.

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