Memory data signal quality determination method and device, equipment and medium
The method addresses the challenge of evaluating DDR data signal quality at the CPU end by determining the target signal line and constructing scattering parameter models to simulate CPU-end eye diagram data, thereby ensuring system stability and performance.
Patent Information
- Application Number
- CN202411745086.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-29
- Publication Date
- 2025-03-14
AI Technical Summary
Current DDR data signal quality evaluation for the CPU end is challenging due to the lack of defined signal eye diagram metrics, which hinders ensuring system performance and stability.
A method involving extreme testing of memory data signal links with varying signal line lengths to determine the target signal line, constructing no-source scattering parameter models, and simulating CPU-end eye diagram data using source models to assess signal quality.
This approach effectively determines DDR data signal quality at the CPU end, ensuring system performance and stability by identifying the optimal signal line topology and simulating signal conditions.
Smart Images
Figure CN119621510A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of servers, and in particular to a method, device, equipment and medium for determining the quality of a memory data signal. Background Art
[0002] With the rapid development of cloud data centers, server memory technology has undergone many changes, from Synchronous Dynamic Random Access Memory (SDRAM) to the fifth-generation Double Data Rate 5 Synchronous Dynamic Random Access Memory (DDR5). Each generation of Double Data Rate Synchronous Dynamic Random Access Memory (DDR) technology has made significant progress in bandwidth, performance, and power consumption. While promoting the improvement of computing performance, it has also put forward higher requirements for signal integrity.
[0003] To ensure signal quality, active simulation is usually used to optimize passive links and predict the overall link signal margin. However, the DDR data signal read direction protocol only defines the signal eye diagram indicators of the dynamic random access memory (DRAM) particle transmitter, and does not define the eye diagram indicators of the central processing unit (CPU) at the receiving end. This makes it difficult to evaluate the signal quality of the CPU end of the DDR data signal read direction, and it is impossible to ensure the overall performance and stability of the system.
[0004] In view of the above problems, how to solve the problem that the signal quality on the CPU side cannot determine the reading direction of the DDR data signal, and thus cannot ensure the overall performance and stability of the system, is an urgent problem to be solved by technicians in this field. Summary of the invention
[0005] The purpose of the present invention is to provide a method, device, equipment and medium for determining the quality of a memory data signal, so as to solve the problem that the signal quality of a CPU end in the read direction of a DDR data signal cannot be determined at present, and thus the overall performance and stability of the system cannot be ensured.
[0006] In order to solve the above technical problems, the present invention provides a method for determining the quality of a memory data signal, which is applied to a memory data signal test link; the memory data signal test link comprises a memory, an adapter board comprising a plurality of groups of signal lines, and a mainboard provided with a central processing unit; one end of each signal line in the adapter board is connected to the mainboard, and the other end of each signal line is connected to the memory; the central processing unit and the memory are communicatively connected via the signal line of the adapter board; wherein the lengths of each signal line in the adapter board are different; the method comprises:
[0007] Perform a limit test on the memory data signal test link through a memory margin test tool, and use the longest signal line that passes the limit test among the signal lines of the adapter board as the target signal line;
[0008] Acquire a scattering parameter model of a target signal line, and construct a passive scattering parameter model of a memory data signal test link according to the scattering parameter model of the target signal line;
[0009] Constructing a memory data signal active simulation model of a memory data signal test link according to a passive scattering parameter model;
[0010] The eye diagram data of the central processing unit end in the reading direction of the memory data signal is determined according to the active simulation model of the memory data signal, so as to determine the data signal quality in the reading direction of the memory data signal according to the eye diagram data.
[0011] On the one hand, the lengths of the signal lines in the adapter board are increased in sequence according to the preset lengths;
[0012] Correspondingly, the memory data signal test link is subjected to a limit test by using a memory margin test tool, and the longest signal line that passes the limit test among the signal lines of the adapter board is used as the target signal line, including:
[0013] Obtaining a data line reference voltage parameter and a data line delay parameter corresponding to the central processing unit;
[0014] Selecting the test signal lines in turn from the signal lines of the adapter board according to the preset length;
[0015] Based on the test signal line, a limit test is performed on the memory data signal test link according to the data line reference voltage parameter and the data line delay parameter to determine each test signal line that passes the limit test;
[0016] The longest signal line among the test signal lines that pass the limit test is determined as the target signal line.
[0017] On the other hand, a passive scattering parameter model of the memory data signal test link is constructed according to the scattering parameter model of the target signal line, including:
[0018] Obtaining a scattering parameter model of a printed circuit board routing of a mainboard in a memory data signal test link;
[0019] Obtaining a scattering parameter model of a central processor, and scattering parameter models of related connectors and packages in a memory data signal test link;
[0020] According to the scattering parameter model of the target signal line, the scattering parameter model of the printed circuit board routing of the mainboard, the scattering parameter model of the central processing unit, and the scattering parameter model of related connectors and packages, a passive scattering parameter model of the memory data signal test link is constructed.
[0021] On the other hand, a memory data signal active simulation model of a memory data signal test link is constructed based on the passive scattering parameter model, including:
[0022] Obtaining the algorithm modeling interface simulation model of the central processing unit;
[0023] Get the algorithm modeling interface simulation model of the memory particles of the memory;
[0024] According to the passive scattering parameter model, the algorithm modeling interface simulation model of the central processing unit and the algorithm modeling interface simulation model of the memory particle, a memory data signal active simulation model of the memory data signal test link is constructed.
[0025] On the other hand, the eye diagram data of the central processing unit end in the reading direction of the memory data signal is determined according to the active simulation model of the memory data signal, including:
[0026] Obtaining basic operating parameters of a memory data signal test link; wherein the basic operating parameters at least include a memory particle drive resistance value and an on-chip termination parameter of a central processing unit;
[0027] According to the basic operating parameters of the memory data signal test link, simulation parameters are set for the memory data signal active simulation model;
[0028] The simulation operation of the active simulation model of the memory data signal is performed to obtain the eye diagram data of the central processing unit end in the read direction of the memory data signal.
[0029] On the other hand, there are multiple adapter boards, and the signal line length ranges of each adapter board are different;
[0030] Correspondingly, before performing a limit test on the memory data signal test link by using a memory margin test tool and taking the longest signal line that passes the limit test among the signal lines of the adapter board as the target signal line, the method further includes:
[0031] Selecting a test adapter board from each adapter board, and setting the test adapter board in a memory data signal test link;
[0032] Based on the longest signal line and the shortest signal line in the test adapter board, the memory data signal test link is subjected to limit testing by using the memory margin test tool;
[0033] If the memory data signal test link passes the test under the longest signal line of the test adapter board, or fails the test under the shortest signal line of the test adapter board, then the next adapter board is selected from each adapter board as a new test adapter board, and the process returns to the step of placing the test adapter board in the memory data signal test link;
[0034] If the memory data signal test link fails the test under the longest signal line of the test adapter and passes the test under the shortest signal line of the test adapter, the current test adapter is confirmed to be the target adapter;
[0035] Correspondingly, the memory data signal test link is subjected to a limit test by using a memory margin test tool, and the longest signal line that passes the limit test among the signal lines of the adapter board is used as the target signal line, including:
[0036] Selecting a test signal line from among the signal lines of the target adapter board; wherein the test signal line selected for the first time is the shortest signal line among the signal lines of the target adapter board;
[0037] Enable the test signal line, and perform a limit test on the memory data signal test link according to the data line reference voltage parameter and the data line delay parameter;
[0038] Determine whether the memory data signal test link passes the limit test;
[0039] If it is confirmed that the memory data signal test link passes the limit test, then select the next signal line from the signal lines of the target adapter board as a new test signal line according to the preset length, return to the enable test signal line, and perform a limit test on the memory data signal test link according to the data line reference voltage parameter and the data line delay parameter;
[0040] If it is confirmed that the memory data signal test link fails the limit test, it is confirmed that the last test signal line is the target signal line.
[0041] On the other hand, the data signal quality in the read direction of the memory data signal is determined based on the eye diagram data, including:
[0042] Determine whether the vertical margin in the eye diagram data is not less than a first threshold, and the horizontal margin is not less than a second threshold;
[0043] If not, it is confirmed that the data signal quality in the read direction of the memory data signal does not meet the signal quality requirement;
[0044] If so, it is confirmed that the data signal quality of the memory data signal in the read direction meets the signal quality requirement.
[0045] In order to solve the above technical problems, the present invention also provides a memory data signal quality determination device, which is applied to a memory data signal test link; the memory data signal test link includes a memory, an adapter board including multiple groups of signal lines, and a mainboard provided with a central processing unit; one end of each signal line in the adapter board is connected to the mainboard, and the other end of each signal line is connected to the memory; the central processing unit and the memory are communicatively connected through the signal line of the adapter board; wherein the lengths of each signal line in the adapter board are different; the device includes:
[0046] A test module, used to perform a limit test on a memory data signal test link through a memory margin test tool, and use the longest signal line that passes the limit test among the signal lines of the adapter board as a target signal line;
[0047] A first construction module is used to obtain a scattering parameter model of a target signal line, and to construct a passive scattering parameter model of a memory data signal test link according to the scattering parameter model of the target signal line;
[0048] A second building module is used to build a memory data signal active simulation model of a memory data signal test link according to the passive scattering parameter model;
[0049] The determination module is used to determine the eye diagram data of the central processing unit end in the reading direction of the memory data signal according to the active simulation model of the memory data signal, so as to determine the data signal quality in the reading direction of the memory data signal according to the eye diagram data.
[0050] In order to solve the above technical problems, the present invention further provides a memory data signal quality determination device, comprising:
[0051] Memory for storing computer programs;
[0052] A processor is used to implement the steps of the above-mentioned method for determining the quality of memory data signal when executing the computer program.
[0053] In order to solve the above technical problem, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned method for determining the quality of memory data signal are implemented.
[0054] The memory data signal quality determination method provided by the present invention is applied to a memory data signal test link; the memory data signal test link comprises a memory, an adapter board comprising a plurality of signal lines and a main board provided with a central processing unit; one end of each signal line in the adapter board is connected to the main board, and the other end of each signal line is connected to the memory; the central processing unit and the memory are communicatively connected through the signal lines of the adapter board; wherein the lengths of the signal lines in the adapter board are different; the method specifically performs a limit test on the memory data signal test link through a memory margin test tool, and uses the longest signal line that passes the limit test among the signal lines of the adapter board as a target signal line; obtains a scattering parameter model of the target signal line, and constructs a passive scattering parameter model of the memory data signal test link according to the scattering parameter model of the target signal line; constructs an active simulation model of the memory data signal of the memory data signal test link according to the passive scattering parameter model; determines eye diagram data of the central processing unit end in the read direction of the memory data signal according to the active simulation model of the memory data signal, so as to determine the data signal quality in the read direction of the memory data signal according to the eye diagram data.
[0055] The beneficial effects of the present invention are that a transfer board including multiple groups of signal lines is newly added to a memory data signal link; by performing a limit test on the link, the longest target signal line that can pass the limit test is determined among the signal lines of different lengths on the transfer board, thereby finding the limit topology of the memory data signal reading direction; further, a passive scattering parameter model of the memory data signal test link is constructed according to the scattering parameter model of the target signal line, and a memory data signal active simulation model of the memory data signal test link is constructed according to the passive scattering parameter model, thereby using the memory data signal active simulation model to simulate the test link situation, and then determining the eye diagram data of the central processing unit end in the memory data signal reading direction, thereby making up for the problem that the test cannot point-measure the signal on the central processing unit end; analyzing the data signal quality through the eye diagram data ensures the overall performance and stability of the system.
[0056] On the other hand, the present invention specifically obtains the data line reference voltage parameter and data line delay parameter corresponding to the central processing unit; selects the test signal line in turn from each signal line of the adapter board according to the preset length; based on the test signal line, performs limit test on the memory data signal test link according to the data line reference voltage parameter and the data line delay parameter to determine each test signal line that passes the limit test; determines the longest signal line among each test signal line that passes the limit test as the target signal line, thereby realizing the determination of the limit topology of the test link, so as to facilitate the subsequent construction of the active simulation model of the test link based on the scattering parameter model of the target signal line. By obtaining the scattering parameter model of the printed circuit board routing of the motherboard in the memory data signal test link; obtaining the scattering parameter model of the central processing unit in the memory data signal test link, the scattering parameter model of the related connector and the scattering parameter model of the package; according to the scattering parameter model of the target signal line, the scattering parameter model of the printed circuit board routing of the motherboard, the scattering parameter model of the central processing unit, the scattering parameter model of the related connector and the package, the passive scattering parameter model of the memory data signal test link is constructed. Obtain basic operating parameters of a memory data signal test link; set simulation parameters of an active simulation model of a memory data signal according to the basic operating parameters of the memory data signal test link; perform simulation operations on the active simulation model of the memory data signal to obtain eye diagram data of a central processing unit end in a reading direction of the memory data signal, so as to determine the signal quality of the central processing unit end in a reading direction of the memory data signal according to the eye diagram data.
[0057] In addition, the present invention also provides a memory data signal quality determination device, equipment and medium, which have the same effect as above. BRIEF DESCRIPTION OF THE DRAWINGS
[0058] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0059] Figure 1 A schematic diagram of a memory data signal test link provided by an embodiment of the present invention;
[0060] Figure 2 A schematic diagram of an adapter board provided in an embodiment of the present invention;
[0061] Figure 3 A flow chart of a method for determining the quality of a memory data signal provided by an embodiment of the present invention;
[0062] Figure 4 A schematic diagram of a memory data signal quality determination device provided by an embodiment of the present invention;
[0063] Figure 5 A schematic diagram of a memory data signal quality determination device provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0064] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0065] The core of the present invention is to provide a method, device, equipment and medium for determining the quality of memory data signals to solve the problem that the signal quality of the CPU end in the read direction of the DDR data signal cannot be determined, and thus the overall performance and stability of the system cannot be ensured.
[0066] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.
[0067] To ensure signal quality, currently, active simulation is usually used to optimize passive links and predict the overall link signal margin. However, the DDR data signal read direction protocol only defines the signal eye diagram indicators of the DRAM particle sending end, and does not define the eye diagram indicators of the receiving end CPU, which makes it difficult to evaluate the signal quality of the DDR signal data signal reading direction CPU end, and it is impossible to ensure the overall performance and stability of the system. Therefore, in order to solve the above problems, the present invention provides a method for determining the quality of memory data signals. It should be noted that the method is applied to the memory data signal test link.
[0068] Figure 1 A schematic diagram of a memory data signal test link provided by an embodiment of the present invention. Figure 1 As shown, the memory data signal test link includes a memory 5, an adapter board 6 including multiple groups of signal lines and a main board 8 provided with a central processing unit 7; one end of each signal line in the adapter board is connected to the main board, and the other end of each signal line is connected to the memory; the central processing unit and the memory are communicatively connected via the signal lines of the main board and the adapter board; wherein the lengths of each signal line in the adapter board are different.
[0069] It should be noted that the memory data signal test link is a one DIMM per channel (1DPC) configuration. In the memory data signal test link, the central processing unit is fixed to the motherboard through the central processing unit slot (CPU socket) of the motherboard. Figure 2 A schematic diagram of an adapter board provided by an embodiment of the present invention. Figure 2As shown, one end of the adapter board is a memory adapter interface (gold finger), and the other end is a memory slot interface, and the two interfaces are connected by multiple groups of signal lines; the memory adapter interface of the adapter board is fixed to the mainboard by connecting the dual inline memory module (DIMM) connector of the mainboard, and the memory slot interface of the adapter board is specifically used to connect the memory. It should be noted that in this embodiment, there is no restriction on the number and specific length of each signal line in the adapter board, which depends on the specific implementation situation.
[0070] Figure 3 A flow chart of a method for determining the quality of a memory data signal provided by an embodiment of the present invention. Figure 3 As shown, the method includes:
[0071] S10: Performing a limit test on the memory data signal test link by using a memory margin test tool, and taking the longest signal line that passes the limit test among the signal lines of the adapter board as the target signal line.
[0072] In order to determine the eye diagram data of the CPU end in the memory data signal read direction, it is first necessary to perform a limit test on the memory data signal test link through the memory margin test tool (Memory Margin Tool).
[0073] It should be noted that the memory margin test tool uses system-level stress to test the memory subsystem to determine the boundary parameters of the memory system. The tool includes the data line reference voltage margin test (DQ Vref margin) and the data line delay margin test (DQ Delay margin). The test principle of the data line delay margin test is binary scanning: after the margin test function is turned on, the offset time (offset) will be adjusted to the maximum based on the two delay test results of the signal sending direction from the CPU to the memory particles or the signal receiving direction from the CPU to the memory particles during the current server startup process, and it will be determined whether the server system can be entered normally. If the system cannot be entered, the offset will be reduced. If the system is entered normally, the stress test tool will be run on the memory for a preset time. After the end, it will be detected whether there is an error checking and correcting (ECC) error. If there is an ECC error, it means that the current offset has reached the boundary, and then switch to the next test item (that is, the data line reference voltage margin test); if no ECC error occurs, the offset will be increased, the server will be controlled to restart and the next round of testing will be performed until the boundary is scanned as the final margin result.
[0074] The test principle of the data line reference voltage margin test is also binary scanning: after the margin test function is turned on, the offset will be adjusted to the maximum based on the two reference voltage test results of the signal sending direction from the CPU to the memory particles or the signal receiving direction from the CPU to the memory particles during the current server startup process, and it will be determined whether the system can be entered normally. If the system cannot be entered, the offset will be reduced. If the system can be entered normally, the stress test tool will be run on the memory for a preset time. After the end, it will detect whether there is an ECC error. If there is an ECC error, it is confirmed that the margin boundary has been scanned. If there is no ECC error, the offset will be increased, the server will be controlled to restart and the next round of testing will be performed until the boundary is scanned as the final margin result. It should be noted that for memory margin test tools, CPU manufacturers generally provide Margin test indicators, that is, reference voltage parameters and delay parameters for the data signal sending (TX) direction and the data signal receiving (RX) direction.
[0075] Therefore, in this embodiment, after the memory data signal test link is subjected to a limit test by the memory margin test tool, multiple target signal lines that can pass the limit test can be obtained. However, in order to determine the limit topology of the test link, it is necessary to determine the longest signal line that can pass the limit test among the signal lines of the adapter board as the target signal line. It should be noted that in this embodiment, there is no restriction on the specific process of performing a limit test on the memory data signal test link, and there is no restriction on the specific method of determining the target signal line, which depends on the specific implementation situation.
[0076] S11: Acquire a scattering parameter model of a target signal line, and construct a passive scattering parameter model of a memory data signal test link according to the scattering parameter model of the target signal line.
[0077] S12: Constructing a memory data signal active simulation model of a memory data signal test link according to the passive scattering parameter model.
[0078] S13: determining eye diagram data of the central processing unit end in the memory data signal reading direction according to the memory data signal active simulation model, so as to determine data signal quality in the memory data signal reading direction according to the eye diagram data.
[0079] Furthermore, in order to make the eye diagram data of the memory data signal reading direction determined later more accurate, the scattering parameter (S parameter) model of the target signal line of the adapter under the extreme topology is obtained by actual measurement and extraction. It can be understood that the S parameter is an important parameter that describes the frequency domain characteristics of the linear passive transmission channel, which can reflect the reflection, crosstalk, loss and other information of the signal.
[0080] After obtaining the passive scattering parameter model of the memory data signal test link, in order to realize active simulation of the memory data signal test link, a memory data signal active simulation model of the memory data signal test link is constructed specifically according to the passive scattering parameter model. It should be noted that the specific construction process of the passive scattering parameter model and the memory data signal active simulation model is not limited in this embodiment.
[0081] Finally, the eye diagram data of the CPU end in the read direction of the memory data signal is determined according to the active simulation model of the memory data signal, so as to determine the data signal quality in the read direction of the memory data signal according to the eye diagram data. In addition, in order to ensure the rigor of the simulation, multiple tests and simulations can be performed.
[0082] In this embodiment, an adapter board including multiple groups of signal lines is newly added to the memory data signal link; by performing a limit test on the link, the longest target signal line that can pass the limit test is determined among the signal lines of different lengths on the adapter board, thereby finding the limit topology of the memory data signal reading direction; further, a passive scattering parameter model of the memory data signal test link is constructed based on the scattering parameter model of the target signal line, and a memory data signal active simulation model of the memory data signal test link is constructed based on the passive scattering parameter model, so that the memory data signal active simulation model is used to simulate the test link situation, and then the eye diagram data of the central processing unit end in the memory data signal reading direction is determined, which makes up for the problem that the test cannot point-measure the signal on the central processing unit end; the data signal quality is analyzed by the eye diagram data to ensure the overall performance and stability of the system.
[0083] On the basis of the above embodiments, in some embodiments, the length of each signal line in the adapter board increases in sequence according to the preset length. It should be noted that there is no restriction on the preset length in this embodiment. For example, there are 10 groups of signal lines in the adapter board, and the line length range of the adapter board is 0-2 inches. When the preset length is 0.2 inches, the lengths of the signal lines in the adapter board are 0.2 inches, 0.4 inches, 0.6 inches, 0.8 inches, 1.0 inches, 1.2 inches, 1.4 inches, 1.6 inches, 1.8 inches and 2.0 inches respectively.
[0084] Correspondingly, the memory data signal test link is subjected to a limit test by using a memory margin test tool, and the longest signal line that passes the limit test among the signal lines of the adapter board is used as the target signal line, including:
[0085] S101: Acquire a data line reference voltage parameter and a data line delay parameter corresponding to a central processing unit;
[0086] S102: selecting a test signal line from each signal line of the adapter board in sequence according to a preset length;
[0087] S103: Based on the test signal line, perform a limit test on the memory data signal test link according to the data line reference voltage parameter and the data line delay parameter to determine each test signal line that passes the limit test;
[0088] S104: Determine the longest signal line among the test signal lines that pass the limit test as the target signal line.
[0089] In order to determine the longest target signal line that passes the limit test, in this embodiment, the data line reference voltage parameter and the data line delay parameter corresponding to the central processing unit are specifically obtained, that is, the data line reference voltage parameter and the data line delay parameter provided by the CPU manufacturer. Further, according to the preset length, the test signal line is selected in turn from each signal line of the adapter board, and based on the test signal line, the memory data signal test link is subjected to a limit test according to the data line reference voltage parameter and the data line delay parameter to determine each test signal line that passes the limit test.
[0090] It is understandable that during the limit test, when the increase in the signal line length Margin just reaches the specification (spec) value given by the CPU manufacturer, that is, reaches the given data line reference voltage parameter and data line delay parameter, and the increase in length does not meet the spec value, it can be considered that the limit topology of the data signal has been found, and the signal line has reached the maximum length. Therefore, after performing the limit test using each test signal line, the longest signal line among the test signal lines that pass the limit test is determined as the target signal line.
[0091] In this embodiment, by obtaining data line reference voltage parameters and data line delay parameters corresponding to the central processing unit; selecting test signal lines in turn from the signal lines of the adapter board according to preset lengths; based on the test signal lines, a limit test is performed on the memory data signal test link according to the data line reference voltage parameters and the data line delay parameters to determine the test signal lines that pass the limit test; the longest signal line among the test signal lines that pass the limit test is determined as the target signal line, thereby achieving the determination of the limit topology of the test link, so as to facilitate the subsequent construction of an active simulation model of the test link based on the scattering parameter model of the target signal line.
[0092] On the basis of the above embodiments, in some embodiments, a passive scattering parameter model of a memory data signal test link is constructed according to a scattering parameter model of a target signal line, including:
[0093] S111: Obtain a scattering parameter model of a printed circuit board routing of a mainboard in a memory data signal test link;
[0094] S112: Acquire a scattering parameter model of a central processor, and scattering parameter models of related connectors and packages in a memory data signal test link;
[0095] S113: Construct a passive scattering parameter model of a memory data signal test link according to a scattering parameter model of a target signal line, a scattering parameter model of a printed circuit board routing of a mainboard, a scattering parameter model of a central processing unit, and scattering parameter models of related connectors and packages.
[0096] Specifically, electromagnetic simulation software is first used to obtain the scattering parameter model of the printed circuit board routing of the mainboard in the memory data signal test link. In this embodiment, there is no restriction on the specific electromagnetic simulation software selected. The scattering parameter model of the central processing unit in the memory data signal test link, the scattering parameter model of the related connector and the package are further obtained.
[0097] It should be noted that the relevant connectors and packages in this embodiment at least include a CPU socket and a DIMM connector on a motherboard, and it is also necessary to obtain scattering parameter models of the CPU package and the memory package.
[0098] Finally, based on the scattering parameter model of the target signal line, the scattering parameter model of the printed circuit board routing of the motherboard, the scattering parameter model of the central processing unit, and the scattering parameter model of the related connectors and packages, the passive scattering parameter model of the memory data signal test link is constructed. In this way, the construction of the passive S parameter model of the entire test link is realized.
[0099] On the basis of the above embodiments, in some embodiments, a memory data signal active simulation model of a memory data signal test link is constructed according to a passive scattering parameter model, including:
[0100] S121: Acquire an algorithm modeling interface simulation model of a central processing unit;
[0101] S122: Acquire an algorithm modeling interface simulation model of a memory particle of the memory;
[0102] S123: constructing a memory data signal active simulation model of a memory data signal test link according to the passive scattering parameter model, the algorithm modeling interface simulation model of the central processing unit, and the algorithm modeling interface simulation model of the memory particle.
[0103] In order to construct the active simulation model of the memory data signal, in this embodiment, the algorithmic modeling interface simulation (AMI) model of the central processing unit is specifically obtained, and the algorithmic modeling interface simulation model of the memory particles of the memory is obtained at the same time. According to the passive scattering parameter model, the algorithmic modeling interface simulation model of the central processing unit and the algorithmic modeling interface simulation model of the memory particles, the active simulation model of the memory data signal of the memory data signal test link is constructed.
[0104] Based on the above embodiments, in some embodiments, the eye diagram data of the central processing unit end in the read direction of the memory data signal is determined according to the active simulation model of the memory data signal, including:
[0105] S131: Obtain basic operating parameters of a memory data signal test link;
[0106] Among them, the basic operating parameters at least include the memory particle driving resistance value and the on-chip termination parameters of the central processing unit;
[0107] S132: setting simulation parameters for the memory data signal active simulation model according to basic operating parameters of the memory data signal test link;
[0108] S133: Execute a simulation operation of the active simulation model of the memory data signal to obtain eye diagram data of the central processing unit end in the read direction of the memory data signal.
[0109] In order to determine the eye diagram data of the central processing unit end in the reading direction of the memory data signal, the basic operating parameters of the memory data signal test link are specifically obtained in this embodiment. It should be noted that the basic operating parameters at least include the memory particle drive resistance value and the on-die termination (ODT) parameters of the central processing unit. According to the basic operating parameters of the memory data signal test link, the simulation parameters of the active simulation model of the memory data signal are set, that is, the simulation parameter settings are all consistent with the actual measurement. Finally, the simulation operation of the active simulation model of the memory data signal is performed to obtain the eye diagram data of the central processing unit end in the reading direction of the memory data signal, so as to determine the signal quality of the central processing unit end in the reading direction of the memory data signal according to the eye diagram data.
[0110] In order to avoid having too many signal lines in one adapter board, which would make the testing process cumbersome and increase unnecessary hardware costs, in this embodiment, there are multiple adapter boards, and the signal lines of each adapter board have different length ranges.
[0111] For example, there are 5 adapter boards in total, and the length of each group of signal lines on each adapter board increases; the signal line length range of the first adapter board is 0~2 inches, the line length step is 0.2 inches, and there are 10 groups of signal lines of different lengths. The signal line length range of the second adapter board is 2~4 inches, and the line length step is also 0.2 inches. Similarly, the signal line length range of the third adapter board is 4~6 inches, and the line length step is 0.2 inches. The signal line length range of the fourth adapter board is 6~8 inches. The signal line length range of the fifth adapter board is 8~10 inches.
[0112] In order to improve the test efficiency, before determining the target signal line, it is necessary to determine the most suitable adapter board among all adapter boards, that is, it is necessary to first determine the adapter board where the target signal line is located. Correspondingly, before performing a limit test on the memory data signal test link through the memory margin test tool and taking the longest signal line that has passed the limit test among the signal lines of the adapter board as the target signal line, it also includes:
[0113] S14: selecting a test adapter board from each adapter board, and setting the test adapter board in a memory data signal test link;
[0114] S15: Based on the longest signal line and the shortest signal line in the test adapter, a memory data signal test link is subjected to a limit test by using a memory margin test tool;
[0115] S16: If the memory data signal test link passes the test under the longest signal line of the test adapter, or fails the test under the shortest signal line of the test adapter, then select the next adapter from each adapter as a new test adapter, and return to the step of setting the test adapter in the memory data signal test link;
[0116] S17: If the memory data signal test link fails the test under the longest signal line of the test adapter and passes the test under the shortest signal line of the test adapter, the current test adapter is confirmed to be the target adapter.
[0117] Specifically, a test adapter is selected from each adapter, and the test adapter is set in the memory data signal test link. Further, based on the longest signal line and the shortest signal line in the test adapter, the memory data signal test link is subjected to a limit test through a memory margin test tool. For example, if the signal line length range of the test adapter is 0 to 2 inches, then the longest signal line and the shortest signal line in the test adapter are 0.2 inches and 2 inches respectively, and the memory data signal test link is subjected to a limit test based on the signal lines of 0.2 inches and 2 inches in length respectively.
[0118] If the memory data signal test link passes the test under the longest signal line of the test adapter board, or fails the test under the shortest signal line of the test adapter board, it means that the current test adapter board does not meet the requirements and the target signal line is not on the current test adapter board, so the next adapter board is selected from each adapter board as a new test adapter board, and the process returns to the step of setting the test adapter board in the memory data signal test link. If the memory data signal test link fails the test under the longest signal line of the test adapter board, and passes the test under the shortest signal line of the test adapter board, it means that the current test adapter board meets the requirements and the target signal line is on the current test adapter board, and the current test adapter board is confirmed to be the target adapter board.
[0119] Correspondingly, the memory data signal test link is subjected to a limit test by using a memory margin test tool, and the longest signal line that passes the limit test among the signal lines of the adapter board is used as the target signal line, including:
[0120] S105: Selecting a test signal line from the signal lines of the target adapter board;
[0121] The test signal line selected for the first time is the shortest signal line among the signal lines of the target adapter board;
[0122] S106: enabling the test signal line, and performing a limit test on the memory data signal test link according to the data line reference voltage parameter and the data line delay parameter;
[0123] S107: Determine whether the memory data signal test link passes the limit test; if it is confirmed that the memory data signal test link passes the limit test, proceed to step S108; otherwise, proceed to step S109;
[0124] S108: Selecting the next signal line from the signal lines of the target adapter board as a new test signal line according to the preset length, and returning to step S106;
[0125] S109: Confirm that the last tested signal line is the target signal line.
[0126] After the target adapter board is determined, in order to accurately determine the target signal line in the target adapter board, a test signal line is specifically selected from the signal lines of the target adapter board. It is understandable that the test signal line selected for the first time is the shortest signal line among the signal lines of the target adapter board. Enable the test signal line, and perform a limit test on the memory data signal test link according to the data line reference voltage parameters and the data line delay parameters. It should be noted that only the test signal line is enabled at the same time.
[0127] Further determine whether the memory data signal test link passes the limit test; if it is confirmed that the memory data signal test link passes the limit test, select the next signal line from the signal lines of the target adapter board as the new test signal line according to the preset length. For example, if the current test signal line is 0.2 inches, select the 0.4-inch signal line as the new test signal line. If it is confirmed that the memory data signal test link does not pass the limit test, confirm that the current test signal line exceeds the limit, and confirm that the previous test signal line is the target signal line. In this way, the determination of the target signal line is achieved when there are multiple adapter boards of different specifications.
[0128] In addition, in a specific embodiment, multiple adapter boards of the same specifications may be provided. For example, there are 5 adapter boards with signal line lengths ranging from 0 to 2 inches and line length steps of 0.2 inches. An adapter board group is generated by splicing multiple adapter boards. The signal line length of the adapter board group ranges from 0 to 10 inches. After splicing, different signal line lengths can be obtained. When the memory data signal test link is subjected to a limit test through the memory margin test tool, different signal lines are combined by splicing adapter boards to obtain a signal line combination; the longest target signal line that can pass the limit test is determined in each signal line combination. Since the specifications of each adapter board are the same, the hardware cost is greatly reduced while meeting the link test.
[0129] Based on the above embodiments, in some embodiments, determining the data signal quality in the read direction of the memory data signal according to the eye diagram data includes:
[0130] S18: Determine whether the vertical margin in the eye diagram data is not less than the first threshold, and the horizontal margin is not less than the second threshold; if not, confirm that the data signal quality in the reading direction of the memory data signal does not meet the signal quality requirements; if so, confirm that the data signal quality in the reading direction of the memory data signal meets the signal quality requirements.
[0131] After obtaining the eye diagram data of the memory data signal reading direction, in order to determine the signal quality of the memory data signal reading direction, it is specifically determined whether the vertical margin in the eye diagram data is not less than the first threshold, and the horizontal margin is not less than the second threshold. In this embodiment, there is no restriction on the first threshold and the second threshold, which depends on the specific implementation situation.
[0132] If it is confirmed that the vertical margin in the eye diagram data is less than the first threshold value, and / or the horizontal margin is less than the second threshold value, it is confirmed that the data signal quality in the read direction of the memory data signal does not meet the signal quality requirement. If it is confirmed that the vertical margin in the eye diagram data is not less than the first threshold value, and the horizontal margin is not less than the second threshold value, it is confirmed that the data signal quality in the read direction of the memory data signal meets the signal quality requirement.
[0133] In the above embodiments, the determination of the quality of the memory data signal is described in detail. The present invention also provides an embodiment corresponding to the device for determining the quality of the memory data signal.
[0134] Figure 4 A schematic diagram of a memory data signal quality determination device provided by an embodiment of the present invention. The device is applied to a memory data signal test link; the memory data signal test link includes a memory, an adapter board including multiple groups of signal lines, and a mainboard provided with a central processing unit; one end of each signal line in the adapter board is connected to the mainboard, and the other end of each signal line is connected to the memory; the central processing unit and the memory are connected to each other through the signal line of the adapter board; wherein the lengths of each signal line in the adapter board are different; such as Figure 4 As shown, the device comprises:
[0135] The test module 10 is used to perform a limit test on the memory data signal test link through a memory margin test tool, and to use the longest signal line that passes the limit test among the signal lines of the adapter board as the target signal line.
[0136] The first construction module 11 is used to obtain a scattering parameter model of a target signal line, and to construct a passive scattering parameter model of a memory data signal test link according to the scattering parameter model of the target signal line.
[0137] The second building module 12 is used to build a memory data signal active simulation model of the memory data signal test link according to the passive scattering parameter model.
[0138] The determination module 13 is used to determine the eye diagram data of the central processing unit end in the reading direction of the memory data signal according to the active simulation model of the memory data signal, so as to determine the data signal quality in the reading direction of the memory data signal according to the eye diagram data.
[0139] In some embodiments, the lengths of the signal lines in the adapter board are increased in sequence according to the preset lengths;
[0140] Correspondingly, the test module 10 includes:
[0141] A first acquisition submodule, used to acquire a data line reference voltage parameter and a data line delay parameter corresponding to the central processing unit;
[0142] A first selection submodule, used to select a test signal line in sequence from each signal line of the adapter board according to a preset length;
[0143] A first test submodule, for performing a limit test on a memory data signal test link based on a test signal line according to a data line reference voltage parameter and a data line delay parameter, so as to determine each test signal line that passes the limit test;
[0144] The first determining submodule is used to determine the longest signal line among the test signal lines that pass the limit test as the target signal line.
[0145] In some embodiments, the first building block 11 includes:
[0146] A second acquisition submodule is used to acquire a scattering parameter model of a printed circuit board routing of a mainboard in a memory data signal test link;
[0147] A third acquisition submodule is used to acquire a scattering parameter model of a central processor, a scattering parameter model of related connectors and a package in a memory data signal test link;
[0148] The first construction submodule is used to construct a passive scattering parameter model of the memory data signal test link according to the scattering parameter model of the target signal line, the scattering parameter model of the printed circuit board routing of the mainboard, the scattering parameter model of the central processing unit, and the scattering parameter models of related connectors and packages.
[0149] In some embodiments, the second building block 12 includes:
[0150] The fourth acquisition submodule is used to acquire the algorithm modeling interface simulation model of the central processing unit;
[0151] A fifth acquisition submodule is used to acquire an algorithm modeling interface simulation model of a memory particle of the memory;
[0152] The second construction submodule is used to construct a memory data signal active simulation model of a memory data signal test link according to the passive scattering parameter model, the algorithm modeling interface simulation model of the central processing unit and the algorithm modeling interface simulation model of the memory particle.
[0153] In some embodiments, the determination module 13 includes:
[0154] The sixth acquisition submodule is used to acquire basic operating parameters of the memory data signal test link; wherein the basic operating parameters at least include the memory particle drive resistance value and the on-chip termination parameters of the central processing unit;
[0155] A first setting submodule is used to set simulation parameters of the memory data signal active simulation model according to basic operating parameters of the memory data signal test link;
[0156] The simulation submodule is used to perform simulation operations of the active simulation model of the memory data signal to obtain the eye diagram data of the central processing unit end in the reading direction of the memory data signal.
[0157] In some embodiments, there are multiple adapter boards, and the signal line length ranges of each adapter board are different;
[0158] Correspondingly, it also includes:
[0159] A second selection submodule is used to select a test adapter board from each adapter board, and set the test adapter board in the memory data signal test link;
[0160] A second test submodule is used to perform a limit test on a memory data signal test link through a memory margin test tool based on the longest signal line and the shortest signal line in the test adapter board respectively;
[0161] A third selection submodule is used for selecting the next adapter board from among the adapter boards as a new test adapter board if the memory data signal test link passes the test under the longest signal line of the test adapter board, or fails the test under the shortest signal line of the test adapter board, and returns to the step of setting the test adapter board in the memory data signal test link;
[0162] A first confirmation submodule, for confirming that the current test adapter is a target adapter if the memory data signal test link fails the test under the longest signal line of the test adapter and passes the test under the shortest signal line of the test adapter;
[0163] Correspondingly, the test module 10 includes:
[0164] A fourth selection submodule is used to select a test signal line from among the signal lines of the target adapter board; wherein the test signal line selected for the first time is the shortest signal line among the signal lines of the target adapter board;
[0165] A third test submodule, used to enable the test signal line and perform a limit test on the memory data signal test link according to the data line reference voltage parameter and the data line delay parameter;
[0166] The first judgment submodule is used to judge whether the memory data signal test link passes the limit test; if it is confirmed that the memory data signal test link passes the limit test, the next signal line is selected from the signal lines of the target adapter board as a new test signal line according to the preset length, and the test signal line is enabled, and the memory data signal test link is subjected to the limit test according to the data line reference voltage parameter and the data line delay parameter; if it is confirmed that the memory data signal test link does not pass the limit test, the previous test signal line is confirmed to be the target signal line.
[0167] In some embodiments, the determination module 13 includes:
[0168] The second judgment submodule is used to judge whether the vertical margin in the eye diagram data is not less than the first threshold, and the horizontal margin is not less than the second threshold; if not, it is confirmed that the data signal quality in the reading direction of the memory data signal does not meet the signal quality requirements; if so, it is confirmed that the data signal quality in the reading direction of the memory data signal meets the signal quality requirements.
[0169] Since the embodiments of the apparatus part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the apparatus part, which will not be repeated here.
[0170] In addition, the present invention also provides a computer program product, including a computer program / instruction, which implements the steps of the method for determining the quality of a memory data signal when the computer program / instruction is executed by a processor.
[0171] Figure 5 A schematic diagram of a memory data signal quality determination device provided by an embodiment of the present invention. Figure 5 As shown, the memory data signal quality determination device includes:
[0172] A memory 20, used for storing computer programs;
[0173] The processor 21 is used to implement the steps of the method for determining the quality of memory data signal mentioned in the above embodiment when executing the computer program.
[0174] The memory data signal quality determination device provided in this embodiment may include but is not limited to a smart phone, a tablet computer, a laptop computer, or a desktop computer.
[0175] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one hardware form of a digital signal processor (DSP), a field programmable gate array (FPGA), and a programmable logic array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 21 may be integrated with a graphics processing unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.
[0176] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 20 is at least used to store the following computer program 201, wherein, after the computer program is loaded and executed by the processor 21, it can implement the relevant steps of the memory data signal quality determination method disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 202 may include Windows, Unix, Linux, etc. Data 203 may include but is not limited to data involved in the memory data signal quality determination method.
[0177] In some embodiments, the memory data signal quality determination device may further include a display screen 22 , an input / output interface 23 , a communication interface 24 , a power supply 25 , and a communication bus 26 .
[0178] Those skilled in the art will understand that Figure 5 The structure shown in the figure does not constitute a limitation on the memory data signal quality determination device, and may include more or less components than those shown in the figure.
[0179] Finally, the present invention also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps recorded in the above method embodiment are implemented.
[0180] It is understandable that if the method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc. Various media that can store program codes.
[0181] The above is a detailed introduction to a method, device, equipment and medium for determining the quality of a memory data signal provided by the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can be referenced to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the present invention.
[0182] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.
Claims
1. A method for determining the quality of a memory data signal, characterized in that: Applied to memory data signal test link; the memory data signal test link includes memory, an adapter board including multiple groups of signal lines and a mainboard with a central processing unit; one end of each signal line in the adapter board is connected to the mainboard, and the other end of each signal line is connected to the memory; The central processing unit and the memory are connected to each other through signal lines of the adapter board; wherein the lengths of the signal lines in the adapter board are different; and the method comprises: Perform a limit test on the memory data signal test link through a memory margin test tool, and use the longest signal line that passes the limit test among the signal lines of the adapter board as the target signal line; Acquire a scattering parameter model of a target signal line, and construct a passive scattering parameter model of a memory data signal test link according to the scattering parameter model of the target signal line; Constructing a memory data signal active simulation model of a memory data signal test link according to a passive scattering parameter model; The eye diagram data of the central processing unit end in the reading direction of the memory data signal is determined according to the active simulation model of the memory data signal, so as to determine the data signal quality in the reading direction of the memory data signal according to the eye diagram data.
2. The method for determining the quality of memory data signal according to claim 1, characterized in that: The length of each signal line in the adapter board increases in sequence according to the preset length; Correspondingly, the memory data signal test link is subjected to a limit test by using a memory margin test tool, and the longest signal line that passes the limit test among the signal lines of the adapter board is used as the target signal line, including: Obtaining a data line reference voltage parameter and a data line delay parameter corresponding to the central processing unit; Selecting the test signal lines in turn from the signal lines of the adapter board according to the preset length; Based on the test signal line, a limit test is performed on the memory data signal test link according to the data line reference voltage parameter and the data line delay parameter to determine each test signal line that passes the limit test; The longest signal line among the test signal lines that pass the limit test is determined as the target signal line.
3. The method for determining the quality of a memory data signal according to claim 1, wherein: The passive scattering parameter model of the memory data signal test link is constructed based on the scattering parameter model of the target signal line, including: Obtaining a scattering parameter model of a printed circuit board routing of a mainboard in a memory data signal test link; Obtaining a scattering parameter model of a central processor, and scattering parameter models of related connectors and packages in a memory data signal test link; According to the scattering parameter model of the target signal line, the scattering parameter model of the printed circuit board routing of the mainboard, the scattering parameter model of the central processing unit, and the scattering parameter model of related connectors and packages, a passive scattering parameter model of the memory data signal test link is constructed.
4. The method for determining the quality of a memory data signal according to claim 1, wherein: The memory data signal active simulation model of the memory data signal test link is constructed based on the passive scattering parameter model, including: Obtaining the algorithm modeling interface simulation model of the central processing unit; Get the algorithm modeling interface simulation model of the memory particles of the memory; According to the passive scattering parameter model, the algorithm modeling interface simulation model of the central processing unit and the algorithm modeling interface simulation model of the memory particle, a memory data signal active simulation model of the memory data signal test link is constructed.
5. The method for determining the quality of a memory data signal according to claim 1, wherein: The eye diagram data of the central processing unit end of the memory data signal reading direction is determined according to the active simulation model of the memory data signal, including: Obtaining basic operating parameters of a memory data signal test link; wherein the basic operating parameters at least include a memory particle drive resistance value and an on-chip termination parameter of a central processing unit; According to the basic operating parameters of the memory data signal test link, simulation parameters are set for the memory data signal active simulation model; The simulation operation of the active simulation model of the memory data signal is performed to obtain the eye diagram data of the central processing unit end in the read direction of the memory data signal.
6. The method for determining the quality of memory data signal according to claim 2, characterized in that: There are multiple adapter boards, and the signal line length ranges of each adapter board are different; Correspondingly, before performing a limit test on the memory data signal test link by using a memory margin test tool and taking the longest signal line that passes the limit test among the signal lines of the adapter board as the target signal line, the method further includes: Selecting a test adapter board from each adapter board, and setting the test adapter board in a memory data signal test link; Based on the longest signal line and the shortest signal line in the test adapter board, the memory data signal test link is subjected to limit testing by using the memory margin test tool; If the memory data signal test link passes the test under the longest signal line of the test adapter board, or fails the test under the shortest signal line of the test adapter board, then the next adapter board is selected from each adapter board as a new test adapter board, and the process returns to the step of placing the test adapter board in the memory data signal test link; If the memory data signal test link fails the test under the longest signal line of the test adapter and passes the test under the shortest signal line of the test adapter, the current test adapter is confirmed to be the target adapter; Correspondingly, the memory data signal test link is subjected to a limit test by using a memory margin test tool, and the longest signal line that passes the limit test among the signal lines of the adapter board is used as the target signal line, including: Selecting a test signal line from among the signal lines of the target adapter board; wherein the test signal line selected for the first time is the shortest signal line among the signal lines of the target adapter board; Enable the test signal line, and perform a limit test on the memory data signal test link according to the data line reference voltage parameter and the data line delay parameter; Determine whether the memory data signal test link passes the limit test; If it is confirmed that the memory data signal test link passes the limit test, then select the next signal line from the signal lines of the target adapter board as a new test signal line according to the preset length, return to the enable test signal line, and perform a limit test on the memory data signal test link according to the data line reference voltage parameter and the data line delay parameter; If it is confirmed that the memory data signal test link fails the limit test, it is confirmed that the last test signal line is the target signal line.
7. The method for determining the quality of a memory data signal according to any one of claims 1 to 6, characterized in that: Determine the data signal quality in the read direction of the memory data signal based on the eye diagram data, including: Determine whether the vertical margin in the eye diagram data is not less than a first threshold, and the horizontal margin is not less than a second threshold; If not, it is confirmed that the data signal quality in the read direction of the memory data signal does not meet the signal quality requirement; If so, it is confirmed that the data signal quality of the memory data signal in the read direction meets the signal quality requirement.
8. A device for determining the quality of a memory data signal, characterized in that: Applied to memory data signal test link; the memory data signal test link includes memory, an adapter board including multiple groups of signal lines and a mainboard with a central processing unit; one end of each signal line in the adapter board is connected to the mainboard, and the other end of each signal line is connected to the memory; The central processing unit and the memory are connected to each other through the signal lines of the adapter board; wherein the lengths of the signal lines in the adapter board are different; the device comprises: A test module, used to perform a limit test on a memory data signal test link through a memory margin test tool, and use the longest signal line that passes the limit test among the signal lines of the adapter board as a target signal line; A first construction module is used to obtain a scattering parameter model of a target signal line, and to construct a passive scattering parameter model of a memory data signal test link according to the scattering parameter model of the target signal line; A second building module is used to build a memory data signal active simulation model of a memory data signal test link according to the passive scattering parameter model; The determination module is used to determine the eye diagram data of the central processing unit end in the reading direction of the memory data signal according to the active simulation model of the memory data signal, so as to determine the data signal quality in the reading direction of the memory data signal according to the eye diagram data.
9. A device for determining the quality of a memory data signal, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the method for determining the quality of a memory data signal as claimed in any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method for determining the quality of a memory data signal according to any one of claims 1 to 7 are implemented.