Address-based memory control method, mapping control system and chip

Abstract

The invention discloses an address-based memory control method, a mapping control system and a chip, and the memory control method comprises the steps: after executing a preset starting code stored in a first nonvolatile memory, switching an address needing to be accessed into a physical address of a second nonvolatile memory, then determining to call the second non-volatile memory, the first non-volatile memory supporting rewriting, and the second non-volatile memory not supporting rewriting; under the condition that the second nonvolatile memory is called, if interruption occurs, skipping to a corresponding interruption vector position in an interruption vector table in the second nonvolatile memory, and then executing an interruption processing function; wherein the interrupt vector does not support modification; and under the condition of calling the second nonvolatile memory, skipping and executing a performance function based on a to-be-executed address transmitted to the second nonvolatile memory from the outside. And the application flexibility of the nonvolatile memory is improved.

Description

Technical Field

[0001] The present invention relates to the field of computers, and in particular to an address-based memory control method, a mapping control system and a chip. Background Art

[0002] In the current single-chip microcomputer on-chip storage system, after the user program source code is compiled into a binary file, the interrupt vector table is located at the starting position of the binary file. Due to the ARM architecture, when an interrupt occurs, the starting address of the interrupt processing function is obtained from the 0x00000000 address (i.e., the starting address of the storage structure), so after the user program is burned into the storage medium, the interrupt vector table needs to be mapped to the 0 address. However, the Cortex-M0 core cannot support the remapping of the interrupt vector table. Therefore, the interrupt vector table remapping method provided in the related art is usually to first burn the user code to the starting address of at least one newly opened target flash memory storage area (such as the memory space of the flash memory device, the memory space of the random access memory), and then map the target flash memory storage area to the 0x00000000 address of another flash memory storage area, so as to achieve the purpose of remapping, and then jump to another flash memory storage area to execute the user program, thereby limiting the flexibility of the use of the storage area. At the same time, the code pre-cured to the other flash memory storage area is difficult to ensure perfection, and may not be allowed to be modified under certain storage conditions, increasing the difficulty of later maintenance. Summary of the invention

[0003] The present application provides an address-based memory control method, a mapping control system and a chip. The specific technical solutions are as follows: An address-based memory control method, after executing a preset startup code stored in a first non-volatile memory, switches the address to be accessed to the storage address of the interrupt vector table of the second non-volatile memory, so that the first non-volatile memory is mapped to the second non-volatile memory, and then determines to call the second non-volatile memory; wherein, the first non-volatile memory supports rewriting, and the second non-volatile memory does not support rewriting; in the case of calling the second non-volatile memory, if an interrupt occurs, jump to the corresponding interrupt vector in the interrupt vector table in the second non-volatile memory, and then execute the interrupt processing function; wherein, the interrupt vector is used to identify the starting address of the interrupt processing function, and the interrupt vector does not support modification; in the case of calling the second non-volatile memory, based on the to-be-executed address transmitted externally to the second non-volatile memory, jump and execute the function function, wherein the to-be-executed address is the starting address of the function function; the to-be-executed address supports modification.

[0004] To summarize, the technical solution executes function code between two non-volatile memories with different write attributes by bus switching, and maps them to the physical address of the second non-volatile memory in a targeted manner. The mapped address is used to start calling the second non-volatile memory, and the corresponding interrupt vector can be obtained from the interrupt vector table in the second non-volatile memory, and then the stored interrupt processing function can be jumped and executed. Alternatively, the additional function function can be jumped and executed directly based on the address to be executed transmitted externally to the second non-volatile memory. When the address to be executed is modified, the function function to be jumped and executed is directly changed to expand the program code that can be executed when the processor unit calls the second non-volatile memory, and it is also convenient to maintain functions, codes, and programs to improve the functions to be executed.

[0005] Compared with the prior art, the entire process does not require moving code and copying interrupt vectors between two non-volatile memories. Ultimately, the code is run based on the mapping to the second non-volatile memory. This also overcomes the problem that the relevant core of the processor unit cannot support interrupt vector table mapping. Compared with the mutual mapping method between two or more non-volatile memories, the flexibility of program code running in the corresponding memory is improved, thereby solving the problem that the core of the microprocessor in the related technology cannot support the remapping of the interrupt vector table, and the code maintenance problem caused by code modification and improvement under certain storage conditions.

[0006] Further, when the preset boot code stored in the first non-volatile memory starts to be executed, the address to be accessed by the processor unit is switched to the storage address of the preset boot code in the first non-volatile memory, until the preset boot code stored in the first non-volatile memory is executed, and the address to be accessed by the processor unit is switched to the storage address of the interrupt vector table in the second non-volatile memory by configuring the register in the bus; wherein the speed of the processor unit accessing the first non-volatile memory is lower than the speed of the processor unit accessing the second non-volatile memory; wherein the interrupt vector table in the first non-volatile memory is the same as the interrupt vector table in the second non-volatile memory. If the first non-volatile memory does not have the conditions for triggering an interrupt, the interrupt in the first non-volatile memory is not effective, and the processor unit does not choose to execute the interrupt processing function in the first non-volatile memory, but after being mapped to the storage address of the interrupt vector table in the second non-volatile memory, chooses to execute the interrupt processing function in a storage area (second non-volatile memory) with a faster operation / access speed. Implementation: The above switching process will not bring any operational risk to each memory.

[0007] Furthermore, the interrupt vectors included in the interrupt vector table in the first non-volatile memory are the same as the interrupt vectors included in the interrupt vector table in the second non-volatile memory, so that: whether the storage address of the interrupt vector table in the first non-volatile memory is switched to the storage address of the interrupt vector table in the second non-volatile memory, or the storage address of the interrupt vector table in the second non-volatile memory is switched to the storage address of the interrupt vector table in the first non-volatile memory, the vector address currently accessed by the processor unit and the interrupt processing function currently required to be executed are not changed; wherein the vector address is the storage address of the interrupt vector. This ensures that the program will not run wrong after redirection, and there is no need to modify the compilation and download options for remapping, which brings convenience to debugging.

[0008] Furthermore, if the storage address of the interrupt vector table in the second non-volatile memory is not switched, no interruption occurs; if the storage address of the interrupt vector table in the second non-volatile memory is switched, it is determined that the first non-volatile memory is mapped to the second non-volatile memory, and it is determined to call the second non-volatile memory; then the interrupt is allowed to be triggered to establish an interrupt entry, and jump to the corresponding interrupt vector in the second non-volatile memory is realized. The corresponding interrupt vector is started to be obtained from the interrupt vector table in the second non-volatile memory. Furthermore, the address to be executed is the starting address of the function configured by the processor unit, and the processor unit transmits the address to be executed to the second non-volatile memory through the bus; the second non-volatile memory supports jumping and executing the function function through the address to be executed; the function function includes: the solidified program stored in the second non-volatile memory except the interrupt processing function, and / or the new program obtained by modifying the original interrupt processing function by the processor unit, so that when the processor unit calls the second non-volatile memory, it jumps and executes the program except the interrupt processing function. In this way, the problem of imperfect code stored in the second non-volatile memory is overcome. When the code needs to be modified, the function that can be jumped to by the modified address to be executed can be selected. When the address to be executed is modified, the function to be jumped and executed is directly changed to expand the program code that can be executed when the processor unit calls the second non-volatile memory.

[0009] Furthermore, after the processor unit is powered on or reset, the preset startup code is first executed to initialize the processor unit; wherein the preset startup code is an initialization program in the remaining storage space other than the storage space occupied by the interrupt vector table in the first non-volatile memory; wherein the interrupt vector table in the first non-volatile memory is not allowed to change, the program stored in the first non-volatile memory is allowed to be modified, or the first non-volatile memory accepts a new program burned externally. Then the first non-volatile memory forms a storage space that supports user rewriting and compilation.

[0010] A mapping control system, comprising a processor unit, a bus control unit, a second non-volatile memory, and a first non-volatile memory; the processor unit is used to access the second non-volatile memory or the first non-volatile memory through the bus control unit; the processor unit is used to configure the bus control unit to switch the address to be accessed to the storage address of the interrupt vector table in the second non-volatile memory after executing the preset startup code stored in the first non-volatile memory, so that the first non-volatile memory is mapped to the second non-volatile memory, and then determine to access the second non-volatile memory through the bus control unit; the first non-volatile memory supports rewriting, and the second non-volatile memory does not support rewriting; the processor unit is used to configure the bus control unit to switch the address to be accessed to the storage address of the interrupt vector table in the second non-volatile memory after executing the preset startup code stored in the first non-volatile memory, so that the first non-volatile memory is mapped to the second non-volatile memory, and then determine to access the second non-volatile memory through the bus control unit; the first non-volatile memory supports rewriting, and the second non-volatile memory does not support rewriting; A processor unit is used for, when the second non-volatile memory is accessed through the bus control unit, if an interrupt occurs, jumping to the corresponding interrupt vector in the interrupt vector table of the second non-volatile memory, and then executing the interrupt processing function; wherein the interrupt vector is used to identify the starting address of the interrupt processing function, and the interrupt vector does not support modification; the processor unit is also used for, when the second non-volatile memory is accessed through the bus control unit, transmitting the address to be executed to the second non-volatile memory through the bus control unit, and then jumping and executing the function function based on the address to be executed; wherein the address to be executed is the starting address of the function function; the address to be executed supports modification so that the address to be executed is not equal to the interrupt vector.

[0011] A chip, the chip comprises the mapping control system; or the chip stores a computer program, and the chip is configured to execute the memory control method when running. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A flowchart of an address-based memory control method is disclosed as an embodiment of the present application.

[0013] Figure 2 A module schematic diagram of a mapping control system is disclosed for one embodiment of the present application. Implementation

[0014] In the following description, specific details are given to provide a thorough understanding of the embodiment. However, it will be appreciated by those skilled in the art that embodiments can be implemented without these specific details. For example, a circuit can be shown in a block diagram so as not to obscure the embodiment in unnecessary details. In other cases, in order not to confuse the embodiment, known circuits, structures and techniques may not be shown in detail. As used in this application, the term "if" can be interpreted as "when..." or "once" or "in response to determining" or "in response to detecting" according to the context. Similarly, the phrase "if determined" or "if [described condition or event] is detected" can be interpreted as meaning "once determined" or "in response to determining" or "once [described condition or event] is detected" or "in response to detecting [described condition or event]" according to the context.

[0015] In the on-chip storage system of the single-chip microcomputer, two first non-volatile memories that support data and code erasure are used for address mapping. Generally, the user first burns or copies the program code to a first non-volatile memory, and then maps the program code from the first non-volatile memory to another first non-volatile memory, and then jumps to another storage area to execute the program code. Since the operation speed of each first non-volatile memory is relatively slow, at least compared to the operation speed of the read-only memory, the code running performance of the on-chip storage system is reduced, and the interrupt application of a single memory is also restricted.

[0016] The present application discloses an address-based memory control method, the execution subject of which can be regarded as a controller mounted on the same bus as the first non-volatile memory and the second non-volatile memory, such as a processor unit (abbreviated as CPU), which is used to manage the interrupt vectors, physical addresses (storage addresses) and other function addresses of each memory, and can execute the code, program, function corresponding to the function address. Figure 1 As shown, the memory control method includes: After executing the preset startup code stored in the first non-volatile memory, the address that the processor unit needs to access is switched to the storage address of the interrupt vector table in the second non-volatile memory, so that the first non-volatile memory is mapped to the second non-volatile memory, which can realize the mapping of the physical address of the first non-volatile memory to the physical address of the second non-volatile memory, and then determine to call the second non-volatile memory. Among them, the physical address of the first non-volatile memory includes the storage address of the interrupt vector table in the first non-volatile memory, and also includes the storage address of the preset startup code; the physical address of the second non-volatile memory includes the storage address of the interrupt vector table in the second non-volatile memory, and also includes the cache address of the function address transmitted from the outside; in some embodiments, the storage address of the vector table set by the processor unit or the storage address of the interrupt vector table of the first non-volatile memory is mapped to the storage address of the interrupt vector table in the second non-volatile memory, and a mapping relationship is established between the corresponding interrupt vectors, so as to jump from the second non-volatile memory to execute the corresponding function.

[0017] In this embodiment, the switching of the address that the processor unit needs to access is switched by the bus, and the register control switching is configured by software; when the switch circuit connected to the bus selects the access path of the address to the storage address of the corresponding interrupt vector solidified in the second non-volatile memory, the processor unit will access the corresponding interrupt vector solidified in the second non-volatile memory through the bus, start calling the second non-volatile memory, and then jump to the interrupt vector and execute the interrupt processing function; when the switch circuit connected to the bus selects the access path of its address to the storage address in the first non-volatile memory, it starts calling the first non-volatile memory to execute the preset startup code stored in the first non-volatile memory to initialize the relevant registers of the processor unit.

[0018] In the case of calling the second non-volatile memory, if an interrupt occurs, including an abnormal interrupt and a normal interrupt request in response to the processor unit, the corresponding interrupt vector is obtained from the interrupt vector table in the second non-volatile memory, and then based on the obtained interrupt vector, the interrupt processing function is jumped and executed, that is, the interrupt processing function identified by the obtained interrupt vector is first jumped to, and then the interrupt processing function currently jumped to is executed. The interrupt processing function is the executable code of the interrupt service program stored at the interrupt vector; thereby calling the interrupt vector table in the second non-volatile memory and its corresponding interrupt processing function, abandoning the interrupt vector table in the first non-volatile memory, and completing the re-designation of the storage address of the interrupt vector. Among them, the interrupt vector is used to identify the starting address of the interrupt processing function, but not the burning address of the interrupt processing function; the interrupt vector does not support modification so that the interrupt processing function does not allow modification; in the present application, the interrupt vector table stored in the second non-volatile memory is not allowed to be modified, and other interrupt vectors will not be written into it.

[0019] In the second non-volatile memory or the first non-volatile memory, the interrupt vector stores a jump instruction (also an executable code); when responding to an interrupt, the hardware automatically executes the jump instruction at the corresponding interrupt vector, and then jumps to the entry address of the interrupt processing function. At this time, the interrupt processing function is jumped and executed based on the obtained interrupt vector.

[0020] Preferably, the size of the interrupt vector is 4 bytes; the first address of the interrupt vector is pre-configured, and the starting address of the interrupt processing function is taken out from the 4 storage units starting from the first address. It can be understood that the interrupt vector is used to identify the starting address of the interrupt processing function.

[0021] It should be noted that for an interrupt to take effect, the interrupt configuration-related registers of the processor unit, bus and related memory need to be initialized and set, generally after executing the preset startup code stored in the first non-volatile memory and before starting to call the second non-volatile memory. After the interrupt is triggered, the processor unit will jump to the interrupt vector.

[0022] The interrupt vector table in the second non-volatile memory is pre-fixed, and the interrupt processing function corresponding to each interrupt vector in the interrupt vector table is a code that is pre-fixed (which can be understood as pre-burned), and does not need to be copied from the first non-volatile memory to execute the pre-fixed code. The speed at which the second non-volatile memory is read and written is faster than the speed at which the first non-volatile memory is read and written. Therefore, after executing the preset startup code stored in the first non-volatile memory, the processor unit disclosed in the present application preferentially calls the second non-volatile memory and jumps to its interrupt vector to execute the corresponding interrupt processing function.

[0023] In some embodiments, the interrupt vector table in the second non-volatile memory and the interrupt vector table in the first non-volatile memory can use the same storage address and the same interrupt vector in their respective physical storage spaces, so that each interrupt vector included in the interrupt vector table in the second non-volatile memory and each interrupt vector included in the interrupt vector table in the first non-volatile memory are one-to-one corresponding, and then there will be no problem of access address difference or execution function difference in the process of bus switching to select the second non-volatile memory and the first non-volatile memory, ensuring that the program will not run wrong after redirection. With this interrupt vector configuration method, there is no need to modify the compilation and download options of the first non-volatile memory for remapping, which brings convenience to debugging.

[0024] Preferably, the interrupt vector table stored in the second non-volatile memory is not allowed to be modified, and the interrupt vector will not be written therein, so the interrupt vector stored in the second non-volatile memory does not support modification.

[0025] In the case of calling the second non-volatile memory, based on the to-be-executed address externally transmitted to the second non-volatile memory, the function function is jumped and executed, wherein the to-be-executed address is the starting address of the function function, which is generally configured in real time by the processor unit and matches the address currently required to be accessed; the to-be-executed address supports modification, especially accepts the modification and compilation of the processor unit, so that the to-be-executed address is not equal to the interrupt vector, and the function function is also modified. When the to-be-executed address is modified, the function function that is jumped and executed is directly changed to expand the program code that can be executed when the processor unit calls the second non-volatile memory. In some embodiments, the address to be executed is not equal to the interrupt vector, so that the function function is different from the interrupt processing function. The address to be executed is not necessarily stored in the second non-volatile memory, but the address to be executed can guide the processor unit to jump to a function function other than the interrupt processing function within or outside the relevant code area of ​​the second non-volatile memory to call a new function function to meet the functional requirements of the processor unit other than the interrupt processing function. This can make up for the problem of imperfect interrupt processing functions solidified in the second non-volatile memory. Of course, the problem of imperfect interrupt processing functions can also be solved by switching the address of the interrupt vector table in the second non-volatile memory to the address of the interrupt vector table in the first non-volatile memory to call the code function modified and compiled by the user. However, simply calling the second non-volatile memory in conjunction with the editable address to be executed transmitted from the outside is more convenient than repeatedly switching the mapping operation between the two memories, thereby improving the flexibility of using the second non-volatile memory.

[0026] In summary, the present application performs function code operation between two non-volatile memories with different write attributes by bus switching, and maps the function code to the physical address of the second non-volatile memory in a targeted manner, and then uses the mapped address to call the second non-volatile memory, and can obtain the corresponding interrupt vector from the interrupt vector table in the second non-volatile memory, and then jump and execute the stored interrupt processing function, or directly jump and execute the additional function function based on the to-be-executed address transmitted externally to the second non-volatile memory, and when the to-be-executed address is modified, directly change the function function to be jumped and executed, so as to expand the program code that can be executed when the processor unit calls the second non-volatile memory, and also facilitate the maintenance of functions, codes, and programs to improve the functions to be executed. Thus, it replaces the remapping method of first burning the user program to the starting address of the embedded flash memory, and then mapping the starting address of the embedded flash memory to the starting address of the storage structure or other storage structure where the embedded flash memory is located in the prior art.

[0027] Compared with the prior art, the entire process does not require moving code and copying interrupt vectors between two non-volatile memories. Ultimately, the code is run based on the mapping to the second non-volatile memory. This also overcomes the problem that the relevant core of the processor unit cannot support interrupt vector table mapping. Compared with the mutual mapping method between two or more non-volatile memories, the flexibility of program code running in the corresponding non-volatile memory is improved, thereby solving the problem that the core of the microprocessor in the related art cannot support the remapping of the interrupt vector table, and the code maintenance problem caused by code modification and improvement under certain storage conditions.

[0028] As an embodiment, when the processor unit is powered on or reset, the processor unit starts to execute the preset startup code stored in the first non-volatile memory to initialize the relevant registers, but does not modify the interrupt vector table. When starting to execute the preset startup code stored in the first non-volatile memory, the address that the processor unit needs to access is switched to the storage address of the preset startup code in the first non-volatile memory, that is, the running address of the preset startup code is configured as the initial running address of the code in the first non-volatile memory, until the processor unit finishes executing the preset startup code stored in the first non-volatile memory. The processor unit switches the address that needs to be accessed from the storage address of the preset startup code to the storage address of the interrupt vector table in the second non-volatile memory by configuring the relevant registers in the bus, thereby starting to map the storage address of the first non-volatile memory to the storage address of the preset startup code. The second non-volatile memory (which can be further mapped to the storage address of the interrupt vector in the second non-volatile memory) is called, and the second non-volatile memory is started. At this time, there is no storage address mapped to the interrupt vector table of the first non-volatile memory, so that the first non-volatile memory does not have the conditions to trigger an interrupt, and the interrupt in the first non-volatile memory is not effective. The processor unit does not choose to execute the interrupt processing function in the first non-volatile memory, but after mapping to the storage address of the interrupt vector table in the second non-volatile memory, it chooses to execute the interrupt processing function in the storage area (second non-volatile memory) with faster operation / access speed. Implementation: The above switching process will not bring operating risks to each memory, for example, there will be no phenomenon that the interrupt processing function running in the first non-volatile memory conflicts with the interrupt processing function running in the second non-volatile memory.

[0029] It should be noted that the speed at which the processor unit accesses the first non-volatile memory is lower than the speed at which the processor unit accesses the second non-volatile memory. The first non-volatile memory supports being rewritten by external data, while the second non-volatile memory does not support being rewritten by external data. Therefore, the first non-volatile memory can be classified as a boot memory, while the second non-volatile memory is classified as a fast memory. The first non-volatile memory can use OTP (One Time Programming), MTP (multi-time program), flash memory and other memories in which data and code can be rewritten, but the first non-volatile memory may not use SRAM (static random access memory) in this application; the second non-volatile memory is preferably ROM (Read Only Memory), that is, fast memory generally uses read-only memory, which does not support writing new data codes and modifying and compiling the original code data. In order to ensure the access performance of the processor unit, the interrupt entry is selected to be set in the second non-volatile memory, and the first non-volatile memory is selected in the power-on initialization phase, and after executing the preset startup code stored in the first non-volatile memory, a mapping relationship between the first non-volatile memory and the second non-volatile memory with a faster running speed (relative to the running speed of the first non-volatile memory) can be stably established.

[0030] In some embodiments, after the processor unit executes the preset startup code stored in the first non-volatile memory, the processor unit jumps to the main function to configure the function registers, that is, to configure the relevant registers in the bus, and on this basis, the bus switches the address to be accessed from the storage address of the preset startup code or the address of the interrupt vector table in the first non-volatile memory to the storage address of the interrupt vector table in the second non-volatile memory.

[0031] Preferably, in the process of the processor unit switching the address to be accessed from the storage address of the preset startup code to the storage address of the interrupt vector table in the second non-volatile memory by configuring the relevant registers in the bus, a mapping relationship is established between the code storage address of the second non-volatile memory and the code storage address of the first non-volatile memory, and the initial address of the running code of the first non-volatile memory is corresponded to the initial address of the running code stored in the second non-volatile memory, so as to realize the mapping of the first non-volatile memory to the second non-volatile memory. It should be noted that the mapping of the first non-volatile memory to the second non-volatile memory belongs to address mapping, and the address mapping is a one-to-one correspondence between the addresses identified in the two memories.

[0032] On the basis of the above-mentioned embodiment, the interrupt vectors included in the interrupt vector table in the first non-volatile memory are the same as the interrupt vectors included in the interrupt vector table in the second non-volatile memory. Then, the interrupt vector table in the second non-volatile memory and the interrupt vector table in the first non-volatile memory can use storage addresses (physical addresses) of equal values ​​and the same interrupt vectors (corresponding to the identifier of the same interrupt processing function) in their respective physical storage spaces, so that: no matter the storage address of the interrupt vector table in the first non-volatile memory is switched to the storage address of the interrupt vector table in the second non-volatile memory (corresponding to the mapping of the first non-volatile memory to the second non-volatile memory), or the storage address of the interrupt vector table in the second non-volatile memory is switched to the storage address of the interrupt vector table in the first non-volatile memory (corresponding to the mapping of the second non-volatile memory to the first non-volatile memory), the interrupt vector table in the first non-volatile memory is switched to the storage address of the interrupt vector table in the second non-volatile memory (corresponding to the mapping of the second non-volatile memory to the first non-volatile memory). memory), neither the vector address currently accessed by the processor unit nor the interrupt processing function currently to be executed (the function identified by the interrupt vector at the currently accessed vector address) is changed, wherein the vector address is the storage address of the interrupt vector, and on the basis of this address configuration and the interrupt vector configuration, the interrupt vectors included in the interrupt vector table in the second non-volatile memory and the interrupt vectors included in the interrupt vector table in the first non-volatile memory are one-to-one corresponding, and the problem of access address difference or execution function difference will not occur in the process of the bus switching to select the second non-volatile memory and the first non-volatile memory, and thus the function execution will not be terminated due to the access address difference or the execution function difference, and even after the program is terminated, it will still run according to the original logic flow. Therefore, by adopting this interrupt vector configuration method, it is not necessary to modify the compilation and download options of the first non-volatile memory for the remapping of the processor unit, which brings convenience to debugging.

[0033] In the case where the processor unit does not switch the address to be accessed to the storage address of the interrupt vector table in the second non-volatile memory, no interrupt occurs, that is, no jump to the interrupt vector in the second non-volatile memory occurs; specifically, at power-on startup, code is run from the first non-volatile memory, and the processor unit executes the preset startup code. The physical address of the preset startup code is not within the storage address covered by the interrupt vector table, and the function address of the preset startup code is not an interrupt vector. At this time, the storage address of the vector table to be accessed is not switched to the storage address of the interrupt vector table in the first non-volatile memory, and the processor unit does not jump to the interrupt vector, so that the first non-volatile memory does not have the conditions for triggering an interrupt, and the interrupt does not take effect, thereby ensuring that the subsequent switching process will not bring code running risks, for example, there will be no conflict between the interrupt processing function running in the first non-volatile memory and the interrupt processing function running in the second non-volatile memory.

[0034] After the processor unit has switched the address to be accessed to the storage address of the interrupt vector table in the second non-volatile memory, it is determined that the address to be accessed by the processor unit is switched from the storage address of the first non-volatile memory to the storage address of the second non-volatile memory, and it is determined that the first non-volatile memory is mapped to the second non-volatile memory, and it is determined to call the second non-volatile memory, and the corresponding interrupt vector is an interrupt vector pre-solidified in the second non-volatile memory; then the interrupt is allowed to be triggered to establish an interrupt entry in the second non-volatile memory, instead of establishing an interrupt entry in the first non-volatile memory, so as to jump to the corresponding interrupt vector in the second non-volatile memory, wherein the interrupt entry established in the second non-volatile memory is not allowed to be modified, so as to provide a stable interrupt entry resource.

[0035] It should be noted that the interrupt vector is the starting address of the interrupt processing function, and the interrupt vector does not support modification. In the present application, the interrupt vector table stored in the second non-volatile memory is not allowed to be modified, and other interrupt vectors will not be written into it. The interrupt vector is also called the entry address (starting address) of the interrupt processing function (program). The storage address of the interrupt vector stores a jump instruction to the entry address of the interrupt processing function (program), and the starting address of the jump instruction is preferably the interrupt vector.

[0036] Preferably, within the scope understandable to personnel in the relevant technical field, a minimum 1KB storage space of a memory is specified to store interrupt vectors (256 in total), and this minimum 1KB storage space is called an interrupt vector table, and the storage address range in the second non-volatile memory or the first non-volatile memory is 0~3FFH.

[0037] In some embodiments, after the bus control unit switches the address that the processor unit needs to access to the storage address of the interrupt vector table in the second non-volatile memory, it needs to jump to the interrupt vector to execute the interrupt processing function. In the code corresponding to the currently executed interrupt processing function, the interrupt vector table of the first non-volatile memory can be mapped to the 0x00000000 address of the interrupt vector table of the second non-volatile memory; then, the processor unit jumps to the starting address of the interrupt processing function, and then executes the interrupt processing function. Alternatively, the address that the processor unit needs to access is mapped to the address to be executed, and then the processor unit jumps and executes the instruction.

[0038] When the second non-volatile memory is called, the second non-volatile memory cannot be modified by itself, that is, the program code function stored in the second non-volatile memory cannot be modified, which causes troubles in later maintenance. In order to solve this problem, when calling the second non-volatile memory, the parameters passed by the processor unit can include function pointers. The function pointer can save the function address in a memory other than the second non-volatile memory. Then the processor unit can pass it to the second non-volatile memory by means of function pointers, thereby realizing the call of the new function. There is no need to move the code from the second non-volatile memory to run, but to access the second non-volatile memory through the bus and run the new code.

[0039] The address to be executed is the function running address configured by the processor unit. The processor unit transmits the address to be executed to the second non-volatile memory through the bus. At this time, the address that the processor unit needs to access can be understood as the storage address of the interrupt vector table in the second non-volatile memory that has been switched. The processor unit and the second non-volatile memory are both in a functional running state; the second non-volatile memory supports jumping and executing the function function through the address to be executed. The function function includes: a solidified program other than the interrupt processing function stored in the second non-volatile memory, and / or a new program obtained by modifying the original interrupt processing function by the processor unit, so that when the processor unit calls the second non-volatile memory, it jumps and executes the program other than the interrupt processing function. In this way, the problem of imperfect code stored in the second non-volatile memory is overcome. When the code needs to be modified, the function to which the modified address to be executed can be jumped can be selected.

[0040] Specifically, in the case of calling the second non-volatile memory, based on the address to be executed transmitted externally to the second non-volatile memory, the function function is jumped and executed, wherein the address to be executed is the starting address of the function function, which is generally configured in real time by the processor unit and matches the address currently required to be accessed; the address to be executed supports modification, especially accepting modification compilation by the processor unit so that the address to be executed is not equal to the interrupt vector; when the address to be executed is modified, the function function to be jumped and executed is directly changed to expand the program code that can be executed when the processor unit calls the second non-volatile memory.

[0041] As an embodiment, after the processor unit is powered on or reset, the preset startup code is first executed to initialize the processor unit and trigger the first non-volatile memory to be mapped to the second non-volatile memory; the processor unit starts to execute the preset startup code stored in the first non-volatile memory to initialize relevant registers, and the processor unit enters the power-on startup state, but does not modify the interrupt vector table. Specifically, before the first non-volatile memory is mapped to the second non-volatile memory, the address that the processor unit needs to access is switched to the storage address of the preset startup code in the first non-volatile memory until the processor unit executes the preset startup code stored in the first non-volatile memory. The processor unit switches the address that needs to be accessed from the storage address of the preset startup code to the address of the interrupt vector table in the second non-volatile memory by configuring the relevant registers in the bus, thereby starting to map the address that the processor unit needs to access to the storage address of the interrupt vector table in the second non-volatile memory (which can be further mapped to the interrupt vector in the second non-volatile memory), that is, the first non-volatile memory is mapped to the second non-volatile memory, and then it is determined to start calling the second non-volatile memory.

[0042] In this embodiment, the preset startup code is an initialization program in the remaining storage space outside the storage area occupied by the interrupt vector table in the first non-volatile memory; wherein, the interrupt vector table in the first non-volatile memory is not allowed to change, the program stored in the first non-volatile memory is allowed to be modified, or the first non-volatile memory accepts a new program burned externally, then the first non-volatile memory forms a storage space that supports users to rewrite and compile. Moreover, the various vector addresses covered by the interrupt vector table in the first non-volatile memory are the same as the various vector addresses covered by the interrupt vector table in the second non-volatile memory, so that each vector address in the first non-volatile memory is mapped to the corresponding vector address in the second non-volatile memory; the vector address is the storage address of the interrupt vector. Since the interrupt vector in the first non-volatile memory does not support self-modification, it is ensured that the program will not run wrong after redirection, and there is no need to modify the compilation and download options for remapping, which brings convenience to debugging.

[0043] The present application also discloses a mapping control system, such as Figure 2 As shown, the mapping control system includes a processor unit, a bus control unit, a second non-volatile memory, and a first non-volatile memory; the processor unit is used to access the second non-volatile memory or the first non-volatile memory through the bus control unit; in the mapping control system, the first non-volatile memory and the second non-volatile memory are mounted on the same bus, and the bus control unit controller determines whether the processor unit accesses the second non-volatile memory, the first non-volatile memory, or other memories, wherein the processor unit (abbreviated as CPU) is used to manage the interrupt vectors, physical addresses (storage addresses), and other function addresses of each memory, and can execute the code, program, and function corresponding to the function address. Among them, the first non-volatile memory supports rewriting, and the second non-volatile memory does not support rewriting.

[0044] The processor unit is used to configure the bus control unit to switch the address to be accessed to the storage address of the interrupt vector table in the second non-volatile memory after executing the preset startup code stored in the first non-volatile memory, so that the first non-volatile memory is mapped to the second non-volatile memory. In this embodiment, the switching of the address to be accessed by the processor unit is performed by the switch circuit device included in the bus control unit, and the register control switching is configured by software, which is a mapping process implemented by hardware, and the storage address of the corresponding interrupt vector solidified in the second non-volatile memory is mapped to the storage address of the interrupt vector table in the first non-volatile memory, and then the second non-volatile memory is determined to be accessed through the bus control unit. The storage address of the vector table set by the processor unit or the storage address of the interrupt vector table in the first non-volatile memory is mapped to the storage address of the interrupt vector table in the second non-volatile memory, and a mapping relationship is established between the corresponding interrupt vectors, so as to jump from the second non-volatile memory and execute the corresponding function.

[0045] When the bus control unit selects the access path of the address to the storage address of the corresponding interrupt vector solidified in the second non-volatile memory, the processor unit will access the corresponding interrupt vector solidified in the second non-volatile memory through the bus, and the processor unit starts to access the second non-volatile memory, jumps to the interrupt vector, and executes the interrupt processing function; when the bus control unit selects the access path of its address to the storage address in the first non-volatile memory, the processor unit starts to access the first non-volatile memory to execute the preset startup code stored in the first non-volatile memory and initialize the relevant registers of the processor unit.

[0046] The processor unit is used for, when the second non-volatile memory is accessed through the bus control unit, if an interrupt occurs, obtaining the corresponding interrupt vector from the interrupt vector table in the second non-volatile memory, and then jumping and executing the interrupt processing function based on the obtained interrupt vector; wherein, the interrupt vector is used to identify the starting address of the interrupt processing function, and the interrupt vector does not support modification; when the processor unit accesses the second non-volatile memory, if an interrupt occurs, including an abnormal interrupt and a response to a normal interrupt request, obtaining the corresponding interrupt vector from the interrupt vector table in the second non-volatile memory, then jumping to the interrupt processing function identified by the currently obtained interrupt vector, and then executing the currently jumped interrupt processing function, the interrupt processing function is the executable code responsible for the interrupt service program stored at the interrupt vector; thereby, the processor unit accesses the interrupt vector table and its corresponding interrupt processing function in the second non-volatile memory, abandons the interrupt vector table in the first non-volatile memory, and completes the re-assignment of the storage address of the interrupt vector. Among them, the interrupt vector is used to identify the starting address of the interrupt processing function, but it is not the burned address of the interrupt processing function; the interrupt vector does not support modification so that the interrupt processing function is not allowed to be modified; in the present application, the interrupt vector table stored in the second non-volatile memory is not allowed to be modified, and other interrupt vectors will not be written into it.

[0047] In the second non-volatile memory or the first non-volatile memory, the interrupt vector stores a jump instruction (also an executable code); when responding to an interrupt, the hardware automatically executes the jump instruction at the corresponding interrupt vector, and then jumps to the entry address of the interrupt processing function. At this time, the interrupt processing function is jumped and executed based on the obtained interrupt vector.

[0048] Preferably, the size of the interrupt vector is 4 bytes; the first address of the interrupt vector is pre-configured, and the starting address of the interrupt processing function is taken out from the 4 storage units starting from the first address. It can be understood that the interrupt vector is used to identify the starting address of the interrupt processing function.

[0049] It should be noted that for an interrupt to take effect, the interrupt configuration-related registers of the processor unit, bus and related memory need to be initialized and set, generally after executing the preset startup code stored in the first non-volatile memory and before starting to call the second non-volatile memory. After the interrupt is triggered, the processor unit will jump to the interrupt vector.

[0050] The interrupt vector table in the second non-volatile memory is pre-fixed, and the interrupt processing function corresponding to each interrupt vector in the interrupt vector table is a code that is pre-fixed (which can be understood as pre-burned), and does not need to be copied from the first non-volatile memory to execute the pre-fixed code. The speed at which the second non-volatile memory is read and written is faster than the speed at which the first non-volatile memory is read and written. Therefore, after executing the preset startup code stored in the first non-volatile memory, the processor unit disclosed in the present application preferentially accesses the second non-volatile memory and jumps to its interrupt vector to execute the corresponding interrupt processing function.

[0051] In some embodiments, the interrupt vector table in the second non-volatile memory and the interrupt vector table in the first non-volatile memory can use the same storage address and the same interrupt vector in their respective physical storage spaces, so that the interrupt vectors included in the interrupt vector table in the second non-volatile memory and the interrupt vectors included in the interrupt vector table in the first non-volatile memory are one-to-one corresponding. Then, when the bus control unit switches and selects the second non-volatile memory and the first non-volatile memory, there will be no problem of difference in access address or execution function of the processor unit, ensuring that the program will not run wrong after redirection. With this interrupt vector configuration method, there is no need to modify the compilation and download options of the first non-volatile memory for the remapping of the processor unit, which brings convenience to debugging.

[0052] The processor unit is used to transmit the address to be executed to the second non-volatile memory through the bus control unit when accessing the second non-volatile memory through the bus control unit, and then jump and execute the function function based on the address to be executed; wherein the address to be executed is the starting address of the function function; the address to be executed is not an interrupt vector, so that the function function is different from the interrupt processing function, and the processor unit can call the program function that is not solidified in the processor unit during the process of accessing the second non-volatile memory. In the case of the processor unit accessing the second non-volatile memory, based on the address to be executed output by the processor unit, jump and execute the function function, wherein the address to be executed is the starting address of the function function, which is generally configured by the processor unit and matches the address currently required to be accessed; the address to be executed supports modification, especially accepts the modification and compilation of the processor unit, so that the address to be executed is not equal to the interrupt vector, and the function function will also be modified. When the address to be executed is modified, the jump position is directly changed to expand the program code that can be executed when the processor unit accesses the second non-volatile memory. In some embodiments, the address to be executed is not equal to the interrupt vector, so that the function function is different from the interrupt processing function. The address to be executed is not necessarily stored in the second non-volatile memory, but the address to be executed can guide the processor unit to execute the interrupt in the second non-volatile memory. Figure 2 The code area of ​​the second non-volatile memory jumps to a function function other than the interrupt processing function to call a new function function to meet the functional requirements of the processor unit for functions other than the interrupt processing function. This can make up for the problem of imperfect interrupt processing functions that are solidified in the second non-volatile memory. Of course, the problem of imperfect interrupt processing functions can also be solved by switching the address of the interrupt vector table in the second non-volatile memory to the address of the interrupt vector table in the first non-volatile memory to call the code function modified and compiled by the user. However, simply calling the second non-volatile memory in conjunction with the editable address to be executed transmitted from the outside is more convenient than repeatedly switching the mapping operation between the two non-volatile memories, thereby improving the flexibility of using the second non-volatile memory.

[0053] To summarize, the present application uses a bus control unit to select function code execution between two non-volatile memories of different write types, and maps them to the physical address of the second non-volatile memory in a targeted manner. The mapped address is then used to start calling the second non-volatile memory, and the corresponding interrupt vector can be obtained from the interrupt vector table in the second non-volatile memory, and then the stored interrupt processing function can be jumped and executed. Alternatively, the additional function function can be directly jumped and executed based on the address to be executed transmitted externally to the second non-volatile memory, thereby expanding the program code that can be executed when the processor unit calls the second non-volatile memory, and facilitating the maintenance of functions, codes, and programs to improve the functions to be executed.

[0054] Compared with the prior art, the entire mapping control system does not need to move code and copy interrupt vectors between two non-volatile memories, and ultimately all codes are run based on the mapping to the second non-volatile memory. This also overcomes the problem that the related core of the processor unit cannot support the mapping of the interrupt vector table. Compared with the mutual mapping method between two or more non-volatile memories, the flexibility of the program code running process is improved, thereby solving the problem in the related art that the core of the on-chip processor cannot support the remapping of the interrupt vector table, and the code maintenance problem caused by code modification and improvement under certain storage conditions.

[0055] As an embodiment, the bus control unit is used to switch the address that the processor unit needs to access to the storage address of the preset startup code in the first non-volatile memory when the processor unit starts to execute the preset startup code, that is, the running address of the preset startup code is configured as the initial running address of the code of the first non-volatile memory, wherein the processor unit is configured to initialize the relevant registers but not modify the interrupt vector table during the process of executing the preset startup code; until the processor unit completes the execution of the preset startup code stored in the first non-volatile memory, the address that the processor unit needs to access is switched from the storage address of the preset startup code to the storage address of the interrupt vector table in the second non-volatile memory by configuring the relevant registers, thereby starting to initialize the storage address of the first non-volatile memory. If the storage address is mapped to the second non-volatile memory (which can be further mapped to the storage address of the interrupt vector in the second non-volatile memory), the processor unit switches to access the second non-volatile memory. Therefore, the storage address of the interrupt vector table is not mapped to the first non-volatile memory, so that the first non-volatile memory does not have the condition to trigger an interrupt, and the interrupt in the first non-volatile memory is not effective. The processor unit does not choose to execute the interrupt processing function in the first non-volatile memory, but after being mapped to the storage address of the interrupt vector table in the second non-volatile memory, chooses to execute the interrupt processing function in the storage area (the second non-volatile memory) with faster operation / access speed. Then, the bus control unit will not bring operation risks to each memory during the access address switching process of the processor unit.

[0056] In this embodiment, the speed at which the processor unit accesses the first non-volatile memory is lower than the speed at which the processor unit accesses the second non-volatile memory. The first non-volatile memory supports being rewritten by external data, while the second non-volatile memory does not support being rewritten by external data. Therefore, the first non-volatile memory is configured as a boot memory, and the second non-volatile memory is configured as a fast memory. The first non-volatile memory can use a memory such as OTP (One Time Programming), MTP (multi-time programmable memory), flash memory, etc., in which data and code can be rewritten, but the first non-volatile memory may not use SRAM (static random access memory) in this application; the second non-volatile memory is preferably ROM (Read Only Memory), that is, the second non-volatile memory generally uses a read-only memory, which does not support the processor unit writing new data code to the second non-volatile memory, or the processor unit modifying and compiling the original code data. In order to ensure the access performance of the processor unit, under the decision of the bus control unit, the processor unit chooses to set the interrupt entry in the second non-volatile memory, and after the processor unit is powered on, the initialization phase is selected to be performed in advance in the first non-volatile memory, and after executing the preset startup code stored in the first non-volatile memory, a mapping relationship between the first non-volatile memory and the second non-volatile memory with a faster running speed (relative to the running speed of the first non-volatile memory) can be stably established. .

[0057] In some embodiments, after the processor unit executes the preset startup code stored in the first non-volatile memory, the processor unit jumps to the main function to configure the function registers, that is, to configure the relevant registers in the bus control unit. On this basis, the bus control unit switches the address to be accessed from the storage address of the preset startup code (or the address of the interrupt vector table in the first non-volatile memory) to the storage address of the interrupt vector table in the second non-volatile memory.

[0058] Preferably, in the process of the processor unit switching the address to be accessed from the storage address of the preset startup code to the storage address of the interrupt vector table in the second non-volatile memory by configuring the relevant registers in the bus control unit, a mapping relationship is established between the code storage address of the second non-volatile memory and the code storage address of the first non-volatile memory, wherein the processor unit corresponds the initial address of the running code of the first non-volatile memory to the initial address of the running code stored in the second non-volatile memory, thereby realizing the mapping of the first non-volatile memory to the second non-volatile memory. It should be noted that the mapping of the first non-volatile memory to the second non-volatile memory belongs to address mapping, and address mapping is a one-to-one correspondence between the addresses identified in the two memories.

[0059] It should be noted that the interrupt vectors included in the interrupt vector table in the first non-volatile memory are the same as the interrupt vectors included in the interrupt vector table in the second non-volatile memory. Then, the interrupt vector table in the second non-volatile memory and the interrupt vector table in the first non-volatile memory can use storage addresses (physical addresses) of equal values ​​and the same interrupt vectors (corresponding to the identifier of the same interrupt processing function) in their respective physical storage spaces, so that: no matter whether the storage address of the interrupt vector table in the first non-volatile memory is switched to the storage address of the interrupt vector table in the second non-volatile memory, or the storage address of the interrupt vector table in the second non-volatile memory is switched to the storage address of the interrupt vector table in the first non-volatile memory, the vector currently accessed by the processor unit is not changed. The address and the interrupt processing function currently to be executed (the function identified by the interrupt vector at the currently accessed vector address), wherein the vector address is the storage address of the interrupt vector. On the basis of this address configuration and the interrupt vector configuration, the interrupt vectors included in the interrupt vector table in the second non-volatile memory and the interrupt vectors included in the interrupt vector table in the first non-volatile memory are one-to-one corresponding. Then, in the process of the bus control unit switching and selecting the second non-volatile memory and the first non-volatile memory, the function execution will not be terminated due to the difference in access address or execution function. Even after the program is terminated, it will still run according to the original logical flow. Therefore, by adopting this interrupt vector configuration method, there is no need to modify the compilation and download options of the first non-volatile memory for remapping of the processor unit, which brings convenience to debugging.

[0060] As an embodiment, when the bus control unit does not switch the address that the processor unit needs to access to the address of the interrupt vector table in the second non-volatile memory, the second non-volatile memory is configured by the processor unit to not cause an interrupt, that is, it does not jump to the interrupt vector in the second non-volatile memory, and the processor unit does not trigger an interrupt in the second non-volatile memory. Specifically, when powered on, the code is run from the first non-volatile memory, and the processor unit executes the preset startup code. The physical address of the preset startup code is not within the storage address covered by the interrupt vector table, and the function address of the preset startup code is not an interrupt vector. At this time, there is no storage address mapped to the interrupt vector table of the first non-volatile memory, and the processor unit does not jump to the interrupt vector, so that the first non-volatile memory does not have the conditions to trigger an interrupt, and the interrupt does not take effect, thereby ensuring that the subsequent switching process will not bring code running risks.

[0061] After the bus control unit has switched the address that the processor unit needs to access to the address of the interrupt vector table in the second non-volatile memory, the processor unit determines that the address that it needs to access is switched from the storage address of the first non-volatile memory to the storage address of the second non-volatile memory, and determines that the first non-volatile memory is mapped to the second non-volatile memory, and determines to call the second non-volatile memory, and the corresponding interrupt vector is the interrupt vector pre-solidified in the second non-volatile memory; then the second non-volatile memory is allowed to trigger an interrupt to establish the interrupt entry of the processor unit, so that the processor unit starts to read the interrupt vector table in the second non-volatile memory. Obtain the corresponding interrupt vector instead of establishing an interrupt entry in the first non-volatile memory, and start obtaining the corresponding interrupt vector from the interrupt vector table in the second non-volatile memory. Based on the fact that the speed at which the processor unit accesses the first non-volatile memory is lower than the speed at which the processor unit accesses the second non-volatile memory, after executing the preset startup code stored in the first non-volatile memory, it is selected to establish an interrupt entry in the second non-volatile memory and run the interrupt processing function, thereby improving the speed at which the processor unit executes the program in the memory. Compared with the method of mapping and running the program between two non-volatile memories in the prior art, the access performance of the mapping control system is improved.

[0062] It should be noted that the interrupt vector is the starting address of the interrupt processing function, and the interrupt vector does not support modification. In the present application, the interrupt vector table stored in the second non-volatile memory is not allowed to be modified, and other interrupt vectors will not be written into it. The interrupt vector is also called the entry address (starting address) of the interrupt processing function (program). The storage address of the interrupt vector stores a jump instruction to the entry address of the interrupt processing function (program), and the starting address of the jump instruction is preferably the interrupt vector. Therefore, the interrupt entry established in the second non-volatile memory is not allowed to be modified, providing the processor unit with a stable interrupt entry resource, thereby stably establishing a mapping relationship between the first non-volatile memory and the second non-volatile memory with a faster running speed (relative to the running speed of the first non-volatile memory).

[0063] As an embodiment, the address to be executed is configured by the processor unit, and the processor unit transmits the address to be executed to the second non-volatile memory through the bus control unit; the second non-volatile memory supports the processor unit to jump and execute the function function through the address to be executed; the function function includes: the solidified program stored in the second non-volatile memory except the interrupt processing function, and / or the new program obtained by modifying the original interrupt processing function by the processor unit. In this embodiment, the processor unit transmits the address to be executed to the second non-volatile memory through the bus, and the processor unit and the second non-volatile memory both enter the functional running state, and the processor unit uses the address to be executed to jump and execute the corresponding function in the second non-volatile memory, so that when the processor unit calls the second non-volatile memory, it jumps and executes the program except the interrupt processing function. In this way, the problem of imperfect code stored in the second non-volatile memory is overcome, and when the code needs to be modified, the function to which the modified address to be executed can be jumped can be selected.

[0064] Specifically, when the processor unit accesses the second non-volatile memory, based on the address to be executed transmitted by the processor unit to the second non-volatile memory, the function function is jumped and executed, wherein the address to be executed is the starting address of the function function, which is generally configured by the processor unit in real time and matches the address currently required to be accessed; the address to be executed supports modification, especially accepts the modification and compilation of the processor unit, so that the address to be executed is not equal to the interrupt vector, wherein the interrupt vector solidified in the second non-volatile memory is not allowed to be modified; when the address to be executed is modified by the processor unit, the new function function is directly changed and executed to expand the type and application scope of the program code that can be executed when the processor unit accesses the second non-volatile memory. In this way, only one second non-volatile memory is called to cooperate with the variable address to be executed transmitted by the processor unit, so as to overcome the problem of imperfection of some interrupt processing functions solidified in the second non-volatile memory, so as to be more convenient than repeatedly switching mapping operations between the two memories, and improve the flexibility of the use of the second non-volatile memory.

[0065] As an embodiment, the processor unit is used to execute the preset startup code after power-on or reset to initialize the processor unit, thereby triggering the mapping of the relevant storage address in the first non-volatile memory to the relevant storage address in the second non-volatile memory, and then a software-level jump behavior occurs. In this embodiment, the preset startup code is an initialization program in the remaining storage space other than the storage space occupied by the interrupt vector table in the first non-volatile memory; the processor unit starts to execute the preset startup code stored in the first non-volatile memory to initialize the relevant registers, and the processor unit enters the power-on startup state, but does not modify the interrupt vector table. The interrupt vector table in the first non-volatile memory is not allowed to change, the program stored in the first non-volatile memory is allowed to be modified, or the first non-volatile memory accepts a new program burned externally, then the first non-volatile memory forms a storage space that is rewritten and compiled by the user.

[0066] Specifically, before the first non-volatile memory is mapped to the second non-volatile memory, the address that the processor unit needs to access is switched to the storage address of the preset startup code in the first non-volatile memory until the processor unit executes the preset startup code stored in the first non-volatile memory. The processor unit switches the address that needs to be accessed from the storage address of the preset startup code to the address of the interrupt vector table in the second non-volatile memory by configuring the relevant registers in the bus, thereby starting to map to the storage address of the interrupt vector table in the second non-volatile memory (which can be further mapped to the interrupt vector in the second non-volatile memory), realizing the mapping of the first non-volatile memory to the second non-volatile memory, and then the processor unit starts accessing the second non-volatile memory.

[0067] Based on the above embodiments, the present application discloses a chip, which includes the mapping control system, thereby forming an on-chip chip integrating a processor unit and two memories with different erasable properties. Alternatively, a computer program is stored in the chip, and when the chip is set to run, the memory control method is executed, which can be understood as running the memory control method in an embedded system chip to control the processor unit to call the memory mounted on the same bus to map to the corresponding memory to run the program.

[0068] It should be noted that, in the chip, the storage structure includes a first non-volatile memory and a second non-volatile memory, and the speed at which the processor unit accesses the first non-volatile memory is lower than the speed at which the processor unit accesses the second non-volatile memory.

[0069] Therefore, the first non-volatile memory is classified as a boot storage area in the chip, while the second non-volatile memory is classified as a fast storage area. The first non-volatile memory adopts a memory that can rewrite data codes, such as OTP (One Time Programming), MTP (multi-time program), flash memory, etc. The second non-volatile memory generally adopts a read-only memory, which does not support writing new data codes and modifying and compiling the original code data. The second non-volatile memory is preferably a ROM (Read Only Memory). In order to ensure the access performance of the processor unit, the interrupt entry is selected to be set in the second non-volatile memory, and the first non-volatile memory is selected in the power-on startup initialization stage. After executing the preset boot code stored in the first non-volatile memory, a mapping relationship between the first non-volatile memory and the second non-volatile memory with a faster running speed (relative to the running speed of the first non-volatile memory) can be stably established.

[0070] If the interrupt vectors included in the interrupt vector table in the first non-volatile memory are the same as the interrupt vectors included in the interrupt vector table in the second non-volatile memory, the interrupt vector table in the second non-volatile memory and the interrupt vector table in the first non-volatile memory may use storage addresses (physical addresses) of equal values ​​and the same interrupt vectors (corresponding to identifiers of the same interrupt processing functions) in their respective physical storage spaces, so that: no matter whether the storage address of the interrupt vector table in the first non-volatile memory is switched to the storage address of the interrupt vector table in the second non-volatile memory, or the storage address of the interrupt vector table in the second non-volatile memory is switched to the storage address of the interrupt vector table in the first non-volatile memory, the vector address currently accessed by the processor unit and the interrupt processing currently required to be executed are not changed. Function (the function identified by the interrupt vector at the vector address currently accessed), wherein the vector address is the storage address of the interrupt vector, and based on this address configuration and the interrupt vector configuration, the interrupt vectors included in the interrupt vector table in the second non-volatile memory and the interrupt vectors included in the interrupt vector table in the first non-volatile memory are one-to-one corresponding, so there will be no problem of access address difference or execution function difference in the process of bus switching to select the second non-volatile memory and the first non-volatile memory, and thus the function execution will not be terminated due to the access address difference or the execution function difference, and even after the program is terminated, it will still run according to the original logic flow. Therefore, by adopting this interrupt vector configuration method, there is no need to modify the compilation and download options of the first non-volatile memory for remapping of the processor unit, which brings convenience to debugging.

[0071] In some embodiments, when the processor unit accesses the second non-volatile memory, based on the to-be-executed address transmitted by the processor unit to the second non-volatile memory, a function function is jumped and executed; the to-be-executed address supports modification, especially accepts the modified compilation of the processor unit, so that the to-be-executed address is not equal to the interrupt vector, wherein the interrupt vector solidified in the second non-volatile memory is not allowed to be modified; when the to-be-executed address is modified by the processor unit, the jump is directly changed and a new function function is executed, the to-be-executed address is not equal to the interrupt vector, so that the function function is different from the interrupt processing function, the to-be-executed address is not necessarily stored in the second non-volatile memory, but the to-be-executed address can guide the processor unit in Figure 2The code area of ​​the second non-volatile memory shown jumps to a function other than the interrupt processing function to call a new function to meet the functional requirements of the processor unit other than the interrupt processing function, thereby expanding the type and application range of program codes that can be executed when the processor unit accesses the second non-volatile memory.

[0072] In this way, only by calling the second non-volatile memory to cooperate with the changeable address to be executed transmitted by the processor unit, the problem of imperfect interrupt processing functions solidified inside the second non-volatile memory can be overcome, which is more convenient than repeatedly switching mapping operations between the two non-volatile memories, and improves the flexibility of using the second non-volatile memory.

[0073] The above-mentioned unit modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to this: the above-mentioned unit modules can all be located in the same processor; or, the above-mentioned unit modules can be located in different processors in any combination.

[0074] Although the embodiments of the present invention have been shown and described, it is understood by those skilled in the art that various changes, modifications, substitutions and variations may be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is limited by the appended claims and their equivalents. The above description is only the preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and variations. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A memory control method based on an address, characterized in that: The memory control method comprises: After executing the preset startup code stored in the first non-volatile memory, the address to be accessed is switched to the storage address of the interrupt vector table of the second non-volatile memory, so that the first non-volatile memory is mapped to the second non-volatile memory, and then the second non-volatile memory is determined to be called; wherein the first non-volatile memory supports rewriting, and the second non-volatile memory does not support rewriting; When the second non-volatile memory is called, if an interrupt occurs, the interrupt vector table in the second non-volatile memory jumps to the corresponding interrupt vector, and then executes the interrupt processing function; wherein the interrupt vector is used to identify the starting address of the interrupt processing function, and the interrupt vector does not support modification; When the second non-volatile memory is called, the function function is jumped and executed based on the address to be executed transmitted externally to the second non-volatile memory, wherein the address to be executed is the starting address of the function function; the address to be executed supports modification.

2. The memory control method according to claim 1, characterized in that: When the preset boot code stored in the first non-volatile memory starts to be executed, the address to be accessed by the processor unit is switched to the storage address of the preset boot code in the first non-volatile memory, until the preset boot code stored in the first non-volatile memory is executed, and the address to be accessed by the processor unit is switched to the storage address of the interrupt vector table in the second non-volatile memory by configuring the register in the bus; wherein a speed at which the processor unit accesses the first non-volatile memory is lower than a speed at which the processor unit accesses the second non-volatile memory; The interrupt vector table in the first non-volatile memory is the same as the interrupt vector table in the second non-volatile memory.

3. The memory control method according to claim 2, characterized in that: The interrupt vectors included in the interrupt vector table in the first non-volatile memory are the same as the interrupt vectors included in the interrupt vector table in the second non-volatile memory, so that: no matter the storage address of the interrupt vector table in the first non-volatile memory is switched to the storage address of the interrupt vector table in the second non-volatile memory, or the storage address of the interrupt vector table in the second non-volatile memory is switched to the storage address of the interrupt vector table in the first non-volatile memory, the vector address currently accessed by the processor unit and the interrupt processing function currently required to be executed are not changed; Among them, the vector address is the storage address of the interrupt vector.

4. The memory control method according to claim 2, characterized in that: In the case where the storage address of the interrupt vector table in the second non-volatile memory is not switched, no interruption occurs; In a case where the storage address of the interrupt vector table in the second non-volatile memory has been switched, determining that the first non-volatile memory is mapped to the second non-volatile memory, and determining to call the second non-volatile memory; Then, the interrupt is triggered to establish an interrupt entry, so as to jump to the corresponding interrupt vector in the second non-volatile memory.

5. The memory control method according to claim 2, characterized in that: The address to be executed is a starting address of a function configured by the processor unit, and the processor unit transmits the address to be executed to the second non-volatile memory through a bus; The second non-volatile memory supports jumping and executing the function through the address to be executed; The functional function includes: a solidified program other than the interrupt handling function stored in the second non-volatile memory, and / or a new program obtained by modifying the original interrupt handling function by the processor unit, so that when the processor unit calls the second non-volatile memory, it jumps and executes the program other than the interrupt handling function.

6. The memory control method according to claim 2, characterized in that: After the processor unit is powered on or reset, the preset startup code is first executed to initialize the processor unit; The preset startup code is an initialization program in the remaining storage space other than the storage space occupied by the interrupt vector table in the first non-volatile memory; The interrupt vector table in the first non-volatile memory is not allowed to change, the program stored in the first non-volatile memory is allowed to be modified, or the first non-volatile memory accepts a new program burned externally.

7. A mapping control system, characterized in that: The mapping control system includes a processor unit, a bus control unit, a second non-volatile memory, and a first non-volatile memory; a processor unit, configured to access the second non-volatile memory or the first non-volatile memory through the bus control unit; A processor unit, configured to, after executing a preset startup code stored in a first non-volatile memory, configure the bus control unit to switch a required access address to a storage address of an interrupt vector table in a second non-volatile memory, so that the first non-volatile memory is mapped to the second non-volatile memory, and then determine to access the second non-volatile memory through the bus control unit; The first non-volatile memory supports rewriting, and the second non-volatile memory does not support rewriting; A processor unit, configured to jump to a corresponding interrupt vector in an interrupt vector table of the second non-volatile memory and execute an interrupt processing function if an interrupt occurs when the second non-volatile memory is accessed through the bus control unit; wherein the interrupt vector is used to identify a starting address of the interrupt processing function, and the interrupt vector does not support modification; The processor unit is also used to transmit the address to be executed to the second non-volatile memory through the bus control unit when accessing the second non-volatile memory through the bus control unit, and then jump and execute the function function based on the address to be executed; wherein the address to be executed is the starting address of the function function; the address to be executed supports modification so that the address to be executed is not equal to the interrupt vector.

8. The mapping control system according to claim 7, characterized in that: The bus control unit is used to switch the address that the processor unit needs to access to the storage address of the preset startup code in the first non-volatile memory when the processor unit starts to execute the preset startup code, until the processor unit finishes executing the preset startup code stored in the first non-volatile memory, and switches the address that the processor unit needs to access from the storage address of the preset startup code to the storage address of the interrupt vector table in the second non-volatile memory by configuring the register; wherein a speed at which the processor unit accesses the first non-volatile memory is lower than a speed at which the processor unit accesses the second non-volatile memory; Among them, the vector address covered by the interrupt vector table in the first non-volatile memory is the same as the vector address covered by the interrupt vector table in the second non-volatile memory; the vector address is the storage address of the interrupt vector; the interrupt vector included in the interrupt vector table in the first non-volatile memory is the same as the interrupt vector located at the same vector address in the second non-volatile memory.

9. The mapping control system according to claim 8, characterized in that: When the bus control unit does not switch the address to be accessed by the processor unit to the storage address of the interrupt vector table in the second non-volatile memory, the second non-volatile memory is configured to not cause an interrupt; After the bus control unit has switched the address that the processor unit needs to access to the storage address of the interrupt vector table in the second non-volatile memory, the processor unit determines that the first non-volatile memory is mapped to the second non-volatile memory, and then allows the second non-volatile memory to trigger an interrupt to establish an interrupt entry for the processor unit, so that the processor unit starts to jump to the corresponding interrupt vector in the second non-volatile memory.

10. The mapping control system according to claim 8, characterized in that: The address to be executed is configured by the processor unit, and the processor unit transmits the address to be executed to the second non-volatile memory through the bus control unit; The second non-volatile memory supports the processor unit to jump to the address to be executed and then execute the function; The second non-volatile memory is a read-only memory; The functional function includes: a fixed program stored in the second non-volatile memory except for the interrupt processing function, and / or a new program obtained by modifying the original interrupt processing function by the processor unit.

11. The mapping control system according to claim 8, characterized in that: The processor unit is used to execute the preset startup code after power-on or reset to initialize the processor unit; The preset startup code is an initialization program in the remaining storage space other than the storage space occupied by the interrupt vector table in the first non-volatile memory; The interrupt vector table in the first non-volatile memory is not allowed to change, the program stored in the first non-volatile memory is allowed to be modified, or the first non-volatile memory accepts a new program burned externally.

12. A chip, characterized in that: The chip comprises the mapping control system according to any one of claims 7 to 11; or, a computer program is stored in the chip, and when the chip is configured to run, the memory control method according to any one of claims 1 to 6 is executed.

Images