Recommendation system calculation acceleration method based on analog in-memory calculation circuit

Abstract

The invention provides a recommendation system calculation acceleration method based on an analog in-memory calculation circuit, and belongs to the technical field of semiconductors, analog calculation and integrated circuits. According to the method, on the basis of iterative computation of an alternating least square method, a block matrix method is designed, the problem of large-scale matrix decomposition is solved by utilizing a variable resistor array, and a large amount of ridge regression computation contained in the block matrix method is accelerated in an analog computation mode, so that analog computation acceleration of a recommendation system is realized. According to the method, high-speed and high-energy-efficiency recommendation system matrix decomposition can be realized, a new solution is provided for hardware acceleration of a recommendation system training process under a big data background, and the method has a wide application prospect.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor, analog computing and integrated circuit, and relates to a method for accelerating the calculation of a recommendation system based on an analog in-memory computing circuit, and specifically to a block matrix method for realizing matrix decomposition and its implementation in an analog computing circuit based on a variable resistor array. Background Art

[0002] Recommendation system algorithms play a vital role in the modern Internet society and are widely and frequently used in many large Internet companies, such as Amazon, ByteDance, and JD. It can connect people with potential hobbies, thus bringing convenience to users and economic benefits to enterprises. Among them, matrix factorization (MF) has become the main algorithm in collaborative filtering recommendation systems due to its accuracy and scalability, and has also become a key component of many hybrid models based on deep neural networks. Based on the known entries in the user-item rating matrix, the basic idea of ​​MF is to map users and items into the same latent feature space, and then predict unknown entries through simple dot product calculations to evaluate the user's interest in specific items.

[0003] Considering n users and m items, the user's ratings on the items will form a rating matrix R of size n×m. A user often only experiences and rates a few items. Similarly, an item is often used and rated by only a few users. Therefore, there are quite a few entries in the rating matrix R that are unknown and to be predicted, that is, R is usually very sparse. The task of MF is to decompose the original rating matrix R into the product of two small matrices based on these known ratings, that is, R≈UV T , where U and V are the latent feature matrices of users and items, respectively, with sizes of n×k and m×k, respectively, k is the number of latent features, and usually satisfies k<<n,m. Therefore, the unknown ratings in R can be predicted by the dot product of the vectors in U and V. The MF problem can be solved by minimizing the total loss function: To solve the matrix decomposition problem. Where λ is the L2 penalty term coefficient, used to prevent overfitting, Ω * represents the set of known entries in the original rating matrix, which means that the optimization process is only performed on known rating data.

[0004] However, in today's big data era, the user-item rating matrix R is often very large and sparse, that is, n and m are usually in the order of thousands to millions, which leads to extremely high computational requirements. Traditional digital computers are limited by the von Neumann bottleneck and are difficult to handle computationally intensive MF tasks. Due to the extremely high computational complexity and the large scale of the rating matrix, the most advanced methods currently still use digital accelerators with separate storage and computation, such as graphics processing units (GPUs) and field programmable gate arrays (FPGAs). Analog computing based on variable resistor arrays is a promising solution. This is an in-situ calculation performed inside the memory, which reduces data transfer and greatly improves the parallelism of the calculation, which can effectively improve the speed and energy efficiency of the calculation. Therefore, it is of great significance to study a method based on variable resistor array analog in-memory computing for acceleration of recommendation system calculations. Summary of the invention

[0005] The purpose of the present invention is to provide a method for accelerating the calculation of a recommendation system based on an analog in-memory calculation circuit. On the basis of the iterative calculation of the alternating least squares method, a block matrix method is designed, and the most complex ridge regression calculation in the analog in-memory calculation circuit acceleration method is adopted, so as to complete the matrix decomposition (MF) algorithm in the recommendation system and realize the analog calculation acceleration of the recommendation system. The method is applicable to the current large and sparse user-item rating matrix, which can greatly improve the calculation speed and energy efficiency of the most complex training process in the recommendation system.

[0006] The technical solution of the present invention is as follows:

[0007] A method for accelerating the calculation of recommendation systems based on analog in-memory computing circuits. For a user-item rating matrix R of size n×m, R≈UV T , where U and V are the potential feature matrices of users and items, respectively, with sizes of n×k and m×k, respectively, k is the number of potential features, k<<n,m, U i / V i Represents the potential feature matrix of the i-th user / item; the method is based on the alternating least squares method, designs a block matrix method, and uses analog in-memory computing circuit mapping and calculation to accelerate the ridge regression calculation and the minimization process of the total loss function of the recommendation system matrix decomposition algorithm, including the following steps:

[0008] 1) Randomly generate the first user potential feature matrix U1;

[0009] 2) Get V1 based on R and U1

[0010] 2-1) The user potential feature matrix U1 and the original rating matrix R are divided into blocks according to the block matrix method, and U1 is divided into h1 sub-feature matrices of size d×k according to the rows Divide the original rating matrix R into h1 sub-rating matrices of size d×m by row Where n = h1 × d, the choice of parameter d depends on the scale of the variable resistor array;

[0011] 2-2) Based on the h1 pair matrix Perform ridge regression calculations separately, map the sub-matrices after block division to the analog memory calculation circuit, and accelerate them by analog calculation to obtain h1 intermediate feature matrices

[0012] 2-3) Output results of the simulation in-memory computing circuit Perform nonlinear operations to obtain the potential feature matrix V1 of the first item;

[0013] 2-4) Calculate the total loss function value of the recommendation system matrix decomposition algorithm based on U1 and V1;

[0014] 3) Get U2 based on R and V1

[0015] 3-1) The user potential feature matrix V1 and the original rating matrix R are divided into blocks according to the block matrix method, and V1 is divided into h2 sub-feature matrices of size d×k according to the rows The transposed matrix of the initial rating matrix R is divided into h2 sub-rating matrices of size d×n by row Where m = h2 × d, the choice of parameter d depends on the scale of the variable resistor array;

[0016] 3-2) Based on the h2 pair matrix Perform ridge regression calculations separately, map the sub-matrices after block division to the analog memory calculation circuit, and accelerate them by analog calculation to obtain h2 intermediate feature matrices

[0017] 3-3) Output results of the simulation in-memory computing circuit Perform nonlinear operations to obtain the potential feature matrix U2 of the second user;

[0018] 3-4) Calculate the total loss function value of the recommendation system matrix decomposition algorithm based on U2 and V1;

[0019] 4) Repeat step 2) according to R and U i Get V i and step 3) according to R and V i Get U i+1 The method process is repeated and iterated to obtain V2, U3, ..., U i , V i , …, U i+1, … and calculate the corresponding total loss function value until the total loss function of the recommendation system matrix decomposition algorithm converges.

[0020] Further, the block matrix method in steps 2-1) and 3-1) is agreed to be i,j / V i,j is the jth intermediate feature matrix in the i-th user / item potential feature matrix, U i[j] / V i[j] is the jth sub-feature matrix of the i-th user / item potential feature matrix; the block matrix method specifically includes:

[0021] S1-1) If we want to i Get V i , then the potential feature matrix U of the i-th user i Divide into h1 sub-feature matrices of size d×k according to the equal spacing of the rows Correspondingly, the original rating matrix R is also divided into h1 sub-rating matrices of size d×m by row spacing For the j-th pair of submatrices U i[j] and R [j] By doing ridge regression calculation, we can get the jth intermediate feature matrix, namely V i,j , perform ridge regression calculations on the h1 pair of sub-matrices to obtain all h1 intermediate feature matrices

[0022] S1-2) If you want to use R and V i Get U i+1 , then the potential feature matrix V of the i-th item i Divide into h2 sub-matrices of size d×k according to the equal spacing of rows Correspondingly, the transposed matrix R of the original rating matrix T It is also divided into h2 sub-rating matrices of size d×n by equal spacing in rows For the j-th pair of submatrices V i[j] and R T [j] By doing ridge regression calculation, we can get the jth intermediate feature matrix, namely U i+1,j , perform ridge regression calculations on the h2 pair of sub-matrices to obtain all the h2 intermediate feature matrices

[0023] Further, the ridge regression calculation in the steps 2-2) and 3-2) is accelerated by analog calculation by mapping the sub-matrix after block division into an analog in-memory calculation circuit, wherein the analog in-memory calculation circuit is composed of a variable resistor array of size (2k+1)×d, d analog switches, d fixed resistors as input resistors, k operational amplifiers and their k fixed resistors as feedback resistors, wherein the first 2k rows of the variable resistor array are used to store the transpose of two identical sub-feature matrices, and the last row is used for conductance compensation; the row lines of the first k rows of the variable resistor array are respectively connected to the inverting input terminals of the operational amplifiers, the non-inverting input terminals of the operational amplifiers are all grounded, and the output terminals are respectively connected to the row lines of the last k rows of the variable resistor array, and the last row of the array is grounded; the column lines of the variable resistor array are connected to the input voltage source through input resistors, and are respectively connected to the ground terminals through analog switches; the mapping of the sub-matrix after block division into the analog in-memory calculation circuit to realize the ridge regression calculation is specifically as follows:

[0024] S2-1) Sub-feature matrix U i[j] / V i[j] The transpose of is mapped to the simulated conductance values ​​of the first 2k rows of the variable resistor array, and the compensated conductance value is mapped to the last row of the variable resistor array, so that the sum of the conductance values ​​of all devices in each column is equal;

[0025] S2-2) The original score matrix R / R T The block matrix of is mapped column by column to the input voltage value of the variable resistor array circuit. Since there are a lot of unknown data in the original scoring matrix, the algorithm only needs to optimize the loss function of the known entries. This is achieved by closing the ground analog switch corresponding to the column of unknown data. At this time, the column line is grounded, and all the variable resistor devices on the column line do not participate in the circuit calculation. The voltage at the output of the operational amplifier is the ridge regression calculation result of only calculating the known data; each R / R T When one column of the block matrix is ​​mapped to the input voltage of the circuit and input, a group of voltages is obtained at the output of the operational amplifier, which represents a row of an intermediate characteristic matrix in the successive iterations; by collecting the voltage data of the output of the operational amplifier of the analog circuit in sequence, a complete intermediate characteristic matrix in one iteration can be obtained. After mapping and calculating h1 / h2 sub-matrices, all h1 / h2 intermediate characteristic matrices in this iteration can be obtained.

[0026] Furthermore, the nonlinear operations in steps 2-3) and 3-3) are maximum value and scaling operations.

[0027] Furthermore, the total loss function of the recommendation system matrix decomposition algorithm is:

[0028]

[0029] Where λ is the L2 penalty term coefficient, Ω * Represents the set of known entries in the original rating matrix.

[0030] Furthermore, the variable resistor devices in the variable resistor array are non-volatile memory devices, including resistive memory, phase change memory, magnetic memory and ferroelectric memory.

[0031] The beneficial effects of the present invention are as follows:

[0032] The invention discloses a method for accelerating the calculation of a recommendation system based on an analog in-memory calculation circuit. Through a block matrix method, it is possible to accelerate large-scale matrix decomposition using an analog in-memory calculation circuit with limited hardware resources. The analog in-memory calculation circuit is used to accelerate a large number of ridge regression calculations contained in the block matrix method in an analog calculation manner, thereby realizing analog calculation acceleration of the recommendation system. Compared with traditional digital methods, this method can greatly improve the calculation speed and calculation energy efficiency of large-scale matrix decomposition tasks in the recommendation system, and provides a new solution for hardware acceleration of the training process of the recommendation system under the background of big data. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a schematic diagram of the alternating least squares method provided by an embodiment of the present invention;

[0034] Figure 2 It is a flow chart of a matrix decomposition simulation calculation acceleration method provided by an embodiment of the present invention;

[0035] Figure 3 Schematic diagram of a block matrix method for implementing matrix decomposition provided by an embodiment of the present invention;

[0036] Figure 4 It is a schematic diagram of a simulation calculation method for accelerating ridge regression calculation by simulating an in-memory calculation circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0037] In order to more clearly illustrate the purpose, technical solutions and advantages of the present invention, the following is a further detailed description in conjunction with the accompanying drawings. The description herein is only used to explain the present invention and is not intended to limit the present invention.

[0038] The recommendation system MF problem to be solved by the present invention is described as follows:

[0039] Considering n users and m items, the user ratings of the items will form a rating matrix R of size n×m. Most of the entries are unknown, so the task of MF in the recommendation system is to decompose the original rating matrix R into the product of two small matrices based on the known ratings, that is, R≈UV T, where U and V are the latent feature matrices of users and items, respectively, with sizes of n×k and m×k, respectively, k is the number of latent features, and usually satisfies k<<n,m. Then the unknown entries in the matrix R can be predicted by the dot product of the vectors in U and V. The MF problem can be described as minimizing the total loss function: Where λ is the L2 penalty coefficient, used to prevent overfitting, Ω * Represents the known set of items in the original rating matrix, which means that the optimization process is only performed on the known rating data. In the present invention, the loss function is minimized by simulation calculation based on the alternating least squares algorithm to obtain the decomposition result of MF, that is, the user feature matrix and item feature matrix with converged loss function, so as to predict unknown items and achieve the purpose of evaluating the user's interest in a certain item, thereby realizing the acceleration of the recommendation system.

[0040] Figure 1 is a schematic diagram of the alternating least squares method provided in an embodiment of the present invention. In the present invention, it is agreed that U i / V i is the i-th user / item potential feature matrix, and R is the initial rating matrix. First, the first user feature matrix U1 is randomly generated, and based on the known matrices R and U1, a specific ridge regression is used to calculate In the next iteration, based on the known matrix R and V1, a similar ridge regression is used to calculate Then U2 is obtained, and the matrix U2 will be used as the known matrix in the next iteration. Through this alternating least squares method, until the total loss function converges to the minimum value, the user and item potential feature matrix in the last iteration is the final result of MF.

[0041] Figure 2 1 is a flowchart of a matrix decomposition simulation calculation acceleration method provided by an embodiment of the present invention, which describes an implementation flowchart of a matrix decomposition simulation calculation acceleration method based on an alternating least squares method. First, as shown in step S210, randomly generate the first user potential feature matrix U1, then execute step S220, obtain the next item feature matrix V1 according to U1 and R, and then obtain the next user feature matrix U2 (S230) according to the obtained V1 and the original rating matrix R, and finally execute step S240, that is, repeat steps S220 and S330, that is, iteratively execute according to R and U i Get V i The process and according to R and V i Get U i+1 By the process of , we can get U2, V2, U3, ..., U i , V i ,…,U i+1 , ... until the total loss function Convergence. Step S220 is divided into four sub-steps S221, S222, S223 and S224, that is, the current user feature matrix and the original rating matrix R are divided into blocks according to the block matrix method (step S221), and then the divided matrix is ​​mapped to the analog calculation circuit, and the key step (ridge regression calculation) is accelerated by analog calculation (S222) to obtain the intermediate feature matrix, and then the output result of the analog calculation is subjected to the corresponding nonlinear operation to obtain the next item feature matrix (S223), and finally the value of the total loss function is calculated according to the user feature matrix and the item feature matrix at this time (S224). Among them, step S230 is divided into 4 sub-steps S231, S232, S233 and S234, that is, the current item feature matrix and the original score matrix R are divided into blocks according to the block matrix method (step S231), and then, the divided matrix is ​​mapped to the analog calculation circuit, and the key step (ridge regression calculation) is accelerated by analog calculation (S232) to obtain the intermediate feature matrix, and then the output result of the analog calculation is subjected to the corresponding nonlinear operation to obtain the next user feature matrix (S233), and finally the value of the total loss function is calculated according to the user feature matrix and the item feature matrix at this time (S234). Among them, the nonlinear operation in steps S223 and S233 provides an implementation method in the present invention, namely, maximization and scaling operations.

[0042] Figure 3 Schematic diagram of a block matrix method for realizing matrix decomposition provided by an embodiment of the present invention, the purpose of which is to realize in the form of a block matrix Figure 2 In the block matrix method of the present invention, it is agreed that U i,j / V i,j is the jth intermediate feature matrix in the i-th user / item potential feature matrix, U i[j] / V i[j] is the jth submatrix of the i-th user / item latent feature matrix. In each iteration of the alternating least squares method, since the original rating matrix R and the latent feature matrix are too large to be deployed on related hardware with limited resources, the matrices R, U, and V need to be divided into blocks and then calculated to adapt to the limited resource analog computing circuit. Figure 2 In step S220 shown in FIG. i Get V i , you need to first i Divide into h1 sub-matrices of size d×k according to the row Correspondingly, the original rating matrix is ​​also divided into h1 sub-rating matrices of size d×m by row: Where n = h1 × d, the choice of parameter d depends on the size of the variable resistor array. Then, ridge regression calculations are performed on the h1 pair of sub-matrices, which can be accelerated by analog calculations to obtain h1 intermediate feature matrices. By taking the maximum value of the elements at the same position in the h1 matrices and scaling them according to the same ratio (i.e. maximization and scaling), we can get V i Similarly, in Figure 2 In step S230 shown in FIG. i Get U i+1 , you need to first set V i Divide into h2 sub-feature matrices V of size d×k according to the rows i[1～h2] , the original rating matrix R is also divided into h2 sub-rating matrices R of size d×n by column T [1～h2] , where m = h2 × d, and the choice of parameter d depends on the scale of the variable resistor array. Performing ridge regression calculations on the h2 pair matrices separately, we can obtain h2 intermediate feature matrices U i+1,1～h2 , U can be generated by maximizing and scaling operations i+1 matrix.

[0043] Figure 4 The schematic diagram of the simulation calculation method for accelerating ridge regression calculation by simulating an in-memory calculation circuit provided by an embodiment of the present invention includes a simulation circuit for realizing ridge regression calculation for only known data and a mapping method of the block matrix method therein. The circuit is used to accelerate Figure 2 The key calculation in step S222 and step S232 is Figure 3The ridge regression calculation of the sub-matrix after block division mentioned in the embodiment is composed of a variable resistor array with 2k+1 rows and d columns, d+k analog switches, d+k fixed resistors and k operational amplifiers. The first k rows of the variable resistor array are respectively connected to the reverse input terminals of the k operational amplifiers, and the following k rows are respectively connected to the output terminals of the k operational amplifiers, thereby forming a feedback loop, and the last row is grounded for conductance compensation. The d fixed resistors are connected to the d columns of the cross array as input resistors, and the other k fixed resistors are connected between the output terminals and the reverse input terminals of the k operational amplifiers through k analog switches as feedback resistors. One end of the remaining d analog switches is connected to the d column lines of the variable resistor array, and the other end is grounded. The variable resistor devices in the array include but are not limited to non-volatile memory devices such as resistive random access memory (RRAM), phase change memory (PCM), magnetic random access memory (MRAM), and ferroelectric memory (FeRAM). In the present invention, the unit conductance g0 is agreed to be 1. Since the sizes of the sub-feature matrices are the same, for the convenience of expression, the symbol A is used to replace U. i[j] / V i[j] , which will be mapped to the simulated conductance value in the variable resistor array. And replace R with the symbol y [q] / R T [q] This will be mapped to the input voltage of the circuit. It is agreed that p represents the pth row and q represents the qth column. T Simultaneously mapped to the upper and lower halves of the 2k-row variable resistor array in the form of analog conductance values, forming two conductance matrices g0A T The qth input voltage is -y q , the voltage on the qth column line of the variable resistor array is V BL,q , the output voltage of the pth op amp is x p According to Kirchhoff's current law, the current flowing into the qth column line is equal to the current flowing out of it, so

[0044]

[0045] where g c,q is the conductance value of the qth compensation resistor. The conductance value of the compensation resistor is adjusted so that the sum of the conductance values ​​of all resistive devices on each column line is equal and equal to the constant c, that is, If we write the above equation in matrix form, we have Ax-y=cV BL According to the virtual disconnect property of the op amp, the current flowing into the op amp is 0, so The conductance of the feedback resistor in the operational amplifier is λ / cg0, which can be written in matrix form as A. T V BL +λ / cx=0. Combining the two matrix equations, we can get the solution of ridge regression calculation: x=(A T A+λI) -1 A T y, where I is the identity matrix, so the function can be minimized When the circuit is working, since the input voltage vector y maps to a column in the sub-score matrix after block division, which contains unknown elements, if the qth element y q If the qth analog switch is unknown, the qth column of the variable resistor array is closed to ground the qth column. Finally, the circuit can realize the ridge regression calculation of only the known data, which is formula (1) in the attached figure.

[0046]

[0047] Therefore, in order to complete Figure 2 The key calculation mentioned in steps S222 and S232 is Figure 3 The ridge regression calculation of the sub-matrix after block partitioning shown in needs to convert the sub-feature matrix U i[j] Mapped to the simulated conductance value of the above variable resistor array, the sub-scoring matrix R is converted column by column (total m columns) [j] Mapped to input voltage, collecting all output voltages can obtain an intermediate feature matrix V i,j , repeat mapping other sub-feature matrices and input the corresponding voltages column by column, repeat h1 times, and all the intermediate feature matrices V can be obtained i，1～h1 Similarly, the sub-feature matrix V i[j] Mapped to the simulated conductance value of the above variable resistor array, R is mapped column by column (n columns in total) to T [j] Mapping it to the input voltage and collecting the output voltage, we can get an intermediate feature matrix U i+1,j , iteratively map the sub-feature matrix and input the corresponding voltage column by column, repeat h2 times, and all the intermediate feature matrices U i+1,1～h2 .

[0048] Finally, it should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

Claims

1. A method for accelerating the calculation of a recommendation system based on analog in-memory computing circuits. For a user-item rating matrix R of size n×m, R≈UV T , where U and V are the potential feature matrices of users and items, respectively, with sizes of n×k and m×k, respectively, k is the number of potential features, k<<n,m, U i / V i represents the i-th user / item potential feature matrix; The method is based on the alternating least squares method, which is characterized by: Design a block matrix method and use analog in-memory computing circuit mapping and calculation to accelerate ridge regression calculation and the minimization process of the total loss function of the recommendation system matrix decomposition algorithm, including the following steps: 1) Randomly generate the first user potential feature matrix U1; 2) Get V1 based on R and U1 2-1) The user potential feature matrix U1 and the original rating matrix R are divided into blocks according to the block matrix method, and U1 is divided into h1 sub-feature matrices U of size d×k according to the rows 1[1～h1] ; Divide the original rating matrix R into h1 sub-rating matrices R of size d×m by row [1～h1] ; Where n = h1 × d, the choice of parameter d depends on the scale of the variable resistor array; 2-2) Based on the h1 pair matrix U 1[1～h1] , R [1～h1] Perform ridge regression calculations separately, map the sub-matrices after block division to the analog memory calculation circuit, and accelerate them by analog calculation to obtain h1 intermediate feature matrices V 1,1～h1 ; 2-3) The output result V of the analog in-memory calculation circuit 1,1～h1 Perform nonlinear operations to obtain the potential feature matrix V1 of the first item; 2-4) Calculate the total loss function value of the recommendation system matrix decomposition algorithm based on U1 and V1; 3) Get U2 based on R and V1 3-1) The user potential feature matrix V1 and the original rating matrix R are divided into blocks according to the block matrix method, and V1 is divided into h2 sub-feature matrices V of size d×k according to the rows 1[1～h2] ; The transposed matrix of the initial score matrix R is divided into h2 sub-score matrices R of size d×n by row T [1～h2] ; Where m = h2 × d, the choice of parameter d depends on the scale of the variable resistor array; 3-2) Based on the h2 pair matrix V 1[1～h2] , R T [1～h2] Perform ridge regression calculations separately, map the sub-matrices after block division to the analog memory computing circuit, and accelerate them by analog calculation to obtain h2 intermediate feature matrices U 2,1～h2 ; 3-3) The output result U of the simulation memory calculation circuit 2,1～h2 Perform nonlinear operations to obtain the potential feature matrix U2 of the second user; 3-4) Calculate the total loss function value of the recommendation system matrix decomposition algorithm based on U2 and V1; 4) Repeat step 2) according to R and U i Get V i and step 3) according to R and V i Get U i+1 The method process is repeated and iterated to obtain V2, U3, ..., U i , V i , …, U i+1 , … and calculate the corresponding total loss function value until the total loss function of the recommendation system matrix decomposition algorithm converges.

2. The method for accelerating the calculation of a recommendation system based on simulating an in-memory calculation circuit according to claim 1, characterized in that: The block matrix method in steps 2-1) and 3-1) is agreed to be U i,j / V i,j is the jth intermediate feature matrix in the i-th user / item potential feature matrix, U i[j] / V i[j] is the jth sub-feature matrix of the i-th user / item potential feature matrix; The block matrix method specifically includes: S1-1) If we want to i Get V i , then the potential feature matrix U of the i-th user i Divide into h1 sub-feature matrices U of size d×k according to the equal spacing of rows i[1～h1] , accordingly, the original rating matrix R is also divided into h1 sub-rating matrices R of size d×m by row spacing [1～h1] ; For the j-th pair of submatrices U i[j] and R [j] By doing ridge regression calculation, we can get the jth intermediate feature matrix, namely V i,j , perform ridge regression calculations on the h1 pair of sub-matrices respectively, and you can get all the h1 intermediate feature matrices V i,1～h1 ; S1-2) If you want to use R and V i Get U i+1 , then the potential feature matrix V of the i-th item i Divide into h2 sub-matrices V of size d×k according to the row spacing i[1～h2] , accordingly, the transposed matrix R of the original rating matrix T It is also divided into h2 sub-rating matrices R of size d×n by equal spacing in rows T [1～h2] ; For the j-th pair of submatrices V i[j] and R T [j] By doing ridge regression calculation, we can get the jth intermediate feature matrix, namely U i+1,j , perform ridge regression calculations on the h2 pair matrices respectively, and you can get all the h2 intermediate feature matrices U i+1,1～h2 .

3. The method for accelerating the calculation of a recommendation system based on simulating an in-memory calculation circuit according to claim 1, characterized in that: The ridge regression calculation in the steps 2-2) and 3-2) is accelerated by analog calculation by mapping the sub-matrix after block division into an analog in-memory calculation circuit, wherein the analog in-memory calculation circuit is composed of a variable resistor array of size (2k+1)×d, d analog switches, d fixed resistors as input resistors, k operational amplifiers and their k fixed resistors as feedback resistors, wherein the first 2k rows of the variable resistor array are used to store the transpose of two identical sub-feature matrices, and the last row is used for conductance compensation; the row lines of the first k rows of the variable resistor array are respectively connected to the inverting input terminals of the operational amplifiers, the non-inverting input terminals of the operational amplifiers are all grounded, and the output terminals are respectively connected to the row lines of the last k rows of the variable resistor array, and the last row of the array is grounded; the column lines of the variable resistor array are connected to the input voltage source through input resistors, and are respectively connected to the ground terminals through analog switches; the ridge regression calculation is realized by mapping the sub-matrix after block division into the analog in-memory calculation circuit, specifically: S2-1) Sub-feature matrix U i[j] / V i[j] The transpose of is mapped to the simulated conductance values ​​of the first 2k rows of the variable resistor array, and the compensated conductance value is mapped to the last row of the variable resistor array, so that the sum of the conductance values ​​of all devices in each column is equal; S2-2) The original score matrix R / R T The block matrix of is mapped column by column to the input voltage value of the variable resistor array circuit. Since there are a lot of unknown data in the original scoring matrix, the algorithm only needs to optimize the loss function of the known entries. This is achieved by closing the ground analog switch corresponding to the column of unknown data. At this time, the column line is grounded, and all the variable resistor devices on the column line do not participate in the circuit calculation. The voltage at the output of the operational amplifier is the ridge regression calculation result of only calculating the known data; each R / R T When one column of the block matrix is ​​mapped to the input voltage of the circuit and input, a group of voltages is obtained at the output of the operational amplifier, which represents a row of an intermediate characteristic matrix in the successive iterations; by collecting the voltage data of the output of the operational amplifier of the analog circuit in sequence, a complete intermediate characteristic matrix in one iteration can be obtained. After mapping and calculating h1 / h2 sub-matrices, all h1 / h2 intermediate characteristic matrices in this iteration can be obtained.

4. The method for accelerating the calculation of a recommendation system based on simulating an in-memory calculation circuit according to claim 1, characterized in that: The nonlinear operations in steps 2-3) and 3-3) are maximum value taking and scaling operations.

5. The method for accelerating the calculation of a recommendation system based on simulating an in-memory calculation circuit according to claim 1, characterized in that: The total loss function of the recommendation system matrix decomposition algorithm is: Where λ is the L2 penalty term coefficient, Ω * Represents the set of known entries in the original rating matrix.

6. The method for accelerating the calculation of a recommendation system based on simulating an in-memory calculation circuit according to claim 1, characterized in that: The variable resistor devices in the variable resistor array are non-volatile memory devices, including resistive memory, phase change memory, magnetic memory and ferroelectric memory.

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