Data processing method and device, equipment and medium
By parallel processing of diagonal elements and non-diagonal elements in Jacobi iteration method in SIMD hardware architecture, the problem of low computational efficiency in solving large-scale matrix equation systems is solved, and a more efficient solution process is achieved.
Patent Information
- Application Number
- CN202411710339.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-27
- Publication Date
- 2025-03-14
AI Technical Summary
The existing Jacobian iterative method has low computational efficiency when solving large-scale matrix equation systems, mainly due to the high time complexity caused by the serial solution method.
The single-instruction multi-data SIMD hardware architecture is adopted to process diagonal and non-diagonal elements in the data structure in parallel, and the Jacobian iterative method is used to solve the solution parameters to improve the calculation efficiency.
By processing data in parallel, the calculation efficiency of Jacobian iteration method is significantly improved and the time complexity of solving large-scale matrix equation systems is reduced.
Smart Images
Figure CN119622173A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to the field of data processing technology, and in particular, to a data processing method, device, equipment and medium. Background Art
[0002] The Jacobi iteration method is a classic numerical analysis method. This method is mainly used to iteratively solve the parameters to be solved in the matrix equation system. It is widely popular due to its simplicity and robustness. In the prior art, the Jacobi iteration method is mainly used to solve the parameters to be solved in a serial solution mode. For example, for a matrix of size n×n, the time complexity of each iteration is O(n^2). In large-scale problems, the amount of calculation is huge, resulting in low calculation efficiency. Summary of the invention
[0003] The embodiments of the present invention provide a data processing method, apparatus, device and medium, which can improve the computational efficiency of the Jacobi iteration method solution process.
[0004] In a first aspect, an embodiment of the present invention provides a data processing method, the method being executed by a controller in a single instruction multiple data (SIMD) hardware architecture, the SIMD hardware architecture being a hardware architecture for processing data in parallel, comprising:
[0005] Acquire input data; wherein the input data includes a first coefficient, a first parameter, and a parameter to be solved; the first coefficient is represented by a matrix, and the first parameter and the parameter to be solved are represented by a vector;
[0006] Extracting diagonal elements and off-diagonal elements from the first coefficients;
[0007] Storing the diagonal elements, the off-diagonal elements and the first parameter in parallel in corresponding registers;
[0008] The diagonal elements, the off-diagonal elements and the first parameters are read from corresponding registers, and the parameters to be solved are iteratively solved by Jacobi iteration method to obtain target solution results, and the target solution results are stored in a memory; wherein the registers and the memory are located in the SIMD hardware architecture.
[0009] In a second aspect, an embodiment of the present invention further provides a data processing device, wherein the device is arranged in a controller in a single instruction multiple data (SIMD) hardware architecture, wherein the SIMD hardware architecture is a hardware architecture for processing data in parallel, and the device comprises:
[0010] A data acquisition module, used to acquire input data; wherein the input data includes a first coefficient, a first parameter and a parameter to be solved; the first coefficient is represented by a matrix, and the first parameter and the parameter to be solved are represented by a vector;
[0011] An element extraction module, used for extracting diagonal elements and off-diagonal elements in the first coefficient;
[0012] A data storage module, used for storing the diagonal elements, the off-diagonal elements and the first parameter in parallel in corresponding registers;
[0013] A target solution result acquisition module is used to read the diagonal elements, the off-diagonal elements and the first parameter from the corresponding registers, and iteratively solve the parameters to be solved through the Jacobi iteration method to obtain the target solution result, and store the target solution result in a memory; wherein the registers and the memory are located in the SIMD hardware architecture.
[0014] In a third aspect, an embodiment of the present invention further provides an electronic device, the electronic device comprising:
[0015] at least one processor; and
[0016] a memory communicatively connected to the at least one processor; wherein,
[0017] The memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the data processing method described in the embodiment of the present invention.
[0018] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the data processing method described in the embodiment of the present invention when executed.
[0019] In a fifth aspect, an embodiment of the present invention further provides a computer program product, including a computer program, which implements the data processing method described in the embodiment of the present invention when executed by a processor.
[0020] The embodiment of the present invention discloses a data processing method, device, equipment and medium, wherein the method is executed by a controller in a single instruction multiple data (SIMD) hardware architecture, and the SIMD hardware architecture is a hardware architecture for parallel processing of data, including: obtaining input data; wherein the input data includes a first coefficient, a first parameter and a parameter to be solved; the first coefficient is represented by a matrix, and the first parameter and the parameter to be solved are represented by a vector; extracting diagonal elements and non-diagonal elements in the first coefficient; storing the diagonal elements, non-diagonal elements and the first parameter in parallel in corresponding registers; reading the diagonal elements, non-diagonal elements and the first parameter from the corresponding register, and iteratively solving the parameter to be solved by the Jacobi iteration method, obtaining a target solution result, and storing the target solution result in a memory; wherein the register and the memory are located in the SIMD hardware architecture. The above technical solution is executed in a single instruction multiple data (SIMD) hardware architecture, and since the SIMD hardware architecture is a hardware architecture for parallel processing of data, it has a certain ability to process data in parallel, and thus can accelerate the operation of the Jacobi iteration method, thereby improving the computational efficiency of the Jacobi iteration method. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 is a flow chart of a data processing method in Embodiment 1 of the present invention;
[0022] Figure 2 is a flow chart of a data processing method in Embodiment 2 of the present invention;
[0023] Figure 3 is a structural schematic diagram of a data processing device in Embodiment 3 of the present invention;
[0024] Figure 4 It is a structural schematic diagram of an electronic device in Embodiment 4 of the present invention. DETAILED DESCRIPTION
[0025] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.
[0026] Embodiment 1
[0027] Figure 1 This is a flowchart of a data processing method provided in Embodiment 1 of the present invention. This embodiment is applicable to the case where a parameter to be solved is to be solved. The method can be executed by a data processing device, which can be implemented in the form of software and / or hardware. Optionally, it can be implemented by an electronic device, which can be a mobile terminal, a PC or a server, etc. Specifically, it includes the following steps:
[0028] S110: Obtain input data.
[0029] In this embodiment, the execution subject is a controller in a single instruction multiple data SIMD hardware architecture, and the SIMD hardware architecture is a hardware architecture for parallel processing of data. Furthermore, the input data is data in a linear equation system to be solved, and specifically, the input data may include a first coefficient, a first parameter, and a parameter to be solved; wherein the first coefficient is represented by a matrix, and the first parameter and the parameter to be solved are represented by a vector. Exemplarily, taking a linear equation system of the form Ax=b as an example, A represents the first coefficient, x represents the parameter to be solved, and b represents the first parameter. wherein A can be an n×n matrix, x is an unknown vector, and b is a known vector.
[0030] S120. Extract diagonal elements and off-diagonal elements in the first coefficient.
[0031] In this embodiment, the method of extracting diagonal elements and non-diagonal elements in the first coefficient can be: performing a preprocessing operation on the first coefficient to obtain the preprocessed first coefficient; and extracting the diagonal elements and non-diagonal elements in the preprocessed first coefficient.
[0032] Continuing with the above description, since the first coefficient is represented by a matrix, the way of performing a preprocessing operation on the first coefficient may be: processing the first coefficient into a symmetric matrix or an asymmetric matrix.
[0033] Furthermore, the matrix includes multiple elements, and the diagonal elements can be understood as elements located at the diagonal positions of the matrix; the non-diagonal elements can be understood as other elements in the matrix except the diagonal elements.
[0034] S130. Store the diagonal elements, the off-diagonal elements and the first parameter in parallel in corresponding registers.
[0035] In this embodiment, the register is located in the SIMD hardware architecture and is used to store data.
[0036] In this embodiment, the diagonal elements, non-diagonal elements and the first parameter are pre-stored in the memory. Specifically, the diagonal elements, non-diagonal elements and the first parameter can be stored in parallel in the corresponding registers by: according to the address of the diagonal elements in the memory, the diagonal elements in the memory are loaded into the first register by using SIMD load instructions; according to the address of the non-diagonal elements in the memory, the non-diagonal elements in the memory are loaded into the second register by using SIMD load instructions; according to the address of the first parameter in the memory, the first parameter in the memory is loaded into the third register by using SIMD load instructions. The above three loading processes are implemented in parallel.
[0037] Furthermore, each register has a corresponding bit width, such as a 128-bit register, a 256-bit register, etc. If there are many diagonal elements, multiple first registers may be required to store the diagonal elements; similarly, there may be multiple second registers to store non-diagonal elements, and there may be multiple third registers to store the first parameter.
[0038] Exemplarily, the SIMD load instruction may be movaps or movups. Taking movaps as an example, assuming that the first register is x1, then according to the address of the diagonal element in the memory, the method of using the SIMD load instruction to load the diagonal element in the memory into the first register may be: using the movaps x1, [address of the diagonal element in the memory] instruction to load the diagonal element in the memory into the first register x1.
[0039] Further, assuming that the second register is x2, then according to the address of the non-diagonal elements in the memory, the method of using SIMD load instructions to load the non-diagonal elements in the memory into the second register can be: using movaps x2 [address of the non-diagonal elements in the memory] instruction to load the non-diagonal elements in the memory into the second register x2.
[0040] Further, assuming that the third register is x3, the method of using the SIMD load instruction to load the first parameter in the memory into the third register according to the address of the first parameter in the memory can be: using the movaps x3 [address of the first parameter in the memory] instruction to load the first parameter in the memory into the third register x3.
[0041] S140, reading the diagonal elements, the off-diagonal elements and the first parameter from the corresponding registers, and iteratively solving the parameters to be solved by the Jacobi iteration method to obtain the target solution result, and storing the target solution result in the memory.
[0042] In this embodiment, the Jacobi iteration method is used to solve the parameter x to be solved in the linear equation system Ax=b; the target solution result is the solution result of the parameter x to be solved, and the target solution result is represented by a vector; the memory is located in the SIMD hardware architecture.
[0043] Furthermore, the method of iteratively solving the parameters to be solved by the Jacobi iteration method can be: using the Jacobi iteration formula x (k+1) =D -1 (b-Rx (k) ) Iterate the solution of the parameter x to be solved until the iteration end condition is met. -1 represents the inverse of the diagonal element D, R represents the off-diagonal element, x (k)represents the solution after the kth iteration, x (k+1) represents the solution after the k+1th iteration. Before using the Jacobi iteration formula for iterative solution, an initial estimate x of the parameter to be solved needs to be given (0) , then based on the initial estimate x (0) And the above Jacobi iteration formula is used to iteratively solve the parameter x to be solved.
[0044] For example, assuming that after the 100th iteration, the iteration end condition is met, the target solution result is x (100) , and since the target solution result is a vector containing multiple elements, storing the target solution result in the memory can be understood as storing multiple elements in the target solution result in the memory.
[0045] The technical solution of this embodiment obtains input data; extracts diagonal elements and non-diagonal elements in the first coefficient; stores the diagonal elements, non-diagonal elements and first parameters in parallel in corresponding registers; reads the diagonal elements, non-diagonal elements and first parameters from the corresponding registers, and iteratively solves the parameters to be solved by the Jacobi iteration method to obtain the target solution result, and stores the target solution result in a memory. The above technical solution is executed in a single instruction multiple data SIMD hardware architecture. Since the SIMD hardware architecture is a hardware architecture for parallel processing of data and has a certain ability to process data in parallel, it can accelerate the operation of the Jacobi iteration method, thereby improving the computational efficiency of the Jacobi iteration method.
[0046] Embodiment 2
[0047] Figure 2 This is a flow chart of a data processing method provided in Embodiment 2 of the present invention. Based on the above embodiment, the method includes the following steps:
[0048] S210: Obtain input data.
[0049] S220. Extract diagonal elements and off-diagonal elements in the first coefficient.
[0050] S230, storing the diagonal elements, the off-diagonal elements and the first parameter in parallel in corresponding registers.
[0051] In this embodiment, the diagonal elements, the off-diagonal elements and the first parameter are stored in the first register, the second register and the third register respectively.
[0052] S240: Obtain a preset solution result, and use the preset solution result as the current solution result.
[0053] In this embodiment, the preset solution result is a preset solution result. For example, the preset solution result can be understood as an initial estimate x of the parameter x to be solved. (0) .
[0054] S250, storing the current solution result in the fourth register.
[0055] In this embodiment, the current solution result is pre-stored in the memory, and the current solution result can be stored in the fourth register by: according to the address of the current solution result in the memory, using the SIMD load instruction to load the current solution result in the memory into the fourth register.
[0056] S260, reading the current solution result from the fourth register, and controlling the multi-core processor based on the SIMD instruction to update the current solution result according to the diagonal elements, the off-diagonal elements and the first parameter to obtain an updated solution result.
[0057] In this embodiment, the SIMD instruction may be a SIMD multiplication instruction, a SIMD subtraction instruction, a SIMD reciprocal instruction, etc. The multi-core processor may process different tasks in parallel or different parts of the same task that can be executed in parallel.
[0058] In this embodiment, based on the SIMD instruction, the multi-core processor is controlled to update the current solution result according to the diagonal elements, the off-diagonal elements and the first parameter to obtain the updated solution result. One implementation method can be described as the following steps:
[0059] a1) controlling the multi-core processor to perform a multiplication operation on the non-diagonal elements in the second register and the current solution result in the fourth register based on the SIMD multiplication instruction to obtain a first intermediate parameter, and storing the first intermediate parameter in the fifth register;
[0060] In this embodiment, the SIMD multiplication instruction may be a mulps instruction, a mulpd instruction, a vmulps instruction, and a vmulpd instruction. For example, assuming that the current solution result is x (k) , and then control the multi-core processor based on the SIMD multiplication instruction to multiply the off-diagonal element R in the second register with the current solution result x in the fourth register (k) Perform parallel multiplication to obtain the first intermediate parameter Rx (k) , and the first intermediate parameter Rx (k) Stored in the fifth register.
[0061] b1) controlling the multi-core processor to perform a subtraction operation on the first parameter in the third register and the first intermediate parameter in the fifth register based on the SIMD subtraction instruction to obtain a second intermediate parameter, and storing the second intermediate parameter in the sixth register;
[0062] In this embodiment, the SIMD subtraction instruction may be a subps instruction, a subpd instruction, a vsubps instruction, and a vsubpd instruction. Exemplarily, based on the SIMD subtraction instruction, the multi-core processor is controlled to add the first parameter b in the third register to the first intermediate parameter Rx in the fifth register. (k) Perform parallel subtraction to obtain the second intermediate parameter (b-Rx (k) ), and the second intermediate parameter (b-Rx (k) ) is stored in the sixth register.
[0063] c1) controlling the multi-core processor to perform parallel reciprocal operations on the diagonal elements in the first register based on the SIMD reciprocal instruction to obtain the reciprocal elements, and updating the diagonal elements in the first register to the reciprocal elements;
[0064] In this embodiment, the SIMD reciprocal instruction may be an rcpps instruction, an rcpss instruction, a vrcpps instruction, and a vrcpss instruction. Exemplarily, based on the SIMD reciprocal instruction, the multi-core processor is controlled to perform a parallel reciprocal operation on the diagonal element D in the first register to obtain the reciprocal element D -1 , and update the diagonal elements in the first register to the inverse element D -1 .
[0065] d1) Based on the SIMD multiplication instruction, the multi-core processor is controlled to perform a multiplication operation on the inverse element in the first register and the second intermediate parameter in the sixth register to obtain an updated solution result.
[0066] Exemplarily, based on the SIMD multiplication instruction, the multi-core processor is controlled to calculate the inverse element D in the first register. -1 and the second intermediate parameter (b-Rx (k) ) performs parallel multiplication operations to obtain the updated solution result D -1 (b-Rx (k) ), that is, x (k+1) .
[0067] S270: Determine whether the iteration end condition is met.
[0068] In this embodiment, one way to determine whether the iteration end condition is met is: based on SIMD instructions, the multi-core processor is controlled to determine whether the iteration end condition is met according to the updated solution result and the current solution result.
[0069] For example, the updated solution is x (k+1) , the current solution is x (k) .
[0070] Following the above description, one implementation method of controlling the multi-core processor based on SIMD instructions to determine whether the iteration end condition is met according to the updated solution result and the current solution result can be described as the following steps:
[0071] a2) Based on the SIMD subtraction instruction, the multi-core processor is controlled to perform a parallel subtraction operation on the updated solution result and the current solution result to obtain a difference;
[0072] Exemplarily, based on the SIMD subtraction instruction, the multi-core processor is controlled to update the solution result x (k+1) With the current solution x (k) Perform parallel subtraction to obtain the difference x (k+1) -x (k) .
[0073] b2) determining the target norm of the difference;
[0074] In this embodiment, the target norm may be a Euclidean norm. Further, the difference (x (k+1) -x (k) )’s Euclidean norm: ||x (k+1) -x (k) ||.
[0075] c2) If the target norm is less than or equal to the convergence threshold, the iteration end condition is met;
[0076] In this embodiment, the convergence threshold is a preset value, such as e. If the target norm || x (k+1) -x (k) ||<=e, the iteration end condition is met, that is, the iteration is ended at this time.
[0077] d2) If the target norm is greater than the convergence threshold, the iteration end condition is not met.
[0078] In this embodiment, if the target norm ||x (k+1) -x (k) ||>e, the iteration end condition is not met, that is, the iteration has not ended at this time.
[0079] In this embodiment, another way to determine whether the iteration end condition is met is as follows: determine whether the iteration end condition is met according to the current iteration count and the set maximum iteration count; wherein, the current iteration count is obtained from the counter of the SIMD hardware architecture.
[0080] Furthermore, the set maximum iteration count is a pre-set value, such as S. The way to determine whether the iteration end condition is met according to the current iteration count and the set maximum iteration count is as follows: if the current iteration count is equal to S, then the iteration end condition is met; if the current iteration count < S, then the iteration end condition is not met.
[0081] S280. If the iteration end condition is met, then use the updated solution result as the target solution result, and store the target solution result in the memory.
[0082] Exemplarily, if the iteration end condition is met, then use the updated solution result x (k+1) as the target solution result, and store the target solution result x (k+1) in the memory.
[0083] S290. If the iteration end condition is not met, then use the updated solution result as the current solution result, and return to execute the operation of storing the current solution result in the fourth register.
[0084] Exemplarily, if the iteration end condition is not met, then use the updated solution result x (k+1) as the current solution result, and return to execute step S250 to store the current solution result in the fourth register, and continue the iterative update.
[0085] The technical solution of this embodiment is to obtain input data; extract diagonal elements and non-diagonal elements in the first coefficient; store the diagonal elements, non-diagonal elements and the first parameter in parallel in the corresponding registers; obtain a preset solution result, and use the preset solution result as the current solution result; store the current solution result in a fourth register; read the current solution result from the fourth register, and control the multi-core processor based on the SIMD instruction to update the current solution result according to the diagonal elements, non-diagonal elements and the first parameter to obtain an updated solution result; determine whether the iteration end condition is met; if the iteration end condition is met, the updated solution result is used as the target solution result, and the target solution result is stored in the memory; if the iteration end condition is not met, the updated solution result is used as the current solution result, and the operation of storing the current solution result in the fourth register is returned. The above technical solution is executed in a single instruction multiple data SIMD hardware architecture. Since the SIMD hardware architecture is a hardware architecture for parallel processing of data, it has a certain ability to process data in parallel, so it can accelerate the operation of the Jacobi iteration method, thereby improving the computational efficiency of the Jacobi iteration method.
[0086] Embodiment 3
[0087] Figure 3 Schematic diagram of the structure of a data processing device provided in Embodiment 3 of the present invention, wherein the device is arranged in a controller in a single instruction multiple data (SIMD) hardware architecture, wherein the SIMD hardware architecture is a hardware architecture for processing data in parallel, such as Figure 3 As shown, the device comprises:
[0088] The data acquisition module 310 is used to acquire input data; wherein the input data includes a first coefficient, a first parameter, and a parameter to be solved; the first coefficient is represented by a matrix, and the first parameter and the parameter to be solved are represented by a vector;
[0089] An element extraction module 320, configured to extract diagonal elements and off-diagonal elements from the first coefficient;
[0090] A data storage module 330, configured to store the diagonal elements, the off-diagonal elements and the first parameter in parallel in corresponding registers;
[0091] The target solution result acquisition module 340 is used to read the diagonal elements, the non-diagonal elements and the first parameters from the corresponding registers, and iteratively solve the parameters to be solved through the Jacobi iteration method to obtain the target solution results, and store the target solution results in the memory; wherein the registers and the memory are located in the SIMD hardware architecture.
[0092] Optionally, the diagonal elements, the off-diagonal elements and the first parameter are stored in a first register, a second register and a third register, respectively.
[0093] Optionally, the target solution result obtaining module 340 may specifically include:
[0094] A preset solution result acquisition unit, used to acquire a preset solution result and use the preset solution result as the current solution result;
[0095] A current solution result storage unit, used for storing the current solution result in a fourth register;
[0096] A current solution result updating unit, used for reading the current solution result from the fourth register, and controlling the multi-core processor to update the current solution result according to the diagonal elements, the off-diagonal elements and the first parameter based on a SIMD instruction to obtain an updated solution result;
[0097] A condition judgment unit, used to judge whether the iteration end condition is met;
[0098] A target solution result acquisition unit, configured to use the updated solution result as the target solution result if the iteration end condition is met;
[0099] The return execution unit is used to use the updated solution result as the current solution result if the iteration end condition is not met, and return to execute the operation of storing the current solution result in the fourth register.
[0100] Optionally, the current solution result updating unit may be specifically used for:
[0101] Based on the SIMD multiplication instruction, the multi-core processor is controlled to multiply the non-diagonal elements in the second register with the current solution result in the fourth register to obtain a first intermediate parameter, and the first intermediate parameter is stored in the fifth register; based on the SIMD subtraction instruction, the multi-core processor is controlled to subtract the first parameter in the third register from the first intermediate parameter in the fifth register to obtain a second intermediate parameter, and the second intermediate parameter is stored in the sixth register; based on the SIMD reciprocal instruction, the multi-core processor is controlled to perform parallel reciprocal operations on the diagonal elements in the first register to obtain the reciprocated elements, and the diagonal elements in the first register are updated to the reciprocated elements; based on the SIMD multiplication instruction, the multi-core processor is controlled to multiply the reciprocated elements in the first register with the second intermediate parameter in the sixth register to obtain an updated solution result.
[0102] Optionally, the condition judgment unit may be specifically used to:
[0103] Control the multi-core processor based on SIMD instructions to determine whether an iteration end condition is met according to the updated solution result and the current solution result; or
[0104] Whether an iteration end condition is satisfied is determined according to the current number of iterations and the set maximum number of iterations; wherein the current number of iterations is obtained from a counter of the SIMD hardware architecture.
[0105] Optionally, the method of controlling the multi-core processor based on the SIMD instruction to determine whether the iteration end condition is met according to the updated solution result and the current solution result is:
[0106] Based on the SIMD subtraction instruction, the multi-core processor is controlled to perform a parallel subtraction operation on the updated solution result and the current solution result to obtain a difference; a target norm of the difference is determined; if the target norm is less than or equal to a convergence threshold, an iteration end condition is met; if the target norm is greater than the convergence threshold, the iteration end condition is not met.
[0107] The above device can execute the methods provided by all the above embodiments of the present invention, and has the corresponding functional modules and beneficial effects of executing the above methods. For technical details not described in detail in this embodiment, please refer to the methods provided by all the above embodiments of the present invention.
[0108] Embodiment 4
[0109] Figure 4 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.
[0110] like Figure 4As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.
[0111] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.
[0112] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as a data processing method.
[0113] In some embodiments, the data processing method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the data processing method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the data processing method in any other appropriate manner (e.g., by means of firmware).
[0114] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.
[0115] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.
[0116] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
[0117] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).
[0118] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.
[0119] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.
[0120] An embodiment of the present invention further provides a computer program product, including a computer program, which, when executed by a processor, implements the data processing method provided in any embodiment of the present application.
[0121] In the process of implementation, the computer program product can be written in one or more programming languages or a combination thereof to perform the computer program code of the present invention, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, using an Internet service provider to connect through the Internet).
[0122] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.
[0123] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims
1. A data processing method, characterized in that: The method is executed by a controller in a single instruction multiple data (SIMD) hardware architecture, where the SIMD hardware architecture is a hardware architecture for processing data in parallel, and the method includes: Acquire input data; wherein the input data includes a first coefficient, a first parameter, and a parameter to be solved; the first coefficient is represented by a matrix, and the first parameter and the parameter to be solved are represented by a vector; Extracting diagonal elements and off-diagonal elements from the first coefficients; Storing the diagonal elements, the off-diagonal elements and the first parameter in parallel in corresponding registers; The diagonal elements, the off-diagonal elements and the first parameters are read from corresponding registers, and the parameters to be solved are iteratively solved by Jacobi iteration method to obtain target solution results, and the target solution results are stored in a memory; wherein the registers and the memory are located in the SIMD hardware architecture.
2. The method according to claim 1, characterized in that The diagonal elements, the off-diagonal elements and the first parameter are stored in a first register, a second register and a third register, respectively.
3. The method according to claim 2, characterized in that The diagonal elements, the off-diagonal elements, and the first parameter are read from corresponding registers, and the parameters to be solved are iteratively solved by the Jacobi iteration method to obtain a target solution result, including: Obtaining a preset solution result, and using the preset solution result as the current solution result; storing the current solution result in a fourth register; Reading the current solution result from the fourth register, and controlling the multi-core processor based on the SIMD instruction to update the current solution result according to the diagonal elements, the off-diagonal elements and the first parameter to obtain an updated solution result; Determine whether the iteration end condition is met; If the iteration end condition is met, the updated solution result is used as the target solution result; If the iteration end condition is not met, the updated solution result is used as the current solution result, and the operation of storing the current solution result in the fourth register is returned to be executed.
4. The method according to claim 3, characterized in that Controlling the multi-core processor based on the SIMD instruction to update the current solution result according to the diagonal elements, the off-diagonal elements and the first parameter to obtain an updated solution result includes: Controlling the multi-core processor to perform a multiplication operation on the non-diagonal elements in the second register and the current solution result in the fourth register based on the SIMD multiplication instruction to obtain a first intermediate parameter, and storing the first intermediate parameter in a fifth register; Controlling the multi-core processor to perform a subtraction operation on the first parameter in the third register and the first intermediate parameter in the fifth register based on the SIMD subtraction instruction to obtain a second intermediate parameter, and storing the second intermediate parameter in the sixth register; Controlling the multi-core processor to perform parallel reciprocal operations on the diagonal elements in the first register based on the SIMD reciprocal instruction to obtain the reciprocal elements, and updating the diagonal elements in the first register to the reciprocal elements; Based on the SIMD multiplication instruction, the multi-core processor is controlled to perform a multiplication operation on the inverse element in the first register and the second intermediate parameter in the sixth register to obtain an updated solution result.
5. The method according to claim 3, characterized in that: Determine whether the iteration end conditions are met, including: Control the multi-core processor based on SIMD instructions to determine whether an iteration end condition is met according to the updated solution result and the current solution result; or Whether an iteration end condition is satisfied is determined according to the current number of iterations and the set maximum number of iterations; wherein the current number of iterations is obtained from a counter of the SIMD hardware architecture.
6. The method according to claim 5, characterized in that Controlling the multi-core processor based on the SIMD instruction to determine whether an iteration end condition is met according to the updated solution result and the current solution result, includes: Controlling the multi-core processor to perform a parallel subtraction operation on the updated solution result and the current solution result based on a SIMD subtraction instruction to obtain a difference; determining a target norm of the difference; If the target norm is less than or equal to the convergence threshold, the iteration end condition is met; If the target norm is greater than the convergence threshold, the iteration end condition is not met.
7. A data processing device, characterized in that: The device is arranged in a controller in a single instruction multiple data (SIMD) hardware architecture, which is a hardware architecture for processing data in parallel, and includes: A data acquisition module, used to acquire input data; wherein the input data includes a first coefficient, a first parameter and a parameter to be solved; the first coefficient is represented by a matrix, and the first parameter and the parameter to be solved are represented by a vector; An element extraction module, used for extracting diagonal elements and off-diagonal elements in the first coefficient; A data storage module, used for storing the diagonal elements, the off-diagonal elements and the first parameter in parallel in corresponding registers; A target solution result acquisition module is used to read the diagonal elements, the off-diagonal elements and the first parameter from the corresponding registers, and iteratively solve the parameters to be solved through the Jacobi iteration method to obtain the target solution result, and store the target solution result in a memory; wherein the registers and the memory are located in the SIMD hardware architecture.
8. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the data processing method according to any one of claims 1 to 6.
9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the data processing method according to any one of claims 1 to 6 when executed.
10. A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements the data processing method according to any one of claims 1 to 6.