Noise reduction method based on FPGA

Abstract

The invention relates to the technical field of noise reduction, in particular to an FPGA (Field Programmable Gate Array)-based noise reduction method, which comprises the following steps of: S1, converting an image into two mif files which can be identified by an FPGA as an operation image and a backup image, and storing the two mif files through a storage module; s2, performing 5 * 5 Gaussian Laplacian operator convolution on the operation image, and thresholding the operation image; s3, using templates of sobel operators in four directions of 0 degree, 45 degrees, 90 degrees and 135 degrees to calculate maximum first-order partial derivatives in four directions at a central point in the 7 * 7 array; and S4, for a suspicious zero cross point, when the direction of the suspicious zero cross point is consistent with the solved normal direction of the gradient at the central point, the point is considered as a true zero cross point. According to the noise reduction method based on the FPGA, the image obtained by sleeving the image edge noise reduction model into the image splicing model and the backup image are extracted to obtain the noise reduction image, so that the image noise reduction effect is improved, the image edge continuity is better, and more details are reserved.

Description

Technical Field

[0001] The invention relates to the technical field of noise reduction, and in particular to a noise reduction method based on FPGA. Background Art

[0002] Image noise reduction is a technique used to improve digital images by reducing noise in the image.

[0003] In the existing image denoising process, it is inevitable that details in the image will be lost and the image will be poorly continuous. Summary of the invention

[0004] The purpose of the present invention is to provide a denoising method based on FPGA to solve the problem that details in the image are inevitably lost and the image continuity is poor in the existing image denoising process proposed in the above background technology. To achieve the above purpose, the present invention provides the following technical solution: a denoising method based on FPGA, comprising the following steps: S1: Convert the image into two mif files recognizable by FPGA as the operation image and backup image, and store them through the storage module; S2: Perform 5×5 Gaussian Laplacian convolution on the operation image and threshold it; S3: Calculate the maximum first-order partial derivatives in four directions at the center point of the 7×7 array using templates of the Sobel operator in four directions: 0°, 45°, 90°, and 135°; S4: For suspicious zero crossing points, when their direction is consistent with the normal direction of the gradient at the center point, this point is considered to be a true zero crossing point, otherwise it is a false zero crossing point, and the expansion and corrosion operations in the gradient direction are performed respectively through the basic bodies in the four directions of 0°, 45°, 90° and 135°. For non-zero crossing points, the opening operation of corrosion and expansion is performed to denoise the image and obtain the image edge denoising model; S5: The training image data is input into the image segmentation model, and the image segmentation model and the image edge denoising model process the data in sequence; S6: The image obtained by S5 is compared with the backup image, and repeated highly consistent pixels are extracted through the image stitching model to generate a denoised image.

[0005] The thresholding is a preset positive and negative threshold, and a three-bit sign bit register is allocated in the FPGA. When the convolution value is greater than the positive threshold, the sign bit is "001", when it is less than the negative threshold, the sign bit is "010", and in other cases the sign bit is "100". According to the signs of the LOG convolution values ​​at the center point and the adjacent points, the suspicious zero crossing points are found from the two cases of "001" and "010", among which the case of "100" is a non-zero crossing point.

[0006] The training image data adds noise to low-noise image data, including: Generate a two-dimensional random number matrix of the same size as the low-noise image data. For each pixel in the low-noise image data, obtain a random number from the corresponding same position in the two-dimensional random number matrix and set the noise density. Set the pixel value of the pixel in the low-noise image data according to the following formula:

[0007] x is the position of the pixel, I(x) is the pixel value after the pixel is set, P(x) is the pixel value before the pixel is set, Ns(x) is the pixel value corresponding to white, NP(x) is the pixel value corresponding to black, rand is the random number corresponding to the x position in the two-dimensional random number matrix, and p is the noise density.

[0008] The convolution operation is as follows: image data is cached in 7 lines through a shift register, and the 7 lines of data are stored in a 7×7 register array with the cycle, and the shift operator in the Verilog language is used to achieve a power-of-2 effect, and then the 25 registers covered by the template are added to obtain the convolution value.

[0009] Compared with the prior art, the present invention has the following beneficial effects: In the present invention, the image obtained by fitting the image stitching model into the image edge denoising model and the backup image are extracted to obtain a denoised image, thereby improving the image denoising effect, making the image edge continuity better and retaining more details. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a flowchart of the present invention. DETAILED DESCRIPTION

[0011] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technical personnel in this field without creative work are within the scope of protection of the present invention.

[0012] See also Figure 1 The present invention provides a technical solution: a noise reduction method based on FPGA, comprising the following steps: S1: Convert the image into two mif files recognizable by FPGA as the operation image and backup image, and store them through the storage module; S2: Perform 5×5 Gaussian Laplacian convolution on the operation image and threshold it; S3: Calculate the maximum first-order partial derivatives in four directions at the center point of the 7×7 array using templates of the Sobel operator in four directions: 0°, 45°, 90°, and 135°; S4: For suspicious zero crossing points, when their direction is consistent with the normal direction of the gradient at the center point, this point is considered to be a true zero crossing point, otherwise it is a false zero crossing point, and the expansion and corrosion operations in the gradient direction are performed respectively through the basic bodies in the four directions of 0°, 45°, 90° and 135°. For non-zero crossing points, the opening operation of corrosion and expansion is performed to denoise the image and obtain the image edge denoising model; S5: The training image data is input into the image segmentation model, and the image segmentation model and the image edge denoising model process the data in sequence; S6: The image obtained by S5 is compared with the backup image, and repeated highly consistent pixels are extracted through the image stitching model to generate a denoised image.

[0013] The threshold is set to preset positive and negative thresholds, and a three-bit sign bit register is allocated in the FPGA. When the convolution value is greater than the positive threshold, the sign bit is "001", when it is less than the negative threshold, the sign bit is "010", and in other cases the sign bit is "100". According to the signs of the LOG convolution values ​​at the center point and the adjacent points, the suspicious zero crossing points are found from the two cases of "001" and "010", among which the case of "100" is a non-zero crossing point.

[0014] The training image data adds noise to the low-noise image data, including: Generate a two-dimensional random number matrix of the same size as the low-noise image data. For each pixel in the low-noise image data, obtain a random number from the corresponding same position in the two-dimensional random number matrix and set the noise density. Set the pixel value of the pixel in the low-noise image data according to the following formula:

[0015] x is the position of the pixel, I(x) is the pixel value after the pixel is set, P(x) is the pixel value before the pixel is set, Ns(x) is the pixel value corresponding to white, NP(x) is the pixel value corresponding to black, rand is the random number corresponding to the x position in the two-dimensional random number matrix, and p is the noise density.

[0016] The convolution operation is as follows: the image data is cached in 7 lines through the shift register, and the 7 lines of data are stored in the 7×7 register array with the cycle. The shift operator in the Verilog language is used to achieve the effect of multiplication by a power of 2, and then the 25 registers covered by the template are added to obtain the convolution value.

[0017] The above shows and describes the basic principles, main features and advantages of the present invention. Technical personnel in this industry should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only preferred examples of the present invention and are not used to limit the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A noise reduction method based on FPGA, characterized in that: The steps include: S1: Convert the image into two mif files recognizable by FPGA as the operation image and backup image, and store them through the storage module; S2: Perform 5×5 Gaussian Laplacian convolution on the operation image and threshold it; S3: Calculate the maximum first-order partial derivatives in four directions at the center point of the 7×7 array using templates of the Sobel operator in four directions: 0°, 45°, 90°, and 135°. S4: For suspicious zero crossing points, when their direction is consistent with the normal direction of the gradient at the center point, this point is considered to be a true zero crossing point, otherwise it is a false zero crossing point, and the expansion and corrosion operations in the gradient direction are performed respectively through the basic bodies in the four directions of 0°, 45°, 90° and 135°. For non-zero crossing points, the opening operation of corrosion and expansion is performed to denoise the image and obtain the image edge denoising model; S5: The training image data is input into the image segmentation model, and the image segmentation model and the image edge denoising model process the data in sequence; S6: The image obtained by S5 is compared with the backup image, and repeated highly consistent pixels are extracted through the image stitching model to generate a denoised image.

2. The FPGA-based noise reduction method according to claim 1, characterized in that: The thresholding is a preset positive and negative threshold, and a three-bit sign bit register is allocated in the FPGA. When the convolution value is greater than the positive threshold, the sign bit is "001", when it is less than the negative threshold, the sign bit is "010", and in other cases the sign bit is "100". According to the signs of the LOG convolution values ​​at the center point and the adjacent points, the suspicious zero crossing points are found from the two cases of "001" and "010", among which the case of "100" is a non-zero crossing point.

3. The FPGA-based noise reduction method according to claim 1, characterized in that: The training image data is low-noise image data with noise added, including: Generate a two-dimensional random number matrix of the same size as the low-noise image data. For each pixel in the low-noise image data, obtain a random number from the corresponding same position in the two-dimensional random number matrix and set the noise density. Set the pixel value of the pixel in the low-noise image data according to the following formula: x is the position of the pixel, I(x) is the pixel value after the pixel is set, P(x) is the pixel value before the pixel is set, Ns(x) is the pixel value corresponding to white, NP(x) is the pixel value corresponding to black, rand is the random number corresponding to the x position in the two-dimensional random number matrix, and p is the noise density.

4. The FPGA-based noise reduction method according to claim 1, characterized in that: The convolution operation is as follows: image data is cached in 7 lines through a shift register, and the 7 lines of data are stored in a 7×7 register array with the cycle, and the shift operator in the Verilog language is used to achieve a power-of-2 effect, and then the 25 registers covered by the template are added to obtain the convolution value.

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