Pixel circuit, driving method of pixel circuit and display substrate

Abstract

The invention discloses a pixel circuit, a driving method of the pixel circuit and a display substrate. The pixel circuit comprises a data writing module, a storage module, a bias module and a driving module, the bias module is coupled with at least one control signal, a first power supply end, a reference voltage signal, a bias voltage signal and a fifth node, and the bias module is configured to write data to the fifth node under the control of the at least one control signal. And providing one of the reference voltage signal, the bias voltage signal and the first power end signal to the fifth node in different periods. One of a reference voltage signal, a bias voltage signal and a first power supply end signal can be provided for a fifth node in different time periods through a bias module, the potential of a first node is adjusted through a storage module, and a grid electrode of a driving transistor is biased; when the pixel circuit drives the light-emitting module to emit light, uneven current caused by voltage drop of the first power supply end can be compensated, the problem of uneven display is solved, and the uniformity of a display picture is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel circuit, a driving method for a pixel circuit, and a display substrate. Background Art

[0002] Organic Light-Emitting Diode (OLED) has been widely used in the display field. In the pixel circuit of the related technology, when emitting light, the current Ioled flowing through the light-emitting device is related to the power supply VDD, so the VDD voltage drop in the remote display area will cause uneven display. In order to eliminate the influence of the power supply VDD on the current, the related technology uses multiple capacitors, but such a solution is not conducive to improving the resolution.

[0003] The above statements are only used to provide background information related to the present application and do not necessarily constitute prior art. Summary of the invention

[0004] The purpose of the present application is to provide a pixel circuit, a driving method of the pixel circuit and a display substrate. In order to have a basic understanding of some aspects of the disclosed embodiments, a simple summary is given below. This summary is not a general review, nor is it intended to identify key / important components or describe the scope of protection of these embodiments. Its only purpose is to present some concepts in a simple form as a preface to the detailed description that follows.

[0005] According to one aspect of an embodiment of the present application, a pixel circuit is provided, including:

[0006] a data writing module coupled to the first scanning signal terminal, the second scanning signal terminal, the data signal terminal, the second node, the third node and the first node, and configured to provide the signal of the data signal terminal to the first node through the second node and the third node under the control of the signal of the first scanning signal terminal and the second scanning signal terminal;

[0007] a storage module, two ends of which are respectively coupled to the first node and the fifth node, and configured to store the signal of the first node;

[0008] a bias module coupled to at least one control signal, a first power supply terminal, a reference voltage signal, a bias voltage signal and a fifth node, and configured to provide one of the reference voltage signal, the bias voltage signal and the first power supply terminal signal to the fifth node in time periods under the control of the at least one control signal;

[0009] The driving module is coupled to the first node, the second node and the third node, and is configured to provide a driving electrical signal to the third node based on the signal of the second node under the control of the signal of the first node.

[0010] In some embodiments of the present application, the bias module includes a first bias submodule and a second bias submodule;

[0011] A first bias submodule, coupled to the first control signal, the first power supply terminal and the fifth node, and configured to provide a signal of the first power supply terminal to the fifth node under the control of the first control signal in a first preset stage;

[0012] The second bias submodule is coupled to the second control signal, the voltage signal terminal and the fifth node, and is configured to provide the signal of the voltage signal terminal to the fifth node under the control of the second control signal, and the voltage signal terminal can provide the reference voltage signal or the bias voltage signal to the fifth node in time periods.

[0013] In some embodiments of the present application, the first bias submodule and the second bias submodule are both connected to a first signal terminal, and the first signal terminal provides the first control signal in the first preset stage and provides the second control signal in a period outside the first preset stage.

[0014] In some embodiments of the present application, the first bias submodule includes an eighth transistor, the second bias submodule includes a ninth transistor, and one of the eighth transistor and the ninth transistor is a PMOS and the other is an NMOS.

[0015] In some embodiments of the present application, the second bias submodule includes a first unit and a second unit, and the second control signal includes a first control sub-signal and a second control sub-signal;

[0016] The first unit is coupled to the first control sub-signal, the reference voltage terminal and the fifth node, and is configured to provide the reference voltage signal of the reference voltage terminal to the fifth node under the control of the first control sub-signal in the second preset stage;

[0017] The second unit is coupled to the second control sub-signal, the bias voltage terminal and the fifth node, and is configured to provide the bias voltage signal of the bias voltage terminal to the fifth node under the control of the second control sub-signal in a third preset stage.

[0018] In some embodiments of the present application, the second bias submodule includes at least one of the following:

[0019] The first unit includes a ninth transistor, a gate of the ninth transistor is coupled to the first control sub-signal, and a first electrode and a second electrode of the ninth transistor are coupled to the reference voltage terminal and the fifth node respectively;

[0020] The second unit includes a tenth transistor, a gate of the tenth transistor is coupled to the second control sub-signal, and a first electrode and a second electrode of the tenth transistor are coupled to the bias voltage terminal and the fifth node respectively.

[0021] In some embodiments of the present application, when both the first scan signal and the second scan signal provide valid signals, the bias module is configured to provide the reference voltage signal to the fifth node under the control of the at least one control signal in a second preset stage.

[0022] In some embodiments of the present application, the bias module is further configured to provide the bias voltage signal to the fifth node under the control of the at least one control signal in a third preset stage, and the third preset stage is located after the data writing period in the second preset stage within a light-emitting cycle.

[0023] In some embodiments of the present application, the bias module is also configured to provide the reference voltage signal to the fifth node under the control of the at least one control signal during a bias reset period of the second preset stage, and the bias reset period is located after the third preset stage and before the first preset stage.

[0024] In some embodiments of the present application, the pixel circuit further includes:

[0025] A first switch module is coupled to the enable signal terminal, the first power terminal and the second node, and is configured to provide a signal from the first power terminal to the second node under the control of a signal from the enable signal terminal;

[0026] The second switch module is coupled to the enable signal terminal, the third node and the fourth node, and is configured to provide the driving electrical signal of the third node to the fourth node under the signal control of the enable signal terminal to drive the light-emitting module to emit light.

[0027] In some embodiments of the present application, the pixel circuit further includes:

[0028] A first reset module, coupled to the first reset signal terminal, the first initial signal terminal and the third node, and configured to provide the signal of the first initial signal terminal to the third node under the control of the signal of the first reset signal terminal;

[0029] A second reset module, coupled to the second reset signal terminal, the second initial signal terminal and the fourth node, and configured to provide the signal of the second initial signal terminal to the fourth node under the control of the signal of the second reset signal terminal;

[0030] The bias module is further configured to provide the reference voltage signal to the fifth node under the control of the at least one control signal when the first reset signal terminal and / or the second reset signal terminal provides a valid signal.

[0031] In some embodiments of the present application, at least one of the following is satisfied:

[0032] The data writing module includes a second transistor and a fourth transistor, the gate of the second transistor is coupled to the second scanning signal terminal, the first electrode and the second electrode of the second transistor are respectively coupled to the third node and the first node, the gate of the fourth transistor is coupled to the first scanning signal terminal, and the first electrode and the second electrode of the fourth transistor are respectively coupled to the data signal terminal and the second node;

[0033] The first switch module includes a fifth transistor, a gate of the fifth transistor is coupled to the enable signal terminal, and a first electrode and a second electrode of the fifth transistor are coupled to the first power supply terminal and the second node respectively;

[0034] The driving module comprises a third transistor, a gate of the third transistor is coupled to the first node, and a first electrode and a second electrode of the third transistor are coupled to the second node and the third node respectively;

[0035] The second switch module includes a sixth transistor, a gate of the sixth transistor is coupled to the enable signal terminal, and a first electrode and a second electrode of the sixth transistor are coupled to the third node and the fourth node respectively;

[0036] The first reset module comprises a first transistor, a gate of the first transistor is coupled to the first reset signal terminal, and a first electrode and a second electrode of the first transistor are respectively coupled to the first initial signal terminal and the first node;

[0037] The second reset module includes a seventh transistor, a gate of the seventh transistor is coupled to the second reset signal terminal, and a first electrode and a second electrode of the seventh transistor are coupled to the second initial signal terminal and the fourth node, respectively.

[0038] According to another aspect of an embodiment of the present application, a driving method of a pixel circuit is provided, which is applied to the pixel circuit described in any embodiment of the present application, and the driving method includes:

[0039] In a data writing period, providing corresponding valid signals to both the first scanning signal terminal and the second scanning signal terminal, so that the signal of the data signal terminal is written into the first node through the data writing module; and providing a first valid signal to the bias module, so that the reference voltage signal is provided to the fifth node through the bias module;

[0040] In a bias period, providing a second valid signal to the bias module, so that the bias voltage signal is provided to the fifth node through the bias module;

[0041] During the bias end period, providing a first valid signal to the bias module, so that the reference voltage signal is provided to the fifth node through the bias module;

[0042] During the coupling period and the light-emitting period, a third effective signal is provided to the bias module, so that the signal at the first power supply terminal is provided to the fifth node through the bias module; and during the light-emitting period, a corresponding effective signal is provided to the enable signal terminal, so that the fourth node is provided with a driving electrical signal to drive the light-emitting module to emit light.

[0043] According to another aspect of the embodiments of the present application, a display substrate is provided, comprising the pixel circuit described in any embodiment of the present application.

[0044] The technical solution provided by one aspect of the embodiments of the present application may have the following beneficial effects:

[0045] The pixel circuit provided in the embodiment of the present application can provide a reference voltage signal, a bias voltage signal and one of the first power supply terminal signals to the fifth node in time periods through the bias module, and then the potential of the first node can be adjusted through the storage module to bias the gate of the driving transistor, so that the pixel circuit can compensate for the current unevenness caused by the voltage drop of the first power supply terminal when driving the light-emitting module to emit light, improve the problem of uneven display, and enhance the uniformity of the display screen. Compared with the pixel circuit in the related art, the scheme disclosed in the present invention does not need to add additional capacitors, which helps to improve the resolution of the display panel.

[0046] The above description is only an overview of the technical solution of the embodiment of the present application. In order to more clearly understand the technical means of the embodiment of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0048] Figure 1 A structural block diagram of a pixel circuit according to an embodiment of the present application is shown.

[0049] Figure 2 A structural block diagram of a pixel circuit according to another embodiment of the present application is shown.

[0050] Figure 3 A circuit diagram of a pixel circuit according to an embodiment of the present application is shown.

[0051] Figure 4 A circuit diagram of a pixel circuit according to another embodiment of the present application is shown.

[0052] Figure 5 A timing diagram of a pixel circuit according to an embodiment of the present application is shown.

[0053] Figure 6 A timing diagram of a pixel circuit according to another embodiment of the present application is shown. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0055] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art to which this application belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined as here.

[0056] The transistors used in all embodiments of the present invention can be thin film transistors or field effect transistors or other devices with the same characteristics. According to the role in the circuit, the transistors used in the embodiments of the present invention are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiment of the present invention, the source (source electrode) is called the first electrode, the drain (drain electrode) is called the second electrode, or the drain can be called the first electrode and the source is called the second electrode. According to the form in the accompanying drawings, the middle end of the transistor is defined as the gate (also called the gate electrode), the signal input end is the source, and the signal output end is the drain. The switching transistor used in the embodiment of the present invention can be a P-type transistor (PMOS) or an N-type transistor (NMOS). The P-type transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level; the N-type transistor is turned on when the gate is at a high level and is turned off when the gate is at a low level. In addition, multiple signals in each embodiment of the present invention correspond to a first potential and a second potential. The first potential and the second potential only represent two different potential state quantities of the signal, and do not represent that the first potential or the second potential in the full text has a specific value. In the embodiment of the present invention, the first potential is taken as an effective potential for description.

[0057] In the related art, some OLED products use 8T1C pixel circuits, which use a thin film transistor (TFT) to directly bias the source of the driving transistor. When such a pixel circuit emits light, the current flowing through the light-emitting device is related to the power supply VDD. The power supply VDD voltage drop in the remote display area will cause uneven display. If you want to eliminate the influence of the power supply VDD on the current, you can use two capacitors, that is, a separate circuit, but this is not conducive to improving resolution.

[0058] In order to solve some problems in the related art, embodiments of the present disclosure provide a pixel circuit, a driving method of the pixel circuit, and a display substrate.

[0059] A pixel circuit, a driving method of a pixel circuit, and a display substrate proposed according to an embodiment of the present application are described below in conjunction with the accompanying drawings.

[0060] An embodiment of the present application provides a pixel circuit, which can realize the bias (Bias) of a driving transistor (driving transistor for short DTFT) through a bias module without adding capacitance, so that the driving transistor has a variable refresh rate (variable refresh rate, full name Variable Refresh Rate, abbreviated as VRR), and can also supplement the voltage drop of the power supply VDD, thereby improving the uneven display quality caused by the VDD voltage drop in the remote display area.

[0061] refer to Figure 1As shown, an embodiment of the present application provides a pixel circuit, including a data writing module 20 , a storage module 30 , a bias module 80 and a driving module 60 .

[0062] The data writing module 20 is coupled to the first scan signal terminal Gate_P, the second scan signal terminal Gate_N, the data signal terminal Data, the second node N2, the third node N3 and the first node N1, and is configured to provide the signal of the data signal terminal Data to the first node N1 through the second node N2 and the third node N3 under the control of the signal of the first scan signal terminal Gate_P and the second scan signal terminal Gate_N. For example, when the first scan signal terminal Gate_P and the second scan signal terminal Gate_N both provide corresponding valid signals, the signal of the data signal terminal Data is written to the first node N1 through the data module 20, the second node N2 and the third node N3. When one of the first scan signal terminal Gate_P and the second scan signal terminal Gate_N provides a corresponding invalid signal, the signal of the data signal terminal Data cannot be written to the first node N1.

[0063] The storage module 30 has two ends coupled to the first node N1 and the fifth node N5 respectively, and is configured to store the signal of the first node N1.

[0064] The bias module 80 is coupled to at least one control signal, the first power supply terminal VDD, the reference voltage signal, the bias voltage signal and the fifth node N5, and is configured to provide one of the reference voltage signal, the bias voltage signal and the first power supply terminal VDD signal to the fifth node N5 in time periods under the control of at least one control signal. For example, in a first preset period, the bias module 80 provides the signal of the first power supply terminal VDD to the fifth node N5 under the control of at least one control signal; in a second preset period, the bias module 80 provides the reference voltage signal to the fifth node N5 under the control of at least one control signal; in a third preset period, the bias module 80 provides the bias voltage signal to the fifth node N5 under the control of at least one control signal.

[0065] The driving module 60 is coupled to the first node N1, the second node N2 and the third node N3, and is configured to provide a driving electrical signal to the third node N3 based on the signal of the second node N2 under the control of the signal of the first node N1. For example, when both the first node N1 and the second node N2 provide valid signals, the driving module 60 provides the driving electrical signal to the third node N3.

[0066] Exemplarily, the pixel circuit may further include a first switch module 40 and a second switch module 70 .

[0067] The first switch module 40 is coupled to the enable signal terminal EM, the first power supply terminal VDD and the second node N2, and is configured to provide the signal of the first power supply terminal VDD to the second node N2 under the control of the signal of the enable signal terminal EM. For example, when the enable signal terminal EM provides a valid signal, the first switch module 40 is turned on, and the signal of the first power supply terminal VDD is provided to the second node N2; when the enable signal terminal EM provides an invalid signal, the first switch module 40 disconnects the first power supply terminal VDD from the second node N2.

[0068] The second switch module 70 is coupled to the enable signal terminal EM, the third node N3 and the fourth node N4, and is configured to provide the driving electrical signal of the third node N3 to the fourth node N4 under the control of the signal of the enable signal terminal EM to drive the light emitting module 90 to emit light. For example, when the enable signal terminal EM provides a valid signal, the second switch module 70 is turned on, and the driving electrical signal of the third node N3 is provided to the fourth node N4, and the driving electrical signal of the fourth node N4 drives the light emitting module 90 to emit light.

[0069] The pixel circuit provided in the embodiment of the present application can provide a reference voltage signal, a bias voltage signal and one of the first power supply terminal signals to the fifth node N5 in time periods through the bias module, and then the potential of the first node N1 can be adjusted through the storage module to bias the gate of the driving transistor, so that the pixel circuit can compensate for the current unevenness caused by the voltage drop of the first power supply terminal VDD when driving the light-emitting module 90 to emit light, improve the problem of uneven display, and enhance the uniformity of the display screen. Compared with the pixel circuit in the related art, the scheme disclosed in the present invention does not need to add additional capacitors, which helps to improve the resolution of the display panel.

[0070] For example, the pixel circuit of the embodiment of the present application may adopt LTPO technology. The full name of LTPO is Low Temperature Polycrystalline Oxide, and its corresponding Chinese name is low temperature polycrystalline oxide.

[0071] refer to Figure 2 As shown, in some embodiments, the pixel circuit includes a data writing module 20, a storage module 30, a bias module 80, a first switch module 40, a driving module 60 and a second switch module 70, and further includes:

[0072] The first reset module 10 is coupled to the first reset signal terminal Reset_P1, the first initial signal terminal Vinit1 and the third node N3, and is configured to provide the signal of the first initial signal terminal to the third node N3 under the control of the signal of the first reset signal terminal Reset_P1;

[0073] The second reset module 50 is coupled to the second reset signal terminal Reset_P2, the second initial signal terminal Vinit2 and the fourth node N4, and is configured to provide the signal of the second initial signal terminal to the fourth node N4 under the control of the signal of the second reset signal terminal Reset_P2;

[0074] The bias module 80 is further configured to provide a reference voltage signal to the fifth node N5 under the control of at least one control signal when the first reset signal terminal Reset_P1 and / or the second reset signal terminal Reset_P2 provide a valid signal.

[0075] The first reset signal terminal Reset_P1 and the second reset signal terminal Reset_P2 may be the same reset signal terminal Reset_P.

[0076] For example, reference Figure 3 As shown, the data writing module 20 may include a second transistor T2 and a fourth transistor T4, the gate of the second transistor T2 is coupled to the second scan signal terminal Gate_N, the first electrode and the second electrode of the second transistor T2 are coupled to the third node N3 and the first node N1 respectively, the gate of the fourth transistor T4 is coupled to the first scan signal terminal Gate_P, and the first electrode and the second electrode of the fourth transistor T4 are coupled to the data signal terminal Data and the second node N2 respectively.

[0077] The first switch module 40 includes a fifth transistor T5 , a gate of the fifth transistor T5 is coupled to the enable signal terminal EM, and a first electrode and a second electrode of the fifth transistor T5 are coupled to the first power terminal VDD and the second node N2 , respectively.

[0078] The driving module 60 may include a third transistor T3 , a gate of the third transistor T3 is coupled to the first node N1 , and a first electrode and a second electrode of the third transistor T3 are coupled to the second node N2 and the third node N3 , respectively.

[0079] The second switch module 70 may include a sixth transistor T6 , a gate of the sixth transistor T6 is coupled to the enable signal terminal EM, and a first electrode and a second electrode of the sixth transistor T6 are coupled to the third node N3 and the fourth node N4 , respectively.

[0080] The first reset module 10 may include a first transistor T1 , a gate of the first transistor T1 is coupled to the first reset signal terminal Reset_P1 , and a first electrode and a second electrode of the first transistor T1 are coupled to the first initial signal terminal and the first node N1 , respectively.

[0081] The second reset module 50 may include a seventh transistor T7 , a gate of the seventh transistor T7 is coupled to the second reset signal terminal Reset_P2 , and a first electrode and a second electrode of the seventh transistor T7 are coupled to the second initial signal terminal and the fourth node N4 , respectively.

[0082] The storage module 30 may include a capacitor Cst.

[0083] Exemplarily, the bias module 80 may include a first bias submodule and a second bias submodule; the first bias submodule is coupled to the first control signal, the first power supply terminal VDD and the fifth node N5, and is configured to provide the signal of the first power supply terminal VDD to the fifth node N5 under the control of the first control signal in the first preset stage; the second bias submodule is coupled to the second control signal, the voltage signal terminal and the fifth node N5, and is configured to provide the signal of the voltage signal terminal to the fifth node N5 under the control of the second control signal, and the voltage signal terminal can provide the reference voltage signal or the bias voltage signal to the fifth node N5 in time periods. The first bias submodule and the second bias submodule can both be connected to the first signal terminal, and the first signal terminal provides the first control signal in the first preset stage, and provides the second control signal in the time period outside the first preset stage.

[0084] Specifically, refer to Figure 3 As shown, the first bias submodule may include an eighth transistor T8, and the second bias submodule may include a ninth transistor T9, one of the eighth transistor T8 and the ninth transistor T9 is a PMOS, and the other is an NMOS.

[0085] Among them, the second transistor T2 and the ninth transistor T9 are oxide TFTs (oxide thin film transistors), and the remaining transistors can be low-temperature polysilicon LTPS transistors. The gates of the eighth transistor T8 and the ninth transistor T9 are connected to the first control sub-signal s1, and one end of the channel of the ninth transistor T9 is directly connected to the driving signal terminal Gate_B of GOA (GOA is the abbreviation of Gate Driven on Array, that is, gate drive integration on the array substrate).

[0086] Exemplarily, the second bias submodule may include a first unit and / or a second unit, and the second control signal includes a first control sub-signal s1 and a second control sub-signal s2;

[0087] The first unit is coupled to the first control sub-signal s1, the reference voltage terminal and the fifth node N5, and is configured to provide a reference voltage signal Vref of the reference voltage terminal to the fifth node N5 under the control of the first control sub-signal s1 in the second preset stage;

[0088] The second unit is coupled to the second control sub-signal s2, the bias voltage terminal and the fifth node N5, and is configured to provide a bias voltage signal Vbias of the bias voltage terminal to the fifth node N5 under the control of the second control sub-signal s2 in the third preset stage.

[0089] Specifically, refer to Figure 4 As shown, the first unit may include a ninth transistor T9, a gate of the ninth transistor T9 is coupled to the first control sub-signal s1, and a first electrode and a second electrode of the ninth transistor T9 are respectively coupled to a reference voltage terminal and a fifth node N5; the second unit may include a tenth transistor T10, a gate of the tenth transistor T10 is coupled to the second control sub-signal s2, and a first electrode and a second electrode of the tenth transistor T10 are respectively coupled to a bias voltage terminal and a fifth node N5.

[0090] When both the first scan signal and the second scan signal provide valid signals, the bias module 80 is configured to provide a reference voltage signal to the fifth node N5 under the control of at least one control signal in the second preset stage.

[0091] The bias module 80 is further configured to provide a bias voltage signal to the fifth node N5 under the control of at least one control signal in a third preset stage, the third preset stage being located after the data writing period in the second preset stage within one light emitting cycle.

[0092] The bias module 80 is further configured to provide a reference voltage signal to the fifth node N5 under the control of at least one control signal during a bias reset period of the second preset stage, which is located after the third preset stage and before the first preset stage.

[0093] Exemplarily, the transistor T2 is an oxide thin-film transistor (full name in English: oxide thin-film transistor, referred to as Oxide TFT), and the remaining transistors may be low temperature polysilicon (Low Temperature Poly-Silicon, referred to as LTPS) transistors.

[0094] The pixel circuit of the embodiment of the present application can bias the gate of the driving transistor in a capacitive coupling manner through a bias module, so that it has a variable refresh rate without adding additional capacitors, which helps to improve the resolution of the display panel.

[0095] Another embodiment of the present application provides a driving method for a pixel circuit, which is applied to the pixel circuit of any embodiment of the present application. The driving method may include:

[0096] S10, in the data writing period, providing corresponding valid signals to the first scan signal terminal Gate_P and the second scan signal terminal Gate_N, so that the signal of the data signal terminal Data is written to the first node N1 through the data writing module 20; and providing the first valid signal to the bias module 80, so that the reference voltage signal is provided to the fifth node N5 through the bias module 80;

[0097] S20, in the bias period, providing a second valid signal to the bias module 80, so that the bias voltage signal is provided to the fifth node N5 through the bias module 80;

[0098] S30, during the bias end period, providing a first valid signal to the bias module 80, so that the reference voltage signal is provided to the fifth node N5 through the bias module 80;

[0099] S40. During the coupling period and the light-emitting period, a third valid signal is provided to the bias module 80, so that the signal of the first power supply terminal VDD is provided to the fifth node N5 through the bias module 80; and during the light-emitting period, a corresponding valid signal is provided to the enable signal terminal EM, so that the fourth node N4 is provided with a driving electrical signal to drive the light-emitting module 90 to emit light.

[0100] Exemplarily, the bias module 80 in the pixel circuit includes a first bias submodule and a second bias submodule, and the first bias submodule and the second bias submodule are both coupled to the first signal terminal. The method includes:

[0101] Providing the first effective signal to the bias module 80 may include: providing an effective signal for the second bias submodule to the first signal terminal, and providing a reference voltage signal to the voltage signal terminal;

[0102] Providing the second effective signal to the bias module 80 may include: providing an effective signal for the second bias submodule to the first signal terminal, and providing a bias voltage signal to the voltage signal terminal;

[0103] Providing the third valid signal to the bias module 80 may include: providing a valid signal for the first bias submodule to the first signal terminal.

[0104] Exemplarily, the bias module 80 in the pixel circuit includes a first bias submodule and a second bias submodule, the second bias submodule includes a first unit and a second unit, and the method includes:

[0105] Providing a first valid signal to the bias module 80 includes: providing a corresponding valid signal to the first control sub-signal s1;

[0106] Providing a second valid signal to the bias module 80 includes: providing a corresponding valid signal to the second control sub-signal s2;

[0107] Providing the third effective signal to the bias module 80 includes: providing a corresponding effective signal to the first control signal.

[0108] Exemplarily, the pixel circuit also includes a first reset module 10 and / or a second reset module 50, and the method may further include: during the reset period, providing a corresponding valid signal to the first reset signal terminal Reset_P1 and / or the second reset signal terminal Reset_P2, and providing a first valid signal to the bias module 80.

[0109] refer to Figure 5 As shown, Figure 5 for Figure 3 The corresponding timing diagram of the pixel circuit, wherein the first preset stage includes the t5 time period and the t6 time period, the second preset stage includes the t1 time period, the t2 time period and the t4 time period, the third preset stage includes the t3 time period, and the first reset signal terminal Reset_P1 and the second reset signal terminal Reset_P2 are the same reset signal terminal Reset_P. Specifically, each time period is described as follows:

[0110] Time period t1: implements the reset process.

[0111] The reset signal terminal Reset_P is at a low level, the second scan signal terminal Gate_N is at a high level, the first control sub-signal s1 is at a low level, the second control sub-signal s2 and the third control sub-signal s3 are at a high level, the eighth transistor T8 / the tenth transistor T10 is turned off, the first transistor T1, the second transistor T2, the seventh transistor T7, and the ninth transistor T9 are turned on, the voltage of the first node N1 / the third node N3 is reset to Vinit1, the voltage of N4 is reset to Vint2, and the voltage of the fifth node N5 is Vref.

[0112] Time period t2: the process of realizing data writing and voltage compensation.

[0113] The first scanning signal terminal Gate_P is at a low level, the second scanning signal terminal Gate_N is at a high level, the first control sub-signal s1 is at a low level, the second control sub-signal s2 and the third control sub-signal s3 are at high levels, the second transistor T2, the third transistor T3, the fourth transistor T4, and the ninth transistor T9 are turned on, the eighth transistor T8 and the tenth transistor T10 are turned off, the voltage of the second node N2 is Vdata, the voltage of the first node N1 is Vdata+Vth, Vth is the compensation voltage, and the voltage of the fifth node N5 is Vref at this time.

[0114] Time period t3: the process of realizing DTFT bias.

[0115] The first control sub-signal s1 and the third control sub-signal s3 are at a high level, the second control sub-signal s2 is at a low level, the eighth transistor T8 and the ninth transistor T9 are turned off, and the tenth transistor T10 is turned on. The voltage of the fifth node N5 changes from Vref to Vbias, the voltage of the first node N1 jumps to Vdata+Vth+(Vbias-Vref) through the capacitor Cst, the voltage of the second node N2 remains at Vdata, and the voltage difference Vgs between the first node N1 and the second node N2 is Vth+(Vbias-Vref), which acts as a bias for the DTFT.

[0116] Time period t4: bias ends.

[0117] The first control sub-signal s1 is at a low level, the second control sub-signal s2 and the third control sub-signal s3 are at a high level, the eighth transistor T8 and the tenth transistor T10 are turned off, and the ninth transistor T9 is turned on. The voltage of the fifth node N5 changes from Vbias to Vref, and the voltage of the first node N1 jumps back to Vdata+Vth and is stabilized by the reference voltage terminal.

[0118] Time period t5: the process of realizing VDD coupling.

[0119] The third control sub-signal s3 is at a low level, the first control sub-signal s1 and the second control sub-signal s2 are at a high level, the eighth transistor T8 is turned on, and the ninth transistor T9 and the tenth transistor T10 are turned off. The voltage of the fifth node N5 changes from Vref to VDD, and the voltage of the first node N1 jumps to

[0120] Vdata+Vth+(VDD-Vref).

[0121] Time period t6: the process of realizing light emission.

[0122] The enable signal terminal EM is at a low level, and the fifth transistor T5 and the sixth transistor T6 are turned on. The voltage of the second node N2 becomes VDD, and at this time, the voltage difference between the first node N1 and the second node N2 is Vgs=VN1-VN2=Vdata+Vth+(VDD-Vref)-VDD=Vdata+Vth-Vref. The current flowing through the third transistor T3 is K*(Vgs-Vth)^2=K*(Vdata-Vref)^2, and the current size has nothing to do with VDD, which can improve the uneven display caused by the uneven current caused by the VDD voltage drop.

[0123] During the frame hold phase, only the reset and bias processes are performed.

[0124] refer to Figure 6 As shown, Figure 6 for Figure 4The timing diagram of the pixel circuit shown in FIG. The first preset stage includes the t5 time period and the t6 time period, the second preset stage includes the t1 time period, the t2 time period and the t4 time period, and the third preset stage includes the t3 time period. The description of each time period in the timing diagram is as follows:

[0125] Time period t1: implements the reset process.

[0126] The reset signal terminal Reset_P is at a low level, the second scan signal terminal Gate_N is at a high level, the first control sub-signal s1 is at a high level, the eighth transistor T8 is turned off, the first transistor T1, the second transistor T2, the seventh transistor T7, and the ninth transistor T9 are turned on, the first node N1 / the third node N3 is reset to Vinit1, the fourth node N4 is reset to Vint2, and the fifth node N5 is VGH (full name: Gate High Voltage) of the drive signal terminal Gate_B.

[0127] Time period t2: the process of data writing and Vth compensation.

[0128] The first scan signal terminal Gate_P is at a low level, the second scan signal terminal Gate_N is at a high level, the first control sub-signal s1 is at a high level, the second transistor T2, the third transistor T3, the fourth transistor T4, and the ninth transistor T9 are turned on, and the eighth transistor T8 is turned off. The voltage of the second node N2 is Vdata, the voltage of the first node N1 is Vdata+Vth, and the voltage of the fifth node N5 is the gate high voltage of the drive signal terminal Gate_B.

[0129] Time period t3: DTFT bias process.

[0130] The first control sub-signal s1 is at a high level, the eighth transistor T8 is turned off, and the ninth transistor T9 is turned on. The voltage of the driving signal terminal Gate_B changes from VGH2 to VGL2, the voltage of the fifth node N5 changes from VGH2 to VGL2, the voltage of the first node N1 jumps to Vdata+Vth+(VGL2-VGH2) through the capacitor Cst, the voltage of the second node N2 remains at Vdata, and the voltage of Vgs is Vth+(VGL2-VGH2) at this time, which acts as a bias for the DTFT.

[0131] Time period t4: bias ends.

[0132] The first control sub-signal s1 is at a high level, the eighth transistor T8 is turned off, and the ninth transistor T9 is turned on. The driving signal terminal Gate_B of GOA changes from VGL2 to VGH2, the voltage of the fifth node N5 changes from VGL2 to VGH2, the voltage of the first node N1 jumps back to Vdata+Vth, and the high level of the driving signal terminal Gate_B of GOA is stabilized.

[0133] Time period t5: the process of realizing VDD coupling.

[0134] The first control sub-signal s1 is at a low level, the eighth transistor T8 is turned on, and the ninth transistor T9 is turned off. The voltage of the fifth node N5 changes from VGH2 of the driving signal terminal Gate_B to VDD, and the voltage of the first node N1 jumps to Vdata+Vth+(VDD-VGH2).

[0135] Time period t6: the process of realizing light emission.

[0136] The enable signal terminal EM is at a low level, and the fifth transistor T5 and the sixth transistor T6 are turned on. The voltage of the second node N2 becomes VDD, and at this time Vgs=VN1-VN2=Vdata+Vth+(VDD-VGH2)-VDD=

[0137] Vdata+Vth-VGH2. The current flowing through the third transistor T3 is

[0138] K*(Vgs-Vth)^2=K*(Vdata-VGH2)^2. The current size has nothing to do with VDD, and can compensate for the uneven display problem caused by uneven current caused by VDD voltage drop.

[0139] During the frame holding stage, only the reset signal terminal Reset_P, the drive signal terminal Gate_B, and the first control sub-signal s1 are turned on, that is, only the reset and bias processes are performed.

[0140] This bias is not limited to the first node N1, but can also be used for the second node N2 and the third node N3.

[0141] In this way, the pixel circuit of the embodiment of the present application can bias the gate of the driving transistor (driving transistor for short DTFT) by capacitive coupling and compensate for the VDD voltage drop.

[0142] The driving method of the pixel circuit of the embodiment of the present application can bias the gate of the driving transistor through a bias module so that it has a variable refresh rate without adding additional capacitors, which helps to improve the resolution of the display panel.

[0143] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

[0144] Those skilled in the art will understand that Figure 3 and Figure 4 The schematic diagram of each module structure can be a simple structure of each module. Those skilled in the art can Figure 3 and Figure 4 The structure of each module in the invention is to add devices to realize the functions of each module. Therefore, the specific structure of each module is not limited to Figure 3 and Figure 4 Any structure shown may be used as long as the function can be achieved.

[0145] Another embodiment of the present application provides a display substrate, including the pixel circuit of any embodiment of the present application. The display substrate of the embodiment of the present application can achieve the same beneficial effects as the pixel circuit of the embodiment of the present application.

[0146] Another embodiment of the present application provides a display device, including the display substrate of any embodiment of the present application. The display substrate of the embodiment of the present application can achieve the same beneficial effects as the pixel circuit of the embodiment of the present application.

[0147] It should be noted that the above embodiments only express the implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A pixel circuit, characterized in that: include: a data writing module coupled to the first scanning signal terminal, the second scanning signal terminal, the data signal terminal, the second node, the third node and the first node, and configured to provide the signal of the data signal terminal to the first node through the second node and the third node under the control of the signal of the first scanning signal terminal and the second scanning signal terminal; a storage module, two ends of which are respectively coupled to the first node and the fifth node, and configured to store the signal of the first node; a bias module coupled to at least one control signal, a first power supply terminal, a reference voltage signal, a bias voltage signal and a fifth node, and configured to provide one of the reference voltage signal, the bias voltage signal and the first power supply terminal signal to the fifth node in time periods under the control of the at least one control signal; The driving module is coupled to the first node, the second node and the third node, and is configured to provide a driving electrical signal to the third node based on the signal of the second node under the control of the signal of the first node.

2. The pixel circuit according to claim 1, characterized in that: The bias module includes a first bias submodule and a second bias submodule; A first bias submodule, coupled to the first control signal, the first power supply terminal and the fifth node, and configured to provide a signal of the first power supply terminal to the fifth node under the control of the first control signal in a first preset stage; The second bias submodule is coupled to the second control signal, the voltage signal terminal and the fifth node, and is configured to provide the signal of the voltage signal terminal to the fifth node under the control of the second control signal, and the voltage signal terminal can provide the reference voltage signal or the bias voltage signal to the fifth node in time periods.

3. The pixel circuit according to claim 2, characterized in that: The first bias submodule and the second bias submodule are both connected to a first signal terminal, and the first signal terminal provides the first control signal in the first preset stage, and provides the second control signal in a period outside the first preset stage.

4. The pixel circuit according to claim 3, characterized in that: The first bias submodule includes an eighth transistor, the second bias submodule includes a ninth transistor, one of the eighth transistor and the ninth transistor is a PMOS, and the other is an NMOS.

5. The pixel circuit according to claim 2, characterized in that: The second bias submodule includes a first unit and a second unit, and the second control signal includes a first control sub-signal and a second control sub-signal; The first unit is coupled to the first control sub-signal, the reference voltage terminal and the fifth node, and is configured to provide the reference voltage signal of the reference voltage terminal to the fifth node under the control of the first control sub-signal in the second preset stage; The second unit is coupled to the second control sub-signal, the bias voltage terminal and the fifth node, and is configured to provide the bias voltage signal of the bias voltage terminal to the fifth node under the control of the second control sub-signal in a third preset stage.

6. The pixel circuit according to claim 5, characterized in that: The second bias submodule includes at least one of the following: The first unit includes a ninth transistor, a gate of the ninth transistor is coupled to the first control sub-signal, and a first electrode and a second electrode of the ninth transistor are coupled to the reference voltage terminal and the fifth node respectively; The second unit includes a tenth transistor, a gate of the tenth transistor is coupled to the second control sub-signal, and a first electrode and a second electrode of the tenth transistor are coupled to the bias voltage terminal and the fifth node respectively.

7. The pixel circuit according to any one of claims 2 to 6, characterized in that: In the case where both the first scan signal and the second scan signal provide valid signals, the bias module is configured to provide the reference voltage signal to the fifth node under the control of the at least one control signal in a second preset stage.

8. The pixel circuit according to claim 7, characterized in that: The bias module is further configured to provide the bias voltage signal to the fifth node under the control of the at least one control signal in a third preset stage, wherein the third preset stage is located after a data writing period in the second preset stage within a light emitting cycle.

9. The pixel circuit according to claim 8, characterized in that: The bias module is further configured to provide the reference voltage signal to the fifth node under the control of the at least one control signal during a bias reset period of the second preset stage, wherein the bias reset period is located after the third preset stage and before the first preset stage.

10. The pixel circuit according to any one of claims 1 to 6, characterized in that: The pixel circuit further includes: A first switch module is coupled to the enable signal terminal, the first power terminal and the second node, and is configured to provide a signal from the first power terminal to the second node under the control of a signal from the enable signal terminal; The second switch module is coupled to the enable signal terminal, the third node and the fourth node, and is configured to provide the driving electrical signal of the third node to the fourth node under the signal control of the enable signal terminal to drive the light-emitting module to emit light.

11. The pixel circuit according to any one of claims 1 to 6, characterized in that: The pixel circuit further includes: A first reset module, coupled to the first reset signal terminal, the first initial signal terminal and the third node, and configured to provide the signal of the first initial signal terminal to the third node under the control of the signal of the first reset signal terminal; A second reset module, coupled to the second reset signal terminal, the second initial signal terminal and the fourth node, and configured to provide the signal of the second initial signal terminal to the fourth node under the control of the signal of the second reset signal terminal; The bias module is further configured to provide the reference voltage signal to the fifth node under the control of the at least one control signal when the first reset signal terminal and / or the second reset signal terminal provides a valid signal.

12. The pixel circuit according to claim 11, characterized in that: Satisfy at least one of the following: The data writing module includes a second transistor and a fourth transistor, the gate of the second transistor is coupled to the second scanning signal terminal, the first electrode and the second electrode of the second transistor are respectively coupled to the third node and the first node, the gate of the fourth transistor is coupled to the first scanning signal terminal, and the first electrode and the second electrode of the fourth transistor are respectively coupled to the data signal terminal and the second node; The first switch module includes a fifth transistor, a gate of the fifth transistor is coupled to the enable signal terminal, and a first electrode and a second electrode of the fifth transistor are coupled to the first power supply terminal and the second node respectively; The driving module comprises a third transistor, a gate of the third transistor is coupled to the first node, and a first electrode and a second electrode of the third transistor are coupled to the second node and the third node respectively; The second switch module includes a sixth transistor, a gate of the sixth transistor is coupled to the enable signal terminal, and a first electrode and a second electrode of the sixth transistor are coupled to the third node and the fourth node respectively; The first reset module comprises a first transistor, a gate of the first transistor is coupled to the first reset signal terminal, and a first electrode and a second electrode of the first transistor are respectively coupled to the first initial signal terminal and the first node; The second reset module includes a seventh transistor, a gate of the seventh transistor is coupled to the second reset signal terminal, and a first electrode and a second electrode of the seventh transistor are coupled to the second initial signal terminal and the fourth node, respectively.

13. A method for driving a pixel circuit, characterized in that: The pixel circuit according to any one of claims 1 to 12, wherein the driving method comprises: In a data writing period, providing corresponding valid signals to both the first scanning signal terminal and the second scanning signal terminal, so that the signal of the data signal terminal is written into the first node through the data writing module; and providing a first valid signal to the bias module, so that the reference voltage signal is provided to the fifth node through the bias module; In a bias period, providing a second valid signal to the bias module, so that the bias voltage signal is provided to the fifth node through the bias module; During the bias end period, providing a first valid signal to the bias module, so that the reference voltage signal is provided to the fifth node through the bias module; During the coupling period and the light-emitting period, a third effective signal is provided to the bias module, so that the signal at the first power supply terminal is provided to the fifth node through the bias module; and during the light-emitting period, a corresponding effective signal is provided to the enable signal terminal, so that the fourth node is provided with a driving electrical signal to drive the light-emitting module to emit light.

14. A display substrate, characterized in that: The method comprises a pixel circuit as claimed in any one of claims 1 to 12.

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