Semiconductor device and preparation method thereof

Abstract

The invention relates to a semiconductor device and a preparation method thereof. The preparation method comprises the steps that a pseudo gate structure is formed on a substrate, and the pseudo gate structure comprises a pseudo gate electrode and a protective dielectric layer covering the pseudo gate electrode; forming a first interlayer dielectric layer on the substrate and the dummy gate structure, the first interlayer dielectric layer covering the substrate and the dummy gate structure; executing a first grinding process to remove a part of the first interlayer dielectric layer so as to expose the protective dielectric layer; forming a buffer layer on the first interlayer dielectric layer and the protective dielectric layer; and performing a second grinding process to remove at least a portion of the buffer layer and the protective dielectric layer to expose the dummy gate electrode. The hardness of the buffer layer is greater than that of the first interlayer dielectric layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In the manufacturing process of advanced logic chips using a gate-last process, a grinding process is usually used to remove the first interlayer dielectric layer. The first interlayer dielectric layer may have a significant dishing problem during the grinding process, resulting in uneven grinding, especially in the formation of depressions in local areas, also known as dishing depressions. These depressions may damage the gate structure and cause gate metal residues.

[0003] In order to prevent this gate metal residue phenomenon, it is often necessary to use over-etching in the planarization process of the gate metal to extend the etching time and eliminate the gate metal residue, which will lead to a reduction in the height of the gate structure and affect the performance of the semiconductor device.

[0004] Therefore, how to effectively control the influence of the discing problem on the gate structure has become an urgent problem to be solved in related fields. Summary of the invention

[0005] The present application provides a semiconductor device and a method for preparing the same, so as to reduce the influence of the dishing phenomenon and avoid over-etching, thereby improving the performance and yield of the semiconductor device.

[0006] To achieve the above technical objectives, the first aspect of the present application provides a method for preparing a semiconductor device. The preparation method includes: forming a dummy gate structure on a substrate, the dummy gate structure including a dummy gate electrode and a protective dielectric layer covering the dummy gate electrode; forming a first interlayer dielectric layer on the substrate and the dummy gate structure, the first interlayer dielectric layer covering the substrate and the dummy gate structure; performing a first grinding process to remove part of the first interlayer dielectric layer to expose the protective dielectric layer; forming a buffer layer on the first interlayer dielectric layer and the protective dielectric layer; and performing a second grinding process to remove at least a portion of the buffer layer and the protective dielectric layer to expose the dummy gate electrode. The hardness of the buffer layer is greater than the hardness of the first interlayer dielectric layer.

[0007] To achieve the above technical objectives, the second aspect of the present application provides a semiconductor device. The semiconductor device includes: a substrate, a gate structure, a first interlayer dielectric layer and a buffer layer. The gate structure is located on the substrate. The first interlayer dielectric layer is located on the substrate and is adjacent to the gate structure. The first interlayer dielectric layer is formed with a dish-shaped recess. The buffer layer is filled in the dish-shaped recess. The hardness of the buffer layer is greater than the hardness of the first interlayer dielectric layer.

[0008] In the present application, a novel method for preparing a semiconductor device is provided. In the preparation method, after performing a first grinding process to remove a portion of the first interlayer dielectric layer to expose the protective dielectric layer, a buffer layer is formed on the first interlayer dielectric layer and the protective dielectric layer, and the hardness of the buffer layer is greater than the hardness of the first interlayer dielectric layer. Subsequently, a second grinding process is performed to remove at least a portion of the buffer layer and the protective dielectric layer to expose the pseudo gate electrode. In the preparation method, the first grinding process can form a dish-shaped depression. By forming a buffer layer after the first grinding process, the depth of continuous grinding of the first interlayer dielectric layer can be reduced, and the dish-shaped depression caused by the dishing phenomenon can be avoided from damaging the pseudo gate structure. The material of the buffer layer can also fill the current dish-shaped depression to avoid further deepening of the current dish-shaped depression. Further, by introducing a buffer layer with greater hardness above the protective dielectric layer, the possibility of the appearance and deepening of the dish-shaped depression in the subsequent grinding process can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present application will illustrate the implementation methods in conjunction with the accompanying drawings. The accompanying drawings of the present application are only used to describe the embodiments for the purpose of demonstration. Without departing from the principles of the present application, those skilled in the art can easily make other embodiments according to the steps described below through the following description.

[0010] Figure 1 is a flow chart of a method for preparing a semiconductor device according to some embodiments of the present application;

[0011] Figure 2 is a flow chart of a method for preparing a semiconductor device according to other embodiments of the present application;

[0012] Figure 3 is a first structural schematic diagram of a semiconductor device during preparation according to some embodiments of the present application;

[0013] Figure 4 is a second structural schematic diagram of a semiconductor device during preparation according to some embodiments of the present application;

[0014] Figure 5 is a third structural schematic diagram of a semiconductor device during preparation according to some embodiments of the present application;

[0015] Figure 6 is a fourth structural schematic diagram of a semiconductor device during preparation according to some embodiments of the present application;

[0016] Figure 7 is a fifth structural schematic diagram of a semiconductor device during preparation according to some embodiments of the present application;

[0017] Figure 8 is a sixth structural schematic diagram of a semiconductor device during preparation according to some embodiments of the present application;

[0018] Fig. 9 is a seventh structural schematic diagram of a semiconductor device during preparation according to some embodiments of the present application;

[0019] Fig.10 This is the eighth structural schematic diagram of the preparation process of the semiconductor device according to some embodiments of the present application. DETAILED DESCRIPTION

[0020] The scheme of the embodiment of the present application is described in detail below in conjunction with the drawings of the specification.

[0021] In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures, interfaces, and technologies are provided to facilitate a thorough understanding of the present application.

[0022] The term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship. In addition, "many" in this article means two or more than two.

[0023] The terms "first", "second", and "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second", and "third" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise specified in some embodiments. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products, or devices.

[0024] refer to Figure 1 , Figure 1 is a flow chart of a method for preparing a semiconductor device according to some embodiments of the present application.

[0025] In some embodiments, the semiconductor device of the present application may be an integrated circuit or a part of an integrated circuit, including a memory, a logic device, etc. The semiconductor device may also be a power device, etc., which is not specifically limited in the present application.

[0026] In some embodiments, the preparation method of the present application can be applied to a gate-last process. In the process of preparing a semiconductor device using the gate-last process, a dummy gate structure can be first formed, and then the dummy gate electrode in the dummy gate structure can be removed and replaced with a metal gate.

[0027] like Figure 1 As shown, the preparation method of the present application includes the following operations.

[0028] Operation S11: forming a dummy gate structure on a substrate. The dummy gate structure includes a dummy gate electrode and a protective dielectric layer covering the dummy gate electrode.

[0029] refer to Figure 3 , Figure 3 It is a first structural schematic diagram of a semiconductor device 1 during the preparation process according to some embodiments of the present application.

[0030] In some embodiments, the substrate 10 may be, for example, a semiconductor substrate. The substrate 10 may be made of a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, other III / V or II / VI compound semiconductors, or may include a layered substrate such as Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator, which is not limited in the present application.

[0031] In some embodiments, the substrate 10 may include different types of doped well regions (not shown), such as a P-type well region or an N-type well region. The P-type well region is formed by P-type doping, and the N-type well region is formed by N-type doping.

[0032] In P-type doping, a P-type doping element (also called an acceptor impurity) is introduced into a semiconductor material, so that holes are the majority carriers in the doped semiconductor material, and the semiconductor material exhibits a P-type conductive characteristic. Examples of acceptor impurities are boron (B) and gallium (Ga). In N-type doping, an N-type doping element (also called a donor impurity) is introduced into a semiconductor material, so that electrons are the majority carriers in the doped semiconductor material, and the semiconductor material exhibits an N-type conductive characteristic. Examples of donor impurities are phosphorus (P) and arsenic (As).

[0033] like Figure 3As shown, the dummy gate structure 20 includes a dummy gate electrode 220 and a protective dielectric layer 240 covering the dummy gate electrode 220. The protective dielectric layer 240 may be disposed on the dummy gate electrode 220. The protective dielectric layer 240 may include any suitable material and / or thickness. The protective dielectric layer 240 may include silicon nitride, silicon oxynitride, other suitable nitrogen-containing materials and / or a combination of the above. The protective dielectric layer 240 may be formed to an appropriate thickness by any suitable process. For example, the protective dielectric layer 240 may be formed by a deposition process. The deposition process may, for example, include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma chemical vapor deposition (HPCVD), metal organic chemical vapor deposition (MOCVD), remote plasma chemical vapor deposition (RPCVD), plasma enhanced chemical vapor deposition (PECVD), electroplating, other suitable methods and / or a combination of the above methods.

[0034] In some embodiments, the dummy gate electrode 220 may include a material with a high etching selectivity ratio, such as a polysilicon material, so that the dummy gate electrode 220 can be removed in a subsequent process.

[0035] like Figure 3 As shown, the dummy gate structure 20 may further include a gate insulating layer 210. The gate insulating layer 210 is located between the dummy gate electrode 220 and the substrate 10. The gate insulating layer 210 is used to isolate the dummy gate electrode 220 from the substrate 10. The gate insulating layer 210 may be formed of, for example, silicon oxide, silicon oxynitride, a high-κ dielectric, or other insulating materials.

[0036] like Figure 3 As shown, the pseudo gate structure 20 also includes a sidewall 250 (spacer). The sidewall 250 may include one or more layers of walls. The sidewall 250 includes one or more dielectric layers on both sides of the pseudo gate electrode 220, such as an ONO (Oxide-Nitride-Oxide, such as silicon oxide-silicon nitride-silicon oxide) structure. During the preparation process of the semiconductor device 1, the sidewall 250 can isolate and protect the pseudo gate electrode 220, and this application will not repeat it.

[0037] In some embodiments, the process of forming the dummy gate structure 20 on the substrate 10 may include: forming a gate insulating layer 210 on the substrate 10; forming a dummy gate electrode 220 on the substrate 10 and / or the gate insulating layer 210; preparing a spacer 250; and depositing a protective dielectric layer 240 on the dummy gate structure 20. The protective dielectric layer 240 is, for example, a SiN layer.

[0038] In some embodiments, after forming the dummy gate structure 20, a source region and a drain region may be formed in the substrate 10 by doping. The doping process may be formed, for example, by one or more ion implantation processes, photolithography, diffusion and / or other suitable processes. The specific doping process may be determined according to the requirements, and the present application does not limit the doping method and type.

[0039] Operation S12: forming a first interlayer dielectric layer 30 on the substrate 10 and the dummy gate structure 20. The first interlayer dielectric layer 30 covers the substrate 10 and the dummy gate structure 20.

[0040] refer to Figure 3 , a first interlayer dielectric layer 30 is formed on the substrate 10 and the dummy gate structure 20 by a deposition process. The deposition process may include, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma chemical vapor deposition (HPCVD), metal organic chemical vapor deposition (MOCVD), remote plasma chemical vapor deposition (RPCVD), plasma enhanced chemical vapor deposition (PECVD), electroplating, other suitable methods and / or a combination of the above methods, and the present application does not make specific limitations on this.

[0041] In some embodiments, the first interlayer dielectric layer 30 may include, for example, a silicon oxide material. In the case where there are a plurality of dummy gate structures 20 , the first interlayer dielectric layer 30 may fill the gaps between the plurality of dummy gate structures 20 .

[0042] In some embodiments, the height of the first interlayer dielectric layer 30 may be set so as to cover the entire dummy gate structure 20 .

[0043] As an example but not limitation, the first interlayer dielectric layer 30 may be, for example, an oxide layer deposited by a high aspect ratio (HARP) process, with a height of 2500 angstroms.

[0044] Operation S13 : performing a first grinding process to remove a portion of the first interlayer dielectric layer 30 to expose the protective dielectric layer 240 .

[0045] refer to Figure 4 , Figure 4 1 is a second structural schematic diagram of a semiconductor device 1 during preparation according to some embodiments of the present application. Specifically, Figure 4 FIG. 4 is a schematic structural diagram of the semiconductor device 1 after the first grinding process.

[0046] In some embodiments, the first grinding process is chemical mechanical grinding. The first grinding process can also be other grinding processes, which are not specifically limited in the present application.

[0047] Chemical-mechanical polishing (CMP), also known as chemical-mechanical planarization (CMP), is a technology used in the manufacturing process of semiconductor devices 1, which uses chemical corrosion and mechanical force to planarize the material during processing.

[0048] In some embodiments, the abrasive of the chemical mechanical polishing can react with the material of the first interlayer dielectric layer 30, thereby effectively reducing the hardness and mechanical strength of the material of the first interlayer dielectric layer 30, and then removing at least a portion of the first interlayer dielectric layer 30 under the action of mechanical force to expose the protective dielectric layer 240. In other words, the first polishing process uses the protective dielectric layer 240 as a stop layer.

[0049] like Figure 4 As shown, after the first grinding process, a dished depression 32 can be formed on the remaining first interlayer dielectric layer 30. In the related art, the dished depression 32 often damages the dummy gate structure 20. In the present application, by using the protective dielectric layer 240 as a stop layer for the first grinding process and then forming a buffer layer 40 as described below, further deepening of the dished depression 32 can be avoided, thereby avoiding damage to the dummy gate structure 20 by the dished depression 32.

[0050] Operation S14 : forming a buffer layer 40 on the first interlayer dielectric layer 30 and the protective dielectric layer 240 .

[0051] refer to Figure 6 , Figure 6 1 is a fourth structural schematic diagram of a semiconductor device 1 during preparation according to some embodiments of the present application. Specifically, Figure 6 FIG. 4 is a schematic structural diagram of the semiconductor device 1 after the buffer layer 40 is formed.

[0052] In some embodiments, the hardness of the buffer layer 40 is greater than the hardness of the first interlayer dielectric layer 30. The buffer layer 40 can fill the dish-shaped depression 32 on the current first interlayer dielectric layer 30. The buffer layer 40 has a greater hardness, which can reduce the possibility of the dish-shaped depression 32, prevent the current dish-shaped depression 32 from further deepening, and thus prevent the dishing phenomenon from damaging the dummy gate structure 20. In addition, since damage to the dummy gate structure 20 is avoided, the preparation method does not need to use over-etching, thereby allowing the height of the dummy gate structure 20 to be reduced, making the entire preparation process easier to control, reducing the preparation cost of the semiconductor device 1, and improving the yield of the semiconductor device 1.

[0053] In some embodiments, the protective dielectric layer 240 and the buffer layer 40 are made of the same material, and the same material is SiN. In this case, operation S14 includes: depositing SiN material on the first interlayer dielectric layer 30 and the protective dielectric layer 240 to form the buffer layer 40. The deposition and removal process of SiN material is mature, which can reduce the preparation cost of the semiconductor device 1.

[0054] In some embodiments, the buffer layer 40 may be planarized. The planarization process may be performed, for example, by a grinding process, which is not specifically limited in the present application.

[0055] Operation S15 : performing a second grinding process to remove at least a portion of the buffer layer 40 and the protective dielectric layer 240 to expose the dummy gate electrode 220 .

[0056] refer to Figure 7 , Figure 7 1 is a fifth structural diagram of a semiconductor device 1 during the preparation process according to some embodiments of the present application. Specifically, Figure 7 FIG. 4 is a schematic diagram showing the structure of the semiconductor device 1 after the second grinding process.

[0057] In some embodiments, the second polishing process may be a chemical mechanical polishing process as described above.

[0058] In some embodiments, a second grinding process may be performed to sequentially remove the buffer layer 40 and the protective dielectric layer 240 above the dummy gate structure 20 to open or expose the dummy gate electrode 220. In other words, the second grinding process uses the dummy gate electrode 220 as a stop layer.

[0059] As mentioned above, the buffer layer 40 and / or the protective dielectric layer 240 may be made of SiN material. SiN material has a high hardness and is not prone to discing during the grinding process.

[0060] Operation S16: removing the dummy gate electrode 220 to define a gate cavity, and forming a metal gate 230 in the gate cavity.

[0061] refer to Figure 8 and Fig. 9 , Figure 8 is a sixth structural schematic diagram of a semiconductor device 1 during preparation according to some embodiments of the present application, Fig. 9 1 is a seventh structural diagram of a semiconductor device 1 during the preparation process according to some embodiments of the present application. Specifically, Figure 8 FIG. 1 is a schematic diagram showing the structure of the semiconductor device 1 after the dummy gate electrode 220 is removed. Fig. 9 FIG. 1 is a schematic structural diagram of the semiconductor device 1 after a metal gate 230 is formed in the gate cavity 260 .

[0062] In some embodiments, a high selectivity etching process may be performed to remove the dummy gate electrode 220 , such as a polysilicon layer, in the dummy gate structure 20 , thereby generating a corresponding gate cavity 260 .

[0063] In some embodiments, forming the metal gate 230 in the gate cavity 260 includes depositing a metal gate material in the gate cavity 260 to form the metal gate 230. For example, TaN, TiN, TaN, and TiN / Ti / Al multilayer materials may be sequentially deposited in the gate cavity 260 to form the metal gate 230. Other metal materials may also be deposited in the gate cavity 260, and the present application is not limited thereto. Among them, Ti may be deposited, for example, by a physical vapor deposition (PVD) process.

[0064] In some embodiments, the metal gate 230 may be grown using an atomic layer deposition (ALD) method.

[0065] In some embodiments, the deposited metal gate 230 may be planarized to remove excess metal gate 230 to form a gate structure 22. Fig.10 , Fig.10 1 is an eighth structural schematic diagram of a semiconductor device 1 during preparation according to some embodiments of the present application. Specifically, Fig.10 FIG. 2 shows a schematic structural diagram of the semiconductor device 1 after the metal gate 230 is planarized. Fig.10 As shown, after the metal gate 230 is planarized, some portions of the buffer layer 40 may be included on the first interlayer dielectric layer 30 . The gate structure 22 may include a gate insulating layer 210 , a metal gate 230 , and a spacer 250 .

[0066] In some embodiments, after the gate structure 22 is formed in the gate-last process, the manufacturing method of the present application may further include: forming a second interlayer dielectric layer covering the gate structure 22. The second dielectric layer may include silicon oxide, for example.

[0067] In some embodiments, the present application may also form a contact window in the second dielectric layer, and fill the contact window with metal to form a contact window metal or a contact hole, thereby connecting the corresponding part of the semiconductor device 1 to the electrical interconnection structure.

[0068] The first grinding process may form a dish-shaped depression 32 due to the dishing phenomenon. In the preparation method of the present application, by forming a buffer layer 40 after the first grinding process, the depth of continuous grinding of the first interlayer dielectric layer 30 can be reduced, and the dish-shaped depression 32 caused by the dishing phenomenon can be prevented from damaging the dummy gate structure 20. The material of the buffer layer 40 can also fill the current dish-shaped depression 32.

[0069] Furthermore, by introducing a buffer layer 40 with a greater hardness above the protective medium layer 240 , the possibility of the dished depression 32 appearing and deepening in the subsequent grinding process can be reduced.

[0070] In addition, since the dishing phenomenon is avoided to damage the pseudo gate structure 20, the preparation method does not need to use over-etching, thereby allowing the height of the pseudo gate structure 20 to be reduced, making the entire preparation process easier to control, reducing the preparation cost of the semiconductor device 1, and improving the yield of the semiconductor device 1.

[0071] refer to Figure 2 , Figure 2 FIG. 1 is a flow chart showing a method for preparing a semiconductor device 1 according to another embodiment of the present application. Figure 2 As shown, the preparation method of the present application may include the following steps.

[0072] Operation S21 : forming a dummy gate structure 20 on the substrate 10 . The dummy gate structure 20 includes a dummy gate electrode 220 and a protective dielectric layer 240 covering the dummy gate electrode 220 .

[0073] The operation of operation S21 is substantially similar to that of operation S11 and will not be described in detail herein.

[0074] Operation S22: forming a first interlayer dielectric layer 30 on the substrate 10 and the dummy gate structure 20. The first interlayer dielectric layer 30 covers the substrate 10 and the dummy gate structure 20.

[0075] The operation of operation S22 is substantially similar to that of operation S12 and will not be described in detail herein.

[0076] Operation S23 : performing a first grinding process to remove a portion of the first interlayer dielectric layer 30 to expose the protective dielectric layer 240 .

[0077] The operation of operation S23 is substantially similar to that of operation S13 and will not be described in detail herein.

[0078] Operation S24 : performing a third grinding process to remove a portion of the protective medium layer 240 .

[0079] refer to Figure 5 , Figure 5 1 is a third structural schematic diagram of a semiconductor device 1 during preparation according to some embodiments of the present application. Specifically, Figure 5 FIG. 4 is a schematic diagram showing the structure of the semiconductor device 1 after the third grinding process.

[0080] In some embodiments, the third grinding process is performed to remove a portion of the protective dielectric layer 240 , thereby shortening the speed of exposing or opening the dummy gate electrode 220 in subsequent processes.

[0081] In some embodiments, the third polishing process may be, for example, the chemical mechanical polishing process described above, and the first polishing process may also be other polishing processes, which is not specifically limited in the present application.

[0082] In some embodiments, the third grinding process is performed for a preset time length or a fixed time length. That is, the user can set the execution time length of the third grinding process to a fixed value without adjusting the execution time length of the third grinding process according to the grinding progress or other signals.

[0083] Operation S25 : forming a buffer layer 40 on the first interlayer dielectric layer 30 and the protective dielectric layer 240 .

[0084] The operation of operation S25 is substantially similar to that of operation S14 and will not be described in detail herein.

[0085] Operation S26 : performing a second grinding process to remove at least a portion of the buffer layer 40 and the protective dielectric layer 240 to expose the dummy gate electrode 220 .

[0086] The operation of operation S26 is substantially similar to that of operation S15 and will not be described in detail herein.

[0087] Operation S27 : removing the dummy gate electrode 220 to define a gate cavity 260 , and forming a metal gate 230 in the gate cavity 260 .

[0088] The operation of operation S27 is substantially similar to that of operation S16 and will not be described in detail herein.

[0089] The present application also provides a semiconductor device 1 manufactured using the above manufacturing method.

[0090] like Fig.10 As shown, the semiconductor device 1 includes: a substrate 10, a gate structure, a first interlayer dielectric layer 30 and a buffer layer 40. Specifically, the gate structure is located on the substrate 10. The first interlayer dielectric layer 30 is located on the substrate 10 and is adjacent to the gate structure, and the first interlayer dielectric layer 30 is formed with a dish-shaped recess 32. The buffer layer 40 is filled in the dish-shaped recess 32. The dish-shaped recess 32 can be formed by performing a first grinding process on the first interlayer dielectric layer 30. That is, the dish-shaped recess 32 is generated by a dishing phenomenon when the first interlayer dielectric layer 30 is subjected to the first grinding process.

[0091] In some embodiments, the buffer layer 40 includes SiN material.

[0092] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: forming a dummy gate structure on the substrate, wherein the dummy gate structure comprises a dummy gate electrode and a protective dielectric layer covering the dummy gate electrode; forming a first interlayer dielectric layer on the substrate and the dummy gate structure, wherein the first interlayer dielectric layer covers the substrate and the dummy gate structure; Performing a first grinding process to remove a portion of the first interlayer dielectric layer to expose the protective dielectric layer; forming a buffer layer on the first interlayer dielectric layer and the protective dielectric layer; and performing a second grinding process to remove at least a portion of the buffer layer and the protective dielectric layer to expose the dummy gate electrode, Wherein, the hardness of the buffer layer is greater than the hardness of the first interlayer dielectric layer.

2. The preparation method according to claim 1, characterized in that: The protective dielectric layer and the buffer layer are made of the same material, and the material is SiN.

3. The preparation method according to claim 2, characterized in that: Before forming a buffer layer on the first interlayer dielectric layer and the protective dielectric layer, the preparation method further includes: performing a third grinding process to remove a portion of the protective dielectric layer; The forming of a buffer layer on the first interlayer dielectric layer and the protective dielectric layer comprises: The SiN is deposited on the first interlayer dielectric layer and the protective dielectric layer to form the buffer layer.

4. The preparation method according to claim 3, characterized in that: The performing the third grinding process to remove at least a portion of the protective dielectric layer comprises: The third grinding process is performed for a preset time length.

5. The preparation method according to claim 3, characterized in that: The forming of a buffer layer on the first interlayer dielectric layer and the protective dielectric layer further comprises: The buffer layer is planarized.

6. The preparation method according to claim 5, characterized in that: The first polishing process, the second polishing process and the third polishing process are all chemical mechanical polishing processes.

7. The preparation method according to claim 1, characterized in that: Also includes: removing the dummy gate electrode to define a gate cavity; as well as A metal gate is formed in the gate cavity.

8. The preparation method according to claim 7, characterized in that: The forming of a metal gate in the gate cavity comprises: TaN, TiN, TaN, TiN / Ti / Al are sequentially deposited in the gate cavity to form a metal gate.

9. The preparation method according to claim 1, characterized in that: Before forming the first interlayer dielectric layer on the substrate and the dummy gate structure, the method further includes: A source region and a drain region are formed in the substrate by doping.

10. The preparation method according to claim 1, characterized in that: The pseudo gate structure also includes a gate insulating layer and a sidewall. The gate insulating layer is located between the dummy gate electrode and the substrate. The sidewall spacer surrounds the dummy gate electrode and the protective dielectric layer.

11. A semiconductor device, characterized in that: include: substrate; A gate structure, located on the substrate; A first interlayer dielectric layer, located on the substrate and adjacent to the gate structure, wherein the first interlayer dielectric layer is formed with a dish-shaped recess; as well as A buffer layer is filled in the dish-shaped depression, Wherein, the hardness of the buffer layer is greater than the hardness of the first interlayer dielectric layer.

12. The semiconductor device according to claim 11, characterized in that The buffer layer includes SiN material.

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