Packaging substrate structure and preparation method thereof

Abstract

The invention provides a package substrate structure and a preparation method thereof. The preparation method comprises the following steps: respectively arranging pattern conductive layers on the upper surface and the lower surface of a core plate layer, arranging a medium adding layer on the pattern conductive layers, arranging a silicon-based middle adding layer on the medium adding layer, and arranging patterned solder mask layers on the upper surface and the lower surface of the formed structure to lead out conductive connection. The silicon-based middle layer is arranged on the medium adding layer of the packaging substrate, the warping problem of the packaging substrate is reduced by utilizing the high flatness and low ductility of the silicon-based middle layer on the medium adding layer, and the plate surface flatness of the packaging substrate is improved; meanwhile, the dielectric constant and the dielectric loss factor of the silicon-based intermediate layer are relatively low, so that the performance of the packaging substrate can be improved; in addition, through the characteristic that a finer circuit can be manufactured through the silicon-based middle layer, a packaging substrate structure integrated with higher density is achieved. And finally, the performance of the packaging substrate is further improved by wrapping the middle conductive layer with the two silicon-based middle layers.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuit manufacturing, and in particular relates to a packaging substrate structure and a preparation method thereof. Background Art

[0002] With the rapid development of semiconductor industry technology, the number of input and output pins (I / O) on chips has increased. As the connecting bridge between chips and printed circuit boards, the packaging substrate has higher and higher requirements for line precision, which puts forward more stringent requirements for the preparation of packaging substrates. Traditional packaging substrates are no longer sufficient. In addition, heterogeneous integration applications are becoming more and more widespread. Multiple chips are embedded on the packaging substrate at the same time to form 2.5D or 3D multi-chip packaging. This technology also requires a smaller wiring density and higher integration of the packaging substrate. At the same time, heterogeneous integration technology also further increases the manufacturing cost of the packaging substrate.

[0003] In the prior art, a silicon-based intermediate layer is usually embedded in a packaging substrate to improve the wiring density of the packaging substrate. However, the process of setting a groove to embed the silicon-based intermediate layer is prone to cause warping problems of the packaging substrate. At the same time, the process flow is also relatively complicated and the cost is high.

[0004] Therefore, there is an urgent need for a packaging substrate structure and a preparation method that can achieve high-precision circuits while avoiding warping problems and reducing process costs.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology part of the present application. Summary of the invention

[0006] In view of the above shortcomings of the prior art, an object of the present invention is to provide a packaging substrate structure and a preparation method thereof, so as to solve the warping problem of the packaging substrate in the prior art.

[0007] To achieve the above object, the present invention provides a method for preparing a packaging substrate structure, the method comprising:

[0008] Providing a core board, the core board comprising an upper surface and a lower surface arranged opposite to each other, the upper surface and the lower surface are both provided with a first conductive layer, the core board and the first conductive layer constitute a core board layer;

[0009] A through groove is provided in the core plate layer;

[0010] The surface of the core plate layer exposed after the through grooves are provided is covered with a first seed conductive layer, and the surface of the first seed conductive layer is covered with a second conductive layer;

[0011] Filling the through groove with a filling layer, wherein the filling layer fills the gap of the second conductive layer in the through groove and covers the surface of the second conductive layer;

[0012] Disposing a third conductive layer on the surface of the filling layer;

[0013] Disposing a patterned first mask layer on the surface of the third conductive layer to expose a portion of the third conductive layer below;

[0014] Etching the exposed third conductive layer and the filling layer, the second conductive layer, the first seed conductive layer and the first conductive layer below the third conductive layer to expose a portion of the core board;

[0015] Removing the first mask layer to expose the third conductive layer thereunder, and a pattern conductive layer formed by the third conductive layer, the filling layer, the second conductive layer, the first seed conductive layer and the first conductive layer;

[0016] A substrate dielectric layer is provided on the surface of the third conductive layer, wherein the substrate dielectric layer fills the gaps in the etched pattern conductive layer and covers the surface thereof;

[0017] Disposing a dielectric build-up layer on the surface of the substrate dielectric layer;

[0018] Disposing a silicon-based intermediate layer build-up layer on the dielectric build-up layer;

[0019] A patterned outer plating layer is provided on both the upper surface and the lower surface of the package substrate structure thus formed, and the outer plating layer forms a conductive connection portion with a portion of the package substrate structure thus formed that is intended to be conductively connected;

[0020] A patterned solder resist layer is covered on the outer plating layer, and the solder resist layer fills the gaps between the patterned outer plating layers and exposes the conductive connection parts preset by the outer plating layers.

[0021] Optionally, the method for preparing the dielectric build-up layer includes:

[0022] A first blind hole is provided in the substrate dielectric layer to expose a portion of the third conductive layer that is preset to be conductively connected;

[0023] A second seed conductive layer is disposed on the substrate dielectric layer behind the first blind hole, wherein the second seed conductive layer covers the substrate dielectric layer and the exposed third conductive layer;

[0024] Disposing a patterned second mask layer on the second conductive seed layer;

[0025] Filling the gaps between the patterned second mask layers with a build-up conductive layer;

[0026] Removing the second mask layer and the second seed conductive layer exposed under the second mask layer to expose a portion of the substrate dielectric layer, thereby obtaining the patterned build-up conductive layer and the patterned second seed conductive layer;

[0027] A build-up dielectric layer is filled in the gap between the patterned build-up conductive layer and the second seed conductive layer, thereby obtaining a layer of the dielectric build-up layer.

[0028] Optionally, the method for preparing the silicon-based intermediate layer build-up layer comprises:

[0029] A silicon-based intermediate layer is provided on the surface of the dielectric build-up layer, and a second blind hole is provided to penetrate the silicon-based intermediate layer and the uppermost build-up dielectric layer of the dielectric build-up layer to expose a portion of the dielectric build-up layer that is preset to be electrically connected;

[0030] Disposing a third seed conductive layer on the surface of the silicon-based intermediate layer, wherein the third seed conductive layer covers the silicon-based intermediate layer and the surface exposed by the second blind hole;

[0031] Disposing a patterned third mask layer on the surface of the third conductive seed layer;

[0032] Filling the gaps between the patterned third mask layers with an intermediate conductive layer;

[0033] Removing the third mask layer and the third seed conductive layer exposed under the third mask layer to expose a portion of the silicon-based intermediate layer, thereby obtaining the patterned intermediate conductive layer and the patterned third seed conductive layer;

[0034] An intermediate dielectric layer is covered on the patterned intermediate conductive layer and the third seed conductive layer, and the intermediate dielectric layer fills the gap between the patterned intermediate conductive layer and the third seed conductive layer, thereby obtaining a layer of the silicon-based intermediate layer build-up layer.

[0035] Optionally, after removing the third mask layer and the third seed conductive layer exposed under the third mask layer, a silicon-based intermediate layer is further covered on the exposed third seed conductive layer, the intermediate conductive layer and the silicon-based intermediate layer, and then the intermediate dielectric layer is covered.

[0036] Optionally, the dielectric build-up layer is repeatedly provided multiple times to form a multi-layer stack of the dielectric build-up layer; and / or the silicon-based intermediate layer build-up layer is repeatedly provided multiple times to form a multi-layer stack of the silicon-based intermediate layer build-up layer.

[0037] Optionally, the surface of the silicon-based intermediate layer is plasma bombarded with CF4 gas, and the surface of the silicon-based intermediate layer bombarded with plasma is brought into contact with the build-up dielectric layer of the uppermost dielectric build-up layer; or the surface of the silicon-based intermediate layer is chemically etched, and the surface of the silicon-based intermediate layer that is chemically etched is brought into contact with the build-up dielectric layer of the uppermost dielectric build-up layer.

[0038] Optionally, the silicon-based intermediate layer build-up layer is disposed on only one of two surfaces of the packaging substrate structure that are disposed oppositely, or the silicon-based intermediate layer build-up layer is disposed on both surfaces of the packaging substrate structure that are disposed oppositely.

[0039] The present invention also provides a packaging substrate structure, which is obtained by any one of the above-mentioned preparation methods, and comprises: a core board, a patterned conductive layer, a substrate dielectric layer, a dielectric build-up layer, a silicon-based intermediate layer build-up layer, an outer plating layer and a patterned solder resist layer;

[0040] The graphic conductive layer is arranged on the upper surface and the lower surface of the core board and penetrates the core board at a preset position, the substrate dielectric layer covers the graphic conductive layer and covers the gaps in the graphic conductive layer; the dielectric build-up layer is arranged on the substrate dielectric layer, the silicon-based intermediate layer build-up layer is arranged on the dielectric build-up layer, the graphic outer coating is provided with a conductive connection at a portion of the surface of the packaging substrate structure that is preset to be conductively connected, the solder resist layer covers the outer coating and fills the gaps between the outer coatings, and conductive connection portions are formed in sequence among the core board, the graphic conductive layer, the dielectric build-up layer, the silicon-based intermediate layer build-up layer, and the outer coating, and the conductive connection portions are led out to the surface of the packaging substrate structure through the outer coating.

[0041] Optionally, the silicon-based intermediate layer build-up layer is disposed on only one of two oppositely disposed surfaces of the packaging substrate structure, or the silicon-based intermediate layer build-up layer is disposed on both oppositely disposed surfaces of the packaging substrate structure.

[0042] Optionally, the silicon-based intermediate layer build-up layer includes two silicon-based intermediate layers, a third seed conductive layer, an intermediate conductive layer and an intermediate dielectric layer. The third seed conductive layer and the intermediate conductive layer are arranged between the two silicon-based intermediate layers. The intermediate dielectric layer covers the silicon-based intermediate layer on the side of the silicon-based intermediate layer build-up layer away from the core board layer, and the intermediate dielectric layer is in contact with the outer coating layer.

[0043] As described above, the packaging substrate structure and the preparation method thereof of the present invention have the following beneficial effects:

[0044] The present invention arranges a silicon-based intermediate layer on the dielectric build-up layer of the packaging substrate, and utilizes the high flatness and low ductility of the silicon-based intermediate layer on the dielectric build-up layer to reduce the warping problem of the packaging substrate and improve the flatness of the surface of the packaging substrate.

[0045] The silicon-based intermediate layer of the present invention has a low dielectric constant and dielectric loss factor, which can improve the performance of the packaging substrate;

[0046] The present invention uses the characteristic of the silicon-based intermediate layer to produce finer circuits, thereby realizing a packaging substrate structure with higher density integration;

[0047] The present invention further improves the performance of the packaging substrate by wrapping the middle conductive layer with two silicon-based middle layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 It is a schematic diagram showing the structure of the core board layer in step 1 in the first embodiment of the present invention.

[0049] Figure 2 It is a schematic diagram of the structure presented by setting the through groove in step 2 in the first embodiment of the present invention.

[0050] Figure 3 It is a schematic diagram of the structure presented by setting the first seed conductive layer and the second conductive layer in step 3 in the first embodiment of the present invention.

[0051] Figure 4 It shows a schematic diagram of the structure presented by setting the filling layer in step 4 in the first embodiment of the present invention.

[0052] Figure 5 It is a schematic diagram of the structure presented by setting the third conductive layer in step 5 in the first embodiment of the present invention.

[0053] Figure 6 It is a schematic diagram showing the structure of the first mask layer in step 6 in the first embodiment of the present invention.

[0054] Figure 7 It is a schematic diagram showing the structure of the core board revealed by etching in step 7 of the first embodiment of the present invention.

[0055] Figure 8 It is a schematic diagram of the structure presented by removing the first mask layer in step 8 in the first embodiment of the present invention.

[0056] Fig. 9 It is a schematic diagram of the structure presented by setting a substrate dielectric layer in step 9 and setting a first blind hole in an optional example of step 10 in embodiment 1 of the present invention.

[0057] Fig.10It is a schematic diagram of the structure presented by setting a second seed conductive layer in an optional example of step 10 in embodiment 1 of the present invention.

[0058] Fig.11 It is a schematic diagram of the structure presented by setting the second mask layer in an optional example of step 10 in embodiment 1 of the present invention.

[0059] Fig.12 It is a schematic diagram of the structure presented by the filling build-up conductive layer in an optional example of step 10 in the first embodiment of the present invention.

[0060] Fig.13 It is a schematic diagram of the structure presented by removing the second mask layer and the second seed conductive layer in an optional example of step 10 in the first embodiment of the present invention.

[0061] Fig.14 It is a schematic diagram of the structure presented by filling the build-up dielectric layer in an optional example of step 10 in embodiment 1 of the present invention.

[0062] Fig.15 It is a schematic diagram of the structure presented by setting two dielectric build-up layers in an optional example of step 10 in embodiment 1 of the present invention.

[0063] Fig.16 It shows a schematic diagram of the structure presented by setting a silicon-based intermediate layer and a second blind hole in an optional example of step 11 in embodiment 1 of the present invention.

[0064] Fig.17 It is a schematic diagram of the structure presented by setting a third seed conductive layer in an optional example of step 11 in embodiment 1 of the present invention.

[0065] Fig.18 It is a schematic diagram of the structure presented by setting the third mask layer in an optional example of step 11 in embodiment 1 of the present invention.

[0066] Fig.19 It is a schematic diagram of the structure presented by filling the middle conductive layer in an optional example of step 11 in embodiment 1 of the present invention.

[0067] Fig. 20 It is a schematic diagram of the structure presented by removing the third mask layer and the third seed conductive layer in an optional example of step 11 in embodiment 1 of the present invention.

[0068] Fig.21 It shows a schematic diagram of the structure presented by covering the intermediate dielectric layer and setting two silicon-based intermediate layer build-up layers in an optional example of step 11 in embodiment 1 of the present invention.

[0069] Fig. 22 It is a schematic diagram of the structure presented by setting the outer plating layer in step 12 in the first embodiment of the present invention.

[0070] Fig.23 It is a schematic diagram of the structure presented by the covering solder mask layer in step 13 in the first embodiment of the present invention.

[0071] Fig.24 It shows a schematic diagram of the structure presented by setting a silicon-based intermediate layer and a second blind hole in an optional example of step 11 in embodiment 2 of the present invention.

[0072] Fig.25 It is a schematic diagram of the structure presented by setting a third seed conductive layer in an optional example of step 11 in embodiment 2 of the present invention.

[0073] Fig.26 It is a schematic diagram of the structure presented by setting the third mask layer in an optional example of step 11 in the second embodiment of the present invention.

[0074] Fig. 27 It is a schematic diagram of the structure presented by filling the middle conductive layer in an optional example of step 11 in the second embodiment of the present invention.

[0075] Fig.28 It is a schematic diagram of the structure presented by removing the third mask layer and the third seed conductive layer in an optional example of step 11 in the second embodiment of the present invention.

[0076] Fig.29 It shows a schematic diagram of the structure presented by covering the intermediate dielectric layer and setting two silicon-based intermediate layer build-up layers in an optional example of step 11 in the second embodiment of the present invention.

[0077] Fig.30 It is a schematic diagram of the structure presented by setting the outer plating layer in step 12 in the second embodiment of the present invention.

[0078] Fig.31 It is a schematic diagram of the structure presented by the covering solder resist layer in step 13 in the second embodiment of the present invention.

[0079] Fig.32 It shows a schematic structural diagram of a packaging substrate structure in accordance with a fifth embodiment of the present invention in which two silicon-based intermediate layers wrap a third seed conductive layer and an intermediate conductive layer.

[0080] Component number description

[0081] 11. core board; 12. first conductive layer; 13. through groove; 14. first seed conductive layer; 15. second conductive layer; 16. filling layer; 17. third conductive layer; 18. first mask layer; 19. substrate dielectric layer;

[0082] 21. first blind hole; 22. second seed conductive layer; 23. second mask layer; 24. build-up conductive layer; 25. build-up dielectric layer; 31. silicon-based intermediate layer; 32. second blind hole; 33. third seed conductive layer; 34. third mask layer; 35. intermediate conductive layer; 36. intermediate dielectric layer;

[0083] 41. Fourth seed conductive layer; 42. External plated conductive layer; 43. Solder resist layer; 44. Protective layer. DETAILED DESCRIPTION

[0084] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0085] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0086] For convenience of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings.

[0087] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0088] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0089] Embodiment 1:

[0090] like Figure 1-Figure 23 As shown, the present invention provides a method for preparing a packaging substrate structure, the preparation method comprising:

[0091] Step 1: providing a core board 11, the core board 11 comprises an upper surface and a lower surface arranged opposite to each other, the upper surface and the lower surface are both provided with a first conductive layer 12, and the core board 11 and the first conductive layer 12 constitute a core board layer;

[0092] Step 2: Setting a through groove 13 in the core plate layer;

[0093] Step 3: Covering the surface of the core plate layer exposed after the through grooves 13 are provided with a first seed conductive layer 14 , and covering the surface of the first seed conductive layer 14 with a second conductive layer 15 ;

[0094] Step 4: Filling the through groove 13 with a filling layer 16 , the filling layer 16 fills the gaps of the second conductive layer 15 in the through groove 13 and covers the surface of the second conductive layer 15 ;

[0095] Step 5: Disposing a third conductive layer 17 on the surface of the filling layer 16;

[0096] Step 6: Disposing a patterned first mask layer 18 on the surface of the third conductive layer 17 to expose a portion of the third conductive layer 17 below;

[0097] Step 7: etching the exposed third conductive layer 17 and the filling layer 16, the second conductive layer 15, the first seed conductive layer 14 and the first conductive layer 12 below the third conductive layer 17 to expose a portion of the core board 11;

[0098] Step 8: removing the first mask layer 18 to expose the third conductive layer 17 thereunder, the third conductive layer 17, the filling layer 16, the second conductive layer 15, the first seed conductive layer 14 and the first conductive layer 12 constitute a pattern conductive layer, and both the upper surface and the lower surface of the core board 11 are provided with a pattern conductive layer;

[0099] Step 9: a substrate dielectric layer 19 is disposed on the surface of the third conductive layer 17 close to the upper surface and the lower surface of the core board 11, and the substrate dielectric layer 19 fills the gaps in the etched pattern conductive layer and covers its surface;

[0100] Step 10: a dielectric build-up layer is provided on the surface of the substrate dielectric layer 19 close to the upper surface and the lower surface of the core board 11;

[0101] Step 11: a silicon-based intermediate layer is provided on the surfaces of the dielectric build-up layers close to the upper surface and the lower surface of the core board 11;

[0102] Step 12: a patterned outer coating is provided on the upper surface of the package substrate structure thus formed, and a portion of the silicon-based intermediate layer build-up layer close to the upper surface of the core board 11 that is preset to be conductively connected to form a conductive connection portion; a patterned outer coating is provided on the lower surface of the package substrate structure thus formed, and a portion of the silicon-based intermediate layer build-up layer close to the lower surface of the core board 11 that is preset to be conductively connected to form a conductive connection portion;

[0103] Step 13: Cover the outer plating layer with a patterned solder resist layer 43 , wherein the solder resist layer 43 fills the gaps between the patterned outer plating layers and exposes the conductive connection portions of the outer plating layers that are preset to be led out.

[0104] The preparation method of the packaging substrate structure of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the preparation method of the packaging substrate structure protected by the present invention, and those skilled in the art may change it according to the actual preparation steps.

[0105] First, if Figure 1 As shown, step 1 is performed to provide a core board 11, the core board 11 includes an upper surface and a lower surface arranged opposite to each other, both of which are provided with a first conductive layer 12, and the core board 11 and the first conductive layer 12 constitute a core board layer.

[0106] In one embodiment, the material of the first conductive layer 12 is a copper layer.

[0107] In one embodiment, the first conductive layer 12 is thinned.

[0108] In one embodiment, the thickness of the first conductive layer 12 is 10-15 microns, and the thickness of the first conductive layer 12 after thinning is 2.5-3.5 microns.

[0109] Then, if Figure 2 As shown, step 2 is performed to set a through groove 13 in the core plate layer.

[0110] In one embodiment, the through slot 13 is provided by mechanical drilling.

[0111] Then, if Figure 3 As shown, step 3 is performed to cover the surface of the core layer exposed after the through grooves 13 are provided with the first seed conductive layer 14 , and the surface of the first seed conductive layer 14 is covered with the second conductive layer 15 .

[0112] In one embodiment, the first seed conductive layer 14 is chemical copper obtained by chemical copper deposition.

[0113] In one embodiment, the second conductive layer 15 is provided by electroplating.

[0114] Then, if Figure 4As shown, step 4 is performed to fill the through groove 13 with a filling layer 16 . The filling layer 16 fills the gap of the second conductive layer 15 in the through groove 13 and covers the surface of the second conductive layer 15 .

[0115] In one embodiment, the material of the filling layer 16 is resin, or non-dielectric materials such as metal or metal compound, which is used to fill the gaps in the through grooves 13 to avoid reliability problems of the package substrate structure caused by the gaps. Resin is preferably used as the filling material, which has a simple process and low cost, and is conducive to the production and manufacturing of the package substrate.

[0116] In one embodiment, after filling the filling layer 16 , the obtained package substrate structure is ground to remove the micro-etched portion of the surface of the filling layer 16 .

[0117] Then, if Figure 5 As shown, step 5 is performed to dispose a third conductive layer 17 on the surface of the filling layer 16 .

[0118] In one embodiment, the third conductive layer 17 is electroplated copper.

[0119] Then, if Figure 6 As shown, step 6 is performed to dispose a patterned first mask layer 18 on the surface of the third conductive layer 17 to expose a portion of the third conductive layer 17 underneath.

[0120] In one embodiment, the first mask layer 18 is a photosensitive material, and the first mask layer 18 can be patterned by exposure and development.

[0121] Then, if Figure 7 As shown, step 7 is performed to etch the exposed third conductive layer 17 and the filling layer 16 , the second conductive layer 15 , the first seed conductive layer 14 and the first conductive layer 12 below the third conductive layer 17 to expose a portion of the core board 11 .

[0122] Then, if Figure 8 As shown, step 8 is performed to remove the first mask layer 18 to expose the third conductive layer 17 underneath. The third conductive layer 17, the filling layer 16, the second conductive layer 15, the first seed conductive layer 14 and the first conductive layer 12 constitute a graphic conductive layer. The upper and lower surfaces of the core board 11 are both provided with a graphic conductive layer.

[0123] Then, if Fig. 9 As shown, step 9 is performed to set a substrate dielectric layer 19 on the surface of the third conductive layer 17 close to the upper surface and the lower surface of the core board 11, and the substrate dielectric layer 19 fills the gaps of the etched pattern conductive layer and covers its surface.

[0124] Then, step 10 is performed to provide dielectric build-up layers on the surfaces of the substrate dielectric layer 19 close to the upper surface and the lower surface of the core board 11 .

[0125] In one embodiment, a method for preparing a dielectric build-up layer includes:

[0126] like Fig. 9 As shown, a first blind hole 21 is provided in the substrate dielectric layer 19 to expose a portion of the third conductive layer 17 that is pre-set for conductive connection;

[0127] like Fig.10 As shown, a second seed conductive layer 22 is disposed on the substrate dielectric layer 19 behind the first blind hole 21, and the second seed conductive layer 22 covers the substrate dielectric layer 19 and the exposed third conductive layer 17;

[0128] like Fig.11 As shown, a patterned second mask layer 23 is disposed on the second seed conductive layer 22;

[0129] like Fig.12 As shown, the gaps between the patterned second mask layers 23 are filled with a build-up conductive layer 24;

[0130] like Fig.13 As shown, the second mask layer 23 and the second seed conductive layer 22 exposed under the second mask layer 23 are removed to expose a portion of the substrate dielectric layer 19, thereby obtaining a patterned build-up conductive layer 24 and a patterned second seed conductive layer 22;

[0131] like Fig.14 As shown, a build-up dielectric layer 25 is filled in the gap between the patterned build-up conductive layer 24 and the second seed conductive layer 22, thereby obtaining a dielectric build-up layer.

[0132] In one embodiment, the dielectric build-up layer is repeatedly provided multiple times to form a multi-layer stack of dielectric build-up layers, such as Figure 14-15 The diagram shown is a schematic diagram presented when two dielectric build-up layers are provided. More than two dielectric build-up layers may also be provided.

[0133] In one embodiment, the first blind hole 21 is obtained by UV laser (ultraviolet light), CO2 laser, Pico (picosecond) laser, etc., and a plasma etching method can also be used to etch the barrier layer to form a hole.

[0134] In one embodiment, the second seed conductive layer 22 is chemical copper obtained by chemical copper deposition.

[0135] In one embodiment, the second mask layer 23 is a photosensitive material, and the second mask layer 23 can be patterned by exposure and development.

[0136] In one embodiment, the second seed conductive layer 22 under the second mask layer 23 is removed by flash etching.

[0137] In one embodiment, the material of the build-up dielectric layer 25 can be one or any combination of epoxy resin-based polymer materials, nitrogen-containing polymer materials, Ajinomoto built-up film (ABF), polyimide materials (PI), fluorine-containing polymer materials, polymaleimide triazine resin polymers, and polyphenylene ether.

[0138] Next, step 11 is performed to provide a silicon-based intermediate layer build-up layer on the surfaces of the dielectric build-up layers close to the upper surface and the lower surface of the core board 11 .

[0139] In one embodiment, a method for preparing a silicon-based intermediate layer build-up layer includes:

[0140] like Fig.16 As shown, a silicon-based intermediate layer 31 is provided on the surface of the dielectric build-up layer close to the upper surface and the lower surface of the core board 11, and a second blind hole 32 is provided to penetrate the two silicon-based intermediate layers 31 and the uppermost build-up dielectric layer 25 of the dielectric build-up layer respectively to expose a portion of the dielectric build-up layer that is preset to be conductively connected;

[0141] like Fig.17 As shown, a third seed conductive layer 33 is respectively disposed on the surfaces of the two silicon-based intermediate layers 31 , and the third seed conductive layer 33 covers the exposed surface of the silicon-based intermediate layer 31 and the second blind hole 32 ;

[0142] like Fig.18 As shown, a patterned third mask layer 34 is respectively disposed on the surfaces of the two third conductive seed layers 33;

[0143] like Fig.19 As shown, the gaps between the two patterned third mask layers 34 are filled with an intermediate conductive layer 35 respectively;

[0144] like Fig. 20 As shown, the third mask layer 34 and the third seed conductive layer 33 exposed under the third mask layer 34 are removed to expose a portion of the silicon-based intermediate layer 31, thereby obtaining a patterned intermediate conductive layer 35 and a patterned third seed conductive layer 33;

[0145] like Fig.21 As shown, an intermediate dielectric layer 36 is covered on the patterned intermediate conductive layer 35 and the third seed conductive layer 33, and the intermediate dielectric layer 36 fills the gap between the patterned intermediate conductive layer 35 and the third seed conductive layer 33, thereby obtaining two silicon-based intermediate layer build-up layers respectively close to the upper surface and the lower surface of the core board 11.

[0146] In this embodiment, the silicon-based intermediate layer build-up layers are disposed on two opposite surfaces of the packaging substrate structure.

[0147] The present invention can further improve the integration of the packaging substrate structure by arranging silicon-based intermediate layers on both sides of the packaging substrate structure, but the process complexity will increase.

[0148] In one embodiment, the material of the silicon-based intermediate layer 31 includes silicon and silicon compounds.

[0149] In one embodiment, the silicon compound in the silicon-based intermediate layer 31 is silicon oxide and / or silicon nitride.

[0150] In one embodiment, the silicon-based intermediate layer build-up layer is repeatedly provided multiple times to form a multi-layer stack of silicon-based intermediate layer build-up layers, such as Fig.21 The figure shows a schematic diagram of setting two silicon-based intermediate layer build-up layers. More than two silicon-based intermediate layer build-up layers may also be set.

[0151] In the prior art, the silicon-based intermediate layer 31 is usually embedded in the packaging substrate to increase the exposure density. During the embedding process, a groove needs to be set in the packaging substrate. The setting process is likely to cause the structural warping of the packaging substrate. At the same time, the steps for setting the groove are complicated and costly. The present invention sets the silicon-based intermediate layer 31 in a layer-building manner on the dielectric layer of the packaging substrate. The silicon-based intermediate layer 31 structure can be introduced without setting a groove, thereby avoiding the problem of warping of the packaging substrate during the preparation process. At the same time, the preparation method is similar to the general circuit layer-building process, and there is no need to change the process equipment and process on a large scale, thereby greatly reducing the preparation cost required to increase the technical solution of the present invention. At the same time, the step of preparing the groove is omitted, and the preparation process is simple. In addition, the present invention ensures that the packaging substrate is not affected by the warping problem and the process efficiency remains unchanged, and utilizes the low dielectric constant, low dielectric loss factor and high-precision circuit characteristics of the silicon-based intermediate layer 31 to achieve a high-integration, high-performance packaging substrate structure.

[0152] In one embodiment, after removing the third mask layer 34 and the third seed conductive layer 33 exposed under the third mask layer 34 , a silicon-based intermediate layer 31 is covered on the exposed third seed conductive layer 33 , the intermediate conductive layer 35 and the silicon-based intermediate layer 31 , and then the intermediate dielectric layer 36 is covered.

[0153] The present invention provides two silicon-based intermediate layers 31 to wrap the intermediate conductive layer 35 and the third seed conductive layer 33 , and utilizes the low dielectric constant and low dielectric loss factor of the two silicon-based intermediate layers 31 to further improve the signal transmission performance of the line.

[0154] In one embodiment, an adhesive layer is disposed between the build-up dielectric layer 25 and the silicon-based intermediate layer 31 .

[0155] In one embodiment, CF4 gas is used to perform plasma bombardment on the surface of the silicon-based intermediate layer 31, and the plasma-bombarded surface of the silicon-based intermediate layer 31 is in contact with the uppermost build-up dielectric layer 25 of the dielectric build-up layer.

[0156] In one embodiment, the surface of the silicon-based intermediate layer 31 is chemically etched, and the chemically etched surface of the silicon-based intermediate layer 31 is in contact with the uppermost build-up dielectric layer 25 of the dielectric build-up layer.

[0157] The present invention improves the bonding force between the silicon-based intermediate layer 31 and the dielectric build-up layer by plasma bombardment and / or chemical etching, thereby improving the structural reliability of the packaging substrate.

[0158] In one embodiment, the silicon-based intermediate layer 31 is disposed on the dielectric build-up layer by magnetron sputtering, physical vapor deposition or atomic layer deposition.

[0159] The present invention provides a silicon-based intermediate layer 31 on the dielectric build-up layer of the packaging substrate, and can directly deposit the silicon-based intermediate layer 31 by magnetron sputtering, physical vapor deposition, or atomic layer deposition. Compared with the prior art method of providing a groove to place the silicon-based intermediate layer 31, the process is simpler and the cost is lower. Preferably, the silicon-based intermediate layer 31 is provided by magnetron sputtering, which can avoid excessive temperature from damaging the dielectric layer material, thereby improving the reliability of the structure.

[0160] In one embodiment, the method of providing the third seed conductive layer 33 includes atomic layer deposition, physical vapor deposition or electroplating. Preferably, the third seed conductive layer 33 is provided by atomic layer deposition.

[0161] In one embodiment, the material of the third conductive seed layer 33 is one or more of copper, titanium, silver and oxides thereof. Preferably, copper is used as the material of the third conductive seed layer 33 .

[0162] In one embodiment, the third mask layer 34 is a photoresist, and a patterned third mask layer 34 can be obtained by photolithography and development.

[0163] In one embodiment, the third seed conductive layer 33 under the third mask layer 34 is removed by flash etching.

[0164] Then, if Fig. 22 As shown, step 12 is performed, a graphic outer coating is set on the upper surface of the packaging substrate structure formed so far, and a conductive connection portion is formed with a portion of the silicon-based intermediate layer build-up layer preset to be conductively connected to the upper surface of the core board 11, and a graphic outer coating is set on the lower surface of the packaging substrate structure formed so far, and a conductive connection portion is formed with a portion of the silicon-based intermediate layer build-up layer preset to be conductively connected to the lower surface of the core board 11.

[0165] In one embodiment, the method for forming the outer plating layer is: firstly set the fourth seed conductive layer 41, and then set the outer plating conductive layer 42 on the fourth seed conductive layer 41, and the fourth seed conductive layer 41 and the outer plating conductive layer 42 constitute the outer plating layer.

[0166] Finally, if Fig.23 As shown, step 13 is performed to cover the outer plating layer with a patterned solder resist layer 43 , the solder resist layer 43 fills the gaps between the patterned outer plating layers and exposes the conductive connection portions of the outer plating layers that are preset to be led out.

[0167] In one embodiment, the solder resist layer 43 is provided with photoresist, exposed, and developed to obtain a patterned solder resist layer 43 to expose the conductive connection portion.

[0168] In one embodiment, a protective layer 44 is disposed on the surface of the conductive connection portion of the patterned outer plating layer to protect the conductive connection on the surface and prevent oxidation of the portion of the circuit.

[0169] In one embodiment, the material of the protection layer 44 is chemical nickel palladium gold.

[0170] Embodiment 2:

[0171] This embodiment provides a method for preparing a package substrate structure, wherein steps 1 to 10 of the preparation method are substantially the same as those in the first embodiment, except that:

[0172] Step 11: Figure 24-Figure 29 As shown, a silicon-based intermediate layer build-up layer is provided on the surface of the dielectric build-up layer close to the upper surface or the lower surface of the core board 11;

[0173] Step 12: Fig.30 As shown, a patterned outer coating is arranged on the surface of the package substrate structure formed so far and provided with the silicon-based intermediate layer build-up layer, and a portion of the silicon-based intermediate layer build-up layer that is preset to be conductively connected is formed into a conductive connection portion, and a patterned outer coating is arranged on the surface of the package substrate structure formed so far and not provided with the silicon-based intermediate layer, and a portion of the dielectric build-up layer that is preset to be conductively connected is formed into a conductive connection portion exposed on the surface;

[0174] Step 13: Fig.31 As shown, a patterned solder resist layer 43 is covered on the outer plating layer, and the solder resist layer 43 fills the gaps between the patterned outer plating layers and exposes the conductive connection parts preset by the outer plating layers.

[0175] In one embodiment, in step 11, the method for preparing a silicon-based intermediate layer build-up layer includes:

[0176] like Fig.24As shown, a silicon-based intermediate layer 31 is provided on the surface of the dielectric build-up layer close to the upper surface or the lower surface of the core board 11, and a second blind hole 32 is provided to penetrate the silicon-based intermediate layer 31 and the uppermost build-up dielectric layer 25 of the dielectric build-up layer to expose a portion of the dielectric build-up layer that is preset to be electrically conductively connected;

[0177] like Fig.25 As shown, a third seed conductive layer 33 is disposed on the surface of the silicon-based intermediate layer 31 , and the third seed conductive layer 33 covers the exposed surface of the silicon-based intermediate layer 31 and the second blind hole 32 ;

[0178] like Fig.26 As shown, a patterned third mask layer 34 is disposed on the surface of the third conductive seed layer 33;

[0179] like Fig. 27 As shown, the gaps between the patterned third mask layers 34 are filled with an intermediate conductive layer 35;

[0180] like Fig.28 As shown, the third mask layer 34 and the third seed conductive layer 33 exposed under the third mask layer 34 are removed to expose a portion of the silicon-based intermediate layer 31, thereby obtaining a patterned intermediate conductive layer 35 and a patterned third seed conductive layer 33;

[0181] like Fig.29 As shown, an intermediate dielectric layer 36 is covered on the patterned intermediate conductive layer 35 and the third seed conductive layer 33, and the intermediate dielectric layer 36 fills the gap between the patterned intermediate conductive layer 35 and the third seed conductive layer 33, thereby obtaining a silicon-based intermediate layer build-up layer close to the upper surface or lower surface of the core board 11.

[0182] Specifically, in this embodiment, a silicon-based intermediate layer build-up layer is arranged on one side of the packaging substrate, so that a highly integrated packaging substrate structure can be achieved in relatively simple process steps; in Example 1, a silicon-based intermediate layer build-up layer is arranged on both sides of the packaging substrate structure, which can further improve the integration of the packaging substrate structure, but the process complexity will increase. Personnel in this field can make improvements as needed, and all variations are within the protection scope of the present invention.

[0183] In one embodiment, a multi-layer silicon-based intermediate layer build-up layer may be provided on one side of the package substrate, such as Fig.29 The figure shows a schematic diagram of a structure in which two silicon-based intermediate layers are provided on one side of a packaging substrate.

[0184] In one embodiment, after removing the third mask layer 34 and the third seed conductive layer 33 exposed under the third mask layer 34 , a silicon-based intermediate layer 31 is covered on the exposed third seed conductive layer 33 , the intermediate conductive layer 35 and the silicon-based intermediate layer 31 , and then the intermediate dielectric layer 36 is covered.

[0185] The present invention uses two silicon-based intermediate layers 31 to wrap the intermediate conductive layer 35 and the third seed conductive layer 33 , and utilizes the low dielectric constant and low dielectric loss factor of the two silicon-based intermediate layers 31 to further improve the signal transmission performance of the line.

[0186] Embodiment three:

[0187] The present invention provides a packaging substrate structure, which is obtained by any one of the preparation methods in the above-mentioned embodiment 1 or embodiment 2, and the packaging substrate structure includes: a core board 11, a patterned conductive layer, a substrate dielectric layer 19, a dielectric build-up layer, a silicon-based intermediate layer build-up layer, an outer plating layer and a patterned solder resist layer 43;

[0188] The graphic conductive layer is arranged on the upper surface and the lower surface of the core board 11 and penetrates the core board 11 at a preset position. The substrate dielectric layer 19 covers the graphic conductive layer and covers the gaps in the graphic conductive layer; the dielectric build-up layer is arranged on the substrate dielectric layer 19, and the silicon-based intermediate layer build-up layer is arranged on the dielectric build-up layer. The graphic outer coating is provided with a conductive connection at a portion of the surface of the packaging substrate structure that is preset to be conductively connected. The solder resist layer 43 covers the outer coating and fills the gaps between the outer coatings. Conductive connection portions are formed in sequence among the core board 11, the graphic conductive layer, the dielectric build-up layer, the silicon-based intermediate layer build-up layer, and the outer coating, and the conductive connection portions are led out to the surface of the packaging substrate structure through the outer coating.

[0189] The invention in this embodiment arranges the silicon-based intermediate layer 31 on the dielectric build-up layer of the packaging substrate in a build-up manner, and utilizes the high flatness and low ductility of the silicon-based intermediate layer 31 material itself to suppress the warping deformation of the packaging substrate; at the same time, there is no need to set grooves in the packaging substrate structure, and uneven structural distribution will not be generated, thereby further avoiding the warping problem of the packaging substrate structure and improving the structural reliability of the packaging substrate structure; in addition, the low dielectric constant, low dielectric loss factor, and high-precision circuit characteristics of the silicon-based intermediate layer 31 are utilized to improve the performance and integration of the packaging substrate structure, reduce the loss of the packaging substrate structure and the packaging size at the same integration.

[0190] In this embodiment, the silicon-based intermediate layer build-up layer is disposed on two opposite surfaces of the packaging substrate structure.

[0191] The present invention can further improve the integration of the packaging substrate structure by arranging silicon-based intermediate layers on both sides of the packaging substrate structure, but the process complexity will increase.

[0192] Embodiment 4:

[0193] This embodiment provides a packaging substrate structure, which is obtained by using any one of the preparation methods in the above-mentioned embodiment 1 or embodiment 2. The packaging substrate structure is basically the same as that in embodiment 3, except that:

[0194] In this embodiment, the silicon-based intermediate layer build-up layer is disposed on only one of the two surfaces of the packaging substrate structure that are disposed opposite to each other.

[0195] Specifically, in this embodiment, a silicon-based intermediate layer build-up layer is arranged on one side of the packaging substrate, so that a highly integrated packaging substrate structure can be achieved in relatively simple process steps; in Example 3, silicon-based intermediate layer build-up layers are arranged on both sides of the packaging substrate structure, which can further improve the integration of the packaging substrate structure, but the process complexity will increase. Personnel in this field can make improvements as needed, and all variations are within the protection scope of the present invention.

[0196] Embodiment five:

[0197] This embodiment provides a packaging substrate structure, which is obtained by using any one of the preparation methods in the above-mentioned embodiment 1 or embodiment 2. The packaging substrate structure is basically the same as that in embodiment 3 or embodiment 4, and the difference is that:

[0198] like Fig.32 As shown, the silicon-based intermediate layer build-up layer includes two silicon-based intermediate layers 31, a third seed conductive layer 33, an intermediate conductive layer 35 and an intermediate dielectric layer 36. The third seed conductive layer 33 and the intermediate conductive layer 35 are arranged between the two silicon-based intermediate layers 31. The intermediate dielectric layer 36 covers the silicon-based intermediate layer 31 on the side of the silicon-based intermediate layer build-up layer away from the core layer, and the intermediate dielectric layer 36 is in contact with the outer coating layer.

[0199] In this embodiment, a silicon-based intermediate layer 31 is covered on both sides of the third seed conductive layer 33 and the intermediate conductive layer 35 , thereby utilizing the low dielectric constant and low dielectric loss factor of the two silicon-based intermediate layers 31 to further improve the signal transmission performance of the line.

[0200] In summary, the packaging substrate structure and preparation method thereof of the present invention can reduce the warping problem of the packaging substrate and improve the flatness of the board surface of the packaging substrate by setting a silicon-based intermediate layer on the dielectric build-up layer of the packaging substrate and utilizing the high flatness and low ductility of the silicon-based intermediate layer on the dielectric build-up layer; at the same time, the method of depositing the silicon-based intermediate layer on the packaging substrate avoids the warping problem caused by the process of setting a groove to embed the silicon-based intermediate layer; in addition, the silicon-based intermediate layer has low dielectric constant and dielectric loss factor, which can improve the performance of the packaging substrate; finally, the characteristic of the silicon-based intermediate layer that more sophisticated circuits can be produced, thereby realizing a higher density integrated packaging substrate structure.

[0201] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0202] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a packaging substrate structure, characterized in that: The preparation method comprises: Providing a core board, the core board comprising an upper surface and a lower surface arranged opposite to each other, the upper surface and the lower surface are both provided with a first conductive layer, the core board and the first conductive layer constitute a core board layer; A through groove is provided in the core plate layer; The surface of the core plate layer exposed after the through grooves are provided is covered with a first seed conductive layer, and the surface of the first seed conductive layer is covered with a second conductive layer; Filling the through groove with a filling layer, wherein the filling layer fills the gap of the second conductive layer in the through groove and covers the surface of the second conductive layer; Disposing a third conductive layer on the surface of the filling layer; Disposing a patterned first mask layer on the surface of the third conductive layer to expose a portion of the third conductive layer below; Etching the exposed third conductive layer and the filling layer, the second conductive layer, the first seed conductive layer and the first conductive layer below the third conductive layer to expose a portion of the core board; Removing the first mask layer to expose the third conductive layer thereunder, and a pattern conductive layer formed by the third conductive layer, the filling layer, the second conductive layer, the first seed conductive layer and the first conductive layer; A substrate dielectric layer is provided on the surface of the third conductive layer, wherein the substrate dielectric layer fills the gaps in the etched pattern conductive layer and covers the surface thereof; Disposing a dielectric build-up layer on the surface of the substrate dielectric layer; Disposing a silicon-based intermediate layer build-up layer on the dielectric build-up layer; A patterned outer plating layer is provided on both the upper surface and the lower surface of the package substrate structure thus formed, and the outer plating layer forms a conductive connection portion with a portion of the package substrate structure thus formed that is intended to be conductively connected; A patterned solder resist layer is covered on the outer plating layer, and the solder resist layer fills the gaps between the patterned outer plating layers and exposes the conductive connection parts preset by the outer plating layers.

2. The method for preparing a packaging substrate structure according to claim 1, characterized in that: The preparation method of the dielectric build-up layer comprises: A first blind hole is provided in the substrate dielectric layer to expose a portion of the third conductive layer that is preset to be conductively connected; a second seed conductive layer is provided on the substrate dielectric layer behind the first blind hole, the second seed conductive layer covers the substrate dielectric layer and the exposed third conductive layer; Disposing a patterned second mask layer on the second conductive seed layer; Filling the gaps between the patterned second mask layers with a build-up conductive layer; Removing the second mask layer and the second seed conductive layer exposed under the second mask layer to expose a portion of the substrate dielectric layer, thereby obtaining the patterned build-up conductive layer and the patterned second seed conductive layer; A build-up dielectric layer is filled in the gap between the patterned build-up conductive layer and the second seed conductive layer, thereby obtaining a layer of the dielectric build-up layer.

3. The method for preparing the package substrate structure according to claim 1, characterized in that: The preparation method of setting the silicon-based intermediate layer build-up layer comprises: A silicon-based intermediate layer is provided on the surface of the dielectric build-up layer, and a second blind hole is provided to penetrate the silicon-based intermediate layer and the uppermost build-up dielectric layer of the dielectric build-up layer to expose a portion of the dielectric build-up layer that is preset to be electrically connected; Disposing a third seed conductive layer on the surface of the silicon-based intermediate layer, wherein the third seed conductive layer covers the silicon-based intermediate layer and the surface exposed by the second blind hole; Disposing a patterned third mask layer on the surface of the third conductive seed layer; Filling the gaps between the patterned third mask layers with an intermediate conductive layer; Removing the third mask layer and the third seed conductive layer exposed under the third mask layer to expose a portion of the silicon-based intermediate layer, thereby obtaining the patterned intermediate conductive layer and the patterned third seed conductive layer; An intermediate dielectric layer is covered on the patterned intermediate conductive layer and the third seed conductive layer, and the intermediate dielectric layer fills the gap between the patterned intermediate conductive layer and the third seed conductive layer, thereby obtaining a layer of the silicon-based intermediate layer build-up layer.

4. The method for preparing a packaging substrate structure according to claim 3, characterized in that: After removing the third mask layer and the third seed conductive layer exposed under the third mask layer, a silicon-based intermediate layer is covered on the exposed third seed conductive layer, the intermediate conductive layer and the silicon-based intermediate layer, and then the intermediate dielectric layer is covered.

5. The method for preparing a packaging substrate structure according to any one of claims 1 to 4, characterized in that: The dielectric build-up layer is repeatedly arranged multiple times to form a multi-layer stack of the dielectric build-up layer; and / or the silicon-based intermediate layer build-up layer is repeatedly arranged multiple times to form a multi-layer stack of the silicon-based intermediate layer build-up layer.

6. The method for preparing a packaging substrate structure according to claim 1, characterized in that: The surface of the silicon-based intermediate layer is plasma bombarded with CF4 gas, and the surface of the silicon-based intermediate layer bombarded with plasma is brought into contact with the uppermost build-up layer dielectric layer of the dielectric build-up layer; or the surface of the silicon-based intermediate layer is chemically etched, and the surface of the silicon-based intermediate layer that is chemically etched is brought into contact with the uppermost build-up layer dielectric layer of the dielectric build-up layer.

7. The method for preparing a packaging substrate structure according to claim 1, characterized in that: The silicon-based intermediate layer build-up layer is disposed on only one of the two oppositely disposed surfaces of the packaging substrate structure, or the silicon-based intermediate layer build-up layer is disposed on both of the oppositely disposed surfaces of the packaging substrate structure.

8. A packaging substrate structure, characterized in that: The packaging substrate structure is obtained by the preparation method according to any one of claims 1 to 7, and the packaging substrate structure comprises: a core board, a patterned conductive layer, a substrate dielectric layer, a dielectric build-up layer, a silicon-based intermediate layer build-up layer, an outer plating layer and a patterned solder resist layer; The graphic conductive layer is arranged on the upper surface and the lower surface of the core board and penetrates the core board at a preset position, the substrate dielectric layer covers the graphic conductive layer and covers the gaps in the graphic conductive layer; the dielectric build-up layer is arranged on the substrate dielectric layer, the silicon-based intermediate layer build-up layer is arranged on the dielectric build-up layer, the graphic outer coating is provided with a conductive connection at a portion of the surface of the packaging substrate structure that is preset to be conductively connected, the solder resist layer covers the outer coating and fills the gaps between the outer coatings, and conductive connection portions are formed in sequence among the core board, the graphic conductive layer, the dielectric build-up layer, the silicon-based intermediate layer build-up layer, and the outer coating, and the conductive connection portions are led out to the surface of the packaging substrate structure through the outer coating.

9. The packaging substrate structure according to claim 8, characterized in that: The silicon-based intermediate layer build-up layer is disposed on only one of the two oppositely disposed surfaces of the packaging substrate structure, or the silicon-based intermediate layer build-up layer is disposed on both of the two oppositely disposed surfaces of the packaging substrate structure.

10. The packaging substrate structure according to claim 8, characterized in that: The silicon-based intermediate layer build-up layer includes two silicon-based intermediate layers, a third seed conductive layer, an intermediate conductive layer and an intermediate dielectric layer. The third seed conductive layer and the intermediate conductive layer are arranged between the two silicon-based intermediate layers. The intermediate dielectric layer covers the silicon-based intermediate layer on the side of the silicon-based intermediate layer build-up layer away from the core plate layer, and the intermediate dielectric layer is in contact with the outer coating layer.

Images