Semiconductor package with interposer

Abstract

A semiconductor package includes a lead frame, a low side FET, a high side FET, a metal clip, an interposer, an IC controller, and a molded package. A method of manufacturing a semiconductor package includes the steps of: providing a lead frame; connecting the low side FET and the high side FET; installing a metal clamp; connecting the interposer; an IC controller is installed; forming a molded package; and a singulation process is applied.

Description

Technical Field

[0001] The present invention generally relates to a semiconductor package operable to provide electromagnetic interference (EMI) shielding and capacitive shielding. More particularly, the present invention relates to a power semiconductor package having an interposer. Background Art

[0002] Conventional power semiconductor packages arrange a high-side field effect transistor (FET), a low-side FET, and an integrated circuit (IC) controller side by side, resulting in a larger package size.

[0003] The present invention stacks an IC controller on an interposer mounted on a metal clip connecting a high-side FET and a low-side FET to reduce package size and provide EMI shielding and capacitive shielding. Summary of the invention

[0004] An object of the present invention is to provide a semiconductor package with an interposer, reduce the size of the semiconductor package, and provide EMI shielding and capacitance shielding.

[0005] In order to achieve the above object, the present invention discloses a semiconductor package, including a lead frame, a low-side FET, a high-side FET, a metal clip, an interposer, an IC controller and a molded package.

[0006] Specifically, a semiconductor package includes:

[0007] A lead frame consists of

[0008] a first die pad; and

[0009] a second die pad;

[0010] a low-side FET flipped over and attached to the first die pad, the low-side FET including a source electrode and a gate electrode on a top surface of the low-side FET; and

[0011] a drain electrode located on the bottom surface of the low-side FET;

[0012] A high-side FET is connected to the second die pad, the high-side FET comprising

[0013] a source electrode and a gate electrode on a top surface of the high-side FET; and

[0014] a drain electrode on the bottom surface of the high-side FET;

[0015] a metal clip connecting the drain electrode of the low-side FET to the source electrode of the high-side FET;

[0016] an interposer attached to a top surface of the metal clip, the interposer comprising an insulating layer and an upper metal layer above the insulating layer;

[0017] an IC controller attached to the top surface of the interposer; and

[0018] A molded package that encapsulates the low-side FET, high-side FET, metal clip, interposer, and IC controller.

[0019] Optionally, the intermediary layer further includes

[0020] A lower metal layer is provided below the insulating layer.

[0021] Optionally, also include

[0022] An electrical connection electrically connects the upper metal layer of the interposer to the power ground terminal.

[0023] Optionally, also include

[0024] An electrical connection electrically connects the upper metal layer of the interposer to the analog ground terminal.

[0025] Optionally, the electrical connection comprises a plurality of bonding wires.

[0026] Optionally, also include

[0027] A plurality of bonding wires electrically connect the IC controller to the lead frame.

[0028] Optionally, the low-side FET is a MOSFET; and

[0029] The high-side FET is another MOSFET.

[0030] Optionally, the interposer covers at least 50% of a top surface of the metal clip.

[0031] Optionally, the interposer covers at least 75% of a top surface of the metal clip.

[0032] Optionally, the first die pad has a first die pad cut corner adjacent to the second die pad to accommodate one or more low-side gate leads extending into the first die pad cut corner; and

[0033] The second die pad has a second die pad cut corner diagonally opposite to the first die pad cut corner to accommodate leads extending into the second die pad cut corner.

[0034] In addition, the present invention also discloses a method for manufacturing a semiconductor package, which includes the following steps: providing a lead frame; connecting a low-side FET and a high-side FET; installing a metal clip; connecting an interposer; installing an IC controller; forming a molded package; and applying a singulation process.

[0035] Compared with the prior art, the technical solution of the present invention has at least the following beneficial effects: the present invention stacks the IC controller on an interposer, and the interposer is mounted on a metal clip connecting the high-side FET and the low-side FET to reduce the package size and provide EMI shielding and capacitive shielding. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1A shows a perspective view of a semiconductor package in an example of the present disclosure, Figure 1B A side view of a semiconductor package is shown.

[0037] Figure 2A FIG. 2 shows a perspective view of another semiconductor package in an example of the present disclosure, Figure 2B A side view thereof is shown.

[0038] Figure 3 A flow chart showing a process for developing a semiconductor package in an example of the present disclosure.

[0039] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Fig. 4I , Figure 4J , Figure 4K and Figure 4L The process steps for manufacturing a semiconductor package in an example of the present disclosure are shown. DETAILED DESCRIPTION

[0040] The scheme proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0041] Figure 1A 1 shows a perspective view of a semiconductor package 100 in an example of the present disclosure, Figure 1B1 shows a side view thereof. In one example, the semiconductor package 100 is a power semiconductor package. The semiconductor package 100 includes a lead frame 110, a low-side field effect transistor (FET) 140, a high-side FET 150, a metal clip 160, an interposer 170, an integrated circuit (hereinafter referred to as IC) controller 180, and a molded package 190. Figure 1A and Figure 1B , the molded package is shown transparently for clarity.

[0042] The lead frame 110 includes a first die pad 112 and a second die pad 114. The low side FET 140 is flipped over and attached to the first die pad 112. The low side FET 140 includes a source 140S and a gate 140G on a top surface of the low side FET 140 and a drain 140D on a bottom surface of the low side FET 140.

[0043] The high-side FET 150 is attached to the second die pad 114. The high-side FET 150 includes a source electrode 150S and a gate electrode 150G on its top surface, and a drain electrode 150D on its bottom surface. A metal clip 160 connects the drain 140D of the low-side FET 140 to the source electrode 150S of the high-side FET 150. The metal clip 160 includes a horizontal portion 162 and an inclined portion 164. The horizontal portion 162 has a substantially flat top surface. One end of the inclined portion 164 of the metal clip 160 is attached to the end pad 118 of the lead frame 110, which is used as a switching node output in converter applications.

[0044] The interposer 170 is attached to the top surface of the metal clip 160. The IC controller 180 is attached to the top surface of the interposer 170. The molded package 190 surrounds the low-side FET 140, the high-side FET 150, the metal clip 160, the interposer 170, and the IC controller 180. In one example, the molded package 190 also surrounds the entire lead frame 110. In another example, the molded package 190 also surrounds most of the lead frame 110 (greater than 50%), and the bottom surface of the lead frame 110 is exposed from the molded package 190.

[0045] The source 140S of the low-side FET 140 is connected to the Figure 4B The first conductive material 422 is shown electrically and mechanically connected to the first die pad 112. The drain electrode 150D of the high-side FET 150 is connected to the first die pad 112 by Figure 4B The second conductive material 424 is shown electrically and mechanically connected to the second die pad 114. In an example of the present disclosure, each of the first conductive material 422 and the second conductive material 424 includes a solder paste material.

[0046] Metal clip 160 through Figure 4D The third conductive material 442 is electrically and mechanically connected to the drain 140D of the low-side FET 140. The metal clip 160 is connected to the drain 140D of the low-side FET 140 by Figure 4D The fourth conductive material 444 is electrically and mechanically connected to the source electrode 150S of the high-side FET 150. The metal clip 160 is connected to the source electrode 150S of the high-side FET 150 by Figure 4D The fifth conductive material 446 is electrically and mechanically connected to the end pad 118 of the lead frame 110. In an example of the present disclosure, each of the third conductive material 442, the fourth conductive material 444, and the fifth conductive material 446 includes a solder paste material.

[0047] Interposer 170 through Figure 4F A first adhesive material 468 is shown attached to the top surface of the metal clip 160. In an example of the present disclosure, the first adhesive material 468 includes a non-conductive epoxy.

[0048] IC controller 180 through Figure 4H A second adhesive material 482 is shown attached to the top surface of the interposer 170. In an example of the present disclosure, the second adhesive material 482 includes a non-conductive epoxy.

[0049] In an example of the present disclosure, the interposer 170 includes a lower insulating layer 172 and an upper metal layer 174. In an example of the present disclosure, the interposer 170 has a first rectangular prism shape; the lower insulating layer 172 is a second rectangular prism shape; and the upper metal layer 174 is a third rectangular prism shape. In one example, the lower insulating layer 172 includes polyimide. In one example, the upper metal layer 174 includes copper. In another example, the upper metal layer 174 includes aluminum. In an example of the present disclosure, the thickness of the lower insulating layer 172 is in the range of 0.15 mm to 0.25 mm, and the thickness of the upper metal layer 174 is in the range of 5 micrometers to 15 micrometers.

[0050] In an example of the present disclosure, the semiconductor package 100 further includes a plurality of bonding wires 191 that electrically connect the upper metal layer 174 of the interposer 170 to the first die pad 112 used as the power ground terminal 117 of the lead frame 110. In addition, a plurality of bonding wires 193 electrically connect the IC controller 180 to the lead frame 110. Other metal connections, such as clips or straps, can be used to connect the upper metal layer 174 to the power ground terminal 117. The upper metal layer 174 provides EMI and capacitive shielding for the IC controller 180 stacked thereon, thereby avoiding electrical interference caused by capacitive coupling when the IC controller 180 is directly attached to a clip connected to a high-frequency switch node. In an example of the present disclosure, the low-side FET 140 and the high-side FET 150 are arranged side by side. In one example, the low-side FET 140 is a metal oxide semiconductor field effect transistor (MOSFET). The high-side FET 150 is another MOSFET.

[0051] Figure 2A 2 shows a perspective view of a semiconductor package 200 in an example of the present disclosure, Figure 2B A side view thereof is shown. Figure 2A and Figure 2B The semiconductor package 200 shown is similar to Figure 1A The semiconductor package 100, except Figure 2A and Figure 2B The semiconductor package 200 shown includes a plurality of bond wires 291 electrically connecting an upper metal layer 274 of the interposer 270 to the analog ground terminal 217 of the lead frame 210. The upper metal layer 274 provides EMI and capacitive shielding for an IC controller stacked thereon, thereby avoiding electrical interference due to capacitive coupling when the IC controller is directly attached to a clip connected to a high frequency switch node.

[0052] Figure 3 Flowchart showing a process 300 for developing a power semiconductor package in an example of the present disclosure. Process 300 may begin at block 302. For simplicity, Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Fig. 4I , Figure 4J and Figure 4K It only shows Figure 4L One of two semiconductor packages.

[0053] Reference now Figure 4A , in block 302, a lead frame 410 is provided. The lead frame 410 includes a first die pad 412 located in a middle portion, a second die pad 414 located on a first side of the first die pad 412, and an end pad 418 located on a second side opposite to the first side of the first die pad 412. The first die pad 412 has a first die pad cut corner adjacent to the second die pad 414 to accommodate one or more low-side gate leads extending into the first die pad cut corner. The second die pad 414 has a second die pad cut corner diagonally opposite to the first die pad cut corner to accommodate leads extending into the second die pad cut corner. Block 302 may be followed by block 304.

[0054] Reference now Figure 4B and Figure 4C, in block 304, transistors are connected to die pads, respectively. A first conductive material 422 is applied to the top surface of the first die pad 412 of the lead frame 410. A second conductive material 424 is applied to the top surface of the second die pad 414 of the lead frame 410. The low-side FET 440 is flipped over and attached to the first die pad 412 via the first conductive material 422. The low-side FET 440 includes Figure 1B The source 140S and gate 140G of the low-side FET 440 are located on the top surface. The high-side FET 450 is attached to the second die pad 414 by the second conductive material 424. The high-side FET 450 includes Figure 1B The source electrode 150S and the gate electrode 150G are shown located on the top surface of the high-side FET 450. In an example of the present disclosure, each of the first conductive material 422 and the second conductive material 424 includes a solder paste material. In an example of the present disclosure, the low-side FET 440 and the high-side FET 450 are arranged side by side. In an example, the low-side FET 440 is a MOSFET. The high-side FET 450 is another MOSFET. Block 304 may be followed by block 306.

[0055] Reference now Figure 4D and Figure 4E , in block 306, a metal clip 460 is installed. A third conductive material 442 is applied to the top surface of the low-side FET 440. A fourth conductive material 444 is applied to the top surface of the high-side FET 450. A fifth conductive material 446 is applied to the top surface of the end pad 418. In an example of the present disclosure, each of the third conductive material 442, the fourth conductive material 444, and the fifth conductive material 446 includes a solder paste material. In an example of the present disclosure, the solder paste material contains lead (Pb). The reflow temperature of the solder paste material is greater than 200 degrees Celsius. Install the metal clip 460 to fix the low-side FET 440. Figure 1B The drain 140D shown, and the high-side FET 450 Figure 1B The source electrode 150S shown in FIG. 1 is connected to the first end pad 418 of the lead frame 410. The metal clip 460 includes a horizontal portion 462 and an inclined portion 464. One end of the inclined portion 464 of the metal clip 460 is attached to the end pad 418 of the lead frame 410 through the fifth conductive material 446. Block 306 may be followed by block 308.

[0056] Reference now Figure 4F and 4G, in block 308, an interposer 470 is installed. A first adhesive material 468 is applied to the metal clip 460. In an example of the present disclosure, the first adhesive material 468 includes a non-conductive epoxy. The interposer 470 is installed on the first adhesive material 468. In an example of the present disclosure, the interposer 470 includes an upper metal layer 174 covering the lower insulating layer 172, such as Figure 1B As shown. The interposer 470 covers at least 50% of the top surface of the horizontal portion 462 of the metal clip 460, extending from above the high-side FET 450 to above the low-side FET 440. In a preferred example, the interposer 470 covers at least 75% of the top surface of the horizontal portion 462 of the metal clip 460. In an example of the present disclosure, the interposer 470 has a first rectangular prism shape; the lower insulating layer 172 is a second rectangular prism shape; and the upper metal layer 174 is a third rectangular prism shape. In one example, the lower insulating layer 172 includes polyimide. In one example, the upper metal layer 174 includes copper. In another example, the upper metal layer 174 includes aluminum. In an example of the present disclosure, the thickness of the lower insulating layer 172 is in the range of 0.15 mm to 0.25 mm, and the thickness of the upper metal layer 174 is in the range of 5 microns to 15 microns. Alternatively, the interposer 470 may further include a bottom metal layer (not shown), and the interposer 470 may be attached to the metal clip 460 using a conductive first adhesive material 468. Block 308 may be followed by block 310.

[0057] Reference now Figure 4H and Fig. 4I In block 310, IC controller 480 is mounted on interposer 470. A second adhesive material 482 is applied on interposer 470. In an example of the present disclosure, second adhesive material 482 includes a non-conductive epoxy. IC controller 480 is mounted on the top surface of interposer 470 by second adhesive material 482. Block 310 may be followed by block 312 or block 314.

[0058] Reference now Figure 4J In the optional block 312 (shown by the dotted line), a wire bonding process is applied. A plurality of bonding wires 491 are applied to connect the interposer 470 to the substrate. Figure 1B The upper metal layer 174 is shown electrically connected to the first die pad 412 which serves as the power ground terminal 417 of the lead frame 410. The IC controller 480 is electrically connected to the lead frame 110 using another plurality of bond wires 493.

[0059] In another example, Figure 2A and Figure 2B The plurality of bonding wires 291 shown connect the interposer 470 to the Figure 2A and Figure 2B The upper metal layer 274 is shown electrically connected to the lead frame 410. Figure 2Aand Figure 2B The analog ground terminal 217 is shown. Block 312 may be followed by block 314 .

[0060] Reference now Figure 4K , in block 314, a molded package 490 is formed. The molded package 490 surrounds the low-side FET 440, the high-side FET 450, the metal clip 460, the interposer 470, and the IC controller 480. In one example, the molded package 490 also surrounds the entire lead frame 410. In another example, the molded package 490 also surrounds a majority (greater than 50%) of the lead frame 410, and the bottom surface of the lead frame 410 is exposed from the molded package 490. Block 314 may be followed by block 316.

[0061] Reference now Figure 4L , in block 316, a singulation process is applied along line 499. Semiconductor package 496 is separated from adjacent semiconductor package 498. Although Figure 4L Only two power semiconductor packages are shown, but the number of semiconductor packages to be separated in the same singulation process may be different. In the example of the present disclosure, semiconductor package 496 and semiconductor package 498 are power semiconductor packages.

[0062] Those skilled in the art will recognize that modifications to the embodiments disclosed herein are possible. For example, the number of chips in the semiconductor package may vary. Other modifications may be made by those skilled in the art, and all such modifications are considered to fall within the scope of the invention as defined by the claims.

Claims

1. A semiconductor package, characterized in that: include: A lead frame consists of a first die pad; as well as a second die pad; a low-side FET flipped over and attached to the first die pad, the low-side FET including a source electrode and a gate electrode on a top surface of the low-side FET; as well as a drain electrode on the bottom surface of the low-side FET; A high-side FET is connected to the second die pad, the high-side FET comprising a source electrode and a gate electrode on a top surface of the high-side FET; as well as a drain electrode on the bottom surface of the high-side FET; a metal clip connecting the drain electrode of the low-side FET to the source electrode of the high-side FET; an interposer attached to a top surface of the metal clip, the interposer comprising an insulating layer and an upper metal layer above the insulating layer; an IC controller attached to the top surface of the interposer; and A molded package that encapsulates the low-side FET, high-side FET, metal clip, interposer, and IC controller.

2. The semiconductor package according to claim 1, wherein: The intermediary layer also includes A lower metal layer is provided below the insulating layer.

3. The semiconductor package according to claim 1, wherein: Also includes An electrical connection electrically connects the upper metal layer of the interposer to the power ground terminal.

4. The semiconductor package according to claim 1, wherein: Also includes An electrical connection electrically connects the upper metal layer of the interposer to the analog ground terminal.

5. The semiconductor package according to claim 3 or 4, wherein: The electrical connections include a plurality of bond wires.

6. The semiconductor package according to claim 1, wherein: Also includes A plurality of bonding wires electrically connect the IC controller to the lead frame.

7. The semiconductor package according to claim 1, wherein: The low-side FET is a MOSFET; and The high-side FET is another MOSFET.

8. The semiconductor package according to claim 1, wherein: The interposer covers at least 50% of a top surface of the metal clip.

9. The semiconductor package according to claim 1, wherein: The interposer covers at least 75% of a top surface of the metal clip.

10. The semiconductor package according to claim 1, wherein: The first die pad has a first die pad cut corner adjacent to the second die pad to accommodate one or more low-side gate leads extending into the first die pad cut corner; and The second die pad has a second die pad cut corner diagonally opposite to the first die pad cut corner to accommodate leads extending into the second die pad cut corner.

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