Active short-circuit protection circuit, method and chip
By designing an active short circuit protection circuit, using the combination of hardware logic gates and buffers to realize the control of fault logic, the problem of slow response speed of the motor controller and inability to enter the active short circuit safety state in the prior art is solved, and the response speed and reliability of the motor controller are improved.
Patent Information
- Application Number
- CN202510044889.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-10
- Publication Date
- 2025-03-14
AI Technical Summary
In the prior art, the motor controller responds slowly when it fails, and cannot enter the safe state of active short circuit when the MCU fails, which poses a safety hazard.
An active short circuit protection circuit is designed to control the fault logic through the combination of hardware logic gate and buffer, improve the response speed, and set up a fault detection module in the motor controller to control the motor to enter the corresponding safe mode according to the fault type and motor speed.
It improves the response speed and reliability of the motor controller in case of fault conditions, ensures that the motor can safely enter the active short circuit state, and avoids harm to the driver and passengers.
Smart Images
Figure CN119627803A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of new energy vehicle technology, and in particular to an active short-circuit protection circuit, method and chip. Background Art
[0002] The motor is the main power source of electric vehicles. When the motor control system fails, it needs to be put into a safe state to ensure that the vehicle does not cause harm to the driver and passengers after being controlled. When the motor controller has a hardware or software failure and the motor output is abnormal, it is very dangerous whether it is outputting braking torque or driving torque. In the related technology, software is used for logical judgment. Due to the influence of the MCU's computing speed, there is a certain delay in the response speed; in addition, when the MCU fails, the motor will not be able to enter the safe state of active short circuit.
[0003] It should be noted that the statements herein merely provide background information related to the present application and do not necessarily constitute prior art. Summary of the invention
[0004] In view of the above problems, the present application proposes an active short circuit protection circuit, method and chip that overcome the above problems or at least partially solve the above problems.
[0005] The present application embodiment adopts the following technical solutions:
[0006] In a first aspect, an embodiment of the present application provides an active short-circuit protection circuit, which includes: a motor controller, a lower bridge arm fault status confirmation module and an upper bridge arm fault status confirmation module, wherein the motor controller is used to confirm at least one fault module of the lower bridge arm fault status confirmation module and the upper bridge arm fault status confirmation module according to the type of fault triggered, and control the motor connected to the motor controller to enter a corresponding safety mode according to the fault module.
[0007] Preferably, the lower bridge arm fault status confirmation module includes a first OR logic gate, a second OR logic gate, a third OR logic gate, a first NAND logic gate and a second NAND logic gate, the outputs of the first OR logic gate and the second OR logic gate are connected to the input of the first NAND logic gate, the output of the first NAND logic gate is connected to the second input of the third OR logic gate, the output of the third OR logic gate is connected to the first input of the second NAND logic gate, the first inputs of the first OR logic gate, the second OR logic gate and the third OR logic gate are respectively connected to the first fault pin, the second fault pin and the third fault pin, and the second inputs of the first OR logic gate and the second OR logic gate are connected to the fourth fault pin.
[0008] Preferably, the upper bridge arm fault status confirmation module includes a fourth OR logic gate, a fifth OR logic gate, a first AND logic gate and a second AND logic gate, the outputs of the fourth OR logic gate and the fifth OR logic gate are connected to the input of the first AND logic gate, the outputs of the first AND logic gate are respectively connected to the second input of the second AND logic gate and the second input of the second NAND logic gate, the first inputs of the fourth OR logic gate and the fifth OR logic gate are respectively connected to the fifth fault pin and the sixth fault pin, the second inputs of the fourth OR logic gate and the fifth OR logic gate are connected to the fourth fault pin, and the first input of the second AND logic gate is connected to the output of the first NAND logic gate.
[0009] Preferably, the protection circuit further comprises a first buffer and a second buffer, and the outputs of the second NAND logic gate and the second AND logic gate are respectively connected to corresponding pins of the first buffer and the second buffer. The protection circuit further comprises a trigger, and the outputs of the second NAND logic gate and the second AND logic gate are respectively connected to corresponding pins of the trigger.
[0010] Preferably, the protection circuit also includes a third AND logic gate, a third NAND logic gate and a third buffer, the two input ends of the third AND logic gate are respectively connected to the corresponding pins of the trigger, the output end of the third AND logic gate is connected to the first input of the third NAND logic gate, and the output of the third NAND logic gate is connected to the corresponding pin of the third buffer.
[0011] In the second aspect, the embodiment of the present application also provides an active short-circuit protection method, including an active short-circuit protection circuit as described in any one of the first aspects, and the method includes: a motor controller monitors the lower bridge arm combined fault state and the upper bridge arm combined fault state of the power module, wherein the lower bridge arm combined fault includes the lower bridge arm protection withdrawal and fault and the lower bridge arm undervoltage fault, and the upper bridge arm combined fault includes the upper bridge arm protection withdrawal and fault and the upper bridge arm undervoltage fault; when one of the lower bridge arm protection withdrawal and fault and the lower bridge arm undervoltage fault is a low level, the first safety mode entered by the motor is confirmed according to the motor speed and the upper bridge arm fault state at the moment of the fault; when one of the upper bridge arm protection withdrawal and fault and the upper bridge arm undervoltage fault is a low level, the second safety mode entered by the motor is confirmed according to the motor speed and the lower bridge arm fault state at the moment of the fault.
[0012] Preferably, the first safety mode includes a three-phase open circuit safety mode and an upper bridge arm active short circuit safety mode, and the second safety mode includes a three-phase open circuit safety mode and a lower bridge arm active short circuit safety mode; when one of the lower bridge arm withdrawal and fault and the lower bridge arm undervoltage fault is a low level, according to the motor speed and the upper bridge arm fault state at the time of the fault, confirming that the motor enters the first safety mode, including: when the motor speed exceeds the threshold and the upper bridge arm is not faulty, the motor enters the upper bridge arm active short circuit safety mode; when the motor speed exceeds the threshold and the upper bridge arm fails, the motor enters the three-phase open circuit safety mode; when one of the upper bridge arm withdrawal and fault and the upper bridge arm undervoltage fault is a low level, according to the motor speed and the lower bridge arm fault state at the time of the fault, confirming that the motor enters the second safety mode, including: when the motor speed exceeds the threshold and the lower bridge arm is not faulty, the motor enters the lower bridge arm active short circuit safety mode; when the motor speed exceeds the threshold and the lower bridge arm fails, the motor enters the three-phase open circuit safety mode.
[0013] Preferably, the method further comprises: the motor controller monitors MCU fault and overvoltage fault; when one of the MCU fault and the overvoltage fault is at a low level: if the lower bridge arm has no fault, the motor enters the lower bridge arm active short circuit safety mode; if the lower bridge arm has a fault and the upper bridge arm has a fault at the same time, the motor enters the three-phase open circuit safety mode; if the lower bridge arm has a fault and the upper bridge arm has no fault at the same time, the motor enters the upper bridge arm active short circuit safety mode;
[0014] In a third aspect, an embodiment of the present application further provides a chip, comprising a protection circuit as described in any one of the first aspects.
[0015] At least one of the above technical solutions adopted in the embodiments of the present application can achieve the following beneficial effects:
[0016] The present application uses a combination of hardware logic gates and buffers, does not rely on software control, sets a switching dead zone during the switching process, implements fault logic control, and improves response speed.
[0017] The above description of the technical solution of the present application is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:
[0019] Figure 1 This is a block diagram of an active short-circuit protection circuit in an embodiment of the present application;
[0020] Figure 2 This is a circuit diagram of an active short-circuit protection circuit in an embodiment of the present application;
[0021] Figure 3 This is a logical diagram of the active short-circuit protection method in an embodiment of the present application. DETAILED DESCRIPTION
[0022] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.
[0023] The technical terms involved in this application are as follows:
[0024] The idea of the present application is to design an automatic and universal active short-circuit protection circuit in response to the current situation in which active short-circuit is realized by application software in the prior art with large delay and low efficiency. The circuit uses simple hardware logic gates to realize the active short-circuit state, thereby improving the response speed and reliability.
[0025] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.
[0026] The present application embodiment provides an active short circuit protection circuit, such as Figure 1 As shown, a block diagram 100 of an active short-circuit protection circuit in an embodiment of the present application is provided. The protection circuit comprises: a motor controller 110, a lower bridge arm fault state confirmation module 120 and an upper bridge arm fault state confirmation module 130, wherein a controller fault detection module is provided in the motor controller, and the motor controller is used to confirm at least one fault module of the lower bridge arm fault state confirmation module and the upper bridge arm fault state confirmation module according to the triggered fault type, and according to the fault module, control the motor 140 connected to the motor controller to enter the corresponding safety mode.
[0027] like Figure 3As shown, the fault types include upper bridge arm failure and failure of the power module, upper bridge arm undervoltage failure of the power module, lower bridge arm failure and failure of the power module, lower bridge arm undervoltage failure of the power module, MCU failure and overvoltage failure. When upper and lower bridge arm related faults occur, it is determined whether to enter the active short-circuit safety mode based on the vehicle speed at the time of the fault. If the speed is in the mode where active short-circuit is required, the three-phase short-circuit state of the lower bridge arm is entered first. If the power module of the lower bridge arm fails, it automatically switches to the three-phase active short-circuit state of the upper bridge arm. In the process of switching between the upper and lower bridge arms, a dead zone is added to prevent the upper and lower bridge arms from passing through. If both the upper and lower bridge arms are in a faulty state, the six-phase open circuit state is entered.
[0028] It can be understood that the fault handling of the active protection circuit meets the functional safety requirements of new energy vehicles at the moment of motor driver failure, does not require software participation, and has good real-time and reliability.
[0029] In some embodiments, the lower bridge arm fault status confirmation module includes a first OR logic gate U1, a second OR logic gate U2, a third OR logic gate U3, a first NAND logic gate A1 and a second NAND logic gate A2, the outputs of the first OR logic gate U1 and the second OR logic gate U2 are respectively connected to the inputs of the first NAND logic gate A1, the output of the first NAND logic gate A1 is connected to the second input of the third OR logic gate U3, the output of the third OR logic gate U3 is connected to the first input of the second NAND logic gate A2, the first inputs of the first OR logic gate U1, the second OR logic gate U2 and the third OR logic gate U3 are respectively connected to the first fault pin F_DS_BOT, the second fault pin and the third fault pin F_UN_BOT, and the second inputs of the first OR logic gate U1 and the second OR logic gate U2 are connected to the fourth fault pin SPD_SW.
[0030] like Figure 2 As shown, F_DS_BOT is the lower bridge arm warranty and fault pin, F_UN_BOT is the lower bridge arm undervoltage fault pin, SPD_SW is the speed input pin, and the third fault pin of the third OR logic gate U3 includes two fault types, MCU fault ACTIVE SHORT and overvoltage fault F_HV_OV.
[0031] In some embodiments, the upper bridge arm fault status confirmation module includes a fourth OR logic gate U4, a fifth OR logic gate U5, a first AND logic gate B1 and a second AND logic gate B2, the outputs of the fourth OR logic gate U4 and the fifth OR logic gate U5 are respectively connected to the input of the first AND logic gate B1, the outputs of the first AND logic gate B1 are respectively connected to the second input of the second AND logic gate B2 and the second input of the second NAND logic gate A2, the first inputs of the fourth OR logic gate U4 and the fifth OR logic gate U5 are respectively connected to the fifth fault pin F_DS_TOP and the sixth fault pin F_UV_TOP, the second inputs of the fourth OR logic gate U4 and the fifth OR logic gate U5 are connected to the fourth fault pin SPD_SW, and the first input of the second AND logic gate B2 is connected to the output of the first NAND logic gate A1.
[0032] like Figure 2 As shown, F_DS_TOP is the upper arm protection and fault pin, and F_UN_TOP is the upper arm undervoltage fault pin.
[0033] It can be understood that, through the operation of logic gates in the lower bridge arm fault state confirmation module and the upper bridge arm fault state confirmation module, six types of faults and three states can be combined to implement the execution of the fault logic.
[0034] In some embodiments, the protection circuit also includes a first buffer D1 and a second buffer D2, and the outputs of the second NAND logic gate A2 and the second AND logic gate B2 are respectively connected to the corresponding pins (Force_Uppers_ON, Force_Lowers_ON) of the first buffer D1, the corresponding pins (Force_Lowers_ON, Force_Uppers_ON) of the second buffer D2, and the corresponding pins of the third buffer D3.
[0035] The protection circuit also includes a trigger T1, and the outputs of the second NAND logic gate A2 and the second AND logic gate B2 are respectively connected to the corresponding pins of the trigger T1. The trigger T1 is used to add a dead zone during the switching process of the upper and lower bridge arms to prevent the upper and lower bridge arms from being directly connected.
[0036] In some embodiments, the protection circuit further includes a third AND logic gate B3, a third NAND logic gate A3 and a third buffer D3, wherein the two input ends of the third AND logic gate B3 are respectively connected to the corresponding pins (3, 10) of the trigger, the output end of the third AND logic gate B3 is connected to the first input of the third NAND logic gate A3, and the output of the third NAND logic gate A3 is connected to the corresponding pins (1, 19) of the third buffer D3. The third AND logic gate B3 and the third NAND logic gate A3 are used to enable the active protection circuit.
[0037] It can be understood that the active short-circuit protection circuit of the present disclosure is composed of five OR gates, three AND gates, three NAND gates, three buffers and a trigger. Through the operation of the logic gate, six faults and three states are combined, and the dead zone circuit of the trigger is matched to ensure the direct connection problem of the upper and lower bridge arms during the switching process of the upper and lower bridge arms.
[0038] The disclosed embodiment also provides an active short-circuit protection method, including the active short-circuit protection circuit as described above, the method comprising: a motor controller monitors a lower bridge arm combined fault state and an upper bridge arm combined fault state of a power module, wherein the lower bridge arm combined fault includes a lower bridge arm protection withdrawal and fault and a lower bridge arm undervoltage fault, and the upper bridge arm combined fault includes an upper bridge arm protection withdrawal and fault and an upper bridge arm undervoltage fault; when one of the lower bridge arm protection withdrawal and fault and the lower bridge arm undervoltage fault is at a low level, the first safety mode entered by the motor is confirmed according to the motor speed and the upper bridge arm fault state at the moment of the fault; when one of the upper bridge arm protection withdrawal and fault and the upper bridge arm undervoltage fault is at a low level, the second safety mode entered by the motor is confirmed according to the motor speed and the lower bridge arm fault state at the moment of the fault.
[0039] The first safety mode includes a three-phase open circuit safety mode and an upper bridge arm active short circuit safety mode, and the second safety mode includes a three-phase open circuit safety mode and a lower bridge arm active short circuit safety mode; when one of the lower bridge arm withdrawal and fault and the lower bridge arm undervoltage fault is a low level, according to the motor speed and the upper bridge arm fault state at the time of the fault, confirming that the motor enters the first safety mode, including: when the motor speed exceeds the threshold and the upper bridge arm has no fault, the motor enters the upper bridge arm active short circuit safety mode; when the motor speed exceeds the threshold and the upper bridge arm fails, the motor enters the three-phase open circuit safety mode; when one of the upper bridge arm withdrawal and fault and the upper bridge arm undervoltage fault is a low level, according to the motor speed and the lower bridge arm fault state at the time of the fault, confirming that the motor enters the second safety mode, including: when the motor speed exceeds the threshold and the lower bridge arm has no fault, the motor enters the lower bridge arm active short circuit safety mode; when the motor speed exceeds the threshold and the lower bridge arm fails, the motor enters the three-phase open circuit safety mode.
[0040] The active short-circuit protection method also includes: the motor controller monitors MCU faults and overvoltage faults; when one of the MCU faults and the overvoltage faults is at a low level: if the lower bridge arm has no faults, the motor enters the lower bridge arm active short-circuit safety mode; if the lower bridge arm fails and the upper bridge arm fails at the same time, the motor enters the three-phase open circuit safety mode; if the lower bridge arm fails and the upper bridge arm has no faults, the motor enters the upper bridge arm active short-circuit safety mode.
[0041] It can be understood that the motor controller monitors relevant faults in real time, and combines the power module's withdrawal and failure, the power module's undervoltage fault, the MCU and overvoltage fault into six fault combinations. At the same time, it determines whether to enter the active short-circuit safety mode based on the vehicle speed at the time of the fault. If the speed is in the mode that requires active short-circuit, it will first enter the three-phase short-circuit state of the lower bridge arm. If the power module of the lower bridge arm fails, it will automatically switch to the three-phase active short-circuit state of the upper bridge arm. At the same time, a dead zone is added during the switching process of the upper and lower bridge arms to prevent the upper and lower bridge arms from passing through. If both the upper and lower bridge arms are in a faulty state, the six-phase open circuit state is entered. The fault logic meets the functional safety requirements of new energy vehicles at the time of motor driver failure, does not require software participation, and has a high degree of real-time and reliability.
[0042] The present application also provides a chip, including the active short circuit protection circuit as described above. The present application also provides a motor, including the chip as described above. For other parts of the motor, please refer to the prior art and will not be described here.
[0043] It should be noted that, in the description of this application, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "plurality" is two or more.
[0044] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0045] In the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, and “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.
[0046] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.
[0047] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
[0048] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.
Claims
1. An active short circuit protection circuit, characterized in that: The protection circuit comprises: a motor controller, a lower bridge arm fault state confirmation module and an upper bridge arm fault state confirmation module, wherein the motor controller is used to According to the triggered fault type, confirm at least one fault module of the lower bridge arm fault state confirmation module and the upper bridge arm fault state confirmation module, According to the fault module, the motor connected to the motor controller is controlled to enter a corresponding safety mode.
2. The protection circuit according to claim 1, characterized in that: The lower bridge arm fault state confirmation module includes a first OR logic gate, a second OR logic gate, a third OR logic gate, a first NAND logic gate and a second NAND logic gate. The outputs of the first OR logic gate and the second OR logic gate are connected to the input of the first NAND logic gate, The output of the first NAND logic gate is connected to the second input of the third OR logic gate, The output of the third OR logic gate is connected to the first input of the second NAND logic gate, The first inputs of the first OR logic gate, the second OR logic gate and the third OR logic gate are connected to the first fault pin, the second fault pin and the third fault pin respectively. The second inputs of the first OR logic gate and the second OR logic gate are connected to the fourth fault pin.
3. The protection circuit according to claim 2, characterized in that: The upper bridge arm fault state confirmation module includes a fourth OR logic gate, a fifth OR logic gate, a first AND logic gate and a second AND logic gate. The outputs of the fourth OR logic gate and the fifth OR logic gate are connected to the input of the first AND logic gate, The output of the first AND logic gate is connected to the second input of the second AND logic gate and the second input of the second NAND logic gate respectively. The first inputs of the fourth OR logic gate and the fifth OR logic gate are connected to the fifth fault pin and the sixth fault pin respectively. The second inputs of the fourth OR logic gate and the fifth OR logic gate are connected to the fourth fault pin, A first input of the second AND logic gate is connected to an output of the first NAND logic gate.
4. The protection circuit according to claim 3, characterized in that: The protection circuit further includes a first buffer and a second buffer. Outputs of the second NAND logic gate and the second AND logic gate are connected to corresponding pins of the first buffer and the second buffer, respectively.
5. The protection circuit according to claim 4, characterized in that: The protection circuit further includes a trigger, Outputs of the second NAND logic gate and the second AND logic gate are respectively connected to corresponding pins of the trigger.
6. The protection circuit according to claim 5, characterized in that: The protection circuit further includes a third AND logic gate, a third NAND logic gate and a third buffer. The two input terminals of the third AND logic gate are respectively connected to the corresponding pins of the trigger, The output end of the third AND logic gate is connected to the first input of the third NAND logic gate, The output of the third NAND logic gate is connected to the corresponding pin of the third buffer.
7. An active short circuit protection method, characterized in that: The active short circuit protection circuit according to any one of claims 1 to 6, wherein the method comprises: The motor controller monitors the combined fault state of the lower bridge arm and the combined fault state of the upper bridge arm of the power module, wherein the combined fault of the lower bridge arm includes the lower bridge arm warranty withdrawal and failure and the lower bridge arm undervoltage fault, and the combined fault of the upper bridge arm includes the upper bridge arm warranty withdrawal and failure and the upper bridge arm undervoltage fault; When one of the lower bridge arm failure and undervoltage failure is at a low level, the first safety mode entered by the motor is confirmed according to the motor speed at the time of the failure and the upper bridge arm failure state; When one of the upper bridge arm protection withdrawal and fault and the upper bridge arm undervoltage fault is at a low level, the second safety mode entered by the motor is confirmed according to the motor speed and the lower bridge arm fault state at the time of the fault.
8. The active short circuit protection method according to claim 7, characterized in that: The first safety mode includes a three-phase open circuit safety mode and an upper bridge arm active short circuit safety mode, and the second safety mode includes a three-phase open circuit safety mode and a lower bridge arm active short circuit safety mode; When one of the lower bridge arm failure and the lower bridge arm undervoltage failure is at a low level, according to the motor speed at the time of the failure and the upper bridge arm failure state, confirming that the motor enters the first safety mode includes: When the motor speed exceeds a threshold and the upper bridge arm has no fault, the motor enters the upper bridge arm active short circuit safety mode; When the motor speed exceeds a threshold and the upper bridge arm fails, the motor enters the three-phase open circuit safety mode; When one of the upper bridge arm failure and the upper bridge arm undervoltage failure is at a low level, according to the motor speed at the time of the failure and the lower bridge arm failure state, confirming that the motor enters the second safety mode includes: When the motor speed exceeds a threshold and the lower bridge arm has no fault, the motor enters the lower bridge arm active short circuit safety mode; When the motor speed exceeds a threshold and the lower bridge arm fails, the motor enters the three-phase open circuit safety mode.
9. The active short circuit protection method according to claim 8, characterized in that: The method further comprises: The motor controller monitors MCU faults and overvoltage faults; When one of the MCU fault and the overvoltage fault is low: If the lower bridge arm has no fault, the motor enters the lower bridge arm active short circuit safety mode; If the lower bridge arm fails and the upper bridge arm fails at the same time, the motor enters the three-phase open circuit safety mode; If the lower bridge arm fails and the upper bridge arm is not faulty, the motor enters the upper bridge arm active short-circuit safety mode.
10. A chip, characterized in that: Comprising a protection circuit as claimed in any one of claims 1-6.