Time-based converter device and corresponding method

Abstract

The invention relates to a time-based converter device and a corresponding method. The time-based DC-DC converter is controlled in response to a first oscillator signal based on the first control signal, a second oscillator signal based on the second control signal, and a controlled current based on the feedback control signal. The first control signal and the second control signal are a function of the controlled current. The feedback control signal is generated from the first oscillator signal and the second oscillator signal by: generating at least two binary signals including a first binary signal based on a difference between the first oscillator signal and a reference signal and a second binary signal based on a difference between the second oscillator signal and the reference signal; and generating, via the charge pump, a feedback control signal based on the first binary signal and the second binary signal.

Description

[0001] Priority claim

[0002] This application claims the benefit of priority from Italian Patent Application No. 102023000018765, filed on September 13, 2023, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present description relates to a converter arrangement.

[0004] One or more embodiments may be applied to a time-based DC-DC converter. Background Art

[0005] A DC-DC converter is an electronic circuit that can convert a direct current (DC) source from a first voltage level to a second voltage level, operating as a power converter.

[0006] Typically, a DC-DC converter includes a pair of switching transistors, such as power switches, driven by a pulse width modulation (PWM) control signal.

[0007] A time-based DC-DC converter is a DC-DC converter with a time-based control loop that is configured to use the occurrence of rising / falling edges of a binary signal to generate a control signal, such as a PWM signal, fed to a driver of a power switch.

[0008] Figure 1 An exemplary circuit 10 for generating a PWM signal for use in a control loop of a time-based DC-DC converter is illustrated.

[0009] It is noted that in the reference numerals used for the drawings described herein, the subscript R stands for “reference” and the subscript F stands for “feedback”.

[0010] Figure 1 The illustrated exemplary circuit is configured to generate a pulse width modulation (PWM) signal D having a given duty cycle using a phase detector PD. PWM .

[0011] The phase detector PD is configured to receive a pair of input signals through its input terminals and to generate a PWM signal D at its output terminals according to the difference between the phases of the two received input signals. PWM , that is, the signal with the corresponding phase Φ received at the first input terminal R,PID The first delayed input signal S R,PID and received at the second input terminal with a corresponding phase Φ F,PID The second delayed input signal S F,PID .

[0012] The first delayed input signal S R,PID The first current controlled delay line CCDL R Generating, the first current controlled delay line CCDL R is configured to delay the current controlled oscillator CCO from the first R The received signal with the corresponding phase Φ R,I The first input signal S R,I To generate this first delayed input signal S R,PID This delay operation is based on the proportional and differential transconductor (such as a transconductance amplifier) ​​G MPD The first output terminal receives the first control signal to perform, for example, by delaying equal to t d,CCDLr The first time delay of this first input signal S R,I (See Figure 2 ).

[0013] Similarly, the second delayed input signal S F,PID The second current controlled delay line CCDL F The second current controlled delay line CCDL is generated F is configured to delay the second current controlled oscillator CCO by F The received signal with the corresponding phase Φ F,I The second input signal S F,I To generate this second delayed input signal S F,PID , this delay operation is based on the proportional and differential transconductor G MPD The second output terminal receives the second control signal to perform, for example, a delay equal to t d,CCDLf The second time delay of this second input signal S F,I (See Figure 2 ).

[0014] A current controlled oscillator (CCO) is usually configured to generate a signal having a specific frequency, thus: a first current controlled oscillator CCO R is configured to generate a first input signal S R,I , whose frequency is determined by the transconductance amplifier G in the integration path. MI The first output terminal receives a first control signal to determine; and the second current controlled oscillator CCO F is configured to generate a second input signal S F,I , whose frequency is determined by the transconductor G on the integral path. MI The second output terminal of the controller receives a second control signal.

[0015] It is noted that such current controlled oscillators (CCOs) are configured to act as integrators in the phase domain, and therefore, they are configured to perform an integrating action (ie, integral control) on a signal received as input.

[0016] Therefore, it should be noted that the transconductor (such as the transconductor G on the integration path) MI ) may not perform any integration actions.

[0017] This integration action can be achieved by using the transconductor G in the integration path. MI and a current controlled oscillator CCO (from the transconductor input to the current controlled oscillator CCO output in the phase domain), thereby obtaining a voltage controlled oscillator (VCO).

[0018] Therefore, this integration action can be performed by the current controlled oscillator CCO, while the transconductor (such as the transconductor G in the integration path) MI ) can be considered as a simple scaling and / or conversion block, i.e., constant and independent of frequency.

[0019] Transconductor G M It is usually configured to generate a pair of signals, such as a pair of current signals, based on a voltage difference calculated by a first voltage level received at the non-inverting terminal and a second voltage level received at the inverting terminal. MPD is configured to set its non-inverting terminal to a reference voltage V REF , and sets its inverting terminal to the voltage V D , the voltage V D The differential side capacitor C D The voltage measured on this differential side capacitor C D is coupled to receive the output voltage V OUT terminals (i.e., the voltage supplied by the converter to which the exemplary circuit 10 is coupled) and through the differential side resistor R D Coupled to this reference voltage V REF terminals (thus obtaining a differential side capacitor C D And this differential side resistor R D In addition, the transconductor G on the integral path MI is configured to set its non-inverting terminal to a reference voltage V REF , and sets its inverting terminal to the received output voltage V OUT .

[0020] It should be noted that, with this differential side capacitor C D And this differential side resistor R D The filter composed of the first current controlled delay line CCDLR and the second current controlled delay line CCDL F It is typically configured to perform proportional and derivative actions (ie, proportional and derivative control) on the signal received as input.

[0021] Therefore, the general transfer function of the proportional-integral-derivative (PID) compensator (ie, the transfer function obtained by processing the input signal with the current-controlled oscillator CCO and the current-controlled delay line CCDL) is:

[0022]

[0023] in is a ratiometric and differential transconductor G MPD The transfer function, K CCDL is the transfer function of the current controlled delay line CCDL, is the transconductor G on the integration path MI The transfer function of K CCO is the transfer function of the current controlled oscillator CCO.

[0024] Note that, as described previously, the transconductor G in the integrating path MI The combination with a current controlled oscillator CCO may result in a voltage controlled oscillator (VCO), ie an oscillator receiving an input voltage and being configured to convert this input voltage into a phase / frequency at the output.

[0025] Similarly, the ratiometric and differential transconductor G MPD The combination with a controlled delay line CCDL may result in a voltage controlled delay line (VCDL), ie a delay line which receives an input voltage and is configured to perform a delay operation depending on this input voltage.

[0026] Therefore, the transfer function described previously can also be expressed as:

[0027]

[0028] Where K VCDL is the transfer function of the defined voltage-controlled delay line VCDL, that is, And K VCO is the transfer function of the voltage controlled oscillator VCO defined as,

[0029] Figure 1 The circuit is usually operated in its steady state condition, because the received output voltage V OUT The feedback generated (ie, the voltage supplied by the converter to which the exemplary circuit 10 is coupled as a control loop and for generating the PWM signal D PWMThe feedback obtained by the input of the exemplary circuit 10) forces (such as Figure 2 Figure 1): first current controlled oscillator CCO R The first input signal S generated R,I and the second current controlled oscillator CCO F The generated second input signal S F,I The frequency is equal; and the delay line CCDL is controlled by the first current R The first time delay introduced is t d,CCDLr and a second current controlled delay line CCDL F The second time delay t introduced d,CCDLf equal.

[0030] Figure 2 Pictured Figure 1 Example behavior of some signals of a circuit operating under steady-state conditions.

[0031] Figure 2 The first input signal S R,I and the second input signal S F,I , they are binary signals, i.e., signals that have only two states, such as a high logic level and a low logic level.

[0032] This first input signal S R,I And this second input signal S F,I The phase difference ΔΦ between R,I-F,I can be defined as a wave (for example, the second input signal S F,I ) leads another wave (such as this first input signal S) in radians (i.e., an angle called one cycle). R,I ), therefore, as the first input signal Φ R,I The phase of the second input signal Φ F,I The phase difference between .

[0033] Therefore, this first input signal S R，I And this second input signal S F，I The first current controlled delay line CCDL R The delay is equal to t d,CCDLr The amount and the second current controlled delay line CCDL F The delay is equal to t d，CCDLf The amount of the first delayed input signal S R，PID and the second delayed input signal S F，PID .

[0034] It should be noted that in the steady state, due to the first current controlling the delay line CCDL R The first time delay introduced is td，CCDLr and a second current controlled delay line CCDL F The second time delay t introduced d，CCDLf equal, so as the first delayed input signal Φ R，PID The phase and second delayed input signal Φ F，PID The first delayed input signal S is obtained by the phase difference between R，PID And this second delayed input signal S F，PID The phase difference ΔΦ between the first input signal S R，I With this second input signal S F，I The phase difference ΔΦ between R，I-F，I .

[0035] Note that even in the presence of non-ideal conditions, for example when there is a first time delay t d，CCDLr Not equal to the second time delay t d，CCDLf When the first delayed input signal S R，PID And this second delayed input signal S F，PID The phase difference ΔΦ between the two can also be equal to the first input signal S R，I With this second input signal S F，I The phase difference ΔΦ between R，I-FI .

[0036] In fact, under steady-state conditions, the DC-DC converter loop is closed, that is, the time-based control loop is closed, so the output regulation may apply a certain PWM signal D PWM and the exact ΔΦ=Φ R，P I D -Φ F，P I D .

[0037] Therefore, at the first time delay t d，CCDL r and second time delay t d，CCDLf When there is a residual mismatch between them, the resulting effect in the phase domain can be compensated by an integrating action performed by a defined voltage controlled oscillator VCO which temporarily accumulates action to correct the error in the phase domain, resulting in:

[0038] ΔΦ=Φ R，PID -Φ F，PID =Φ R，I -Φ F，I =ΔΦ R，I-F，I

[0039] Therefore, in response to Figure 1 The circuit operates in steady state, the PWM signal D PWM The first delayed input signal S is determined according to the following equationR，PID and the second delayed input signal S F，PID The phase difference between the first input signal S R，I and the second input signal S F，I The phase difference between

[0040] ΔΦ=Φ R，PID -Φ F，PID =Φ R，I -Φ F，I =ΔΦ R，-F，I

[0041]

[0042] And, if the DC-DC converter is a DC-DC buck converter, the following equation can also be considered:

[0043]

[0044] Where V IN is the value of the voltage supplied to the half-bridge (HS; LS) coupled to the output terminals of such a phase detector PD (see Figure 3 ).

[0045] Figure 3 An exemplary time-based DC-DC converter 20, such as a DC-DC buck converter, is illustrated whose control loop includes circuitry for generating a PWM signal.

[0046] For example, Figure 3 The time-based DC-DC converter 20 is configured to supply an output voltage V to a load coupled thereto. OUT , this output voltage V OUT is an output capacitor C coupled between ground GND and the inductor L (ie, the coil of the DC-DC converter). O The voltage measured on the

[0047] This output capacitor C O The inductor L is alternately charged and discharged by a current flowing in the inductor L, the sign of which is determined according to the phase detector PD (e.g. Figure 1 The PWM signal D provided by the phase detector PWM And changes.

[0048] Therefore, such an inductor L is coupled to two switches, which are configured to implement a half-bridge structure and respond to the PWM signal D PWM The state of the signal is changed (eg, from a high logic level to a low logic level, or vice versa) to commute.

[0049] The high-side switch HS is coupled to a supply with a value V IN The voltage of the terminal and the inductor L (ie, the first node LX), and is configured, for example, when the PWM signal D PWM At a high logic level, the PWM signal D PWM Disconnected at low logic level.

[0050] The low-side switch LS is coupled between the inductor L (ie, the first node LX) and the ground GND, and is configured, for example, to PWM At a low logic level, the PWM signal D PWM Disconnected at high logic level.

[0051] PWM signal D PWM Provided by the phase detector PD to the half-bridge structure, such as Figure 1 The phase detector PD is configured to receive a pair of input signals through its input terminals and generate a PWM signal D at its output terminals according to the difference between the phases of the two received input signals. PWM ,For example Figure 1 The signal already described in , i.e., with the corresponding phase Φ R，PID The first delayed input signal S R，PID and with corresponding phase Φ F,PID The second delayed input signal S F,PID .

[0052] exist Figure 3 In the structure of Figure 1 Ratiometric and differential transconductors G MPD is implemented using a pair of transconductors (because this implementation may benefit from structural symmetry and greater freedom, such as the transfer function of ratiometric and differential transconductors May be different from the integral path Transconductor G MI The transfer function of

[0053] Differential transconductor (transconductance amplifier) ​​G MD , is configured to set its non-inverting terminal to the reference voltage V REF , and sets its inverting terminal to the voltage V D , the voltage V D The capacitor C is on the differential side D The voltage measured on the Figure 1 The differential side capacitor, the differential side capacitor C D is coupled to receive (feedback) the output voltage V OUT terminals and through the differential side resistor R DCoupled to this reference voltage V REF terminals (thus obtaining a differential side capacitor C D And this differential side resistor R D ), and

[0054] Proportional transconductance amplifier G MP , is configured to set its non-inverting terminal to the reference voltage V REF , and sets its inverting terminal to the feedback voltage V FB , the feedback voltage V FB is the resistor in the second voltage divider R D2 On the measured voltage, the second voltage divider resistor R D2 is coupled to ground G ND terminals and through the first voltage divider resistor R D1 Receive (feedback) output voltage V OUT terminals (therefore choose this output voltage V OUT The second voltage divider resistor R D2 part above).

[0055] Differential transconductor G MD and proportional transconductor G MP The negative output terminals of are coupled together, for example by connecting such negative terminals directly together.

[0056] Similarly, the differential transconductor G MD and proportional transconductor G MP The positive output terminals of are coupled together, for example by connecting such positive terminals directly together.

[0057] Therefore, the first delayed input signal S R,PID The first current controlled delay line CCDL R Generating, the first current controlled delay line CCDL R is configured by using the corresponding phase Φ R,I Delay the first input signal S R,I (For example Figure 1 The first current controlled oscillator CCO R received signal) to generate this first delayed input signal S R,PID This delay operation is based on the differential transconductor G coupled together. MD and proportional transconductor G MP The two positive output terminals receive the first control signal to perform, for example, by a delay equal to t d,CCDLr The first time delay of this first input signal S R,I (See Figure 2 ).

[0058] Similarly, the second delayed input signal S F,PID The second current controlled delay line CCDL F The second current controlled delay line CCDL is generated F is configured by using the corresponding phase Φ F,I Delay the second input signal S F,I (For example Figure 1 The second current controlled oscillator CCO F received signal) to generate this second delayed input signal S F,PID This delay operation is based on the differential transconductor G coupled together. MD and proportional transconductor G MP The two negative output terminals receive the second control signal to perform, for example, by a delay equal to t d,CCDLf The second time delay of this second input signal S F,I (See Figure 2 ).

[0059] This first current controlled oscillator CCO R And this second current controlled oscillator CCO F Already in Figure 1 Therefore, in order not to overload the description, the description of these elements will not be repeated herein.

[0060] This first current controlled oscillator CCO R And this second current controlled oscillator CCO F Through the transconductance amplifier G in the integration path MI The signal provided to control the integral path is configured to set its non-inverting terminal to the reference voltage V REF , and sets its inverting terminal to the feedback voltage V FB .

[0061] In addition, this transconductor G on the integration path MI The negative output terminal and the positive output terminal of the current generator 200 are coupled to the corresponding output of the current generator 200, which is configured to be supplied with a voltage V CC , and provides a current controlled oscillator CCO with a value of I CM_CCO of common mode current.

[0062] It should be noted that in steady-state conditions, that is, when the control loop is closed, the feedback voltage V FB Equal to the reference voltage V REF , therefore, the first current controlled oscillator CCO R and the second current controlled oscillator CCOF is configured to generate a corresponding signal characterized by the same frequency (as previously described), which is also the PWM signal D PWM Switching frequency:

[0063]

[0064] Among them, F SW is the PWM signal D PWM The switching frequency, is the first input signal S R,I The frequency of the first current controlled oscillator CCO R The frequency of the generated signal, and is the second input signal S F,I The frequency of the second current controlled oscillator CCO F The frequency of the generated signal.

[0065] In this case, the transconductor G M The value of all differential currents provided as outputs is substantially equal to zero (i.e., equal to zero but taking into account a given tolerance), therefore, see Figure 3 :

[0066]

[0067]

[0068]

[0069] where i D The differential transconductor G MD The differential output current provided as an output, i P The proportional transconductor G MP The differential output current is provided as an output, and i I The transconductor G MI The differential output current is provided as an output on the integrating path.

[0070] If the transconductor G MI The differential current i provided as output on the integral path I is substantially equal to zero, then the first current controlled oscillator CCO R and the second current controlled oscillator CCO F Controlled by the same control signal, that is, by the common mode current I CM_CCO Biased equally.

[0071] Therefore, the PWM signal D PWM The switching frequency is based on the common mode current I CM_CCO The common mode current ICM_CCO Under different operating conditions (i.e., voltage V IN , output voltage V OUT , a load current I flowing in a load coupled to such an exemplary time-based DC-DC converter 20 LOAD different selected values ​​of and / or any other operating conditions) are nominally constant.

[0072] It is noted that it would be advantageous to be able to control and monitor this switching activity, for example by controlling and monitoring the PWM signal D PWM and time-based switching of the DC-DC converter 20, rather than having a constant common-mode current I CM_CCO Fixed, uncontrolled and unmonitored switching.

[0073] In order to improve the corresponding performance, a solution that facilitates controlling and monitoring the switching activity of a time-based DC-DC converter without affecting its regulation would be beneficial.

[0074] There is a need in the art to contribute to providing such a solution. Summary of the invention

[0075] One or more embodiments are directed to an apparatus.

[0076] One or more embodiments are directed to a corresponding method.

[0077] The solution described in this article helps to obtain a time-based DC-DC converter, which includes an additional negative feedback loop, which includes: a pair of phase detectors, configured to detect the common-mode frequency of the signal received by the current controlled oscillator of the corresponding DC-DC converter and obtain a balanced PWM signal; and a step-up / step-down charge pump, including, for example, a filtering stage, and configured to receive this balanced PWM signal and generate (according to this balanced PWM signal) a control signal for closing this negative feedback loop by acting on a controlled current generator, which is configured to provide a bias current to this current controlled oscillator of the corresponding DC-DC converter.

[0078] The solution described herein may include an additional low-side current sensor for sensing the current flowing within the coil of the DC-DC converter to facilitate further control and monitoring strategies, such sensing being performed by DC shifting (and amplifying) such current flowing within the coil.

[0079] The solution described herein facilitates controlling and monitoring the switching activity of a time-based DC-DC converter without affecting its regulation in order to improve the corresponding performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0081] Figure 1 is an exemplary circuit for generating a PWM signal for use in a control loop of a time-based DC-DC converter, as already described;

[0082] Figure 2 It's a picture. Figure 1 timing diagrams of exemplary behavior of some signals of a circuit operating under steady-state conditions, as already described;

[0083] Figure 3 is an exemplary time-based DC-DC converter having a control loop including circuitry for generating a PWM signal as already described;

[0084] Figure 4 and Figure 5 is a time-based DC-DC converter having a control loop including a circuit for generating a PWM signal;

[0085] Figure 6 , 7 and 8 are other time-based DC-DC converters having a control loop, wherein the control loop includes a circuit for generating a PWM signal; and

[0086] Fig. 9 and Fig.10 It is a low-side current sensor for DC-DC converters. DETAILED DESCRIPTION

[0087] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.

[0088] The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

[0089] The edges of features drawn in a drawing do not necessarily indicate the end of the extent of the feature.

[0090] In the following description, one or more specific details are illustrated to provide a deeper understanding of the examples of the described embodiments. The embodiments can be obtained without one or more specific details or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that some aspects of the embodiments are not obscured.

[0091] References to "an embodiment" or "one embodiment" in the framework of this description are intended to indicate that a particular configuration, structure, or feature described with respect to the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may be present in one or more points of the description do not necessarily refer to the same embodiment.

[0092] Furthermore, particular configurations, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0093] The headings / references used herein are provided for convenience only and do not limit the scope of protection or the scope of the embodiments.

[0094] For simplicity and ease of explanation, in this description, and unless the context indicates otherwise, like reference symbols are used throughout the various drawings to indicate like parts or elements, and the corresponding description is not repeated for each drawing.

[0095] As previously described, the solution disclosed herein facilitates controlling and monitoring the switching activity of a time-based DC-DC converter without affecting its regulation in order to improve the corresponding performance.

[0096] For example, it would be advantageous to be able to control this switching activity, for example by aligning it with a provided clock or external / internal signal, rather than having the switching PWM signal D PWM The switching time-based DC-DC converter is therefore dependent on this constant common-mode current I CM_CCO .

[0097] In fact, many application scenarios require that the switching activities of the time-based DC-DC converter be aligned with a given clock or signal (eg, a selected reference clock or reference signal generated internally or provided from an external unit).

[0098] Non-exhaustive examples of such applications of a time-based DC-DC converter that needs to be configured to switch according to a given clock / signal could be:

[0099] Applications in which a noise and / or interference sensitive system (e.g., a Nyquist data converter) is physically placed near a time-based DC-DC converter (e.g., the noise and / or interference sensitive system is deployed on the same chip as the time-based DC-DC converter, such as within a power management integrated circuit (PMIC) or system-on-chip (SoC), or at a printed circuit board (PCB) level), and thus the performance of the noise and / or interference sensitive system may be affected by the operation of the time-based DC-DC converter if the time-based DC-DC converter switching activity is not controlled;

[0100] A system comprising an oversampling analog-to-digital converter (ADC) and / or digital-to-analog converter (DAC) to avoid further sampling disturbances injected by a time-based DC-DC converter, for example, on power, ground or a common substrate;

[0101] Time-based DC-DC converters used as phase-locked loop (PLL) reference alignment, e.g. for dynamic scaling, frequency hopping, frequency squelch, etc.

[0102] Time-based DC-DC converters within a power management integrated circuit (PMIC), system-on-chip (SoC), or in the presence of more switch mode power supplies (SMPS) in general, e.g. to maintain proper separation to address electromagnetic interference (EMI) and electromagnetic compatibility (EMC) issues, as interactions between different time-based DC-DC converters (“crosstalk”) may result in performance degradation;

[0103] Modulation schemes that exploit the inherently large bandwidth of time-based DC-DC converters, such as envelope tracking, radio frequency power amplifier (RF PA) power control via adaptive direct current (DC) power supplies, etc.

[0104] Additionally, it is desirable to provide such alignment of switching activity of a time-based DC-DC converter with a given clock / other signal without affecting output regulation and performance of such time-based DC-DC converter and independently of the selected given clock or reference signal under consideration.

[0105] For example, it is desirable to guarantee output regulation even in the presence of: process, voltage, and temperature (PVT) variations; different operating conditions and parameters, such as input voltage V IN , output voltage V OUT , inductor L, output capacitor C O , PWM signal D PWM The switching frequency F SW one or more different values ​​between; or different conditions that may occur after final testing, packaging and assembly, such as aging, soldering, etc.

[0106] Embodiments of the solutions provided herein are based on the following observations and considerations:

[0107] During the transient, the control loop of the time-based DC-DC converter reacts by changing the frequency of the signal generated by the current controlled oscillator CCO in the opposite direction (ie, in a complementary manner), for example changing the first current controlled oscillator CCO R The first input signal S generated R,I The frequency and second current controlled oscillator CCO F The generated second input signal SF,I frequency, thereby acting in differential mode;

[0108] A negative feedback loop may be considered beneficial to compensate for this differential mode affecting circuit behavior during transients, but it is desirable that this negative feedback loop not interfere with the control loop of the time-based DC-DC converter in an attempt to avoid degrading its performance, causing instability, and / or generating a very slow transient response;

[0109] Since the signal generated by the current controlled oscillator CCO varies in opposite directions, a negative feedback loop is required which is sensitive only to the common mode frequency of the signal generated by such current controlled oscillator CCO; and

[0110] It is noted that monitoring the frequency of a single signal within such a time-based DC-DC converter may be inconvenient and misleading because such a single signal may not faithfully represent the nominal switching frequency of the time-based DC-DC converter.

[0111] Figure 4 is a time-based DC-DC converter 30 having a control loop including circuitry for generating a PWM signal.

[0112] It should be noted that Figure 4 The illustrated circuit 30 includes Figure 3 20 (except that the current generator 200 is replaced by a controlled current generator 200'), the details of which are only partially described in order to give priority to this Figure 4 Added clarity of the elements.

[0113] It should be noted that Figure 3 The components of this circuit 20 (except the current generator 200) are therefore also included in Figure 4 In this circuit 30, therefore, in order to make the description concise, the description of this component will not be recorded below.

[0114] Also note that Figure 4 The current generator of the circuit 20 is the (only) Figure 3 The current generator has been modified because this current generator is also configured to be controlled by a feedback control signal, so it will be referred to again. Figure 4 It is described and referred to as 200' to emphasize its Figure 3 The difference of the current generator 200.

[0115] In addition, in the following description, reference has been made to Figure 1 , 2The parts, elements and / or components described in and 3 are denoted by the same reference numerals previously used in such drawings, and in order not to overload the present description, their description will not be repeated below.

[0116] Figure 4 The time-based DC-DC converter 30 includes additional components included in a negative feedback loop, which is configured to advantageously control and monitor the switching activity of the time-based DC-DC converter 30, such as aligning the frequency of the switching activity of the time-based DC-DC converter 30 with a clock signal or any other binary signal generated internally or externally.

[0117] As previously described, a negative feedback loop can be advantageous for filtering differential modes that affect the behavior of the DC-DC converter 30 during transients, and in addition, it can be expected that such a negative feedback loop will not interfere with the control loop of the time-based DC-DC converter, e.g. Figure 3 The loop described in .

[0118] in addition, Figure 4 The negative feedback loop disclosed in may advantageously (because the signal generated by the current controlled oscillator CCO varies in opposite directions) be sensitive only to the common mode frequency of the signal generated by the current controlled oscillator CCO.

[0119] For example, Figure 4 The negative feedback loop of the time-based DC-DC converter 30 may include a reference clock generator 300 (or any other binary signal generator) configured to generate a reference clock signal CLK INT (or binary signal), the reference clock signal CLK INT is used as a reference for aligning and locking the switching frequency of the time-based DC-DC converter 30 to such a reference clock signal CLK INT frequency.

[0120] Such a reference clock generator 300 (or any other binary signal generator) may also be located externally relative to the time-based DC-DC converter 30. In this case, such an external reference clock generator 300 is configured to generate an external reference clock signal CLK EXT , which is again used as a reference for aligning and locking the switching frequency of the time-based DC-DC converter 30 to this external reference clock signal CLK EXT frequency.

[0121] It should be noted that reference symbol CLK INT / EXT is used to indicate a reference clock signal that can be generated internally or externally, thus indicating the reference clock signal CLK INTOr external reference clock signal CLK EXT .

[0122] Similarly, reference numeral 300 is used to indicate a reference clock generator, which may be located internally or externally relative to the time-based DC-DC converter 30 .

[0123] In summary, with this reference phase Φ CLK The reference signal (ie, the reference clock signal CLK INT / EXT ) may include an internally or externally generated clock signal (or any other binary signal used as a reference).

[0124] This reference clock signal CLK INT / EXT is provided as input to the first phase detector PD1 and the second phase detector PD2.

[0125] The first phase detector PD1 is configured to have its first terminal coupled to the first current controlled oscillator CCO. R and has its second terminal coupled to the reference clock generator 300, and generates a first PWM signal D1 according to the difference between the phases of the two signals received as input, i.e., a PWM signal with a corresponding phase Φ received at the first input terminal R,I The first input signal S R,I and received at the second input terminal with a corresponding phase Φ CLK The reference clock signal CLK INT / EXT .

[0126] This second phase detector PD2 is configured to have its first terminal coupled to the reference clock generator 300 and its second terminal coupled to the second current controlled oscillator CCO. F , and generates a second PWM signal D2 according to the difference between the phases of the two signals received as input, i.e., a PWM signal with a corresponding phase Φ received at the first input terminal CLK The reference clock signal CLK INT / EXT and received at the second input terminal with a corresponding phase Φ F,I The second input signal S F,I .

[0127] It is noted that such first phase detector PD1 and such second phase detector PD2 can be embedded in a controller (e.g., a digital controller) which is configured to control the operation of such time-based DC-DC converter 30, for example in order to manage cycle-slipping (also known as “signal wrapping around 2π”) and extend its operation, or to write, synthesize and verify hardware description language (HDL) code.

[0128] It should be noted that such first phase detector PD1 and such second phase detector PD2 may also be phase frequency detectors PFD which are robust to cycle slips.

[0129] The first phase detector PD1 and the second phase detector PD2 control the step-up / step-down charge pump 302 through the output signals generated respectively (i.e., the first PWM signal D1 and the second PWM signal D2), and the step-up / step-down charge pump 302 is configured to generate a control signal V according to the first PWM signal D1 and the second PWM signal D2 using, for example, a filtering stage. CONTROL .

[0130] It should be noted that the step-up / step-down charge pump 302 described below is only an exemplary charge pump and can generate such a control signal V according to such a first PWM signal D1 and a second PWM signal D2. CONTROL Any other configuration may be used, such as any other known charge pump.

[0131] For example, by replacing a single capacitor with Figure 4 The illustrated filtering stage (comprising a first capacitor C1 and a second capacitor C2 and a filtering resistor R Z ), a different step-up / step-down charge pump 302 is available that can be used as an alternative.

[0132] For example, the first phase detector PD1 is configured to detect the first input signal S R,I The first PWM signal D1 is set to a high logic level in response to the rising edge of the reference clock signal CLK INT / EXT The first PWM signal D1 is reset to a low logic level by the rising edge of

[0133] Similarly, for example, the second phase detector PD2 is configured to detect the reference clock signal CLK in response to INT / EXT The second PWM signal D2 is set to a high logic level in response to the rising edge of the second input signal S F,I The rising edge of PWM signal D2 resets the second PWM signal D2 to a low logic level.

[0134] It is to be noted that the logic levels of signals are described herein (and in the following description) only by way of example, and alternatives such as those obtained by switching a high logic level with a low logic level may also be considered.

[0135] Control signal V CONTROL The negative feedback loop is closed by controlling the controlled current generator 200' to change the common mode current I provided by the controlled current generator 200'. CM_CCOThe controlled current generator 200' is configured to be based on the control signal V CONTROL To change the value of the common mode current I supplied to the current controlled oscillator CCO CM_CCO .

[0136] Therefore, this negative feedback loop can be configured to adjust the value of the common-mode current I CM_CCO , to obtain the following situation:

[0137]

[0138] Among them, F SW is the PWM signal D PWM The switching frequency, is the first input signal S R,I The frequency of the first current controlled oscillator CCO R The frequency of the generated signal, is the second input signal S F,I The frequency of the second current controlled oscillator CCO F The frequency of the generated signal, and F CLK is the reference clock signal CLK INT / EXT frequency.

[0139] Therefore, in the steady state of the DC-DC converter 30, the first input signal Φ R,I The frequency of the second input signal Φ F,I The frequency and reference clock signal Φ CLK The frequencies are substantially equal (considering a given threshold).

[0140] The step-up / step-down charge pump 302 is configured to receive the first PWM signal D1 and the second PWM signal D2, and generate a control signal V according to the received signals. CONTROL .

[0141] Such a first PWM signal D1 and such a second PWM signal D2 are respectively used as control signals for controlling on / off switching actuation of a pair of switches DN and UP.

[0142] Therefore, this first PWM signal D1 is used to control the switching of the first switch DN. For example, this first switch DN is coupled between the second node N and the ground GND through the first current generator 304, and is configured to be closed when the first PWM signal D1 is set to a high logic level, and to be opened when the first PWM signal D1 is reset to a low logic level.

[0143] Similarly, this second PWM signal D2 is used to control the switching of the second switch UP, for example, this second switch UP is coupled between the second node N and the terminal supplied with the first power supply voltage VCC through the second current generator 306, and is configured to be closed when the second PWM signal D2 is set to a high logic level, and to be opened when the second PWM signal D2 is reset to a low logic level.

[0144] The first current generator 304 and the second current generator 306 are configured to generate corresponding currents, ie, the first current I CP1 and the second voltage I CP2 , such as currents with the same value, i.e., I CP1 =I CP2 .

[0145] The filter stage is also coupled between the second node N and the ground GND, and the filter stage is configured to provide a control signal V according to the current flowing in the second node N. CONTROL .

[0146] For example, such a filtering stage may include: Z The first capacitor C1 coupled between the second node N and the ground GND and the second capacitor C2 coupled between the second node N and the ground GND, such a control signal V CONTROL is the voltage measured across this second capacitor C2.

[0147] It is to be noted that the current flowing in the second node N may inject a certain amount of charge into the first capacitor C1 and the second capacitor C2 or subtract a certain amount of charge therefrom.

[0148] The amount of charge injected / subtracted can be determined according to the first current I flowing in the first switch DN. CP1 and the second current I flowing in the second switch UP CP2 To obtain.

[0149] In fact, the first current I flowing in the first switch DN CP1 Charge can be subtracted from the first capacitor C1 and the second capacitor C2 to discharge them, and the second current I flowing in the second switch UP CP2 Charges may be injected into such first and second capacitors C1 and C2 to thereby charge them.

[0150] Therefore, the resulting amount of charge injected into / subtracted from such first capacitor C1 and second capacitor C2 may depend on the first current I CP1 and the second current I CP2 .

[0151] In the following description, the first current I flowing in the first switch DN CP1 The value of is considered to be equal to I flowing in the second switch UP CP2 The value of, regardless of their value, makes the amount of charge transferred (injected or subtracted) in a given time equal to the first current I CP1 and the second current I CP2 are equal.

[0152] In the steady state, that is, when the first input signal S R,I Frequency (ie, the first current controlled oscillator CCO R The frequency of the generated signal is substantially equal (taking into account a given tolerance) to the second input signal S F,I Frequency (ie, the second current controlled oscillator CCO F The frequency of the signal generated by the second input signal S is substantially equal to the second input signal S during the complete switching cycle. F,I The first complete cycle of the input signal S R,I In a complete cycle, the first current I flowing in the first switch DN CP1 The amount of charge subtracted from such first capacitor C1 and second capacitor C2 is substantially equal (taking into account a given tolerance) to the amount of charge generated by the second current I flowing in the second switch UP. CP2 The amount of charge injected into the first capacitor C1 and the second capacitor C2.

[0153] It should be noted that when both the time-based control loop and the additional negative feedback loop are in steady state and the reference clock signal CLK INT / EXT In a steady state with a constant or fixed frequency value, this equality condition may exist, that is, when the first input signal S R,I Frequency is substantially equal to the second input signal S F,I Frequency hour.

[0154] It should be noted that after a period of time equal to a complete switching cycle, i.e. at the end of such a period of time equal to a complete switching cycle, the amount of charge subtracted from such first capacitor C1 and second capacitor C2 is substantially equal (taking into account a given tolerance) to the amount of charge injected into such first capacitor C1 and second capacitor C2, and therefore the control signal V obtained after such a period of time is CONTROL The value of is substantially equal (taking into account a given tolerance) to the control signal V measured before the same time period CONTROL The value of .

[0155] Differently, when the time-based DC-DC converter 30 is in a transient condition (e.g., if there is a load transient, a line transient, etc.), the control loop of this time-based DC-DC converter operates by changing the frequency of the signal generated by the current controlled oscillator CCO (as previously described) in the opposite direction (in a complementary manner) (e.g., the first current controlled oscillator CCO R The first input signal S generated R,I The frequency and second current controlled oscillator CCO F The generated second input signal S F,I frequency) to respond, i.e., to act in differential mode.

[0156] Note that operating the circuit in this differential mode results in such frequency changes in opposite directions (complementarily) corresponding to the first input signal S R,I and the second input signal S F,I The frequency of one of the first input signal S is reduced by a given amount. R,I and the second input signal S F,I Such a circuit operates with the frequency of one of the two circuits increased by the same given amount.

[0157] Therefore, as a result, the first input signal S R,I and the second input signal S F,I The period of one of the two signals is reduced by a given amount, and the first input signal S R,I and the second input signal S F,I The period of the other of is increased by the same given amount (thus, they vary in a complementary manner).

[0158] In response to the first input signal S R,I and the second input signal S F,I The periods of the first PWM signal D1 and the second PWM signal D2 change accordingly, that is, the period of the first PWM signal D1 changes according to the first input signal S R,I The period of the second PWM signal D2 increases / decreases according to the change of the second input signal S F,I decrease / increase due to changes in .

[0159] It should be noted that if the reference clock signal CLK INT / EXT In a steady state with a constant or fixed frequency value, such a change may occur, that is, according to the first input signal S R,I The change of the first PWM signal D1 increases / decreases the period of the first PWM signal D1, and according to the second input signal S F,I The change of increases / decreases the period of the second PWM signal D2.

[0160] Therefore, the change of the period of the first PWM signal D1 and the second PWM signal D2 respectively affects the amount of time the first switch DN and the second switch UP remain closed, thereby respectively affecting the first current I CP1 The second current I flows in the first switch DN and CP2 The amount of time that flows within the second switch UP.

[0161] Therefore, also in this case, the amount of time (ie, the period) that the first switch DN and the second switch UP remain closed is also affected in a complementary manner.

[0162] Therefore, during a complete switching cycle, that is, during the first input signal S R,I The complete cycle of the second input signal S F,I The average period is calculated between the complete periods of (because the variation is in the opposite direction, i.e., in a complementary manner), by the first current I flowing in the first switch DN CP1 The amount of charge subtracted from such first capacitor C1 and second capacitor C2 is again substantially equal (taking into account given tolerances) to the amount of charge generated by the second current I flowing in the second switch UP. CP2 The amount of charge injected into the first capacitor C1 and the second capacitor C2.

[0163] Therefore, the control signal V obtained after this complete switching cycle is CONTROL The value of is again substantially equal (taking into account the given tolerances) to the control signal V measured before the same complete switching cycle CONTROL The value of .

[0164] Therefore, in Figure 4 In the embodiment of the present invention, the introduced negative feedback loop can correctly reject the differential operation mode introduced by the transient condition.

[0165] If the reference clock generator 300 is configured to generate a reference clock signal CLK having a different frequency value and thus a different phase value INT / EXT or be configured to generate a plurality of reference clock signals CLK INT / EXT And from the first reference clock signal CLK INT / EXT Switches to a frequency value (and therefore a phase value) different from the first reference clock signal CLK INT / EXT The second reference clock signal CLK INT / EXT , then the negative feedback loop enters a transient condition in which the amount of time that the first switch DN and the second switch UP remain closed varies in a non-complementary manner, ie, the amounts of change are different.

[0166] It is noted that operating the circuit under conditions that result in frequency variations not in opposite directions (non-complementarily) corresponds to operating the circuit under conditions where, at the first input signal S R,I and the second input signal S F,I The frequency of one of the first input signal S is reduced by a first given amount, and the first input signal S R,I and the second input signal S F,I The frequency of the other one of is increased by a second given amount (different from the first given amount).

[0167] In other words, operating the circuit under conditions that result in frequency changes not in opposite directions (non-complementarily) corresponds to the following situation: with the first input signal S R,I and the second input signal S F,I The two frequencies can be equal but relative to the reference clock signal CLK. INT / EXT Frequency F CLK Conversely, increasing or decreasing a given amount (thus, the first input signal S R,I and the second input signal S F,I The frequency of the reference clock signal CLK INT / EXT frequency).

[0168] Therefore, more generally, the first input signal S R,I and the second input signal S F,I The reference clock signal CLK INT / EXT Frequency F CLK common mode frequency operation.

[0169] Therefore, in this non-complementary operating condition, the amount of charge subtracted from the first capacitor C1 and the second capacitor C2 is different from the amount of charge injected into the first capacitor C1 and the second capacitor C2, and therefore, the control signal V CONTROL The value of changes with time until a new steady-state condition is reached.

[0170] For example, if the amount of injected charge is higher than the amount of subtracted charge, the control signal V CONTROL The value of will increase with time until a new steady state is reached (the control signal V CONTROL is set to a higher value).

[0171] Otherwise, if the amount of charge subtracted is higher than the amount of charge injected, the control signal V CONTROL The value of will decrease with time until a new steady-state condition is reached (the control signal V CONTROL is set to a lower value).

[0172] Therefore, the reference phase Φ CLK (i.e., the phase Φ of the reference clock signal CLK)(and reference clock signal CLK INT / EXT The corresponding frequency value of ) can be selectively variable among multiple reference phases, that is, including a set of desired phase values.

[0173] It should be noted that under different steady-state operating conditions of the time-based DC-DC converter 30, that is, under conditions where the reference clock signal CLK INT / EXT Change its frequency value (or select a different reference clock signal CLK INT / EXT ), under different operating conditions from those of the first and second capacitors C1, C2, the amount of charge injected into the first and second capacitors C1, C2 is substantially equal to the amount of charge subtracted from the same first and second capacitors C1, C2, thereby obtaining a net charge injected into / subtracted from such first and second capacitors C1, C2 of the filtering stage of substantially zero.

[0174] It should also be noted that, during the complete switching cycle, that is, substantially equal to the second input signal S F,I The first complete cycle of the input signal S R,I A complete cycle of (under steady-state conditions) or at the first input signal S R,I The complete cycle of the second input signal S F,I The average period calculated between the complete periods of CONTROL The ripple value can vary, and this control signal V CONTROL The average value of can be kept constant and fixed.

[0175] Thus, the filter stage included in the step-up / step-down charge pump 302 of the negative feedback loop is a filter stage that is configured to highly reject the differential mode and pass only the common mode of the signal received as input from the circuitry 20 .

[0176] In summary, the DC-DC converter 30 described herein comprises: a first current controlled oscillator CCO R , is configured to generate a signal having a first phase Φ based on a first control signal R,I The first oscillator signal, that is, the first input signal S R,I ; and a second current controlled oscillator CCO F , is configured to generate a second phase Φ based on the second control signal F,I The second oscillator signal, that is, the second input signal S F,I .

[0177] The converter 30 further includes a controlled current generator 200 ′ configured to control the current based on the feedback control signal V CONTROL Generates a controlled current, i.e., a value of I CM_CCOThe common mode current of the first control signal and the second control signal is the controlled current I CM_CCO and a negative feedback loop configured to receive a current from a first current controlled oscillator CCO R The first oscillator signal S R,I and from the second current controlled oscillator CCO F The second oscillator signal S F,I , and according to this first oscillator signal S R,I and this second oscillator signal S F,I Generate feedback control signal V CONTROL .

[0178] The negative feedback loop includes: a detector configured to receive a current from a first current controlled oscillator CCO R The first oscillator signal S R,I , from the second current controlled oscillator CCO F The second oscillator signal S F,I and with a reference phase Φ CLK The reference signal CLK INT / EXT , and generates at least two binary signals, including according to the reference phase Φ CLK and the first phase Φ R,I The first binary signal D1 is generated by the difference between the reference phase Φ CLK and the second phase Φ F,I A second binary signal D2 generated by the difference between the two; and a charge pump 302, configured to receive at least two binary signals, and generate a feedback control signal V based on the at least two binary signals CONTROL .

[0179] In an embodiment, the detector may include: a first phase detector PD1 configured to receive a first current controlled oscillator CCO R The first oscillator signal S R,I and with a reference phase Φ CLK A reference signal, such as a reference clock signal CLK INT / EXT , and according to the reference phase Φ CLK and the first phase Φ R,I The difference between the first and second phase detectors generates a first binary signal, ie, a first PWM signal D1; and a second phase detector PD2 configured to receive a first current controlled oscillator CCO from the second current controlled oscillator CCO. F The second oscillator signal S F,I and with this reference phase Φ CLK A reference signal, such as a reference clock signal CLK INT / EXT , and according to the reference phase Φ CLK and the second phase ΦF,I The charge pump 302 is configured to receive the first binary signal D1 from the first phase detector PD1 and the second binary signal D2 from the second phase detector PD2, and generate a feedback control signal V based on the first binary signal D1 and the second binary signal D2. CONTROL .

[0180] In the steady state of the DC-DC converter 30, the first oscillator signal S R,I Frequency (ie, the frequency of the first input signal ), the second oscillator signal S F,I Frequency (ie, the frequency of the second input signal ) and reference signal CLK INT / EXT Frequency F INT / EXT (ie, the frequency F of the reference clock signal CLK ) can be equal.

[0181] The charge pump 302 may include a first charge pump current generator, namely, a first current generator 304, configured to be coupled to the ground GND and to generate a first pump current, namely, a first current I CP1 The second charge pump current generator, ie, the second current generator 306, is configured to be supplied with a power supply voltage VCC and generate a second pump current, ie, a second current I CP2 a first switch DN coupled between the node (i.e., the second node N) and the first charge pump current generator 304 to receive the first binary signal D1 from the first phase detector PD1 and switch in response to the first binary signal D1 changing its logic level; a second switch UP coupled between the node N and the second charge pump current generator 306 to receive the second binary signal D2 from the second phase detector PD2 and switch in response to the second binary signal D2 changing its logic level; and a capacitor, i.e., at least a second capacitor C2, configured to be coupled between the node N and the ground GND to receive the second binary signal D2 from the second phase detector PD2 via the second pump current I in response to the second switch UP being turned on. CP2 The first pump current I is charged and in response to the first switch DN being turned on, CP1 discharge, wherein the charged voltage of such capacitor C2 (i.e., the voltage that can be measured on (applied to) such capacitor C2) provides (corresponds to) the feedback control signal V CONTROL , used to control the controlled current generator 200'.

[0182] The first pump current I generated by the first charge pump current generator 304 CP1can be equal to the second pump current I generated by the second charge pump current generator 306 CP2 .

[0183] Figure 5 is a time-based DC-DC converter 301 having a control loop including circuitry for generating a PWM signal.

[0184] Figure 5 The diagram shows a possible implementation of a controlled current generator 200', which is configured to provide a current with a value of I CM_CCO of common mode current.

[0185] It should be noted that, in addition to the controlled current generator 200, the circuit system indicated by reference numeral 20' corresponds to Figure 3 Therefore, the description of such circuit system 20' will not be repeated herein.

[0186] It is also noted that the circuit system included in the negative feedback loop (i.e., the first phase detector PD1 and the second phase detector PD2, the step-up / step-down charge pump 302 and the components included therein, and optionally the reference clock generator 300) corresponds to Figure 4 The circuit system has been described in , therefore, this article will not repeat the description of this negative feedback loop.

[0187] The control signal V generated by the step-up / step-down charge pump 302 according to the first PWM signal D1 and the second PWM signal D2 CONTROL is supplied to a voltage-to-current buffer (converter) comprising an amplifier stage 308 implemented, for example, by an operational amplifier and a first transistor M N0 (eg, any n-type transistor known in the art).

[0188] Therefore, the control signal V CONTROL is provided to the positive input terminal of the amplifier stage 308, which is also configured to have: its negative input terminal, through the base resistor R B is coupled to the ground GND, and is coupled to the first transistor M N0 A source / emitter terminal of, for example, an n-type MOSFET, etc.; and an output terminal thereof, coupled to such a first transistor M N0 The gate / base terminal of an n-type MOSFET, for example.

[0189] Therefore, this voltage-to-current buffer can be configured to receive the control signal V CONTROL , amplifying 308 this received control signal V CONTROL , and use this control signal V CONTROLTo drive the first transistor M N0 The gate / base terminal of this first transistor M N0 is configured to have a value equal to the common mode current value I CM_CCO The mirror current flows in it, thus converting the control signal V CONTROL Converted into a current signal, that is, the value is equal to the common mode current I CM_CCO The mirror current signal, in this first transistor M N0 flows between the drain / collector terminal and the source / emitter terminal.

[0190] This first transistor M N0 The transistor is further configured to be coupled to one or more current mirrors, which are configured to be connected to the first branch (including the second transistor M P0 , such as any p-type transistor known in the art) receives this mirror current and passes through at least a second branch (including a third transistor M P1 and / or the fourth transistor M P2 , such as any p-type transistor known in the art) to reproduce this mirror current to provide a first current controlled oscillator CCO R and the second current controlled oscillator CCO F The generated value is I CM_CCO of common mode current.

[0191] It should be noted that any other current mirror known in the art may replace the current mirror described herein, for example such a current mirror may be implemented using a BJT (“bipolar junction transistor”) or a MOSFET, and may have any structure / components known in the art.

[0192] Therefore, the first transistor M N0 is also configured to have its drain / collector terminal coupled to a second transistor M P0 The drain / collector terminal of the same second transistor M P0 The gate / base terminal of this second transistor M P0 is configured to have its drain / collector terminal coupled to its gate / base terminal.

[0193] For example, the second transistor M P0 The transistor M is also configured to have its source / emitter terminal coupled to a terminal supplied with the first power supply voltage VCC, and to have its gate / base terminal further coupled to the third transistor M. P1 (eg, p-type MOSFET, etc.) and a fourth transistor M P2 The corresponding gate / base terminals of a (e.g., p-type MOSFET, etc.).

[0194] For example, the third transistor MP1 And this fourth transistor M P2 The first and second electrodes are also configured to have their respective source / emitter terminals coupled to such a terminal supplied with a first power supply voltage VCC, and to have their respective drain / collector terminals coupled to a first current controlled oscillator CCO, respectively. R and the second current controlled oscillator CCO F .

[0195] Therefore, this third transistor M P1 And this fourth transistor M P2 are configured to respectively supply current to the first current controlled oscillator CCO R and the second current controlled oscillator CCO F Provide a value of I CM_CCO of common mode current.

[0196] In summary, the DC-DC converter described herein may include a controlled current generator 200', which includes: for example, the amplifier stage 308 described previously, the first transistor M N0 and the base resistor R B implemented voltage-to-current buffer, configured to receive a feedback control signal V CONTROL , a gain of 308 is applied to this feedback control signal V CONTROL , and driving a transistor, such as a first transistor M configured to facilitate the flow of a mirror current therein, using such a feedback control signal having a gain applied thereto. N0 ; and for example through a second transistor M P0 , the third transistor M P1 and (optionally) a fourth transistor M P2 The current mirror implemented is configured to receive the mirror current in a first mirror branch and generate the controlled current by mirroring the mirror current in at least one second mirror branch, that is, the value is I CM_CCO of common mode current.

[0197] Figure 6 Yet another time-based DC-DC converter implementation is illustrated that includes a control loop having circuitry for generating a PWM signal.

[0198] By considering that any frequency locked loop (FLL) (e.g. any classic / standard FLL or any known FLL) can be used to obtain a time-based alignment of the switching activity of the DC-DC converter with the reference clock signal, it is possible to obtain Figure 6 In order to lock the switching activity of the time-based DC-DC converter to a given reference frequency, that is, a reference clock signal (such as the reference clock signal CLK described previously),INT / EXT ) frequency.

[0199] It should be noted that in Figure 6 In an embodiment, the FLL may be configured to implement a portion of the additional negative feedback loop previously described.

[0200] Note that this FLL can be configured to provide a common-mode current I CM_CCO A controlled current generator 200' (already described and therefore not repeated herein) is thus to be identified as an input signal of the FLL in order to lock the switching activity of a time-based DC-DC converter comprising such an FLL acting on a corresponding current controlled generator 200' to a given reference frequency.

[0201] Such an input signal to the FLL may be any digital signal carrying information about the switching activity of such a time-based DC-DC converter, for example Figure 3 The phase detector PD provides the PWM signal D PWM .

[0202] In fact, this PWM signal D PWM Included is information about the actual (ie, instantaneous) switching frequency of the DC-DC converter based on time.

[0203] It should be noted that time-based DC-DC converters are non-fixed frequency DC-DC converters, i.e., their operating frequency may be fixed and defined only during steady-state conditions, while during any transients, the switching frequencies of the two current controlled oscillators CCO may change (for example in order to facilitate overcoming transients and maintain output regulation), thereby causing the frequency of the switching activity of the corresponding DC-DC converter to change.

[0204] The magnitude of variation in the frequency of the switching activity of the DC-DC converter may not be fixed / predictable as it may depend on the actual transient conditions and the negative feedback loop.

[0205] During transient conditions (e.g., load transients, line transients, etc.), locking the FLL to any digital signal carrying information about the switching activity of such a time-based DC-DC converter may result in the following operations: the time-based control loop of the time-based DC-DC converter may attempt to maintain output regulation, and such FLL may attempt to maintain the switching frequency of the time-based DC-DC converter aligned with the reference clock signal CLK INT / EXT locking.

[0206] In fact, even an FLL can detect transient conditions of a DC-DC converter, since the switching frequency of the DC-DC converter is experiencing such transients and such FLL is configured to receive a digital signal carrying information about such switching frequency.

[0207] Therefore, in a time-based DC-DC converter including a FLL locked to a digital signal carrying information about the switching activity of such a time-based DC-DC, the time-based control loop may interact with the FLL, causing stability issues.

[0208] To facilitate solving this stability problem, the FLL may be designed with a bandwidth that is (much) smaller than the time-based control loop of the time-based DC-DC converter. Thus, the FLL may be (much) slower than such a time-based control loop.

[0209] In this case, any transient of the time-based DC-DC converter may not be detected by the FLL because it is filtered out by the (much) faster time-based control loop of the DC-DC converter, i.e., the time-based control loop of the DC-DC converter may resolve the transient condition and restore the steady-state condition before the FLL is able to recognize it.

[0210] It is to be noted that in a solution comprising a FLL locked to a digital signal carrying information about the switching activity of such a time-based DC-DC converter, there is a (relatively deep) interaction between the FLL (included in an additional negative feedback loop) and the time-based control loop. Therefore, in order to reduce this interaction and improve the stability of the time-based DC-DC converter, the crossover frequency of the bandwidth of the time-based control loop must be higher than the crossover frequency of the bandwidth of the FLL, e.g. at least one order of magnitude higher.

[0211] It is noted that the performance of the time-based DC-DC converter 302 (comprising a FLL locked to a digital signal carrying information about the corresponding DC-DC switching activity) may be affected by the trade-off chosen between the bandwidth of the FLL and the DC-DC converter stability / transient performance.

[0212] Figure 6 A possible implementation of a time-based DC-DC converter 302 comprising a FLL locked to a digital signal carrying information about the switching activity of such a time-based DC-DC converter 302 is illustrated.

[0213] It should be noted that Figure 6The illustrated FLL is described by way of example only and is not intended to limit the scope of protection of this document. In fact, as previously described, any other FLL implementation may be considered, such as any classic / standard FLL or any known FLL.

[0214] It should be noted that, in addition to the controlled current generator 200, Figure 6 The circuit system indicated by reference numeral 20' corresponds to Figure 3 Therefore, the description of such circuit system 20' will not be repeated herein.

[0215] It is also noted that the step-up / step-down charge pump 302 includes Figure 6 The circuit system corresponds to Figure 4 Therefore, the description of the step-up / step-down charge pump 302 will not be repeated herein.

[0216] Similarly, it is noted that the controlled current generator 200' includes Figure 6 The circuit system corresponds to Figure 5 Therefore, the description of such a controlled current generator 200' will not be repeated herein.

[0217] Figure 6 The illustrated time-based DC-DC converter 302 includes a FLL comprising: a frequency detector FD, a step-up / step-down charge pump 302 (as previously described), a filtering stage (comprising a first capacitor C1, a second capacitor C2 and a filtering resistor R Z , as previously described) and CCO, which is configured to be driven by the common mode current I CM_CCO A current feed is provided (as previously described).

[0218] The first frequency detector constant pulse block 310a included in the frequency detector FD may be configured to receive a Figure 3 The phase detector PD provides the PWM signal D PWM , and in response to the received PWM signal D PWM Each rising edge of generates a pulse of constant width, for example, a width equal to the time T PULSE Such a constant width pulse shapes the first PWM signal D1 for driving the first switch DN of the step-up / step-down charge pump 302 .

[0219] Reference clock signal CLK INT / EXT (generated as previously described) is provided as a second frequency detector constant pulse block 310 included in the frequency detector FD. b Input.

[0220] This second frequency detector constant pulse block 310 b Can be configured to receive the reference clock signal CLK INT / EXT , and in response to the received reference clock signal CLK INT / EXT Each rising edge of generates a pulse of constant width, for example, a width equal to the time T PULSE Such a constant-width pulse shapes the second PWM signal D2 for driving the second switch UP of the step-up / step-down charge pump 302 .

[0221] It should be noted that the constant pulse block 310 of the first frequency detector a and the second frequency detector constant pulse block 310 b The generated constant width pulses can also be respectively responsive to the received PWM signal D PWM and the received reference clock signal CLK INT / EXT Generated for each falling edge of .

[0222] Therefore, based on the PWM signal D PWM and the reference clock signal CLK INT / EXT From the first frequency detector constant pulse block 310 a and the second frequency detector constant pulse block 310 b Two constant width signals are obtained, namely, a first PWM signal D1 and a second PWM signal D2 .

[0223] It should be noted that the first frequency detector constant pulse block 310 a and the second frequency detector constant pulse block 310 b can be configured to be respectively from the PWM signal D PWM and the reference clock signal CLK INT / EXT The duty cycle dependency is removed (constant width signal is generated) so as to extract frequency information from such signal, and obtain such first PWM signal D1 and such second PWM signal D2 respectively to drive the step-up / step-down charge pump 302 coupled thereto based only on their frequency difference (ie, frequency error).

[0224] The frequency detector FD may be configured to receive the PWM signal D PWM and the reference clock signal CLK INT / EXT , and generate the first PWM signal D1 and the second PWM signal D2 as previously described, including frequency information about such received signals.

[0225] The step-up / step-down charge pump 302 may be configured to receive the PWM signals D PWM and the reference clock signal CLK INT / EXTThe frequency information of the first PWM signal D1 and the second PWM signal D2 is obtained, and a frequency error signal (as previously described) is generated based on the received first PWM signal D1 and the second PWM signal D2, such as the control signal V CONTROL , the frequency error signal is an indication of the PWM signal D PWM The frequency and reference clock signal CLK INT / EXT The frequency error between the frequencies of the voltage signals.

[0226] It should be noted that since the first PWM signal D1 and the second PWM signal D2 driving the step-up / step-down charge pump 302 may depend on the PWM signal D PWM The frequency and reference clock signal CLK INT / EXT The frequency of the PWM signal D is such that the net charge moved in the step-up / step-down charge pump 302 (ie, the charging / discharging of the first capacitor C1 and the second capacitor C2) depends on the PWM signal D PWM And this reference clock signal CLK INT / EXT The frequency difference between them, that is, the frequency error.

[0227] The frequency error signal (eg, the control signal V CONTROL ) may be provided to a controlled current generator 200' (as previously described) to drive such a controlled current generator 200'.

[0228] The frequency detector FD, the step-up / step-down charge pump 302, the filter stage and the controlled current generator 200' may provide an additional negative feedback loop configured to couple the switching activity of the DC-DC converter 302 with the reference clock signal CLK based on the time. INT / EXT frequency alignment.

[0229] Figure 7 A possible implementation of a time-based DC-DC converter 303 is illustrated, which comprises a phase-locked loop PLL instead of an FLL, such PLL being locked to a digital signal carrying information about the switching activity of such time-based DC-DC converter 303 .

[0230] Using a PLL instead of an FLL can help achieve phase alignment, so that in addition to the time-based switching activity of the DC-DC converter 303 and the reference clock signal CLK INT / EXT In addition to frequency alignment, it can even provide phase alignment.

[0231] In fact, certain applications may benefit from alignment of the DC-DC converter switching activity with a given edge (eg, a rising edge or a falling edge) of a reference signal.

[0232] Note that having phase lock may be more stringent than frequency lock, and in fact, using phase lock may automatically provide frequency lock.

[0233] It should be noted that Figure 7 The illustrated PLL is described by way of example only and is not intended to limit the scope of protection of this document. In fact, any other PLL implementation may be considered, such as any classic / standard PLL or any known PLL.

[0234] It should be noted that, in addition to the controlled current generator 200, Figure 7 The circuit system indicated by reference numeral 20' corresponds to Figure 3 Therefore, the description of such circuit system 20' will not be repeated herein.

[0235] Note also that the step-up / step-down charge pump 302 and the filter stage included in the Figure 7 The circuit system corresponds to Figure 4 Therefore, the description of the step-up / step-down charge pump 302 will not be repeated herein.

[0236] Similarly, it is noted that the controlled current generator 200' includes Figure 7 The circuit system corresponds to Figure 5 Therefore, the description of such a controlled current generator 200' will not be repeated herein.

[0237] Figure 7 The illustrated time-based DC-DC converter 303 comprises a PLL comprising: a phase frequency detector PFD (e.g., any type of step-up / step-down phase frequency detector), a step-up / step-down charge pump 302 (as previously described), a filtering stage (comprising a first capacitor C1, a second capacitor C2, and a filtering resistor R Z , as previously described) and CCO, which is configured to be driven by the common mode current I CM_CCO A current feed is provided (as previously described).

[0238] The phase frequency detector PFD (e.g., any type of step-up / step-down phase frequency detector) is configured to: receive the PWM signal D PWM and the reference clock signal CLK INT / EXT , including phase and frequency information; generating a first PWM signal D1 and a second PWM signal D2, including phase and frequency information about such received signal, removing duty cycle dependency; and providing such generated signal to a boost / buck charge pump 302 coupled thereto.

[0239] Therefore, in addition to facilitating alignment of the switching frequency of the switching activity of the time-based DC-DC converter 303 with such a reference signal, as Figure 7 As illustrated, the solution including the time-based DC-DC converter 303 may also advantageously facilitate alignment of the phase of the switching activity of the time-based DC-DC converter 303 with a reference signal.

[0240] It is noted that the performance of the time-based DC-DC converter 303 (comprising a PLL locked to a digital signal carrying information about the corresponding DC-DC switching activity) may be affected by the trade-off chosen between the bandwidth of the PLL and the DC-DC converter stability / transient performance.

[0241] Figure 8 Yet another time-based DC-DC converter implementation is illustrated that includes a control loop having circuitry for generating a PWM signal.

[0242] like Figure 8 An embodiment of the invention is obtained by considering that (as previously described) during any transient condition the time-based control loop of the DC-DC converter may react by changing the frequency of the current controlled oscillator CCO in the opposite direction (i.e., in a complementary manner), thereby operating in differential mode.

[0243] Therefore, as previously described, an additional negative feedback loop may be considered that is configured to control the switching frequency of the DC-DC converter under steady-state conditions, limiting disturbances to the time-based control loop of the DC-DC converter (as previously described, to help avoid performance degradation and improve the stability of the time-based control loop and the additional negative feedback loop).

[0244] A possible solution to limit such disturbances can be obtained by considering a signal carrying information about the steady-state frequency of the switching activity of the DC-DC converter, which signal is not affected by any operation of the time-based control loop.

[0245] The first current controlled oscillator CCO R The first input signal S provided R,I and a second current controlled oscillator CCO F The second input signal S provided F,I The first input signal S may be neither affected by the proportional action nor the derivative action of the time-based control loop, but may still be affected by the integral action of such a time-based control loop. R,I And this second input signal S F,I Can not be used alone.

[0246] Additionally, monitoring the frequency of a single signal within a time-based control loop can be misleading because it may not faithfully represent the actual frequency of the DC-DC converter's switching activity, such as during any transient response of the DC-DC converter.

[0247] Therefore, since the first input signal S R,I and the second input signal S F,I The common-mode frequency of the current controlled oscillator CCO can provide information about the instantaneous frequency value of the switching activity of the DC-DC converter under consideration (by measuring the first input signal S R,I and the second input signal S F,I The instantaneous frequency of the first input signal S can be considered to be averaged. R,I and the second input signal S F,I This common-mode frequency is sensitive to the additional negative feedback loop.

[0248] Figure 8 A possible implementation of a time-based DC-DC converter 304 is illustrated, which includes an additional negative feedback loop that is sensitive to the common mode frequency of the current controlled oscillator CCO.

[0249] It should be noted that, in addition to the controlled current generator 200, Figure 8 The circuit system indicated by reference numeral 20' corresponds to Figure 3 Therefore, the description of such circuit system 20' will not be repeated herein.

[0250] Similarly, it is noted that the controlled current generator 200' includes Figure 8 The circuit system corresponds to Figure 5 Therefore, the description of such a controlled current generator 200' will not be repeated herein.

[0251] It is also noted that the three-input step-up / step-down charge pump 302' includes Figure 8 A portion of the circuit system corresponds to Figure 4 The circuit system of the boost / buck charge pump 302 has been described in the previous section, and therefore, the description of the circuit system of the three-input boost / buck charge pump 302' will not be repeated herein, for example, the second current generator 306, the second current I CP2 , description of the second switch UP, and the second node N.

[0252] Similarly, it is noted that the description of the filter stage will not be repeated as it corresponds to Figure 4 The filter stage has already been described in , so this article will not repeat the filter resistor R Z, the first capacitor C1, the second capacitor C2 and the control signal V CONTROL Description.

[0253] like Figure 8 As illustrated, the time-based DC-DC converter 304 may include a three-input step-up / step-down charge pump 302 ′, a filtering stage (as previously described), a first constant pulse block 3101 , a second constant pulse block 3102 , and a third constant pulse block 3103 .

[0254] The step-up / step-down triple-input charge pump 302 ′ may be configured to be controlled by a constant width signal (shaped by constant width pulses) received from the first constant pulse block 3101 , the second constant pulse block 3102 , and the third constant pulse block 3103 .

[0255] The third constant pulse block 3103 may be configured to receive a reference clock signal CLK INT / EXT , and in response to the received reference clock signal CLK INT / EXT Each rising edge of the PULSE This constant width pulse shapes the second PWM signal D2 used to drive the second switch UP included in the three-input step-up / step-down charge pump 302'.

[0256] It should be noted that even in this case, the constant width pulse generated by the third constant pulse block 3103 can also respond to the received reference clock signal CLK INT / EXT Generated for each falling edge of .

[0257] It should be noted that the third constant pulse block 3103 can be configured to receive the reference clock signal CLK INT / EXT The duty cycle dependency is removed (generating a constant width signal) so as to extract frequency information from such a reference signal and obtain the second PWM signal D2 for driving the three-input step-up / step-down charge pump 302' coupled thereto.

[0258] For example, the lower portion of the step-up / step-down three-input charge pump 302 ′ may be split into two branches, each of which includes a corresponding current generator and a corresponding switch configured to generate a corresponding current.

[0259] For example, the first branch may include a first branch current I CP11 The first branch current generator 3041 and the first branch switch DN1, and the second branch may include a first branch current generator 3041 and a first branch switch DN1 configured to generate a corresponding second branch current I CP12 ( Figure 8 The second branch current generator 3042 (not shown) Figure 8) and a second branch switch DN2.

[0260] The first branch and the second branch can be matched, that is, the same, for example, the first branch current I CP11 Can be equal to the second branch current I CP12 , so that the first branch current generator 3041 and the second branch current generator 3042 are configured to sink half of the current generated by the second current generator 306 .

[0261] The first branch of the lower portion of the step-up / step-down three-input charge pump 302' may be configured to receive a constant width signal from the first constant pulse block 3101, ie, the first branch PWM signal D 11 , this first branch PWM signal D 11 Instructing the first branch switch DN1 to be opened or closed, for example, in response to the first branch PWM signal D 11 is set to a high logic level and closed, and in response to this first branch PWM signal D 11 Set to a low logic level to disconnect.

[0262] The first constant pulse block 3101 may be configured to generate a first current controlled oscillator CCO from the first current controlled oscillator CCO R Receive the first input signal S R,I , and in response to the received first input signal S R,I Each rising edge of generates a constant width pulse, for example, whose width is equal to the time T' PULSE This constant width pulse pair is used to drive the first branch PWM signal D of the first branch switch DN1 included in the three-input step-up / step-down charge pump 302'. 11 Perform plastic surgery.

[0263] It should be noted that the constant width pulse generated by the first constant pulse block 3101 may also be in response to the received first input signal S R,I The first constant pulse block 3101 can be configured to generate a first constant pulse from each falling edge of the first input signal S R,I The duty cycle dependency is removed (generating a constant width signal) so as to extract frequency information from such a signal, thereby obtaining the first branch PWM signal D 11 , for driving a three-input step-up / step-down charge pump 302' coupled thereto.

[0264] The second branch of the lower portion of the step-up / step-down three-input charge pump 302' may be configured to receive a constant width signal from the second constant pulse block 3102, ie, the second branch PWM signal D 12 , this second branch PWM signal D 12Instructing the second branch switch DN2 to be opened or closed, for example, in response to the second branch PWM signal D 12 is set to a high logic level and closed, and in response to this second branch PWM signal D 12 Set to a low logic level to disconnect.

[0265] The second constant pulse block 3102 may be configured to generate a second current controlled oscillator CCO from the second current controlled oscillator CCO F Receive the second input signal S F,I , and in response to the received second input signal S F,I Each rising edge of generates a constant width pulse, for example, whose width is equal to the time T' PULSE This constant width pulse pair is used to drive the second branch PWM signal D of the second branch switch DN2 included in the three-input step-up / step-down charge pump 302'. 12 Perform plastic surgery.

[0266] It should be noted that the constant width pulse generated by the second constant pulse block 3102 may also be in response to the received second input signal S F,I The second constant pulse block 3102 can be configured to generate a second constant pulse from the second input signal S F,I The duty cycle dependency is removed (generating a constant width signal) so as to extract frequency information from such a signal, thereby obtaining the second branch PWM signal D 12 , for driving a three-input step-up / step-down charge pump 302' coupled thereto.

[0267] In this way, the charge obtained by the step-up / step-down three-input charge pump 302' on the first capacitor C1 and the second capacitor C2 of the filter stage can be synchronized with the reference clock signal CLK INT / EXT The charge drawn from the first capacitor C1 and the second capacitor C2 can be proportional to the frequency of the first input signal S R,I and the second input signal S F,I is proportional to the common-mode frequency of the current controlled oscillator CCO (ie, the common-mode frequency of the current controlled oscillator CCO).

[0268] Regardless of the operating conditions of the DC-DC converter, the charges obtained on / drawn from the first capacitor C1 and the second capacitor C2 can be substantially stable. In fact, the reference clock signal CLK is stable both in steady-state conditions and during transients (i.e., regardless of the operating conditions). INT / EXT The values ​​of both the frequency of and the common-mode frequency of the current controlled oscillator CCO can be kept substantially stable (taking into account the given tolerances).

[0269] In fact, in steady-state conditions, the current controlled oscillators CCO are configured to have the same frequency, while during transient conditions, the frequency of one of the current controlled oscillators is increased by a given amount and the frequency of the other of the current controlled oscillators is reduced by the same given amount, thus maintaining their average frequency substantially stable (taking into account a given tolerance) regardless of the operating conditions, resulting in a substantially stable value of the common-mode frequency of such current controlled oscillators CCO.

[0270] like Figure 8 As described, the time-based DC-DC converter 304 can provide an average frequency of the current controlled oscillator CCO (ie, the common mode frequency of the current controlled oscillator CCO) and the reference clock signal CLK INT / EXT frequency alignment.

[0271] It should be noted that the common mode frequency of the current controlled oscillator CCO can be configured to be the same as the reference clock signal CLK INT / EXT The structure of the frequency aligned time-based DC-DC converter 304 may also be implemented differently, thus, Figure 8 The structure of the illustrated DC-DC converter is provided herein only by way of example and is not intended to limit the scope of protection of this document.

[0272] For example, if it is configured to generate a corresponding first branch current I CP11 The first branch current generator 3041 is configured to generate a corresponding second branch current I CP12 The second branch current generator 3042 is configured to generate a second current I CP2 The same result can be obtained by providing the corresponding current for half the duration of the second current generator 306 .

[0273] In this case, the first branch current I CP11 , the second branch current I CP12 and the second current I CP2 can have equal values, and therefore, the sizes of the first branch current generator 3041, the second branch current generator 3042, and the second current generator 306 can be adjusted to carry equal amounts of current.

[0274] For example, if the signal generated by the current controlled oscillator CCO (ie, the first input signal S R,I and the second input signal S F,I ) by a factor of 2, for example by using a flip-flop to perform this division, the same result can be obtained.

[0275] It should be noted that even in this case, the first branch current I CP11 , the second branch current I CP12 and the second current I CP2 can have equal values, and therefore, the sizes of the first branch current generator 3041, the second branch current generator 3042, and the second current generator 306 can be adjusted to carry equal amounts of current.

[0276] For example, if the reference clock signal CLK is provided at twice the frequency to which the switching activity of the DC-DC converter is to be locked INT / EXT , the same result can be obtained.

[0277] In this case, the reference clock signal CLK INT / EXT The frequency of the reference clock signal CLK can be divided by a factor equal to 2, for example using a flip-flop to perform this division, and this frequency division INT / EXT The coupling to the three-input step-up / step-down charge pump 302 ′ may be performed with or without such a third constant pulse block 3103 .

[0278] It should be noted that if this frequency-divided reference clock signal CLK INT / EXT In the absence of such a third constant pulse block 3103 coupled to the three-input step-up / step-down charge pump 302', the first input signal S R,I and the second input signal S F,I (generated by the current controlled oscillator CCO) will be divided by a factor of 2 and coupled to the three-input step-up / step-down charge pump 302 ′ without the first constant pulse block 3101 and the second constant pulse block 3102 .

[0279] If the divided reference clock signal CLK INT / EXT In the absence of the third constant pulse block 3103, coupled to the three-input step-up / step-down charge pump 302', the divided reference clock signal CLK INT / EXT May correspond to the second PWM signal D2.

[0280] It is to be noted that such a third constant pulse block 3103 may not be required since the operation of dividing the digital signal by a factor equal to 2 using a flip-flop may already provide a constant width signal, i.e., a signal with a constant duty cycle, e.g. a duty cycle equal to 50%, thereby removing the duty cycle dependency in the absence of the operation of the third constant pulse block 3103.

[0281] It should be noted that the collectively referred to as 310 Figure 6 and 8The constant pulse block in can be implemented in different ways (depending on the selected pulse duration), for example in any known way, such as: a chain of inverters and combinational logic or latches; or an analog timer, such as an inverter or I / C with a hard-squarer comparator, i.e. a known circuit comprising a controlled current generator I, which is coupled to a capacitor C and the non-inverting terminal of a hard-squarer comparator (whose inverting terminal is coupled to the input voltage).

[0282] It should be noted that the duration (ie, width) of the constant width pulse generated by the constant pulse block 310 (ie, time T PULSE or T' PULSE ) may have: a lower limit value given by the nonlinearity and non-ideality of the boost / buck charge pump 302 or the three-input boost / buck charge pump 302'; and an upper limit value given by the maximum operating frequency.

[0283] Note that by using Figures 4 to 8 Embodiments of the present invention may facilitate control, for example by varying the frequency of switching activity of a corresponding time-based DC-DC converter, such switching activity not affecting regulation of such DC-DC converter.

[0284] Therefore, if Figures 4 to 8 Embodiments may help improve the performance of a time-based DC-DC converter, for example because the frequency of the switching activity of the time-based DC-DC converter may be adapted depending on the application by aligning it with a provided internal or external clock signal.

[0285] It is noted that the time-based DC-DC converters 30, 301 and 304 are characterized by a high symmetry, so that, for example, the first current controlled oscillator CCO fed by the first phase detector PD1 and the second phase detector PD2, respectively, R and the second current controlled oscillator CCO F The generated signals can be exchanged without problems when operating such time-based DC-DC converters 30 , 302 and 304 .

[0286] In fact, in steady-state conditions, the first current controls the oscillator CCO R and the second current controlled oscillator CCE F Such signals generated may have the same frequency value.

[0287] It should be noted that the value is configured to provide I CM_CCO Such a controlled current generator 200' of common mode current can be realized with a voltage-to-current buffer, for example Figure 5A voltage-to-current buffer of the type described herein by way of non-limiting example, any voltage-to-current buffer using an operational amplifier, any voltage-to-current buffer using a simple common drain stage, or any other known voltage-to-current buffer configuration.

[0288] It should be noted that the first input signal S may be fed to the first phase detector PD1 and the second phase detector PD2 before being fed to the first phase detector PD1 and the second phase detector PD2. R,I and the second input signal S F,I to perform processing, such as squaring or any other type of processing (in accordance with Figure 4 , 5 and 8 in the embodiments).

[0289] It should be noted that the voltage-increasing / voltage-decreasing charge pump 302 (eg, the first current I CP1 and the second current I CP2 The mismatch between the first phase detector PD1 and the second phase detector PD2 may only affect the corresponding periods of the first PWM signal D1 and the second PWM signal D2, and substantially does not affect the control signal V CONTROL The average value (note that, if Figure 8 As described above, such advantages may not exist in the time-based DC-DC converter 304, and therefore, portions of the following description that reference such advantages should not be considered inconsistent with the time-based DC-DC converter 304. Figure 8 time-based DC-DC converter architecture).

[0290] Therefore, the design of the added negative feedback loop is not critical, i.e., the mismatch (according to Figure 8 With the exception of embodiments of the time-based DC-DC converter 304, the present invention is insensitive to PVT variations and changes in operating conditions.

[0291] For example, a mismatch to which this added negative feedback loop is insensitive may be: the presence of a current different from the second current I CP2 The first current I CP1 There is a first phase detector PD1 different from the second phase detector PD2, for example, having a different propagation delay; there is an offset in the amplifier stage 308; the second transistor M P0 and the third transistor M P1 / The fourth transistor M P2 There is a mismatch between the third transistor M P1 and the fourth transistor M P2 There is a mismatch between them.

[0292] The first four mismatches (as described by the first four points in the previous list) can be compensated by this added negative feedback loop because it is configured to act as an integrator.

[0293] In fact, under steady-state conditions, the control signal V CONTROL is set to a specific value, such as V CONTROL *, this particular value V CONTROL * is helpful to pass the value of I CM_CCO The value of the common-mode current biases the current controlled oscillator CCO to obtain a frequency of the signal generated by such a current controlled oscillator CCO, which is equal to the reference clock signal CLK INT / EXT frequency.

[0294] Therefore, in a steady state, due to the first current I flowing in the first switch DN during a switching cycle, CP1 The amount of charge subtracted from the first capacitor C1 and the second capacitor C2 is equal to the second current I flowing in the second switch UP during the same switching cycle. CP2 The amount of charge injected into the first capacitor C1 and the second capacitor C2 can thus be CONTROL * Maintain the same value, otherwise, this specific value V CONTROL *May be subject to transients (and will not be in steady state conditions).

[0295] Therefore, the mismatches at the first four points described in the above list can be absorbed by the integration action performed by the added negative feedback loop (eg, by the step-up / step-down charge pump 302).

[0296] It should be noted that by including the first capacitor C1, the second capacitor C2 and the filter resistor R Z The added filtering stage can further enhance the integration action performed by the step-up / step-down charge pump 302.

[0297] The mismatch between the third transistor MP1 and the fourth transistor MP2 may cause a differential error, which may affect the switching frequency of the DC-DC converter, thereby causing the first input signal S R,I and the second input signal S F,I The switching frequencies of the DC-DC converters are different (this mismatch is absorbed by the time-based control loop of the DC-DC converter).

[0298] Therefore, advantageously, such mismatch between the third transistor MP1 and the fourth transistor MP2 may not even affect the added negative feedback loop, since it only affects the common mode of such frequency (ie, the first input signal S R,I and the second input signal S F,I common-mode frequencies).

[0299] It should be noted that the behavior of the time-based DC-DC converters 30, 301, 302, 303 and 304 is consistent with the reference clock signal CLK INT / EXTThe duty cycle (i.e., the percentage of the waveform period in which the waveform is set to a high logic level) of the reference clock signal CLK (or reference binary signal) is irrelevant, and therefore, any reference clock signal CLK may be considered INT / EXT (or any reference binary signal), thereby allowing high flexibility.

[0300] like Figures 4 to 8 Embodiments of the present invention may advantageously facilitate monitoring the frequency of the switching activity of the DC-DC converter based on time, since the current reference clock signal CLK synchronized with the switching activity INT / EXT The frequency of may be known; obtain the specific control variable, that is, the control signal V CONTROL , used to compare the frequency of the switching activity of the time-based DC-DC converter to a selected (internal or external, and of any frequency) reference clock signal CLK INT / EXT or any other selected binary signal, thereby facilitating the use of such a time-based DC-DC converter in various applications with different requirements; controlling and monitoring the switching activity frequency, limiting or removing the impact on stability, phase margin or performance during dynamic / transient operation, because a separation between the time-based control loop and the negative feedback loop is provided, i.e., the negative feedback loop does not affect the operation of the time-based control loop because they are decoupled; maintaining high flexibility in designing the time-based DC-DC converter and the corresponding time-based control loop and the negative feedback loop because they can be designed and / or or optimized (i.e., independent of other loops), since the time-based control loop and the negative feedback loop are separated / decoupled (the only shared element is the gain of the current controlled oscillator CCO), facilitating the use of such a negative feedback loop even in the case of differently implemented time-based DC-DC converters and / or differently implemented time-based control loops; and limiting or removing additional fine-tuning of components included in the added negative feedback loop (according to the time-based DC-DC converter) with minimal added current consumption (which may not have an impact on the efficiency / quiescent consumption of the time-based DC-DC converter) using the time-based DC-DC converter. Figure 8 304).

[0301] With regard to the previous point, it should be noted that according to Figure 7 and 8 The embodiments of the present invention may begin to occupy relevant current consumption, complexity and silicon area, and according to Figures 4 to 6 Embodiments of can advantageously have minimal added current consumption, complexity, and silicon area. For example, according to Figure 4 and 5An embodiment may include a pair of phase detectors PD1 and PD2, which may be implemented with digital blocks that may not consume quiescent current, may not require area, and where matching may not be critical.

[0302] As already described, possible applications of the solution described herein are applications where alignment of the switching activity of a time-based DC-DC converter with a given reference signal provided internally or externally can be beneficial, for example non-exhaustive examples of such applications could be: a power management IC (PMIC) for an active matrix organic light emitting diode (AMOLED) power supply incorporating a time-based buck / boost / buck-boost DC-DC converter; a time-based buck DC-DC converter embedded in a SoC and configured to power a microprocessor and / or microcontroller core; or a time-based buck DC-DC converter for industrial and / or automotive applications.

[0303] It should be noted that Figures 4 to 8 The negative feedback loop shown is referenced Figure 3 The illustrated time-based DC-DC converter topology is described, but such a negative feedback loop can also be implemented by coupling the first phase detector PD1 and the second phase detector PD2 to the first input signal S R,I and the second input signal S F,I Corresponding signals (ie, signals with similar usage) may be implemented with any other known topology of a time-based DC-DC converter.

[0304] To further monitor the switching activity of the DC-DC converter based on time, additional current sensors optimized for the DC-DC converter may be integrated in embodiments of the solution described herein.

[0305] It should be noted that even though this additional current sensor is described herein as being integrated in a Figures 4 to 8 Within the illustrated time-based DC-DC converter structure, this additional current sensor can also be advantageously used in other types of DC-DC converters, i.e., not only inductor-based hard-switching converters, but also resonant, hybrid, multi-level, AC to DC converters, etc., because it is configured to be coupled with the low-side switch of a half-bridge, which may be present in many types and configurations of DC-DC converters.

[0306] Thus, embodiments of the time-based DC-DC converter described herein can advantageously be further controlled and monitored using additional current sensors, for example by monitoring the actual value of the current flowing within a coil of a DC-DC converter, and using such information to control the switching activity of such a DC-DC converter (e.g., changing the frequency of a reference signal that is aligned with the switching activity).

[0307] In addition, such additional current sensors can be used to improve the safety and / or stability of a DC-DC converter including the additional negative feedback loop described herein, for example by providing a negative coil current protection feature that helps limit the minimum coil current (i.e., the current flowing within the coil of the DC-DC converter) to a given negative value.

[0308] It is to be noted that, advantageously, settings relating to the safety and / or stability features provided (for example settings relating to such negative coil current protection feature) can be tuned / varied with respect to the frequency of the switching activity of the DC-DC converter under consideration, where such frequency of the switching activity can be configured to be varied depending on the reference clock signal via the additional negative feedback loop described herein.

[0309] Reference is also made to the following related arts (all of which are incorporated herein by reference): “Loop gain analysis and development of high-speed high-accuracy current sensors for switching converters”, published by Lam et al. in the Proceedings of the IEEE Symposium on Circuits and Systems, May 2004, pp. 828-831; and “Power Stages, Gate Drivers and Protection”, published by Wicht at the MEAD Education at the Institute of Microelectronic Systems, Leibniz University Hannover, Germany, on November 24 and 26, and December 1 and 3, 2020.

[0310] It can be noted that if the low-side switch LS of the half-bridge of the time-based DC-DC converter (e.g., the DC-DC converter 30, 301, 302, 303, or 304) (for the description of such low-side switch LS and the corresponding half-bridge LS, HS, refer to Figure 3 ) is closed, then the first node LX (refer to Figure 3 or 6) (ie, such a low-side switch LS (eg, a low-side power MOSFET MN POWERFET The node between the inductor L and the coil current I flowing in the inductor L corresponds to L A low impedance source of information, in fact:

[0311]

[0312] Where V LX(t) is the voltage measured at the first node LX at time t, I L (t) is the coil current I flowing in the inductor L at the same time t L ,and is the value of the on-resistance, i.e., the POWERFET The resistance value between the drain terminal and the source terminal of a MOSFET during operation (i.e., when such a MOSFET is closed).

[0313] Additionally, it may be noted that the DC-shifted (i.e., voltage-shifted by a given DC value (which may also be fixed)) low input impedance node N1 may be considered to retrieve information about the coil current I flowing in the inductor L using a voltage-to-current conversion exploited by the low impedance of the first node LX. L Information (for example, when this coil current I L (assuming both positive and negative values).

[0314] For example, this DC-shifted low input impedance node N1 can be used with a high-gain sensor negative feedback loop (in Fig. 9 The high gain sensor negative feedback loop is realized, for example, using an operational amplifier 400, which can be configured to act on the output transistor (in Fig. 9 M N3 )'s gate, thereby creating a DC-shifted (and fixed) low-impedance node N1 at the source terminal of such transistor.

[0315] If the low-side power MOSFET MN POWERFET closed, i.e. in the conducting state, then for example through the first resistor (in Fig. 9 The source terminal of the transistor (ie, the low impedance node N1) is coupled to the low-side power MOSFET MN. POWERFET The low-side power MOSFET MN can be POWERFET The voltage drop across the coil is converted into corresponding coil current information, which is then converted into corresponding coil current information by an amplifier stage (e.g., a sensor current mirror with an amplification factor equal to M (in Fig. 9 402)) amplified, and in the second matching resistor (in Fig. 9 obtained on (referred to as R2).

[0316] Therefore, the left branch of this additional current sensor is configured to retrieve information about the coil current I L The information of the sensor current mirror may then be used to perform the desired amplification operation, such as using a sensor current mirror having an amplification factor equal to M, for example including a current mirror configured to provide an output current (at Fig. 9 I SENSE) of p-channel MOSFET.

[0317] Fig. 9 is a low-side current sensor 40 for a DC-DC converter, for example, respectively Figures 4 to 8 Time-based DC-DC converters 30 , 301 , 302 , 303 and 304 .

[0318] The low-side current sensor 40 described herein facilitates control and monitoring of a time-based DC-DC converter, such as Figures 4 to 8 As shown, it is configured to monitor the amount of current flowing in the low-side switch LS of the half-bridge (i.e., the current flowing in the coil of the corresponding DC-DC converter, i.e., the coil current I L ), so it has the characteristics of fast transient response; it also monitors the coil current I in DC-DC converters with high-frequency switching activities L This feature is particularly advantageous for the DC-DC converter described herein because by changing the reference clock signal CLK INT / EXT , the frequency of switching activity can be set to any possible value; and the influence of PVT variations and different DC-DC converter operating conditions is limited or removed. This feature is again beneficial for the DC-DC converters described in this article because they can operate under the above-mentioned different conditions (complementary and non-complementary steady state, transient).

[0319] Therefore, such a low-side current sensor 40 may be advantageously used in a DC-DC converter having the structure described herein, helping to obtain a more stable and safer loop, ie, a time-based control loop and / or a negative feedback loop.

[0320] Therefore, it can be noted that Figures 4 to 8 As described, a low-side current sensor 40 coupled to a DC-DC converter can facilitate control of the switching activity of such a DC-DC converter (e.g., by, for example, enabling protection in response to an abnormal current measurement to interrupt an abnormal operating condition) and monitoring (e.g., by storing and / or analyzing the behavior of data collected by such a current sensor) thereby improving its performance.

[0321] As previously described, such a low-side current sensor 40 is configured to be coupled to a low-side power MOSFET MN using, for example, a half-bridge. POWERFET The low-side switch LS coupling is realized (such as Figure 3 and sensing the current flowing in such a low-side switch LS, ie, such a low-side power MOSFET MN POWERFET, the current flowing in the low-side switch LS is the current flowing in the coil (eg, inductor L) of the corresponding DC-DC converter (ie, buck or boost DC-DC converter) (ie, coil current I L ).

[0322] In this way, the coil current I can be obtained. L This information is used for time-based control loops and / or negative feedback loops, for example for the above-mentioned protection purposes.

[0323] It should be noted that the low-side power MOSFET MN POWERFET may be configured to respond to a low-side switching signal LS received at its gate terminal indicating to open or close the low-side switch of the half-bridge, respectively. ON / OFF And open or close.

[0324] This low-side power MOSFET MN POWERFET The (e.g. n-type power MOSFET) may have a first diode D1 coupled between its source terminal and its drain terminal to protect it from reverse current flow, wherein such first diode D1 may already be present in such low-side power MOSFET MN POWERFET in the body well.

[0325] This low-side current sensor 40 is connected through a fifth transistor (eg, a power MOSFET M N1 , such as an n-type MOSFET) is coupled to this low-side power MOSFET MN POWERFET The fifth transistor is configured to realize the low-side current sensor 40 and the low-side power MOSFET MN. POWERFET Decoupling switch.

[0326] This fifth transistor M N1 (i.e., power MOSFET M N1 ) is also configured next to the low-side power MOSFET MN POWERFET After closing, the low-side power MOSFET MN POWERFET Before disconnection (before) disconnection, the low-side power MOSFET MN POWERFET Acting as a safety / protection switch, it helps to comply with the high voltage switching activities of the high voltage DC-DC converter.

[0327] This fifth transistor M N1The fifth transistor M may have a second diode D2 coupled between its source terminal and its drain terminal to protect it from reverse current flow, wherein such a second diode D2 may already be present in the fifth transistor M. N1 in the body trap.

[0328] The fifth transistor M N1 is also configured to have its drain terminal coupled to the first node LX, ie, to such a low-side power MOSFET MN POWERFET The drain terminal of the sixth transistor, such as MOSFET M, is coupled to the drain terminal of the sixth transistor, such as MOSFET M N4 , such as an n-type MOSFET, and is coupled to the third node N1 through the first resistor R1, and has its gate terminal connected to a supply for opening / closing such a fifth transistor M N1 The voltage EN SENSE The node is coupled and supplied with voltage EN SENSE This node is also coupled to the gate terminal of a seventh transistor, for example MOSFET M N2 , such as an n-type MOSFET, and coupled to the sixth transistor M through an inverting stage N4 The gate terminal of MOSFET M N4 .

[0329] This third node N1 is the previously described DC shifted (and fixed) low impedance node that helps to switch the low-side power MOSFET MN POWERFET The voltage drop on the coil is converted into corresponding coil current information.

[0330] The sixth transistor M N4 It is also configured to have its source terminal coupled to the ground GND, and implement a low voltage switch for enhancing the transient response of the low-side current sensor 40 .

[0331] Therefore, the sixth transistor M N4 is configured, for example, with a corresponding voltage V R The first branch of the low-side current sensor 40 (ie, the first branch including the fifth transistor M) is pre-biased. N1 , a first resistor R1, an amplifier stage 400 (ie, a high gain sensor negative feedback loop), an eighth transistor M N3 , the ninth transistor M P3 and the tenth transistor M P4 branch) to improve its transient response, therefore, when the fifth transistor M N1 When disconnected, the sixth transistor M N4 The first branch of the amplifier stage 400 is configured to maintain bias (for this reason, the sixth transistor M N4The gate terminal is configured to be supplied with a voltage EN SENSE The inverted version of the signal at the node is coupled).

[0332] This sixth transistor M may not be used. N4 , thus, increasing the transient response of the low-side current sensor 40 , but also reducing its maximum quiescent current, thereby reducing current consumption.

[0333] For example, the amplifier stage 400 implemented by the operational amplifier 400 corresponds to the operation on the corresponding output transistor (ie, the eighth transistor M1). N3 ) of the gate of the high gain sensor negative feedback loop so that in this eighth transistor M N3 The amplifier stage 400 is also configured to couple its positive input terminal to a voltage set to the input offset voltage V IN OFFSET node, this input offset voltage V IN OFFSET is used as an offset for measuring even negative coil current values; has its negative input terminal coupled to a third node N1, i.e., a low impedance node for DC shifting, such third node N1 being set to a first voltage V1; and has its output terminal coupled to a gate voltage V supplied thereto. G The eighth transistor M N3 (i.e., MOSFET M N3 , such as a gate terminal of an n-type MOSFET).

[0334] The eighth transistor M N3 The sensor current mirror 402 is also configured to have its source terminal coupled to such a third node N1, and have its drain terminal coupled to the input terminal T IN , such as a conventional low voltage cascode current mirror (LVCCM).

[0335] It is to be noted that even though a current mirror comprising a p-type MOSFET arranged in a cascode structure is proposed in the following description, any other type of current mirror may be considered, for example a current mirror comprising a p-type MOSFET not arranged according to the cascode structure.

[0336] The sensor current mirror 402 is configured to receive the current from the input terminal T IN Receive the input current, that is, in the eighth transistor M N3 current flowing within, and from is set to the output voltage V SENSE The output terminal T OUT Provides output current I SENSE , whose value is proportional to the received input current by a factor M. For example, if M = 1, then the output current ISENSE The value of replicates the value of this received input current.

[0337] The sensor current mirror 402 includes: a ninth transistor M P3 , that is, MOSFET M P3 , such as a p-type MOSFET, which is configured so that its drain terminal is coupled to the input terminal T IN , so that its source terminal is coupled to the tenth transistor M P4 The drain terminal of MOSFET M P4， For example, a p-type MOSFET, and having its gate terminal coupled to a supply with a value of V CASC The node of the common source and common gate voltage; the tenth transistor M P4 , that is, MOSFET M P4 , which is configured so that its source terminal is supplied with a second power supply voltage V DD , for example, 1.8V, and connect its gate terminal to the input terminal T IN coupling; eleventh transistor M P5 , that is, MOSFET M P5 , such as a p-type MOSFET, which is configured so that its drain terminal is coupled to the output terminal T OUT , so that its source terminal is coupled to the twelfth transistor M P6 The drain terminal of MOSFET M P6 , such as a p-type MOSFET, and having its gate terminal coupled to a supply having a value of V CASC A node of a common source and common gate voltage; and a twelfth transistor M P6 , that is, MOSFET M P6 , which is configured so that its source terminal is supplied with a second power supply voltage V DD , and its gate terminal is connected to the input terminal T IN coupling.

[0338] It is noted that such a sensor current mirror 402 may also be implemented using a BJT (“bipolar junction transistor”), or may have any other structure / component known in the art.

[0339] The seventh transistor M N2 (i.e., MOSFET M N2 ) is also configured to have its source terminal coupled to the ground GND, and have its drain terminal coupled to the output terminal T through the second matching resistor R2. OUT， This seventh transistor N N2 is configured as the fifth transistor M N1 of replication to improve accuracy.

[0340] This seventh transistor MN2 Can be configured to always be on ( Fig. 9 ) or enabled only during the sensing activity of the low-side current sensor 40 (e.g. Fig. 9 For this reason, the seventh transistor M N2 The gate terminal is coupled to the supply voltage EN SENSE to the same node) to reduce current consumption.

[0341] With this configuration, the output voltage V SENSE By giving the gain is amplified, that is:

[0342]

[0343] in is the low-side power MOSFET MN POWERFET The on-resistance value, which is the resistance value between the drain terminal and the source terminal of the MOSFET during operation (i.e., when such a MOSFET is closed), The seventh transistor M N2 The on-resistance value, and The fifth transistor M N1 The on-resistance value.

[0344] It should be noted that the fifth transistor M N1 and the seventh transistor M N2 (ie, the fifth transistor M N1 The MOSFETs (see Figure 2) can be simple switches and, typically, their on-resistance values ​​can be smaller than R1, so:

[0345]

[0346]

[0347] Therefore, this output voltage V SENSE can be obtained as:

[0348]

[0349] Where V SENESE (t) is the output voltage V at time t SENSE , I L (t) is the coil current I at the same time t L ,therefore:

[0350]

[0351] in Is Fig. 9 The circuit system amplifies the input offset voltage VIN OFFSET , that is, its factor is equal to the gain G SENSE ,Right now:

[0352]

[0353] Also note that:

[0354]

[0355] Therefore, by appropriately selecting the ratio between the second matching resistor R2 and the first resistor R1 (ie, R2 / R1) and / or the factor M of the sensor current mirror 402, a desired amplification factor G can be obtained. SENSE .

[0356] Due to the expected amplification factor G SENSE The sizes of the second matching resistor R2 and the first resistor R1 may be adjusted depending on the ratio between the second matching resistor R2 and the first resistor R1, thereby selecting the value of one of the resistors taking into account the desired current consumption and bandwidth, and keeping their ratio at the desired value by determining the value of the other resistor accordingly.

[0357] The low-side current sensor 40 may be used to sense the negative coil current, for example when the corresponding time-based DC-DC converter is operated in forced continuous conduction mode (forced CCM) at no load or is configured to provide sinking capability.

[0358] In this case, the input offset voltage V provided to the amplifier stage 400 is IN OFFSET is used as an offset to facilitate measuring this negative coil current, and thus, the most negative coil current I to be sensed and used to correctly bias the amplifier stage 400 can be determined based on the most negative coil current I L To select this input offset voltage V IN OFFSET The value of .

[0359] The eighth transistor M N3 The size of the m , for example it can be a natural MOSFET.

[0360] The amplifier stage 400 may be a single-stage OTA (operational transconductance amplifier) ​​or a two-stage class-A operational amplifier, depending on the desired accuracy, bandwidth, and current consumption budget.

[0361] The seventh transistor M N2 The width-to-length ratio W / L (ie, the ratio obtained by dividing the MOSFET channel width W by the MOSFET channel length L) of the fifth transistor MN1 The width-to-length ratio W / L of may be equal to the ratio between the second matching resistor R2 and the first resistor R1, thus:

[0362]

[0363] To further describe the behavior of the low-side current sensor 40 , a small signal analysis is described below.

[0364] The small signal input impedance seen at the input node (ie, first node LX) of such a low-side current sensor 40 can be expressed by the following equation:

[0365]

[0366] where z IN is the small signal input impedance, v LX is the small signal voltage measured at the first node LX, and i IN is a small signal current flowing in such an input node (ie, the first node LX).

[0367] This small signal input impedance z IN It can be further expressed as:

[0368]

[0369] in The eighth transistor M N3 is the transconductance of A(S), and A(S) is the gain of the amplifier (eg, operational amplifier 400) used in the high gain sensor negative feedback loop.

[0370] Therefore, using this small signal analysis, it is noted that the low-side current sensor 40 having the structure described herein can be configured to have a low input impedance, so that, for example, if a high-gain sensor negative feedback loop is changing the gate voltage V G The value of hysteresis, then the corresponding large amount of current can still be supplied by the eighth transistor M N3 Therefore, such a low-side current sensor 40 can be advantageously configured to have a good transient response.

[0371] The good transient response of the low-side current sensor 40 is due to the high gain sensor negative feedback loop changing the gate voltage V G The eighth transistor M is lagging behind in terms of value N3The ability to manage the large amount of current flowing therein may be due to the fact that at sufficiently high frequencies, the gain of the amplifier used in the high gain sensor negative feedback loop A(s) is low (i.e., at a given threshold), i.e., if the amplifier stage 400 does not provide sufficient gain, the high gain sensor negative feedback loop will lag in response, and therefore, the eighth transistor M N3 Any change in the value of the current flowing in the sensor is not managed by the negative feedback loop of this high gain sensor, but only by this eighth transistor M N3 manage.

[0372] Therefore, at high frequencies, the gate voltage V G The value may not move, but due to the high Right now, z IN It may still remain around R1.

[0373] The closed-loop transfer function of the low-side current sensor 40 can be expressed by the following formula:

[0374]

[0375] where v SENSE (S) is at the output terminal T OUT The small signal voltage measured on the

[0376]

[0377] Right now:

[0378]

[0379] If the amplifier used in the high gain sensor negative feedback loop (eg, operational amplifier 400) is configured to have a high gain A(S), and if the eighth transistor M N3 Transconductance is configured to remain high, then:

[0380]

[0381] and:

[0382]

[0383] Therefore, even with this analysis, it can be confirmed that by appropriately selecting the ratio between the second matching resistor R2 and the first resistor R1 (ie, R2 / R1) and / or the factor M of the sensor current mirror 402, the desired amplification factor can be obtained.

[0384] In addition, the loop gain L of the high-gain sensor negative feedback loop Gcan be expressed as:

[0385]

[0386] In summary, the DC-DC converter 30 described herein may further include a low-side switch, ie, a low-side switch LS, which may use a low-side power MOSFET MN, for example. POWERFET The implementation is configured to be coupled between a ground GND and a second node (ie, a first node LX), the second node having a high-side switch (ie, a high-side switch HS) and an inductor L coupled thereto.

[0387] For example, using a low-side power MOSFET MN POWERFET The implemented low-side switch LS is also configured to be coupled to a current sensor 40 through the second node LX. The current sensor 40 is configured to sense a coil current I flowing in the inductor L. L .

[0388] Such a current sensor 40 comprises: a sensor transistor, namely, an eighth transistor M N3 , is configured to couple a current source terminal (eg, a source terminal or an emitter terminal) to, for example, a low-side power MOSFET MN POWERFET The low-side switch LS is implemented so that the control terminal (e.g., gate terminal or base terminal) is coupled to the sensor negative feedback loop 400, and the current drain terminal (e.g., drain terminal or collector terminal) is coupled to the first branch of the sensor current mirror 402; the sensor negative feedback loop 400 is configured to provide such a sensor transistor M N3 This control terminal supplies the control voltage, i.e., the gate voltage V G Sensor current mirror 402, is configured to pass through the sensor current mirror 402 of this first branch from the sensor transistor M N3 The current drain terminal of the sensor current mirror 402 receives the first sensor current, applies a gain, such as a factor M, to the first sensor current to obtain a second sensor current, and provides the second sensor current to the load (e.g., including the second matching resistor R2 and the seventh transistor M) through the second branch of the sensor current mirror 402. N2 ).

[0389] Such a sensor negative feedback loop 400 may include a high gain negative feedback loop and is configured to be coupled to a low side switch LS (eg, using a low side power MOSFET MN). POWERFET The sensor transistor M N3 The current source terminal of may include a DC shifted low impedance node N1.

[0390] For example, using a low-side power MOSFET MN POWERFETThe low-side switch LS implemented can be configured to be connected to the sensor switch (ie, the fifth transistor M N1 ) is coupled to the current sensor 40, the sensor switch M N1 is configured to implement a protection function, including: responding to, for example, using a low-side power MOSFET MN POWERFET The low-side switch LS is turned on, making the sensor switch M P1 conduction; and when using the low-side power MOSFET MN POWERFET Before the low-side switch LS is turned off, the sensor switch M N1 No continuity.

[0391] Such a load may include a replica transistor, ie, a seventh transistor M N2 , which is configured to couple the current source terminal to the ground GND, couple the current drain terminal to the second branch of the sensor current mirror 402, and respond to the sensor switch M N1 Conducting and remaining conductive.

[0392] Sensor transistor M N3 The current source terminal of the sixth transistor M may also be configured to be coupled to a bias transistor (ie, N4 ) of the current drain terminal, wherein such bias transistor M N4 is configured to have its current source terminal coupled to ground GND, and in response to such a sensor switch M N1 The sensor transistor M is not turned on and is maintained by keeping it turned on. N3 The current source terminal is biased.

[0393] In order to sense the positive and negative coil currents, the sensor negative feedback loop 400 can also be configured to receive an offset voltage, that is, an input offset voltage V IN OFFSET , where this control voltage V G is the received offset voltage V IN OFFSET function.

[0394] It is noted that the low-side current sensor 40 having the structure described herein can be used to obtain a current sensor configured to detect the coil current I by adding (a small number of) components. L The low side current sensor 40' detects the valley value or peak value.

[0395] In order to obtain the detection coil current I L The low-side current sensor 40 ′ uses a comparator to measure the amplified and DC-shifted voltage (corresponding to the low-side power MOSFET MN) measured on the first node LX. POWERFETThe drain-to-source voltage V DS , i.e., the voltage between the drain terminal and the source terminal) (i.e., the output voltage V SENSE ) and the selected voltage threshold V VY TH is compared to the selected voltage threshold V VY TH is to select the output voltage V SENSE The desired trigger value of the valley / peak value is selected, which corresponds to the coil current I L and indicates the valley / peak value of such voltage measured on the first node LX.

[0396] Fig.10 is a low-side current sensor 40 ′, which is configured to detect the coil current I L valley value and are used with a DC-DC converter, for example, respectively Figures 4 to 8 The time-based DC-DC converter 30, 301, 302, 303 or 304 is used together.

[0397] Fig. 9 The low-side current sensor 40 can be combined with additional components to obtain Fig.10 The valley detector low side current detector 40'.

[0398] For example, such a valley detector low-side current sensor 40' can be used to monitor the coil current I flowing in the inductor L of a step-down DC-DC converter. L valley value, and when it reaches the corresponding given voltage threshold V VY TH Provide feedback signal VY when

[0399] It should be noted that Fig.10 The low-side current sensor 40' shown in FIG. 4 can be easily modified to implement a peak detector low-side current sensor 40' for use in a step-up DC-DC converter. The peak detector low-side current sensor 40' is configured to detect the coil current I L peak value, for example by changing the sign of the comparison performed by comparator 404.

[0400] For example, such a peak detector low-side current sensor 40' can be used to monitor the coil current I flowing in the inductor L of a step-up DC-DC converter. L The peak value of the voltage reaches the corresponding given threshold value V VY TH When providing feedback signal VY, this given voltage threshold V VY THThe value of is higher than that used for the valley detector low side current sensor 40 ′.

[0401] Replica transistors (e.g. MOSFET MN REPLICAFET , such as an n-type MOSFET) is configured to replicate the low-side power MOSFET MN at different ratios. POWERFET , therefore, it is the low-side power MOSFET MN POWERFET A scaled version of .

[0402] Therefore, the replica MOSFET MN REPLICAFET can be configured to: couple its source terminal to the ground GND; and to have its gate terminal configured to receive a signal indicating that such replica transistor MN REPLICAFET Open or close the low-side switching signal LS ON / OFF , this low-side switching signal LS ON / OFF Also in the low-side power MOSFET MN POWERFET The gate terminal receives and directs this low-side power MOSFET MN POWERFET and its drain terminal is coupled to the fourth node N2, the positive input terminal of the controlled current source 406 and the comparator 404 is also coupled to the fourth node N2, therefore, this replica MOSFETMN REPLICAFET The fourth node N2 is also configured to supply the voltage used by the comparator 404 as the voltage threshold V VY TH , this voltage threshold V VY TH is the low-side power MOSFET MN POWERFET The drain-to-source voltage V DS (ie, the voltage between the drain terminal and the source terminal (as previously described)).

[0403] The controlled current source 406 is configured to be coupled to the second power supply voltage V DD and the fourth node N2, that is, the replica MOSFET MN REPLICAFET and the positive input terminal of the comparator 404.

[0404] The controlled current source 406 is also configured to generate a variable current I VY , whose variable value can be obtained, for example, according to the following formula:

[0405]

[0406] in The low-side power MOSFET MN POWERFET The coil current threshold flowing inside, is the offset current, which is used to obtain the variable current I VY The constant contribution of the summation, and K is the low-side power MOSFET MN POWERFET And this replica MOSFET MN REPLICAFET The ratio between the width and length ratio.

[0407] Therefore, by placing this low-side power MOSFET MN POWERFET The width-to-length ratio W / L (i.e., the ratio obtained by dividing the MOSFET channel width W by the MOSFET channel length L) of the replica MOSFET MN is divided by REPLICAFET This K value is obtained by the width-to-length ratio W / L, so:

[0408]

[0409] This value of K is above 1 ("one") to minimize current consumption, thus:

[0410] K>>1

[0411] This voltage threshold V VY TH By duplicating the MOSFET MN in this way REPLICAFET The variable current I VY To obtain, which helps to select the detection coil current I L The expected trigger value of the valley.

[0412] The negative input terminal of the comparator 404 is configured to be coupled to Fig. 9 The output terminal T of the low-side current sensor 40 OUT , the output terminal T OUT is set to the output voltage V SENSE , and the output current I SENSE Such a comparator 404 is configured to compare signals received at its input terminals (ie, at its positive and negative input terminals) and to provide a comparison signal VY indicative of a result of such a comparison operation.

[0413] It should be noted that according to Fig. 9 Description, output voltage V SENSE Probably corresponds to the low-side power MOSFET MN POWERFET The drain-to-source voltage V DS An amplified and DC-shifted (i.e., a voltage shifted by a given DC value) version of the voltage across the drain and source terminals.

[0414] In summary, the second sensor current provided by the second branch of the sensor current mirror 402 across the load R2, MN2 is configured to generate a sensing voltage, ie, an output voltage V SENSE , this sensing voltage V SENSE Indicates the coil current I flowing in this inductor L L , and wherein the DC-DC converter 30 further includes a comparator 404 configured to receive the sensing voltage V at a first input terminal SENSE , and receives a selected voltage threshold V at the second input terminal VY TH , and by checking this sense voltage V SENSE Whether this selected voltage threshold V is reached VY TH This sensing voltage V SENSE With this selected voltage threshold V VY TH Make a comparison.

[0415] It is noted that this amplification and this DC shift can help provide an output positive signal, that is, a positive output voltage V SENSE , for example, the comparator 404 can use this output positive signal to detect a valley or a peak (depending on the sign of the comparison performed by such comparator 404 and the topology of the DC-DC converter, such as buck, boost, or other).

[0416] It should be noted that in addition to facilitating the control and monitoring of the switching activity of the DC-DC converter, the embodiments of the low-side current sensor 40 or 40 ′ disclosed herein retrieve information about the instantaneous coil current I L The information can also facilitate:

[0417] loop stability compensation operation, since information about such coil current peaks and / or valleys may be useful in many control schemes of a DC-DC converter, such as current mode control (“CMC”), peak current mode control (“PCMC”), valley current mode control (“VCMC”), etc.;

[0418] Operation aimed at improving safety, since such instantaneous (i.e., real-time and not averaged) coil current can be monitored to avoid exceeding predefined values ​​(e.g., to avoid reaching dangerous values), thereby activating overcurrent protection ("OCP"), short circuit protection ("SCP"), etc.;

[0419] Perform auxiliary measurements and add auxiliary features, in that the retrieved values ​​of the instantaneous coil current can be averaged, e.g., low-pass filtered, and optionally weighted with the duty cycle of the corresponding DC-DC converter to obtain average steady-state information about the coil current, input / line current, output / load current, etc., in order to: implement optimized and customized features such as multi-phase management according to load requirements, dynamic transistor size control to optimize efficiency over a wide load range, etc., and respond to user requests to sense and measure values ​​such as the average current drained from the DC-DC converter input supply, the average current supplied to the output load, etc.;

[0420] A low-side current sensor with fast transient response is obtained, which is particularly useful in converters characterized by high switching frequencies and / or tight actuation times, i.e., in e.g. “boost-like” topologies, where the converter has a very short time to turn on T ON , or in a “buck-like” topology with a very short time to turn off T OFF , because the low-side current sensor described in this article can quickly stabilize and track the value of the coil current;

[0421] This coil current is also sensed in high voltage DC-DC converters, thus, complying with DC-DC converters operating with high input voltage and / or high output voltage and / or wide voltage range;

[0422] Such a coil current can be sensed even if its value is negative, for example when the corresponding DC-DC converter is operated in forced CCM (“forced continuous conduction mode”) under no-load conditions, or in case of a required DC-DC sinking capability;

[0423] amplifying by a given gain factor, i.e., the sensed coil current, thereby providing coil current information amplified by such given gain factor (i.e., current to voltage or current to current), useful, for example, in CMC (“current mode control”), since such given gain factor may affect the stability and performance of the loop of a DC-DC converter operating in such CMC mode;

[0424] Obtaining a low-side current sensor that complies with a low voltage supply (e.g., 1.8V) since such a low voltage supply is typically found in PMIC / SoC / DC-DC and furthermore, the low-side current sensor described herein can be implemented analogically using a standard GO1 CMOS device without any special / additional mask requirements; and

[0425] Reduced cost, since neither additional components outside the chip, nor additional voltage supplies / tracks, additional pads / balls, additional process masks are used, and the low-side current sensor described herein may be characterized by a small silicon area and minimal added consumption, which may not affect the efficiency and quiescent current consumption of the corresponding DC-DC converter.

[0426] Advantageously, the above effects can be obtained by the low-side current sensor described herein even in the presence of: PVT (“process, voltage and temperature”) variations; different operating conditions and parameters, such as for the input voltage V IN , output voltage V OUT , coupled to the corresponding DC-DC converter load, inductor L, output capacitor C O , PWM signal D PWM The switching frequency F SW , parasitic elements, etc.; different application scenarios; or different conditions that may occur after final testing, packaging and assembly, such as aging, welding, etc.

[0427] Therefore, such a low-side current sensor can be independent of the direction of the coil current flowing in the corresponding inductor of the DC-DC converter and independent of the DC-DC converter operation mode (such as continuous conduction mode (CCM), discontinuous conduction model (DCM), forced continuous conduction mode (forced CCM), etc.).

[0428] It is to be noted that such additional current sensors described herein may also be used in the previously mentioned application contexts.

[0429] The solution described in this article helps to obtain a time-based DC-DC converter, which includes an additional negative feedback loop, which includes: a pair of phase detectors, configured to detect the common-mode frequency of the signal received by the current controlled oscillator of the corresponding DC-DC converter and obtain a balanced PWM signal; and a step-up / step-down charge pump, including, for example, a filtering stage, and configured to receive this balanced PWM signal and generate (according to this balanced PWM signal) a control signal for closing this negative feedback loop by acting on a controlled current generator, which is configured to provide a bias current to this current controlled oscillator of the corresponding DC-DC converter.

[0430] The solution described herein may include an additional low-side current sensor for sensing the current flowing within the coil of the DC-DC converter to facilitate further control and monitoring strategies, such sensing being performed by DC shifting (and amplifying) such current flowing within the coil.

[0431] Thus, the solution described herein facilitates controlling and monitoring the switching activity of a time-based DC-DC converter without affecting the regulation of such a DC-DC converter to improve its performance, for example such control may be provided by aligning and locking the switching activity of such a time-based DC-DC converter to a given reference clock signal, while further control and monitoring may be provided by such a current sensor that is configured to sense positive and negative coil currents and operates independently of the operating conditions of the time-based DC-DC converter, thereby providing a fast transient response.

[0432] Therefore, the solution described in this article can improve the performance and flexibility of time-based DC-DC converters, and in fact, such time-based DC-DC converters can be used in various applications because their switching activities can be controlled and monitored.

[0433] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described purely by way of example, without departing from the scope of the embodiments.

[0434] The claims are an integral part of the technical teaching provided with respect to the embodiments.

[0435] The scope of protection is determined by the appended claims.

Claims

1. A time-based DC-DC converter circuit comprising: a switching circuit controlled by a pulse width modulated switching signal generated in response to the first oscillator signal and the second oscillator signal; a first current controlled oscillator configured to generate the first oscillator signal based on a first control signal; a second current controlled oscillator configured to generate the second oscillator signal based on a second control signal; a controlled current generator configured to generate a controlled current based on a feedback control signal, wherein the first control signal and the second control signal are functions of the controlled current; as well as a negative feedback loop configured to receive the first oscillator signal from the first current controlled oscillator and the second oscillator signal from the second current controlled oscillator, and to generate the feedback control signal based on the first oscillator signal and the second oscillator signal; The negative feedback loop includes: a detector circuit system configured to receive the first oscillator signal, the second oscillator signal, and a reference signal, and generate at least two binary signals, the at least two binary signals comprising: a first binary signal based on a phase difference between the first oscillator signal and the reference signal, and a second binary signal based on a phase difference between the second oscillator signal and the reference signal; and The charge pump circuit system is configured to receive the at least two binary signals and generate the feedback control signal based on the at least two binary signals.

2. The converter circuit according to claim 1, wherein: The first oscillator signal has a first phase; The second oscillator signal has a second phase; and The reference signal has a reference phase; Wherein the detector circuit system comprises: a first phase detector configured to generate the first binary signal according to a difference between the first phase and the reference phase; and a second phase detector configured to generate the second binary signal according to a difference between the second phase and the reference phase; Wherein the charge pump is configured to generate the feedback control signal based on the first binary signal and the second binary signal. 3 . The converter circuit of claim 2 , wherein the reference signal having the reference phase comprises a clock signal. The converter circuit according to claim 2 , wherein the reference phase is selectively variable among a plurality of reference phases. 5 . The converter circuit of claim 1 , wherein the first oscillator signal, the second oscillator signal from the second current controlled oscillator, and the reference signal have the same frequency under steady-state conditions.

6. The converter circuit of claim 1 , wherein the charge pump circuitry comprises: a first charge pump current generator configured to be coupled to ground and to generate a first pump current; a second charge pump current generator configured to be supplied with a power supply voltage and to generate a second pump current; a first switch coupled between a node and the first charge pump current generator to receive the first binary signal from the detector circuitry and to switch between conducting and non-conducting in response to the first binary signal; a second switch coupled between the node and the second charge pump current generator to receive the second binary signal from the detector circuitry and to switch between conducting and non-conducting in response to the second binary signal; as well as A capacitor is configured to be coupled between the node and ground to be charged via the second pump current in response to the second switch being turned on and to be discharged via the first pump current in response to the first switch being turned on, wherein a charged voltage of the capacitor provides the feedback control signal for controlling the controlled current generator. 7 . The converter circuit of claim 6 , wherein the first pump current generated by the first charge pump current generator is equal to the second pump current generated by the second charge pump current generator.

8. The converter circuit of claim 1 , wherein the controlled current generator comprises: a voltage-to-current buffer configured to receive the feedback control signal, apply a gain to the feedback control signal, and drive a transistor using the feedback control signal to which the gain is applied, the transistor being configured to facilitate a flow of a mirror current in the transistor; as well as A current mirror is configured to receive the mirror current in a first mirror branch and generate the controlled current by mirroring the mirror current in at least one second mirror branch.

9. The converter circuit of claim 1 further comprises a low-side switch configured to be coupled between ground and a second node, the second node having a high-side switch and an inductor coupled to the second node; wherein the low-side switch is further configured to be coupled to a current sensor through the second node, the current sensor being configured to sense a coil current flowing in the inductor.

10. The converter circuit of claim 9, wherein the current sensor comprises: a sensor transistor configured to have: a current source terminal coupled to the low-side switch; A control terminal coupled to a sensor negative feedback loop; and a current drain terminal coupled to a first branch of a sensor current mirror; the sensor negative feedback loop configured to supply a control voltage to the control terminal of the sensor transistor; The sensor current mirror is configured to: receive a first sensor current from the current drain terminal of the sensor transistor through the first branch of the sensor current mirror, apply a gain to the first sensor current to obtain a second sensor current, and provide the second sensor current to a load through the second branch of the sensor current mirror.

11. The converter circuit according to claim 10, wherein: The sensor negative feedback loop comprises a high gain negative feedback loop; and The current source terminal of the sensor transistor configured to be coupled to the low-side switch includes a DC-shifted low impedance node.

12. The converter circuit of claim 9, wherein the low-side switch is configured to be coupled to the current sensor via a sensor switch, the sensor switch being configured to implement a protection function, the protection function comprising: turning on the sensor switch in response to the low-side switch turning on, and The sensor switch is rendered non-conductive before the low-side switch is rendered non-conductive.

13. The converter circuit of claim 12 , wherein the load comprises a replica transistor configured to: have a current source terminal coupled to ground; have a current drain terminal coupled to the second branch of the sensor current mirror; and remain turned on in response to the sensor switch being turned on.

14. The converter circuit of claim 12 , wherein the current source terminal of the sensor transistor is further configured to be coupled to a current drain terminal of a bias transistor, wherein the bias transistor is configured to have its current source terminal coupled to ground and to maintain the current source terminal of the sensor transistor biased by remaining conductive in response to the sensor switch being non-conductive.

15. The converter circuit of claim 10, wherein the sensor negative feedback loop is further configured to receive an offset voltage, wherein the control voltage is a function of the received offset voltage.

16. The converter circuit of claim 10 , wherein the second sensor current provided by the second branch of the sensor current mirror across the load is configured to generate a sense voltage indicative of the coil current flowing within the inductor, and Also included is a comparator configured to receive the sense voltage at a first input terminal and a selected voltage threshold at a second input terminal, and to compare the sense voltage with the selected voltage threshold by checking whether the sense voltage reaches the selected voltage threshold.

17. A method comprising: controlling a switching circuit of a time-based DC-DC converter with a pulse width modulated switching signal generated in response to the first oscillator signal and the second oscillator signal; generating, via a first current controlled oscillator, the first oscillator signal based on a first control signal; generating, via a second current controlled oscillator, the second oscillator signal based on a second control signal; generating, via a controlled current generator, a controlled current based on a feedback control signal, wherein the first control signal and the second control signal are functions of the controlled current; as well as receiving the first oscillator signal from the first current controlled oscillator and the second oscillator signal from the second current controlled oscillator via a negative feedback loop, and generating the feedback control signal according to the first oscillator signal and the second oscillator signal; The generating of the feedback control signal comprises: generating at least two binary signals, the at least two binary signals comprising a first binary signal based on a phase difference between the first oscillator signal and the reference signal, and a second binary signal based on a phase difference between the second oscillator signal and the reference signal; as well as The charge pump circuitry is controlled based on the at least two binary signals to output the feedback control signal.

18. The method of claim 17, wherein: The first oscillator signal has a first phase; The second oscillator signal has a second phase; and The reference signal has a reference phase; The generating of at least two binary signals comprises: detecting a difference between the first phase and the reference phase to generate the first binary signal; and detecting a difference between the second phase and the reference phase to generate the second binary signal; Wherein controlling the charge pump circuit system includes controlling based on the first binary signal and the second binary signal. The method of claim 18 , wherein the reference signal having the reference phase comprises a clock signal.

20. The method of claim 18, wherein the reference phase is selectively variable among a plurality of reference phases.

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