CMOS power-on reset signal generation circuit

Abstract

The invention discloses a CMOS power-on reset signal generating circuit, and relates to the technical field of integrated circuits, the CMOS power-on reset signal generating circuit comprises a PM tube, an NM tube, a VCC, a VSS, a PD, a POR and an XPOR, the PM tube comprises a PM0, a PM1, a PM2, a PM3, a PM4, a PM5, a PM6, a PM7, a PM8, a PM9, a PM10, a PM11, a PM12, a PM13 and a PM14, and the NM tube comprises an NM0, an NM1, an NM2, an NM3, an NM4, an NM5, an NM6, an NM7, an NM8, an NM9, an NM10, an NM11 and an NM12; the starting circuit, the biasing circuit, the reset signal shaping circuit and the output circuit are respectively formed by the elements, the CMOS power-on reset signal generating circuit only adopts two types of devices, namely a PMOS (P-channel Metal Oxide Semiconductor) and an NMOS (N-channel Metal Oxide Semiconductor), can be effectively suitable for various CMOS process processing chips, is relatively simple in design, small in area, low in power consumption and suitable for low-power-consumption application scenes, and has a wide application prospect. By accurately controlling the working state of the MOS tube, stable reset signals can be generated under different power-on conditions, and the stability and reliability of the system are improved.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, in particular to a CMOS power-on reset signal generating circuit. Background Art

[0002] In CMOS technology, the power-on reset (POR) signal generation circuit is a key component to ensure that the chip can be initialized to a known state when powered on. Traditional power-on reset circuits usually use RC delay circuits or circuits based on voltage comparators. These circuits generate delays by charging and discharging capacitors when the system is powered on, thereby generating reset signals.

[0003] Circuit structure and principle: 1. RC delay circuit: A low-pass filter is formed by combining resistors and capacitors. When the power supply voltage is applied, the capacitor charges, causing the output voltage to gradually rise. When the output voltage reaches a certain threshold, the reset signal is released. 2. Voltage comparator circuit: Use one or more voltage comparators to monitor the power supply voltage. When the power supply voltage exceeds a preset threshold, the comparator outputs a reset signal.

[0004] The above circuit has the following problems and shortcomings: 1. Capacitors occupy a large area: The capacitors in RC circuits are usually large, which will occupy a large chip area and is not conducive to chip miniaturization; 2. Power consumption problem: In the case of slow power-on, the capacitor charges slowly, causing the reset signal to be released prematurely, which may not ensure stable initialization of the system; 3. Power supply noise sensitivity: Traditional POR circuits may be sensitive to power supply noise, resulting in unstable reset signals; Therefore, in order to solve the above problem, a CMOS power-on reset signal generating circuit is proposed. Summary of the invention

[0005] In view of the deficiencies in the prior art, the present invention provides a CMOS power-on reset signal generating circuit, which solves the problems raised in the above background technology.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solutions: a CMOS power-on reset signal generating circuit, including a PM tube, an NM tube, VCC, VSS, PD, POR and XPOR, the PM tube includes PM0, PM1, PM2, PM3, PM4, PM5, PM6, PM7, PM8, PM9, PM10, PM11, PM12, PM13 and PM14, the NM tube includes NM0, NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, NM9, NM10, NM11, NM12; The above components respectively form a startup circuit, a bias circuit, a reset signal shaping circuit and an output circuit, and the startup circuit, the bias circuit, the reset signal shaping circuit and the output circuit constitute a CMOS power-on reset signal generating circuit; The startup circuit includes PM0, PM1, NM0 and NM1, which work together to generate an initial reset signal when VCC is powered on; The bias circuit: provides a stable bias current to ensure the current demand of the circuit in a working state, the bias circuit includes PM2, PM11, PM3, PM12 and PM13, and PM2, PM11, PM3, PM12 and PM13 constitute a current mirror for copying and distributing the bias current; The reset signal shaping circuit: includes PM4, PM14, PM5, PM6, PM7, NM3, NM4, NM5, NM6, NM7, NM8, NM9, to ensure the accuracy and stability of the signal; The output circuit includes PM8, PM9, NM10 and NM11, and PM8, PM9, NM10 and NM11 constitute an output stage, and output the shaped reset signal to the POR and XPOR ports.

[0007] Optionally, the functions of the VCC and VSS are to provide the power supply voltage and ground reference of the circuit, and the PD, as an input of an external or internal signal, can be used to trigger a reset process or provide control of a reset signal.

[0008] Optionally, the functions of the POR and XPOR are: outputting a reset signal for resetting the system state when the system is powered on or when needed, the POR represents a master reset signal output; the XPOR represents a reverse reset signal output.

[0009] Optionally, the working process of the CMOS power-on reset signal generating circuit comprises the following steps: S1: When PD is at a low level, pdi controls PM3 to turn on, NM8 to turn off, and xpdi controls PM8 to turn off, providing the necessary current and voltage conditions for the subsequent formation of a reset signal; S2: When PD is at a high level, pdi controls PM3 to turn off, NM8 to turn on, xpdi controls PM8 to turn on, the reset function is turned off, and the circuit generates a signal that follows the power supply voltage; S3: When dpi is low and VCC starts to rise, current mirrors PM3 and NM3 start to work, copying and distributing bias current to ensure the stability of current at key nodes in the circuit; S4: As the power supply voltage rises, PM4, PM5, PM6, NM4, NM5, NM6, NM7, NM9, NM10 and other tubes in the shaping circuit start to work, shaping the reset signal to ensure the stability and accuracy of the signal.

[0010] Optionally, the size of PM6 can be adjusted, thereby trimming the pulse width of the output reset signal.

[0011] Optionally, when the VCC reaches a stable state, the XPOR and POR ports in the output circuit output reset signals to put the system into a reset state.

[0012] The present invention provides a CMOS power-on reset signal generating circuit, which has the following beneficial effects: The CMOS power-on reset signal generating circuit uses only two types of devices, PMOS and NMOS, and can be effectively applied to various CMOS process chips. The design of the circuit is relatively simple, with a small area and low power consumption, and is suitable for low-power application scenarios. By accurately controlling the working state of the MOS tube, a stable reset signal can be generated under different power-on conditions, thereby improving the stability and reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0014] Figure 1 It is the circuit principle diagram of the present invention; Figure 2 It is a schematic diagram of the working process of the circuit of the present invention; Figure 3 This is a diagram of the simulation results of VCC power-on and reset pulses of the present invention; Figure 4 This is a simulation result diagram of the reset pulse width after reducing the W / L of the PM6 control tube in the present invention; Figure 5 This is a simulation result diagram of the reset pulse width after increasing the W / L of the PM6 control tube in the present invention; Figure 6 This is a diagram of simulation results of the arrangement and combination of -40°C, 27°C, 85°C, 2.5V, 2.8V, and 3.3V under the ff corner of the present invention; Figure 7 This is a diagram of simulation results of the arrangement and combination of -40°C, 27°C, 85°C, 2.5V, 2.8V, and 3.3V under tt corner of the present invention; Figure 8 This is a diagram of simulation results of the corner arrangement and combination of -40°C, 27°C, 85°C, 2.5V, 2.8V, and 3.3V of the present invention. DETAILED DESCRIPTION

[0015] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0016] See also Figures 1 to 5 The present invention provides a technical solution: a CMOS power-on reset signal generating circuit, comprising a PM tube, an NM tube, VCC, VSS, PD, POR and XPOR, the PM tube comprises PM0, PM1, PM2, PM3, PM4, PM5, PM6, PM7, PM8, PM9, PM10, PM11, PM12, PM13 and PM14, the NM tube comprises NM0, NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, NM9, NM10, NM11 and NM12; The above components respectively form a startup circuit, a bias circuit, a reset signal shaping circuit and an output circuit, and the startup circuit, the bias circuit, the reset signal shaping circuit and the output circuit form a CMOS power-on reset signal generating circuit; The startup circuit includes components for detecting the power supply voltage and triggering the reset process, PM0, PM1, NM0 and NM1, which work together to generate an initial reset signal when VCC is powered on; Bias circuit: provides a stable bias current to ensure the current demand of the circuit in the working state. The bias circuit includes PM2, PM11, PM3, PM12 and PM13. PM2, PM11, PM3, PM12 and PM13 form a current mirror for copying and distributing the bias current. Reset signal shaping circuit: including components for adjusting and stabilizing the reset signal to ensure the accuracy and stability of the signal, PM4, PM14, PM5, PM6, PM7, NM3, NM4, NM5, NM6, NM7, NM8, NM9, to ensure the accuracy and stability of the signal, PM4, PM14, PM5, PM6, PM7, NM3, NM4, NM5, NM6, NM7, NM8, NM9 participate in signal shaping, and adjust the pulse width and stability of the reset signal through their switching states; The output circuit includes components that output the reset signal to other parts of the system, PM8, PM9, NM10 and NM11. PM8, PM9, NM10 and NM11 constitute the output stage, and output the shaped reset signal to the POR and XPOR ports.

[0017] Table 1: CMOS tube parameters name W / L finger m Device Name PM0、PM1 7u / 0.35u 1 1 pch2p8 NM0, NM1 4u / 0.35u 1 1 nch2p8 PM2、PM11 0.5u / 20u 1 1 pch2p8 PM3、PM12 10u / 20u 1 1 pch2p8 PM13 10u / 10u 1 1 pch2p8 PM4, PM14 0.75u / 20u 1 1 pch2p8 PM5 7u / 0.65u 1 1 pch2p8 PM6 11u / 20u 1 1 pch2p8 PM7 1.2u / 0.35u 1 1 pch2p8 PM8 7u / 0.65u 1 1 pch2p8 PM9 4u / 0.65u 1 1 pch2p8 NM2, NM12 0.5u / 17u 1 1 nch2p8 NM3 6u / 0.65u 1 1 nch2p8 NM4 2.5u / 15u 1 1 nch2p8 NM5 5u / 15u 1 1 nch2p8 NM6 20u / 15u 4 1 nch2p8 NM7 1.2u / 0.35u 1 1 nch2p8 NM8 5u / 15u 1 1 nch2p8 NM9 4u / 0.65u 1 1 nch2p8 NM10 4u / 0.65u 1 1 nch2p8 NM11 8u / 0.65u 1 1 nch2p8 Furthermore, those skilled in the art will appreciate that the functions of VCC and VSS are to provide the power supply voltage and ground reference for the circuit, and PD, as an input of an external or internal signal, can be used to trigger a reset process or provide control of a reset signal.

[0018] Furthermore, those skilled in the art will appreciate that the functions of POR and XPOR are: outputting a reset signal for resetting the system state when the system is powered on or when needed, POR, indicating a master reset signal output; XPOR, indicating a reverse reset signal output.

[0019] Further, those skilled in the art will know that the working process of the CMOS power-on reset signal generating circuit includes the following steps: S1: When PD is at a low level, pdi controls PM3 to turn on, NM8 to turn off, and xpdi controls PM8 to turn off, providing the necessary current and voltage conditions for the subsequent formation of a reset signal; S2: When PD is at a high level, pdi controls PM3 to turn off, NM8 to turn on, xpdi controls PM8 to turn on, the reset function is turned off, and the circuit generates a signal that follows the power supply voltage; S3: When dpi is low and VCC starts to rise, current mirrors PM3 and NM3 start to work, copying and distributing bias current to ensure the stability of current at key nodes in the circuit; S4: As the power supply voltage rises, PM4, PM5, PM6, NM4, NM5, NM6, NM7, NM9, NM10 and other tubes in the shaping circuit start to work, shaping the reset signal to ensure the stability and accuracy of the signal.

[0020] Furthermore, those skilled in the art will appreciate that the size of PM6 can be adjusted, thereby trimming the pulse width of the output reset signal.

[0021] Furthermore, those skilled in the art will appreciate that when VCC reaches a stable state, the XPOR and POR ports in the output circuit output reset signals to put the system into a reset state.

[0022] Perform ADE simulation, tt corner VCC=2.8V 27℃ reset pulse generation result: POR pulse width = 5us, POR pulse width control tube: PM6 W / L = 11u / 20u; POR pulse width = 4us, POR pulse width control tube: PM6 W / L = 8u / 20u; POR pulse width = 6.662us, POR pulse width control tube: PM6 W / L = 16u / 20u.

[0023] Example Perform PVT combination simulation according to different corners, voltages, and temperatures; This simulation is tt corner ff corner ss corner 2.5V 2.8V 3.3V -40℃ 27℃ 85℃; Figure 6 , Figure 7 , Figure 8 These are the simulation results of the permutations and combinations of temperature and voltage under different corners; Figure 6 Display the simulation results of the ff corner at -40℃, 27℃, 85℃, 2.5V, 2.8V, and 3.3V permutations and combinations; Figure 7 Display the simulation results of tt corner at -40℃, 27℃, 85℃, 2.5V, 2.8V, 3.3V permutations and combinations; Figure 8 Displays the simulation results of corners at -40℃, 27℃, 85℃, 2.5V, 2.8V, and 3.3V.

[0024] In the description of the present invention, it is necessary to understand that the terms "coaxial", "bottom", "one end", "top", "middle", "the other end", "upper", "one side", "top", "inside", "front", "center", "both ends" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0025] In addition, the terms "first", "second", "third" and "fourth" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first", "second", "third" and "fourth" may explicitly or implicitly include at least one of such features.

[0026] In the present invention, unless otherwise clearly stipulated and limited, the terms such as "installation", "setting", "connection", "fixation" and "screw-on" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal connection of two elements or the interaction relationship between two elements. Unless otherwise clearly defined, ordinary technicians in this field can understand the specific meanings of the above terms in the present invention according to the specific circumstances.

[0027] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A CMOS power-on reset signal generating circuit, characterized in that: Including PM tube, NM tube, VCC, VSS, PD, POR and XPOR, the PM tube includes PM0, PM1, PM2, PM3, PM4, PM5, PM6, PM7, PM8, PM9, PM10, PM11, PM12, PM13 and PM14, the NM tube includes NM0, NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, NM9, NM10, NM11, NM12; The above components respectively form a startup circuit, a bias circuit, a reset signal shaping circuit and an output circuit, and the startup circuit, the bias circuit, the reset signal shaping circuit and the output circuit constitute a CMOS power-on reset signal generating circuit; The startup circuit includes PM0, PM1, NM0 and NM1, which work together to generate an initial reset signal when VCC is powered on; The bias circuit: provides a stable bias current to ensure the current demand of the circuit in a working state, the bias circuit includes PM2, PM11, PM3, PM12 and PM13, and PM2, PM11, PM3, PM12 and PM13 constitute a current mirror for copying and distributing the bias current; The reset signal shaping circuit: includes PM4, PM14, PM5, PM6, PM7, NM3, NM4, NM5, NM6, NM7, NM8, NM9, to ensure the accuracy and stability of the signal; The output circuit includes PM8, PM9, NM10 and NM11, and PM8, PM9, NM10 and NM11 constitute an output stage, and output the shaped reset signal to the POR and XPOR ports.

2. A CMOS power-on reset signal generating circuit according to claim 1, characterized in that: The functions of the VCC and VSS are to provide the power supply voltage and ground reference of the circuit. The PD, as an input of an external or internal signal, can be used to trigger a reset process or provide control of a reset signal.

3. A CMOS power-on reset signal generating circuit according to claim 1, characterized in that: The functions of the POR and XPOR are: outputting a reset signal for resetting the system state when the system is powered on or when needed, the POR represents the main reset signal output; the XPOR represents the reverse reset signal output.

4. A CMOS power-on reset signal generating circuit according to claim 1, characterized in that: The working process of the CMOS power-on reset signal generating circuit is as follows: The following steps are involved: S1: When PD is at a low level, pdi controls PM3 to turn on, NM8 to turn off, and xpdi controls PM8 to turn off, providing the necessary current and voltage conditions for the subsequent formation of a reset signal; S2: When PD is at a high level, pdi controls PM3 to turn off, NM8 to turn on, xpdi controls PM8 to turn on, the reset function is turned off, and the circuit generates a signal that follows the power supply voltage; S3: When dpi is low and VCC starts to rise, current mirrors PM3 and NM3 start to work, copying and distributing bias current to ensure the stability of current at key nodes in the circuit; S4: As the power supply voltage rises, PM4, PM5, PM6, NM4, NM5, NM6, NM7, NM9, NM10 and other tubes in the shaping circuit start to work, shaping the reset signal to ensure the stability and accuracy of the signal.

5. The CMOS power-on reset signal generating circuit according to claim 1, characterized in that: The size of PM6 can be adjusted, thereby trimming the pulse width of the output reset signal.

6. A CMOS power-on reset signal generating circuit according to claim 1, characterized in that: When the VCC reaches a stable state, the XPOR and POR ports in the output circuit output reset signals to put the system into a reset state.

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