Offset self-calibration circuit for dynamic comparator

Abstract

The invention provides an imbalance self-calibration circuit for a dynamic comparator. The imbalance self-calibration circuit can be applied to the technical field of analog integrated circuit design. The circuit comprises a first transistor array which comprises a first weight transistor group and a first default transistor, and the first weight transistor group comprises a plurality of first weight transistors of which the grid widths are gradually increased according to a preset rule; the second transistor array comprises a second weight transistor group and a second default transistor, and the second weight transistor group comprises a plurality of second weight transistors of which the grid widths are gradually increased according to a preset rule; the first calibration logic module is connected with the first transistor array and is used for providing a first control signal for the first transistor array under the condition that the offset polarity of the dynamic comparator is positive so as to control the first effective transconductance; and the second calibration logic module is connected with the second transistor array and is used for providing a second control signal for the second transistor array under the condition that the offset polarity of the dynamic comparator is negative.

Description

Technical Field

[0001] The present disclosure relates to the technical field of analog integrated circuit design, and more particularly to an offset self-calibration circuit for a dynamic comparator. Background Art

[0002] Dynamic comparators are widely used in analog to digital converters (ADCs) due to their low power consumption due to their dynamic working characteristics. The performance of dynamic comparators, such as speed, noise, and offset, affects the performance of the entire ADC.

[0003] Offset is the main non-ideal characteristic of the dynamic comparator, which is equivalent to the presence of offset voltage at the input end, which will cause the ADC characteristic curve to shift. At the same time, offset will also reduce the dynamic range of the input signal. For multi-channel ADC or time-interleaved ADC, comparator offset is also one of the main reasons for mismatch between channels. Based on this, it is of great significance to optimize the dynamic comparator.

[0004] In the process of realizing the concept of the present disclosure, the inventors found that there are at least technical problems in the related art that the calibration of the dynamic comparator offset will reduce the operating speed and stability of the circuit, introduce a larger circuit area to increase power consumption and affect the ADC conversion accuracy. Summary of the invention

[0005] In view of this, the present disclosure provides an offset self-calibration circuit for a dynamic comparator.

[0006] One aspect of the present disclosure provides an offset self-calibration circuit for a dynamic comparator, comprising:

[0007] A first transistor array includes a first weight transistor group and a first default transistor, the first weight transistor group includes a first weight transistor whose multi-bit gate width increases according to a predetermined rule, and the first transistor array is used to perform offset calibration on the dynamic comparator according to a first effective transconductance corresponding to the first weight transistor, wherein the first default transistor is connected to the first input transistor of the dynamic comparator; a second transistor array includes a second weight transistor group and a second default transistor, the second weight transistor group includes a second weight transistor whose multi-bit gate width increases according to a predetermined rule, and the second transistor array is used to perform offset calibration on the dynamic comparator according to a second effective transconductance corresponding to the second weight transistor , wherein the second default transistor is connected to the second input transistor of the dynamic comparator; a first calibration logic module is connected to the first transistor array, and is used to provide a first control signal to the first transistor array when the offset polarity of the dynamic comparator is positive, so as to control the first effective transconductance; a second calibration logic module is connected to the second transistor array, and is used to provide a second control signal to the second transistor array when the offset polarity of the dynamic comparator is negative, so as to control the second effective transconductance; a delay chain module includes a plurality of inverters, and the delay chain module is used to provide a clearing time to the first calibration logic module and the second calibration logic module before the input level of the dynamic comparator is stabilized.

[0008] According to an embodiment of the present disclosure, the first transistor array also includes a first switching transistor connected to each first weight transistor, and the dynamic comparator is offset calibrated according to the first effective transconductance corresponding to the first weight transistor, including: the multiple first switching transistors control the access of the multiple first weight transistors according to the first control signal, and determine the first target weight transistor from the first weight transistor group; according to the number of the first target weight transistors, determine the first effective transconductance to perform offset calibration on the dynamic comparator.

[0009] According to an embodiment of the present disclosure, the first calibration logic circuit includes a first counter, the first counter includes a first counting output terminal having the same number as the first switching transistors, and provides a first control signal to the first transistor array when the offset polarity of the dynamic comparator is positive to control the first effective transconductance, including: when the offset polarity of the dynamic comparator is positive, the first calibration logic circuit is enabled, and a first control signal corresponding to the first counter is generated according to the clock signal of the dynamic comparator; and multiple first counting output terminals transmit the first control signal to multiple first switching transistors to control the first effective transconductance.

[0010] According to an embodiment of the present disclosure, when the offset polarity of the dynamic comparator is positive, the first calibration logic circuit is enabled, and a first control signal corresponding to the first counter is generated according to the clock signal of the dynamic comparator, including: when the offset polarity of the dynamic comparator is positive, the first calibration logic circuit is enabled; the first counter counts upward according to the period corresponding to the clock signal, and accumulates to obtain a first counting control word; and according to the first counting control word, a first control signal corresponding to the first counter is generated.

[0011] According to an embodiment of the present disclosure, the second transistor array also includes a second switching transistor connected to each second weight transistor, and the dynamic comparator is offset calibrated according to the second effective transconductance corresponding to the second weight transistor, including: the multiple second switching transistors control the opening and closing of the multiple second weight transistors according to the second control signal, and determine the second target weight transistor from the second weight transistor group; according to the second target weight transistor, determine the second effective transconductance to perform offset calibration on the dynamic comparator.

[0012] According to an embodiment of the present disclosure, the second calibration logic circuit includes a second counter, the second counter includes second counting output terminals having the same number as the second switching transistors, and when the offset polarity of the dynamic comparator is positive, a second control signal is provided to the second transistor array to control the second effective transconductance, including: when the offset polarity of the dynamic comparator is negative, the second calibration logic circuit is enabled, and a second control signal corresponding to the second counter is determined according to the clock signal of the dynamic comparator; and multiple second counting output terminals transmit the second control signal to multiple second switching transistors to control the second effective transconductance.

[0013] According to an embodiment of the present disclosure, when the offset polarity of the dynamic comparator is negative, the second calibration logic circuit is enabled, and a second control signal corresponding to the second counter is generated according to the clock signal of the dynamic comparator, including: when the offset polarity of the dynamic comparator is positive, the second calibration logic circuit is enabled; the second counter counts upward according to the period corresponding to the clock signal, and accumulates to obtain a second counting control word; and according to the second counting control word, a second control signal corresponding to the second counter is generated.

[0014] According to an embodiment of the present disclosure, the predetermined rule includes: 2 to the power of n, 0≤n.

[0015] According to an embodiment of the present disclosure, the first weight transistor includes multiple first weight sub-transistors, and the second weight transistor includes multiple second weight sub-transistors; the gate length of each first weight sub-transistor in each first weight transistor is equal to the gate length of the first default transistor, and the gate length of each second weight sub-transistor in each second weight transistor is equal to the gate length of the second default transistor; the number of first weight sub-transistors increases sequentially by 2 to the mth power, and the number of second weight sub-transistors increases sequentially by 2 to the mth power, 0≤m.

[0016] According to an embodiment of the present disclosure, the first counting output terminal and the second counting output terminal are provided with latches.

[0017] According to an embodiment of the present disclosure, by splitting the tail pipe in the traditional dynamic comparator into a first default transistor and a second default transistor, and connecting them to the first transistor array and the second transistor array respectively, the first calibration logic module is used to provide a first control signal to the first transistor array when the offset polarity of the dynamic comparator is positive, so as to control the first effective transconductance corresponding to the first weight transistor, and accordingly, the second calibration logic module is used to provide a second control signal to the first transistor array when the offset polarity of the dynamic comparator is negative, so as to control the second effective transconductance corresponding to the second weight transistor, thereby realizing the calibration of the offset of the dynamic comparator according to the effective transconductance corresponding to the two input transistors in a high-speed scenario, and the gate width of the weight transistor increases according to a predetermined rule, so that the calibration range of the offset is kept linearly increasing. At the same time, the delay chain module provides a clearing time for the two calibration logic modules, further improving the circuit stability and calibration accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0019] Figure 1 The circuit diagram of a conventional two-stage dynamic comparator provided according to an embodiment of the present disclosure is schematically shown.

[0020] Figure 2 The diagram schematically shows a schematic diagram of an offset self-calibration circuit for a dynamic comparator according to an embodiment of the present disclosure.

[0021] Figure 3 A circuit diagram of an offset self-calibration circuit for a dynamic comparator according to an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0023] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0024] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0025] When using expressions such as "at least one of A, B, and C, etc.", they should generally be interpreted according to the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0026] In the embodiments of the present disclosure, the collection, updating, analysis, processing, use, transmission, provision, disclosure, storage, etc. of the data involved (for example, including but not limited to user personal information) are in compliance with the provisions of relevant laws and regulations, are used for legitimate purposes, and do not violate public order and good morals. In particular, necessary measures are taken for user personal information to prevent illegal access to user personal information data and maintain the security of user personal information, network security, and national security.

[0027] In the embodiments of the present disclosure, the user's authorization or consent is obtained before obtaining or collecting the user's personal information.

[0028] In order to reduce the offset of the dynamic comparator, related technologies often use self-zeroing technology or chopping technology. However, although the circuits of these two offset technologies have simple structures, they are not suitable for high-frequency applications.

[0029] In addition, there are some methods that directly calibrate the dynamic comparator itself. The basic idea is to offset the offset by introducing a controllable imbalance on both sides of the dynamic comparator. For example: by adjusting the differential load capacitance of the pre-amplifier stage, but this method will increase power consumption and reduce the comparison speed; for example: using the bias effect, by adjusting the input to the substrate bias of the transistor to change its threshold to offset the offset, but it is necessary to add a special digital-to-analog converter to generate the corresponding bias voltage; for example: by adding additional current paths at the two output ends of the pre-amplifier stage, but this also requires additional digital-to-analog converters to generate the analog quantity that introduces the imbalance, and the introduced parasitics will also reduce the comparison speed.

[0030] In order to solve the technical problems existing in the prior art for dynamic comparator calibration, the offset calibration can be completed by changing the imbalance caused by the effective transconductance of the transistor pairs on both sides of the comparator, such as adjusting the effective transconductance of the first-stage or second-stage input pair transistors, so as to achieve better calibration performance. For the comparator, the mismatch of the first-stage input pair tube is usually the biggest source of comparator offset, and the offset of the second stage will be divided by the first-stage gain when it is equivalent to the input end. Therefore, controlling and adjusting the first-stage effective transconductance can usually obtain a larger calibration range. However, more factors need to be considered when designing a comparator applied to an analog-to-digital converter. If the total size of the transistor group of the input pair is too large, it will lead to an increase in the parasitic capacitance of the input pair and an increase in the kickback noise, which will affect the accuracy of the analog-to-digital converter. For the commonly used transconductance control transistor group using binary weights, when the total size is limited to avoid affecting the accuracy of the analog-to-digital converter, its calibration range and accuracy will depend on and be limited by the minimum gate length supported by the process. Therefore, the calibration performance of the method of adjusting the effective transconductance of the first-stage or second-stage input pair also has certain limitations.

[0031] Figure 1 The circuit diagram of a conventional two-stage dynamic comparator provided according to an embodiment of the present disclosure is schematically shown.

[0032] like Figure 1 As shown, the circuit 100 includes a two-level latch 110, a load transistor 120, a first input transistor 130, a second input transistor 140, and a tail transistor 150. In the prior art, the effective transconductance of the first input transistor 130 and the second input transistor 140 is usually adjusted.

[0033] In view of this, an embodiment of the present disclosure provides an offset self-calibration circuit for a dynamic comparator, comprising: a first transistor array, comprising a first weight transistor group and a first default transistor, the first weight transistor group comprising a first weight transistor whose multi-bit gate width increases according to a predetermined rule, the first transistor array being used to perform offset calibration on the dynamic comparator according to a first effective transconductance corresponding to the first weight transistor, wherein the first default transistor is connected to a first input transistor of the dynamic comparator; a second transistor array, comprising a second weight transistor group and a second default transistor, the second weight transistor group comprising a second weight transistor whose multi-bit gate width increases according to a predetermined rule, the second transistor array being used to perform offset calibration on the dynamic comparator according to a first effective transconductance corresponding to the first weight transistor two effective transconductances, for offset calibration of the dynamic comparator, wherein the second default transistor is connected to the second input transistor of the dynamic comparator; a first calibration logic module, connected to the first transistor array, for providing a first control signal to the first transistor array to control the first effective transconductance when the offset polarity of the dynamic comparator is positive; a second calibration logic module, connected to the second transistor array, for providing a second control signal to the second transistor array to control the second effective transconductance when the offset polarity of the dynamic comparator is negative; a delay chain module, including a plurality of inverters, the delay chain module is used to provide a clearing time to the first calibration logic module and the second calibration logic module before the input level of the dynamic comparator is stabilized.

[0034] To better understand the offset self-calibration circuit for a dynamic comparator according to the embodiment of the present disclosure, a 5-bit weight transistor is used as an example. Figure 2 The self-calibration circuit is described in detail.

[0035] Figure 2 The diagram schematically shows a schematic diagram of an offset self-calibration circuit for a dynamic comparator according to an embodiment of the present disclosure.

[0036] like Figure 2 As shown, the embodiment 200 includes a secondary latch 110, a load tube 120, a first input transistor 130, a second input transistor 140, a first transistor array 210, a second transistor array 220, a first calibration logic module 230, a second calibration logic module 240, a delay chain module 250 and an output NAND gate 260.

[0037] According to an embodiment of the present disclosure, the first transistor array 210 includes a first weight transistor group 211 and a first default transistor 151, the first weight transistor group 211 includes a first weight transistor 211_1 whose multi-bit gate width increases according to a predetermined rule, and the first transistor array 210 is used to perform offset calibration on the dynamic comparator according to the first effective transconductance corresponding to the first weight transistor, wherein the first default transistor 141 is connected to the first input transistor 130 of the dynamic comparator.

[0038] According to an embodiment of the present disclosure, the second transistor array 220 includes a second weight transistor group 221 and a second default transistor 152, the second weight transistor group 221 includes a second weight transistor 221_1 whose multi-bit gate width increases according to a predetermined rule, and the second transistor array 220 is used to perform offset calibration on the dynamic comparator according to the second effective transconductance corresponding to the second weight transistor, wherein the second default transistor 142 is connected to the second input transistor 140 of the dynamic comparator.

[0039] According to an embodiment of the present disclosure, the first calibration logic module 230 includes a pin CLD and a pin CAL, which are connected to the first transistor array, and is used to provide a first control signal to the first transistor array when the offset polarity of the dynamic comparator is positive, so as to control the first effective transconductance. The second calibration logic module 240 includes a pin CLD and a pin CAL, which are connected to the second transistor array, and is used to provide a second control signal to the second transistor array when the offset polarity of the dynamic comparator is negative, so as to control the second effective transconductance.

[0040] According to an embodiment of the present disclosure, the first default transistor and the second default transistor are always connected to the circuit, and the first weight transistor and the second weight transistor adjust the number of connections according to the first control signal and the second control signal, respectively, to change the first effective transconductance and the second effective transconductance, thereby calibrating the offset of the dynamic comparator.

[0041] According to an embodiment of the present disclosure, the delay chain module 250 includes a plurality of inverters 251 . To reduce the circuit area, the delay chain module 250 is simultaneously connected to the pins CLD and CAL of the first calibration logic module and the second calibration logic module.

[0042] According to an embodiment of the present disclosure, all transistors in the first transistor array and the second transistor array are NMOS (N-Metal-Oxide-Semiconductor) transistors.

[0043] According to the embodiments of the present disclosure, compared with the above Figure 1In a conventional two-stage dynamic comparator, the embodiment 200 splits the tail pipe 150 into a first default transistor and a second default transistor.

[0044] According to an embodiment of the present disclosure, in order to reduce the power consumption of the circuit, the first-stage pre-amplifier of the dynamic comparator adopts dynamic amplification, that is, it only works at the moment of clock jump of the dynamic comparator, so there is almost no static power consumption at other times, so it is suitable for application in low-power digital / analog converters such as successive approximation analog-to-digital converters.

[0045] According to the embodiments of the present disclosure, the first default transistor and the second default transistor have the characteristic of working across regions when performing pre-amplification, and the working region in which they are located will also be affected by the gate voltage of the first input transistor and the second input transistor, that is, the input voltage of the dynamic comparator. In order to make the calibration range of the offset cover the distribution of the larger offset of the dynamic comparator as much as possible, it is necessary to regulate the standard deviation of the offset distribution of the dynamic comparator itself, that is, to select the first input transistor and the second input transistor of a relatively moderate size, so that the length and width of the gate can be increased in the same proportion while keeping the width-to-length ratio of the transistor unchanged.

[0046] According to an embodiment of the present disclosure, the calibration range of the offset depends on the maximum change in the effective transconductance of the first transistor array and the second transistor array. Therefore, the minimum calibration step depends on the gate width of the first weight transistor. In order to obtain higher calibration accuracy, the gate width of the first weight transistor can be set to the minimum gate width supported by the process.

[0047] According to an embodiment of the present disclosure, by splitting the tail pipe in the traditional dynamic comparator into a first default transistor and a second default transistor, and connecting them to the first transistor array and the second transistor array respectively, the first calibration logic module is used to provide a first control signal to the first transistor array when the offset polarity of the dynamic comparator is positive, so as to control the first effective transconductance corresponding to the first weight transistor, and accordingly, the second calibration logic module is used to provide a second control signal to the first transistor array when the offset polarity of the dynamic comparator is negative, so as to control the second effective transconductance corresponding to the second weight transistor, thereby realizing the calibration of the offset of the dynamic comparator according to the effective transconductance corresponding to the two input transistors in a high-speed scenario, and the gate width of the weight transistor increases according to a predetermined rule, so that the calibration range of the offset is kept linearly increasing. At the same time, the delay chain module provides a clearing time for the two calibration logic modules, further improving the circuit stability and calibration accuracy.

[0048] According to an embodiment of the present disclosure, the predetermined rule includes: 2 to the power of n, 0≤n.

[0049] For example, taking five-bit weight transistors as an example, the gate width of the first-weighted transistor is W, the gate width of the second-weighted transistor is 2W, the gate width of the third-weighted transistor is 4W, the gate width of the fourth-weighted transistor is 8W, and the gate width of the fifth-weighted transistor is 16W; the gate width of the first-weighted transistor is W, the gate width of the second-weighted transistor is 2W, the gate width of the third-weighted transistor is 4W, the gate width of the fourth-weighted transistor is 8W, and the gate width of the fifth-weighted transistor is 16W.

[0050] According to an embodiment of the present disclosure, the gate lengths of all first weight transistors are equal to the gate length of the first default transistor, and the gate lengths of all second weight transistors are equal to the gate length of the second default transistor.

[0051] According to an embodiment of the present disclosure, the first weight transistor includes multiple first weight sub-transistors, and the second weight transistor includes multiple second weight sub-transistors; the gate length of each first weight sub-transistor in each first weight transistor is equal to the gate length of the first default transistor, and the gate length of each second weight sub-transistor in each second weight transistor is equal to the gate length of the second default transistor; the number of first weight sub-transistors increases sequentially by 2 to the mth power, and the number of second weight sub-transistors increases sequentially by 2 to the mth power, 0≤m.

[0052] According to an embodiment of the present disclosure, each first weight sub-transistor has the same size, and each first weight sub-transistor can be formed by connecting multiple first weight sub-transistors in parallel. By increasing the number of first weight sub-transistors connected in parallel in sequence according to the power of 2 to the mth power, each first weight transistor that increases according to a predetermined rule can be obtained.

[0053] According to an embodiment of the present disclosure, each second weight sub-transistor has the same size, and each second weight sub-transistor can be formed by connecting multiple second weight sub-transistors in parallel. By increasing the number of first weight sub-transistors connected in parallel in sequence according to the power of 2 to the mth power, each first weight transistor that increases according to a predetermined rule can be obtained.

[0054] According to the embodiments of the present disclosure, by increasing the gate width of the first / second weight transistors in equal proportion, the corresponding first / second effective transconductance linearity changes, thereby effectively controlling the offset calibration range and improving the offset calibration accuracy of the dynamic comparator.

[0055] According to an embodiment of the present disclosure, the first transistor array also includes a first switching transistor connected to each first weight transistor, and the dynamic comparator is offset calibrated according to the first effective transconductance corresponding to the first weight transistor, including: the multiple first switching transistors control the access of the multiple first weight transistors according to the first control signal, and determine the first target weight transistor from the first weight transistor group; according to the number of the first target weight transistors, determine the first effective transconductance to perform offset calibration on the dynamic comparator.

[0056] According to an embodiment of the present disclosure, a plurality of first switch transistors are turned on according to a first control signal, and a first weight transistor corresponding to the turned-on first switch transistor is connected to the circuit and determined as a first target weight transistor. The first effective transconductance is adjusted according to the number of first target weight transistors connected to the circuit to perform a positive offset calibration on the dynamic comparator.

[0057] According to an embodiment of the present disclosure, the second transistor array also includes a second switching transistor connected to each second weight transistor, and the dynamic comparator is offset calibrated according to the second effective transconductance corresponding to the second weight transistor, including: the multiple second switching transistors control the opening and closing of the multiple second weight transistors according to the second control signal, and determine the second target weight transistor from the second weight transistor group; according to the second target weight transistor, determine the second effective transconductance to perform offset calibration on the dynamic comparator.

[0058] According to an embodiment of the present disclosure, a plurality of second switch transistors are turned on according to a second control signal, and a second weight transistor corresponding to the turned-on second switch transistor is connected to the circuit and determined as a second target weight transistor. The second effective transconductance is adjusted according to the number of the second target weight transistors connected to the circuit to perform negative offset calibration on the dynamic comparator.

[0059] According to the embodiments of the present disclosure, by controlling the number of weight transistors connected by the first / second switching transistors, the first / second effective transconductance can be accurately adjusted, thereby achieving offset calibration of the dynamic comparator. In high-speed ADC application scenarios, the performance of the comparator can be improved while maintaining low power consumption.

[0060] According to an embodiment of the present disclosure, the first calibration logic circuit includes a first counter, the first counter includes a first counting output terminal having the same number as the first switching transistors, and provides a first control signal to the first transistor array when the offset polarity of the dynamic comparator is positive to control the first effective transconductance, including: when the offset polarity of the dynamic comparator is positive, the first calibration logic circuit is enabled, and a first control signal corresponding to the first counter is generated according to the clock signal of the dynamic comparator; and multiple first counting output terminals transmit the first control signal to multiple first switching transistors to control the first effective transconductance.

[0061] According to an embodiment of the present disclosure, the delay chain module is used to provide a reset time length to the first counter in the first calibration logic module, so that calibration is performed after the levels of the two input terminals of the dynamic comparator become stable.

[0062] According to an embodiment of the present disclosure, when the offset polarity of the dynamic comparator is positive, the first calibration logic circuit is enabled and the second calibration logic circuit cannot be enabled. The first counter generates a first control signal to control the switching state of the first switch tube, thereby controlling the number of bits of the connected first weight transistor. The first transistor array forms source feedback for the first input transistor and the second input transistor. As the first equivalent transconductance increases and the on-resistance decreases, the instantaneous discharge current of the parasitic capacitance of the first-stage output node Vop of the dynamic comparator increases, and the Vop discharge speed gradually catches up with the Von discharge speed, thereby completing the offset calibration of the dynamic comparator.

[0063] According to an embodiment of the present disclosure, when the offset polarity of the dynamic comparator is positive, the first calibration logic circuit is enabled, and a first control signal corresponding to the first counter is generated according to the clock signal of the dynamic comparator, including: when the offset polarity of the dynamic comparator is positive, the first calibration logic circuit is enabled; the first counter counts upward according to the period corresponding to the clock signal, and accumulates to obtain a first counting control word; and according to the first counting control word, a first control signal corresponding to the first counter is generated.

[0064] According to an embodiment of the present disclosure, the trigger in the first counter can be designed as a falling edge trigger mode. When the calibration is completed, the first counter stops counting upwards.

[0065] According to an embodiment of the present disclosure, when the offset polarity of the dynamic comparator is positive, the output signal Von=0 and Vop=1, and the comparison result RDY is a high level.

[0066] According to an embodiment of the present disclosure, the second calibration logic circuit includes a second counter, the second counter includes second counting output terminals having the same number as the second switching transistors, and when the offset polarity of the dynamic comparator is positive, a second control signal is provided to the second transistor array to control the second effective transconductance, including: when the offset polarity of the dynamic comparator is negative, the second calibration logic circuit is enabled, and a second control signal corresponding to the second counter is determined according to the clock signal of the dynamic comparator; and multiple second counting output terminals transmit the second control signal to multiple second switching transistors to control the second effective transconductance.

[0067] According to an embodiment of the present disclosure, the delay chain module is used to provide a reset time length to the second counter in the second calibration logic module, so that calibration is performed after the levels of the two input terminals of the dynamic comparator become stable.

[0068] According to an embodiment of the present disclosure, when the offset polarity of the dynamic comparator is negative, the second calibration logic circuit is enabled, the second calibration logic circuit cannot be enabled, the second counter generates a second control signal to control the switching state of the second switch tube, thereby controlling the number of bits of the connected second weight transistor, and the second transistor array forms source feedback for the first input transistor and the second input transistor.

[0069] According to an embodiment of the present disclosure, when the offset polarity of the dynamic comparator is negative, the second calibration logic circuit is enabled, and a second control signal corresponding to the second counter is generated according to the clock signal of the dynamic comparator, including: when the offset polarity of the dynamic comparator is positive, the second calibration logic circuit is enabled; the second counter counts upward according to the period corresponding to the clock signal, and accumulates to obtain a second counting control word; and according to the second counting control word, a second control signal corresponding to the second counter is generated.

[0070] According to an embodiment of the present disclosure, the second counter counts upward according to a cycle corresponding to the clock signal, and the accumulated second counting control word has a similar working principle to the first counter, which is not elaborated here.

[0071] According to the embodiments of the present disclosure, the delay chain module first generates a reset signal to provide a reset time for the first calibration logic module and the second calibration logic module, so that the control words output by the first counter and the second counter are reset, the first switching transistor and the second transistor are all turned off, and only the first default transistor and the second default transistor are connected to the circuit. At this time, affected by the mismatch on both sides of the circuit, the input transistor with a larger gate voltage has a higher degree of conduction, a larger current, and a faster discharge speed, so that the output signal shows one end high and the other end low during the effective period, indicating the offset polarity.

[0072] According to an embodiment of the present disclosure, the first counting output terminal and the second counting output terminal are provided with latches.

[0073] According to an embodiment of the present disclosure, when the trigger in the first counter or the second counter adopts a TSPC (True Single Phase Clock) trigger, there is a possibility that the first / second control word cannot be maintained for a long time after the calibration is completed due to node leakage. Therefore, a latch can be added to each bit output node of the first counter or the second counter to ensure that the first / second control word remains unchanged during the conversion of the analog-to-digital converter.

[0074] According to an embodiment of the present disclosure, a plurality of logic gates are further provided in the first calibration logic circuit and the second calibration logic circuit. Figure 3 The offset self-calibration circuit for the dynamic comparator is further described.

[0075] Figure 3 A circuit diagram of an offset self-calibration circuit for a dynamic comparator according to an embodiment of the present disclosure is schematically shown.

[0076] like Figure 3 As shown, the embodiment 300 includes a secondary latch 110, a load tube 120, a first input transistor 130, a second input transistor 140, a first transistor array 210, a second transistor array 220, a first calibration logic module 230, a second calibration logic module 240, a delay chain module 250 and an output NAND gate 260.

[0077] The first calibration logic module 230 includes a first counter 231 , a first positive calibration logic gate 232 , a second positive calibration logic gate 233 , a third positive calibration logic gate 234 , a fourth positive calibration logic gate 235 , a fifth positive calibration logic gate 236 and a sixth positive calibration logic gate 237 .

[0078] The second calibration logic module 240 includes a second counter 241 , a first positive calibration logic gate 242 , a second positive calibration logic gate 243 , a third positive calibration logic gate 244 , a fourth positive calibration logic gate 245 , a fifth positive calibration logic gate 246 and a sixth positive calibration logic gate 247 .

[0079] Taking the offset polarity as positive as an example, the enable signal CAL is set from low to high, the circuit enters the calibration mode, the analog-to-digital converter stops the analog-to-digital conversion, and the clock of the dynamic comparator continues to work, and the two input transistors are connected to the common mode level Vcm. When the comparison result RDY is high, the output signal Von=0, Vop=1, at this time, the count values ​​of the first counter and the second counter are both 0, and the CNTR and CNTL signals output by the first calibration logic module and the second calibration logic module are both high. Correspondingly, CAL, CNT, RDY and Vop are all high, so that the first counter is enabled, and counts up according to the cycle corresponding to the clock signal. The control word increases by 1 in each clock cycle, and the second counting control word is accumulated.

[0080] According to an embodiment of the present disclosure, after the first counter starts counting, the CNTR signal changes from 1 to 0, the second counter cannot be enabled, and the second control word is always kept at 0.

[0081] According to an embodiment of the present disclosure, when the discharge speed generated during the calibration process changes the output polarity of the dynamic comparator, the output signal is Von=1, Vop=0, the first counter is no longer enabled during this calibration cycle, the current first control word is maintained, and the calibration is completed.

[0082] According to an embodiment of the present disclosure, after calibration is completed, the enable signal is set to 0, the analog-to-digital converter starts conversion, the second control word of the second counter remains unchanged at 0, and it is confirmed that the first control word after counting stops is the calibration value.

[0083] According to an embodiment of the present disclosure, the case where the offset polarity is negative is similar to the above process. In the calibration cycle, the second control word output by the first calibration logic module will increase until the dynamic comparator output signal becomes Von=0, Vop=1.

[0084] According to the embodiment of the present disclosure, in order to ensure that the calibration range is large enough, the effective period of the enable signal CAL needs to be greater than the maximum calibration period. For the x-th bit first counter, the effective period is the clearing time provided by the delay module plus 2 times the clock period of the dynamic comparator. x times.

[0085] The circuit diagrams and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the circuits according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram may represent a module or part of a circuit, and the module or part of the circuit contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box may also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or circuit diagram, and the combination of boxes in the block diagram or circuit diagram, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions. It can be understood by those skilled in the art that the features recorded in the various embodiments of the present disclosure can be combined and / or combined in various ways, even if such a combination or combination is not explicitly recorded in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features recorded in the various embodiments of the present disclosure can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present disclosure.

[0086] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. An offset self-calibration circuit for a dynamic comparator, comprising: A first transistor array includes a first weight transistor group and a first default transistor, wherein the first weight transistor group includes a first weight transistor whose multi-bit gate width increases according to a predetermined rule, and the first transistor array is used to perform offset calibration on a dynamic comparator according to a first effective transconductance corresponding to the first weight transistor, wherein the first default transistor is connected to a first input transistor of the dynamic comparator; a second transistor array, comprising a second weight transistor group and a second default transistor, wherein the second weight transistor group comprises second weight transistors whose multi-bit gate widths increase in accordance with the predetermined rule, and the second transistor array is used for offset calibration of the dynamic comparator according to a second effective transconductance corresponding to the second weight transistor, wherein the second default transistor is connected to a second input transistor of the dynamic comparator; A first calibration logic module is connected to the first transistor array, and is used to provide a first control signal to the first transistor array to control the first effective transconductance when the offset polarity of the dynamic comparator is positive; A second calibration logic module is connected to the second transistor array, and is used to provide a second control signal to the second transistor array to control the second effective transconductance when the offset polarity of the dynamic comparator is negative; The delay chain module includes a plurality of inverters, and the delay chain module is used to provide a clearing time length to the first calibration logic module and the second calibration logic module before the input level of the dynamic comparator is stabilized.

2. The circuit according to claim 1, wherein The first transistor array further includes a first switch transistor connected to each of the first weight transistors. The offset calibration of the dynamic comparator according to the first effective transconductance corresponding to the first weight transistor includes: The plurality of first switch transistors control access to the plurality of first weight transistors according to the first control signal, and determine a first target weight transistor from the first weight transistor group; The first effective transconductance is determined according to the number of the first target weight transistors to perform offset calibration on the dynamic comparator.

3. The circuit according to claim 2, wherein: The first calibration logic circuit includes a first counter, the first counter includes a first counting output terminal having the same number as the first switch transistors, and when the offset polarity of the dynamic comparator is positive, providing a first control signal to the first transistor array to control the first effective transconductance, including: When the offset polarity of the dynamic comparator is positive, the first calibration logic circuit is enabled and generates a first control signal corresponding to the first counter according to a clock signal of the dynamic comparator; The first counting output terminals transmit the first control signal to the first switching transistors to control the first effective transconductance.

4. The circuit according to claim 3, wherein: When the offset polarity of the dynamic comparator is positive, the first calibration logic circuit is enabled, and generates a first control signal corresponding to the first counter according to the clock signal of the dynamic comparator, including: In case the offset polarity of the dynamic comparator is positive, the first calibration logic circuit is enabled; The first counter counts upward according to a period corresponding to the clock signal, and accumulates to obtain a first counting control word; A first control signal corresponding to the first counter is generated according to the first counting control word.

5. The circuit according to claim 1, wherein: The second transistor array further includes a second switch transistor correspondingly connected to each of the second weight transistors, and the offset calibration of the dynamic comparator according to the second effective transconductance corresponding to the second weight transistor includes: The plurality of second switch transistors control the opening and closing of the plurality of second weight transistors according to the second control signal, and determine a second target weight transistor from the second weight transistor group; The second effective transconductance is determined according to the second target weight transistor to perform offset calibration on the dynamic comparator.

6. The circuit according to claim 5, wherein: The second calibration logic circuit includes a second counter, the second counter includes second counting output terminals having the same number as the second switch transistors, and when the offset polarity of the dynamic comparator is positive, providing a second control signal to the second transistor array to control the second effective transconductance, including: When the offset polarity of the dynamic comparator is negative, the second calibration logic circuit is enabled, and determines a second control signal corresponding to the second counter according to the clock signal of the dynamic comparator; The plurality of second counting output terminals transmit the second control signal to the plurality of second switching transistors to control the second effective transconductance.

7. The circuit according to claim 6, wherein: When the offset polarity of the dynamic comparator is negative, the second calibration logic circuit is enabled, and generates a second control signal corresponding to the second counter according to the clock signal of the dynamic comparator, including: When the offset polarity of the dynamic comparator is positive, the second calibration logic circuit is enabled; The second counter counts upward according to a period corresponding to the clock signal, and accumulates to obtain a second counting control word; A second control signal corresponding to the second counter is generated according to the second counting control word.

8. The circuit according to claim 1, wherein: The predetermined rules include: 2 to the power of n, 0≤n.

9. The circuit according to claim 1, wherein: The first weight transistor includes multiple first weight sub-transistors, and the second weight transistor includes multiple second weight sub-transistors; the gate length of each of the first weight sub-transistors in each bit of the first weight transistor is equal to the gate length of the first default transistor, and the gate length of each of the second weight sub-transistors in each bit of the second weight transistor is equal to the gate length of the second default transistor; the number of the first weight sub-transistors increases sequentially by the mth power of 2, and the number of the second weight sub-transistors increases sequentially by the mth power of 2, 0≤m.

10. The circuit according to claims 3 and 6, wherein The first counting output terminal and the second counting output terminal are provided with latches.

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