Manufacturing method of MOSFET structure and MOSFET structure

Abstract

The invention provides a manufacturing method of an MOSFET structure and the MOSFET structure, and the method comprises the steps: providing a substrate structure, the substrate structure comprises a substrate region, two first doped regions located in the substrate region and a second doped region located between the two first doped regions, the exposed surfaces of the two first doped regions are parts of the exposed surface of the substrate region, and the exposed surfaces of the two first doped regions are parts of the exposed surface of the substrate region; the two first doped regions are arranged at an interval; forming an insulating layer on the partially exposed surface of each first doped region; forming a side wall structure on the exposed surface of the second doped region and the exposed surface of the insulating layer; and sequentially and downwards etching the second doped region and the substrate structure from the partially exposed surface of the second doped region to form a groove. According to the invention, a medium deposition self-alignment process is carried out on the side wall structure, and the self-aligned side wall structure is used as a mask to etch the groove, so that the technical effect of improving the self-alignment of the protection structure and the groove is realized.

Description

Technical Field

[0001] The present application relates to the field of MOSFET devices, and in particular to a method for manufacturing a MOSFET structure and a MOSFET structure. Background Art

[0002] Power MOSFET is a high-efficiency transistor that is mainly used in high-power amplifiers, power switches, motor control and other fields.

[0003] However, since the oxide layer at the bottom of the MOSFET trench made of wide bandgap materials such as silicon carbide requires a special structure for electric field protection, the silicon carbide MOSFET structure usually needs to include a trench protection structure. The relationship between the protection structure and the trench is usually achieved through photolithography layer alignment and overlay, and the overall structure cannot be self-aligned. As a result, it is difficult to maintain uniformity and consistency between the channel and the protection structure, making it difficult to ensure the consistency of parameters such as threshold voltage and on-resistance.

[0004] The above information disclosed in the background technology section is only used to enhance the understanding of the background technology of the technology described in this article. Therefore, the background technology may contain certain information that does not form the prior art known in this country for those skilled in the art. Summary of the invention

[0005] The main purpose of the present application is to provide a method for manufacturing a MOSFET structure and a MOSFET structure to solve the problem of the lack of self-alignment between the groove and the protection structure of the silicon carbide MOSFET structure in the prior art.

[0006] According to one aspect of an embodiment of the present invention, a method for manufacturing a MOSFET structure is provided, comprising: providing a substrate structure, the substrate structure comprising a substrate region, two first doping regions located in the substrate region, and a second doping region located between the two first doping regions, the exposed surfaces of the two first doping regions being parts of the exposed surface of the substrate region, and the two first doping regions being arranged at intervals, the substrate region being doped with impurities of a first doping type, the first doping region and the second doping region being doped with impurities of a second doping type, the first doping type being one of an N-type doping type and a P-type doping type, the second doping type being the other of an N-type doping type and a P-type doping type, and the doping concentration of the impurities of the second doping type in the second doping region being less than the doping concentration of the impurities of the second doping type in the first doping region; forming an insulating layer on a partially exposed surface of each of the first doping regions; forming a sidewall structure on a partially exposed surface of the second doping region and an exposed surface of the insulating layer; and etching the second doping region and the substrate structure in sequence downward from the partially exposed surface of the second doping region to form a groove.

[0007] Optionally, a substrate structure is provided, including: forming a doping layer on a partial area of ​​the substrate region including an exposed surface; forming a mask portion on the partially exposed surface of the doping layer, and the surfaces of the doping layer on both sides of the mask portion are exposed; and performing ion implantation on at least the doping layer on both sides of the mask portion to form two first doping regions, and the remaining doping layer is the second doping region.

[0008] Optionally, after forming an insulating layer on the partially exposed surface of each first doped region and before forming a sidewall structure on the partially exposed surface of the second doped region and on the exposed surface of the insulating layer, the method further includes: removing the mask portion to expose the surface of the second doped region.

[0009] Optionally, performing ion implantation at least into the doping layer on both sides of the mask portion includes: performing ion implantation into the doping layer on both sides of the mask portion and into the substrate region below the doping layer.

[0010] Optionally, an insulating layer is formed on a partially exposed surface of each of the first doping regions, including: forming a preliminary insulating layer on the exposed surface of the first doping region and the exposed surface of the mask portion, and the surface of the preliminary insulating layer away from the base region is a flat surface; at least the preliminary insulating layer on the surface of the mask portion is removed, and the remaining preliminary insulating layer is the insulating layer, and the exposed surfaces of the insulating layer on the surfaces of the two first doping regions and the exposed surface of the mask portion are on the same plane.

[0011] Optionally, the materials of the first doped region, the second doped region, the mask portion, the insulating layer and the sidewall structure are independently selected from any one or more of polysilicon, silicon dioxide, silicon carbide, and photoresist, and the material of the mask portion is different from that of the insulating layer, and the material of the sidewall structure is different from that of the insulating layer.

[0012] Optionally, forming a mask portion includes: forming a first mask layer on the exposed surface of the doping layer; forming a first barrier layer on the exposed surface of the first mask layer; forming a second mask layer on the surface of the first barrier layer away from the first mask layer; and sequentially etching and removing a portion of the first mask layer, a portion of the first barrier layer, and a portion of the second mask layer, so that the remaining first mask layer, the remaining first barrier layer, and the remaining second mask layer form the mask portion.

[0013] Optionally, materials of the first barrier layer, the first mask layer, and the second mask layer are independently selected from any one or more of polysilicon, silicon dioxide, silicon carbide, and photoresist, and the first barrier layer is different from the materials of the first mask layer and the second mask.

[0014] Optionally, a sidewall structure is formed on a portion of the exposed surface of the second doping region and the exposed surface of the insulating layer, including: forming a preliminary sidewall structure on the exposed surface of the second doping region and the exposed surface of the insulating layer; removing a portion of the preliminary sidewall structure on the surface of the second doping region to expose a portion of the surface of the second doping region, and the remaining preliminary sidewall structure forms the sidewall structure.

[0015] Optionally, the method further includes: removing the sidewall structure and the insulating layer.

[0016] According to another aspect of an embodiment of the present invention, there is provided a MOSFET structure manufactured by any one of the methods described, comprising: a substrate region, the substrate region being doped with impurities of a first doping type, the first doping type being one of an N-type doping type and a P-type doping type; two first doping regions, located in the substrate region, the exposed surfaces of the two first doping regions being parts of the exposed surface of the substrate region, and the two first doping regions being spaced apart, the first doping regions being doped with impurities of a second doping type; a second doping region, located between the two first doping regions, the second doping region having a groove extending through the substrate region, the second doping region being doped with impurities of a second doping type, the second doping type being the other of the N-type doping type and the P-type doping type, and the doping concentration of the impurities of the second doping type in the second doping region being less than the doping concentration of the impurities of the second doping type in the first doping region.

[0017] In the manufacturing method of the MOSFET structure of the embodiment of the present invention, first, a substrate structure is provided, which includes a substrate region, two first doping regions located in the substrate region, and a second doping region located between the two first doping regions, wherein the exposed surfaces of the two first doping regions are parts of the exposed surface of the substrate region, and the two first doping regions are arranged at intervals, and the doping concentration of the second doping type impurities in the second doping region is less than the doping concentration of the second doping type impurities in the first doping region; then, an insulating layer is formed on the partially exposed surface of each first doping region; then, a sidewall structure is formed on the partially exposed surface of the second doping region and the exposed surface of the insulating layer; finally, the second doping region and the substrate structure are sequentially etched downward from the partially exposed surface of the second doping region to form a groove. By forming a second doping region and using the second doping region as a protection structure, an insulating layer is formed on a partially exposed surface of each first doping region, and the insulating layer is used to backfill the protection structure above, and then the first mask portion is removed, a side wall structure is formed in the removed area, a dielectric deposition self-alignment process is performed, and the side wall structure after self-alignment is used as a mask to perform groove etching, so as to achieve the purpose of making the distance between the groove and the two sides to the protection structure consistent, thereby achieving the technical effect of improving the self-alignment of the protection structure and the groove, and further solving the technical problem that the silicon carbide MOSFET structure cannot form the self-alignment of the overall structure due to the contrast of the photolithography layer overlay. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings constituting part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0019] Figure 1 A schematic diagram showing a process of a method for manufacturing a MOSFET structure according to an embodiment of the present application is shown;

[0020] Figure 2 A schematic structural diagram of a substrate structure according to an embodiment of the present application is shown;

[0021] Figure 3 Shown in Figure 2 A schematic diagram of a structure in which an insulating layer is formed on the basis of;

[0022] Figure 4 Shown in Figure 3 A schematic diagram of a structure in which a side wall structure is formed on the basis of;

[0023] Figure 5 Shown in Figure 4 A schematic diagram of a structure in which a groove is formed on the basis of the groove;

[0024] Figure 6 Shows another Figure 4A schematic diagram of a structure in which a groove is formed on the basis of the groove;

[0025] Figure 7 A schematic structural diagram of a substrate region, a doping layer, and a mask portion according to an embodiment of the present application is shown;

[0026] Figure 8 Shown in Figure 7 A schematic diagram of a structure in which a preliminary insulating layer is formed on the basis of

[0027] Fig. 9 A schematic diagram of the structure of another mask portion is shown;

[0028] Fig.10 Shown in Figure 3 A schematic diagram of a structure of a preliminary side wall structure is formed on the basis of;

[0029] Fig.11 A schematic structural diagram of a MOSFET structure according to an embodiment of the present application is shown.

[0030] The above drawings include the following reference numerals:

[0031] 11. Base structure; 12. Base region; 13. First doping region; 14. Second doping region; 141. Doping layer; 15. Mask portion; 151. First mask layer; 152. First barrier layer; 153. Second mask layer; 16. Insulating layer; 161. Preparatory insulating layer; 17. Sidewall structure; 171. Preparatory sidewall structure; 18. Groove. DETAILED DESCRIPTION

[0032] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0033] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0035] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be intermediate elements. Moreover, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element through a third element.

[0036] As mentioned in the background technology, in the prior art, the grooves and protection structures of the silicon carbide MOSFET structure have no self-alignment. In order to solve the above problem, in a typical embodiment of the present application, a method for manufacturing a MOSFET structure and a MOSFET structure are provided.

[0037] According to an embodiment of the present application, a method for manufacturing a MOSFET structure is provided.

[0038] Figure 1 FIG. 1 is a flow chart of a method for manufacturing a MOSFET structure according to an embodiment of the present application. Figure 1 As shown, the method comprises the following steps:

[0039] Step S101, as Figure 2 As shown, a substrate structure 11 is provided, the substrate structure 11 includes a substrate region 12, two first doping regions 13 located in the substrate region 12, and a second doping region 14 located between the two first doping regions 13, the exposed surfaces of the two first doping regions 13 are parts of the exposed surface of the substrate region 12, and the two first doping regions 13 are arranged at intervals, the substrate region 12 is doped with impurities of a first doping type, the first doping regions 13 and the second doping regions 14 are doped with impurities of a second doping type, the first doping type is one of an N-type doping type and a P-type doping type, the second doping type is the other of an N-type doping type and a P-type doping type, and the doping concentration of the second doping type impurities in the second doping region 14 is less than the doping concentration of the second doping type impurities in the first doping region 13;

[0040] In the above steps, the first doping region and the second doping region refer to the doping concentration of the second doping region being lower than the concentration of the first doping region in the silicon carbide MOSFET structure. The above second doping region can form a p-type well region (PWL) as a protective structure to perform electric field protection on the oxide layer structure at the bottom of the silicon carbide MOSFET trench. The material of the substrate structure can be a semiconductor material such as silicon crystal. When the first doping type is P-type, the second doping type is N-type; when the first doping type is N-type, the second doping type is P-type. The above substrate structure can provide a substrate for the silicon carbide MOSFET structure. When the conductive layer is N-type, the MOSFET is an N-type MOSFET, and when the conductive layer is P-type, the MOSFET is a P-type MOSFET.

[0041] Step S102, as Figure 3 As shown, an insulating layer 16 is formed on the partially exposed surface of each of the first doping regions 13;

[0042] In the above steps, the role of the above insulating layer is to ensure that the shortest vertical distance from the insulating layer to the surface of the second doping region is the same as the shortest vertical distance from the first mask portion to the surface of the second doping region during the subsequent backfilling of the first mask portion. Specifically, the shortest vertical distance from the insulating layer and the first mask portion to the surface of the second doping region can be equal by removing part of the redundant insulating layer. The material of the above insulating layer can be any one or more of polysilicon, silicon dioxide, silicon carbide, and photoresist. The specific selection of these materials depends on the thickness, dielectric constant, withstand voltage, chemical stability, etc. of the insulating layer.

[0043] Step S103, as Figure 4 As shown, a sidewall structure 17 is formed on a partially exposed surface of the second doping region 14 and an exposed surface of the insulating layer 16;

[0044] In the above steps, the sidewall structure refers to a structure formed by a sidewall process. The sidewall process utilizes the anisotropic characteristics of dry etching, does not require a mask, and performs dry etching after deposition to form a sidewall structure at the step position. The dielectric deposition self-alignment process can ensure the consistency of the sidewall structure.

[0045] Step S104, as Figure 5 As shown, the second doping region 14 and the substrate structure 11 are sequentially etched downward from the partially exposed surface of the second doping region 14 to form a groove 18 .

[0046] In the above steps, the self-aligned sidewall structure is used as a mask to perform trench etching along the second doped region and the substrate structure, so as to achieve the purpose of aligning the groove with the protection structure, thereby achieving the technical effect of improving the self-alignment of the protection structure and the groove. This can ensure the consistency of the device threshold voltage and on-resistance, and improve the device's ability to resist surge characteristics. Furthermore, etching the sidewall structure usually causes loss in the horizontal sidewall, and the amount of loss is related to the etching equipment capability. It may also occur as follows Figure 6 In the structure shown, the second doping region 14 and the substrate structure 11 are sequentially etched downward from the partially exposed surface of the second doping region 14 to form the groove 18. During the process, the sidewall structure on the surface of the insulating layer is completely etched, leaving only the sidewall.

[0047] In an embodiment of the present invention, first, a substrate structure is provided, which includes a substrate region, two first doping regions located in the substrate region, and a second doping region located between the two first doping regions, wherein the exposed surfaces of the two first doping regions are parts of the exposed surface of the substrate region, and the two first doping regions are arranged at intervals, and the doping concentration of the second doping type impurities in the second doping region is less than the doping concentration of the second doping type impurities in the first doping region; then, an insulating layer is formed on the partially exposed surface of each first doping region; then, a sidewall structure is formed on the partially exposed surface of the second doping region and the exposed surface of the insulating layer; finally, the second doping region and the substrate structure are sequentially etched downward from the partially exposed surface of the second doping region to form a groove. By forming a second doping region and using the second doping region as a protection structure, an insulating layer is formed on a partially exposed surface of each first doping region, and the insulating layer is used to backfill the protection structure above, and then the first mask portion is removed, a side wall structure is formed in the removed area, a dielectric deposition self-alignment process is performed, and the side wall structure after self-alignment is used as a mask to perform groove etching, so as to achieve the purpose of making the distance between the groove and the protection structure consistent, thereby achieving the technical effect of improving the self-alignment of the protection structure and the groove, and further solving the technical problem that the silicon carbide MOSFET structure cannot form the self-alignment of the overall structure due to the contrast of the photolithography layer overlay.

[0048] In a specific implementation of the present application, Figure 7As shown, the steps of forming the above-mentioned base structure 11 include: forming a doping layer 141 on a partial area including an exposed surface of the above-mentioned base area 12; forming a mask part 15 on the partially exposed surface of the above-mentioned doping layer 141, and the surface of the above-mentioned doping layer 141 on both sides of the above-mentioned mask part 15 is exposed; at least ion implantation is performed on the above-mentioned doping layer 141 on both sides of the above-mentioned mask part 15 to form two of the above-mentioned first doping regions, and the remaining above-mentioned doping layer is the above-mentioned second doping region. In the above steps, the material of the base structure can be a semiconductor material such as silicon crystal, and the first conductivity type is one of P type or N type. The above method can quickly form the above-mentioned base structure. Ion implantation is a semiconductor processing technology used to implant ions into semiconductor materials to change their electrical properties, thereby forming a doping layer. First, prepare the semiconductor sample to be doped, and clean and treat the surface to ensure that the surface is clean and flat. In addition, photoresist or other protective layers can be coated on the sample as needed to facilitate subsequent processing after ion implantation. The semiconductor sample is placed in an ion implanter, and the ion accelerator and implantation parameters are set, such as ion species, implantation energy, implantation time, and implantation dose. The implanted ion species and energy can be controlled by adjusting the voltage and electric field of the ion accelerator. Then the ion implanter is started, and the dopant ions are injected into the semiconductor material in the form of an ion beam through the acceleration and guidance of the ion implanter to form a doped layer. The implanted ions can be dopants, such as phosphorus (pentavalent ions), boron (trivalent ions), or aluminum (trivalent ions). After ion implantation, further subsequent processing can be performed, such as removing the protective layer, annealing, or rapid thermal processing, to activate the dopant ions and change the electrical properties of the semiconductor material. It should be noted that during the ion implantation process, the dopant ions may only be implanted into the surface layer of the semiconductor material, so subsequent processing is required to diffuse the dopant ion depth and control the concentration distribution of the dopant ions. In addition, ion implantation may also cause lattice defects and stress changes in the semiconductor material, so appropriate subsequent processing and treatment are required to eliminate these defects and changes. The specific implementation steps of ion implantation may also be other feasible methods in the prior art besides the above-mentioned use of dopants, which will not be described in detail here.

[0049] In a specific embodiment of the present application, after forming an insulating layer on the exposed surface of each of the first doped regions, before forming the sidewall structure on the partially exposed surface of the second doped region and the exposed surface of the insulating layer, the method further includes: removing the mask portion to expose a portion of the surface of the second doped region. Since the mask portion is used as a mask for depositing the insulating layer, after forming the insulating layer on the exposed surface of the first doped region, the mask portion can be removed to expose the surface of the second doped region for further forming the sidewall structure. The mask portion can be removed by chemical etching or physical methods. The chemical etching method can use one or more chemical reagents, such as acid or alkali, to dissolve or etch the mask portion. Different chemical reagents are suitable for different mask materials, for example, a silicon oxide mask can be etched using hydrofluoric acid, while a photoresist mask can be removed using an organic solvent. It should be noted that the chemical etching method requires strict control of the use and handling of the reagents to avoid possible dangers or environmental pollution. The physical method can use a mechanical scraper or scraper to remove the mask. This method is suitable for harder mask materials, such as metal or aluminum oxide. In addition, the mask can also be removed by physical methods such as laser or plasma etching, which usually require special equipment and technology. No matter what method is used to remove the mask, it is necessary to protect the area covered by the mask to avoid damage or impact on the protected area. In addition, after removing the mask, it is necessary to clean and treat it to ensure that the surface of the semiconductor material is clean and flat. The above steps are conducive to the rapid formation of the sidewall structure. Removing the above mask part can also be other feasible methods in the prior art in addition to the above chemical corrosion and physical methods, which will not be repeated here.

[0050] In another specific embodiment of the present application, ion implantation is performed at least into the doped layer on both sides of the mask portion, including: ion implantation is performed into the doped layer on both sides of the mask portion and into the substrate region below the doped layer. In the above steps, during the process of ion implantation into the doped layer on both sides of the mask portion, ion implantation is continued into the substrate region on the side of the doped layer away from the mask portion. The above steps can further form the first doped region in the substrate region.

[0051] In another specific embodiment of the present application, an insulating layer is formed on the exposed surface of each of the first doped regions, such as Figure 8As shown, it includes: forming a preliminary insulating layer 161 on the exposed surface of the first doping region 13 and the exposed surface of the mask part 15, and the surface of the preliminary insulating layer 161 away from the base region 12 is a flat surface; at least the preliminary insulating layer 161 on the surface of the mask part 15 is removed, and the remaining preliminary insulating layer 161 is the insulating layer, and the exposed surface of the insulating layer on the surface of the two first doping regions 13 and the exposed surface of the mask part 15 are on the same plane. The preliminary insulating layer can be removed by chemical etching, plasma etching and mechanical removal, wherein the chemical etching method can use one or more chemical reagents, such as acid or alkali, to dissolve or etch the preliminary insulating layer. It should be noted that different insulating layer materials require different chemical reagents, for example, silicon oxide can be corroded using hydrofluoric acid, and silicon carbide can be corroded using sodium hydroxide. The chemical etching method requires strict control of the use and handling of reagents to avoid possible dangers or environmental pollution. The plasma etching method can use plasma to strip or etch away atoms or molecules on the surface of the prepared insulating layer, and accurately etch the prepared insulating layer by controlling plasma parameters and process parameters. It should be noted that the plasma etching method requires special equipment and technology, and may damage or affect the device. The mechanical removal method can use tools such as mechanical scrapers or scrapers to remove the material on the surface of the prepared insulating layer. The mechanical removal method is suitable for thicker insulating layers, but may cause scratches or damage to the device. Regardless of which of the above methods is used to remove the prepared insulating layer, it is necessary to protect other parts of the device to avoid damage or impact on the device. In addition, after removing the prepared insulating layer, it is necessary to clean and process it to ensure that the surface of the semiconductor material is clean and flat. In practical applications, the mask layer before trench etching is thick and needs to be flattened. Part of the prepared insulating layer can be removed by CMP or etching back, but process control accuracy is required. The above method can further ensure the flattening of the mask layer before trench etching. The above-mentioned preliminary insulating layer can also be removed by other feasible methods in the prior art besides the above-mentioned chemical etching method, plasma etching method and mechanical removal method, which will not be described in detail here.

[0052] In another specific embodiment of the present application, the materials of the first doped region, the second doped region, the mask portion, the insulating layer and the sidewall structure are independently selected from any one or more of polysilicon, silicon dioxide, silicon carbide and photoresist, and the mask portion is different from the material of the insulating layer, and the sidewall structure is different from the material of the insulating layer. In the above method, those skilled in the art can select corresponding semiconductor materials according to actual needs, which are not limited to the above four materials of polysilicon, silicon dioxide, silicon carbide and photoresist. However, it is necessary to ensure that the two material layers in contact with each other are different media, that is, the mask portion is different from the insulating layer in material, and the sidewall structure is different from the insulating layer in material.

[0053] In another specific implementation manner of the present application, Fig. 9 As shown, the step of forming the above-mentioned mask portion includes: forming a first mask layer 151 on the exposed surface of the above-mentioned doping layer 141; forming a first barrier layer 152 on the exposed surface of the above-mentioned first mask layer 151; forming a second mask layer 153 on the surface of the above-mentioned first barrier layer 152 away from the above-mentioned first mask layer 151; sequentially etching and removing part of the above-mentioned first mask layer 151, part of the above-mentioned first barrier layer 152 and part of the above-mentioned second mask layer 153, and the remaining above-mentioned first mask layer 151, the remaining above-mentioned first barrier layer 152 and the remaining above-mentioned second mask layer 153 form the above-mentioned mask portion. In the above steps, the barrier layer is a covering layer used to protect semiconductor devices, which is usually made of metal or metal compounds. The main function of the barrier layer is to prevent damage or unnecessary processing of the device during chemical corrosion or physical etching during the manufacturing process of the semiconductor device. Specifically, during the processing process, the insulating layer usually needs to be etched or corroded to form the structure or channel of the device. The etch barrier layer can protect the insulating layer during these processes to prevent the insulating layer from being corroded or damaged, thereby preventing problems such as leakage or short circuit in the device. In addition, the barrier layer can also play a role in controlling the processing accuracy during the semiconductor processing process. For example, during the etching or corrosion process, the etch barrier layer can control the processing depth or shape, thereby ensuring the manufacturing accuracy of the device. Since the junction depth of the protection structure is large, it is necessary to level the thicker protection structure medium, making it difficult to ensure the consistency of leveling. By adding the first barrier layer, the subsequent leveling process can be automatically stopped at the first barrier layer to ensure that the remaining structure meets the requirements of the groove etching mask. The material of the above-mentioned first barrier layer can be a dielectric layer material with a high selectivity ratio. The above steps can further ensure leveling and consistency.

[0054] In another specific embodiment of the present application, the materials of the first barrier layer, the first mask layer, and the second mask layer are independently selected from any one or more of polysilicon, silicon dioxide, silicon carbide, and photoresist, and the first barrier layer is different from the materials of the first mask layer and the second mask. In the above method, those skilled in the art can select corresponding semiconductor materials according to actual needs, which are not limited to the four materials of polysilicon, silicon dioxide, silicon carbide, and photoresist. However, it is necessary to ensure that the two material layers in contact with each other are different media, that is, the materials of the first barrier layer, the first mask layer, and the second mask are different.

[0055] In another specific embodiment of the present application, the method further comprises: removing the sidewall structure and the insulating layer. In the method, the sidewall structure and the insulating layer can be removed by chemical etching, plasma etching and mechanical removal, wherein the chemical etching method can use one or more chemical reagents, such as acid or alkali, to dissolve or etch the sidewall structure and the insulating layer. It should be noted that different materials require different chemical reagents, for example, silicon oxide can be etched with hydrofluoric acid, and silicon carbide can be etched with sodium hydroxide. The chemical etching method requires strict control of the use and treatment of reagents to avoid possible dangers or environmental pollution. The plasma etching method can use plasma to strip or etch the atoms or molecules on the surface of the sidewall structure and the insulating layer, and achieve precise etching of the sidewall structure and the insulating layer by controlling the plasma parameters and process parameters. It should be noted that the plasma etching method requires special equipment and technology, and may cause damage or impact on the device. The mechanical removal method can use tools such as mechanical scrapers or scrapers to remove materials on the surface of the sidewall structure and the insulating layer. The mechanical removal method is suitable for thicker insulating layers, but may cause scratches or damage to the device. No matter which of the above methods is used to remove the side wall structure and the insulating layer, it is necessary to protect other parts of the device to avoid damage or impact on the device. In addition, after removing the side wall structure and the insulating layer, cleaning and processing are required to ensure that the surface of the semiconductor material is clean and flat. Removing the above insulating layer and the side wall structure can also be other feasible methods in the prior art in addition to the above chemical corrosion method, plasma etching method and mechanical removal method, which will not be repeated here. The above method can quickly form the final silicon carbide MOSFET structure.

[0056] In another specific embodiment of the present application, a sidewall structure is formed on a partially exposed surface of the second doping region and an exposed surface of the insulating layer, such as Fig.10As shown, it includes: forming a preliminary sidewall structure 171 on the exposed surface of the second doping region 14 and the exposed surface of the insulating layer 16; removing part of the preliminary sidewall structure 171 on the surface of the second doping region 14 to expose part of the surface of the second doping region 14, and the remaining preliminary sidewall structure 171 forms the sidewall structure. Due to the existence of deposition characteristics, the thickness of the preliminary sidewall structure on the surface of the second doping region is thinner, the thickness of the preliminary sidewall structure on the sidewall is thinner, and the thickness of the preliminary sidewall structure on the surface of the insulating layer is thicker, and the specific thickness difference depends on the actual situation of the equipment processing capacity. The subsequent dielectric deposition self-alignment process can ensure the consistency of the sidewall structure. The above method can quickly form the above sidewall structure.

[0057] According to an embodiment of the present application, a MOSFET structure manufactured by any of the above methods is also provided, such as Fig.11 As shown, including:

[0058] A substrate region 12, wherein the substrate region 12 is doped with impurities of a first doping type, wherein the first doping type is one of an N-type doping type and a P-type doping type;

[0059] Specifically, the material of the base region may be a semiconductor material such as silicon crystal.

[0060] Two first doping regions 13 are located in the base region 12, the exposed surfaces of the two first doping regions 13 are parts of the exposed surface of the base region 12, and the two first doping regions 13 are arranged at intervals, and the first doping regions 13 are doped with impurities of a second doping type;

[0061] Specifically, when the substrate region is of N-type doping type, the first doping region is of P-type doping type; and when the substrate region is of P-type doping type, the first doping region is of N-type doping type.

[0062] The second doping region 14 is located between the two first doping regions 13. The second doping region 14 has a groove 18 that penetrates the base region 12. The second doping region 14 is doped with impurities of a second doping type. The second doping type is the other of the N-type doping type and the P-type doping type. The doping concentration of the impurities of the second doping type in the second doping region 14 is less than the doping concentration of the impurities of the second doping type in the first doping region 13.

[0063] Specifically, the second doped region can form a p-type well region (PWL) as a protective structure to provide electric field protection for the oxide layer structure at the bottom of the silicon carbide MOSFET trench. By using the self-aligned sidewall structure as a mask, trench etching is performed along the second doped region and the substrate structure, so that the groove is consistent with the protective structure, thereby achieving the technical effect of improving the self-alignment of the protective structure and the trench. When the first doping type is P-type, the second doping type is N-type; when the first doping type is N-type, the second doping type is P-type.

[0064] In the above embodiments of the present invention, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0065] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0066] 1) In the manufacturing method of the MOSFET structure of the present application, first, a substrate structure is provided, which includes a substrate region, two first doped regions located in the substrate region, and a second doped region located between the two first doped regions, wherein the exposed surfaces of the two first doped regions are parts of the exposed surface of the substrate region, and the two first doped regions are arranged at intervals, and the doping concentration of the second doping type impurities in the second doped region is less than the doping concentration of the second doping type impurities in the first doped region; then, an insulating layer is formed on the partially exposed surface of each first doped region; then, a sidewall structure is formed on the partially exposed surface of the second doped region and the exposed surface of the insulating layer; finally, the second doped region and the substrate structure are sequentially etched downward from the partially exposed surface of the second doped region to form a groove. By forming a second doping region and using the second doping region as a protection structure, an insulating layer is formed on a partially exposed surface of each first doping region, and the insulating layer is used to backfill the protection structure above, and then the first mask portion is removed, a side wall structure is formed in the removed area, a dielectric deposition self-alignment process is performed, and the side wall structure after self-alignment is used as a mask to perform groove etching, so as to achieve the purpose of making the distance between the groove and the protection structure consistent, thereby achieving the technical effect of improving the self-alignment of the protection structure and the groove, and further solving the technical problem that the silicon carbide MOSFET structure cannot form the self-alignment of the overall structure due to the contrast of the photolithography layer overlay.

[0067] 2) The MOSFET structure of the present application includes a substrate region, two first doping regions and a second doping region, the substrate region is doped with impurities of a first doping type, the first doping type is one of an N-type doping type and a P-type doping type, the two first doping regions are located in the substrate region, the exposed surfaces of the two first doping regions are parts of the exposed surfaces of the substrate region, and the two first doping regions are arranged at intervals, the first doping regions are doped with impurities of a second doping type; the second doping region is located between the two first doping regions, the second doping region has a groove that passes through the substrate region, the second doping region is doped with impurities of a second doping type, the second doping type is another of the N-type doping type and the P-type doping type, and the doping concentration of the impurities of the second doping type in the second doping region is less than the doping concentration of the impurities of the second doping type in the first doping region. The groove of the MOSFET structure is consistent with the distance between the protection structure, thereby achieving the technical effect of improving the self-alignment of the protection structure and the groove, thereby solving the technical problem that the silicon carbide MOSFET structure cannot form the self-alignment of the overall structure due to the contrast of the lithography layer overlay.

[0068] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0069] In the above embodiments of the present invention, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0070] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0071] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0072] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for manufacturing a MOSFET structure, characterized in that: include: A substrate structure is provided, the substrate structure comprising a substrate region, two first doping regions located in the substrate region, and a second doping region located between the two first doping regions, the exposed surfaces of the two first doping regions are parts of the exposed surface of the substrate region, and the two first doping regions are arranged at intervals, the substrate region is doped with impurities of a first doping type, the first doping region and the second doping region are doped with impurities of a second doping type, the first doping type is one of an N-type doping type and a P-type doping type, the second doping type is the other of the N-type doping type and the P-type doping type, and the doping concentration of the impurities of the second doping type in the second doping region is less than the doping concentration of the impurities of the second doping type in the first doping region; forming an insulating layer on a partially exposed surface of each of the first doped regions; forming a sidewall structure on a partially exposed surface of the second doping region and an exposed surface of the insulating layer; The second doping region and the substrate structure are sequentially etched downward from a partially exposed surface of the second doping region to form a groove.

2. The method for manufacturing a MOSFET structure according to claim 1, characterized in that: Provide a base structure, including: forming a doping layer in a partial area of ​​the substrate region including an exposed surface; forming a mask portion on a partially exposed surface of the doping layer, wherein the surfaces of the doping layer on both sides of the mask portion are exposed; Ions are implanted into at least the doping layer on both sides of the mask portion to form two first doping regions, and the remaining doping layer is the second doping region.

3. The method for manufacturing a MOSFET structure according to claim 2, characterized in that: After forming an insulating layer on the partially exposed surface of each of the first doping regions and before forming a sidewall structure on the partially exposed surface of the second doping regions and on the exposed surface of the insulating layer, the method further includes: The mask portion is removed to expose the surface of the second doping region.

4. The method for manufacturing a MOSFET structure according to claim 2, characterized in that: Performing ion implantation at least into the doping layer on both sides of the mask portion comprises: Ions are implanted into the doping layer on both sides of the mask portion and into the base region below the doping layer.

5. The method for manufacturing a MOSFET structure according to claim 2, characterized in that: Forming an insulating layer on a partially exposed surface of each of the first doped regions, comprising: forming a preliminary insulating layer on the exposed surface of the first doping region and the exposed surface of the mask portion, wherein the surface of the preliminary insulating layer away from the base region is a flat surface; At least the preliminary insulating layer on the surface of the mask portion is removed, and the remaining preliminary insulating layer is the insulating layer, and the exposed surface of the insulating layer on the surfaces of the two first doping regions and the exposed surface of the mask portion are on the same plane.

6. The method according to claim 2, characterized in that The materials of the first doped region, the second doped region, the mask portion, the insulating layer and the sidewall structure are independently selected from any one or more of polysilicon, silicon dioxide, silicon carbide, and photoresist, and the material of the mask portion is different from that of the insulating layer, and the material of the sidewall structure is different from that of the insulating layer.

7. The method for manufacturing a MOSFET structure according to claim 2, characterized in that: forming a mask portion, including: forming a first mask layer on the exposed surface of the doped layer; forming a first barrier layer on the exposed surface of the first mask layer; forming a second mask layer on a surface of the first barrier layer away from the first mask layer; Part of the first mask layer, part of the first barrier layer and part of the second mask layer are removed by etching in sequence, and the remaining first mask layer, the remaining first barrier layer and the remaining second mask layer form the mask portion.

8. The method according to claim 7, characterized in that The materials of the first barrier layer, the first mask layer, and the second mask layer are independently selected from any one or more of polysilicon, silicon dioxide, silicon carbide, and photoresist, and the first barrier layer is different from the materials of the first mask layer and the second mask layer.

9. The method for manufacturing a MOSFET structure according to any one of claims 1 to 8, characterized in that: Forming a sidewall structure on a partially exposed surface of the second doping region and an exposed surface of the insulating layer, comprising: forming a preliminary sidewall structure on an exposed surface of the second doping region and an exposed surface of the insulating layer; The prepared sidewall structure on a portion of the surface of the second doping region is removed to expose a portion of the surface of the second doping region, and the remaining prepared sidewall structure forms the sidewall structure.

10. The method for manufacturing a MOSFET structure according to any one of claims 1 to 8, characterized in that: After forming the groove, the method further comprises: The sidewall structure and the insulating layer are removed.

11. A MOSFET structure manufactured by the method according to any one of claims 1 to 10, characterized in that: include: A substrate region, wherein the substrate region is doped with impurities of a first doping type, wherein the first doping type is one of an N-type doping type and a P-type doping type; Two first doping regions are located in the base region, the exposed surfaces of the two first doping regions are parts of the exposed surface of the base region, the two first doping regions are arranged at intervals, and the first doping regions are doped with impurities of a second doping type; A second doping region is located between two of the first doping regions, the second doping region has a groove that penetrates the base region, the second doping region is doped with impurities of a second doping type, the second doping type is the other of the N-type doping type and the P-type doping type, and the doping concentration of the impurities of the second doping type in the second doping region is less than the doping concentration of the impurities of the second doping type in the first doping region.

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