SiC MOSFET maximum surge current test and failure analysis method and device based on three-terminal resistance monitoring

Abstract

The invention discloses a SiC MOSFET maximum surge current test and failure analysis method and device based on three-terminal resistance monitoring. The performance change of the device under the extreme stress is quickly evaluated by applying the stepping surge current and combining the online monitoring of the three-terminal resistor, so that the maximum single surge current bearing capacity and the failure mode of the device are judged. The method comprises the following specific steps: applying proper grid bias voltage to a SiC MOSFET to be tested, and setting parameters of a surge current generating circuit; and after the stepping single surge current is applied, measuring and recording three-terminal static resistance values of the gate-source terminal, the drain-source terminal and the gate-drain terminal. By monitoring the change of the resistance value, the maximum single surge current is determined, the failure mode of the device is judged, and the modes of open circuit, short circuit, electric leakage, burning and the like are determined. The method is easy and convenient to operate and low in cost, and reliability information of the SiC MOSFET can be rapidly provided under the condition that a high-precision instrument is not used.

Description

Technical Field

[0001] The present invention belongs to the field of power semiconductor reliability testing, and in particular relates to a SiC MOSFET maximum surge current testing and failure analysis method and device based on three-terminal resistance monitoring. Background Art

[0002] SiC MOSFET (Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor) is widely used in high-power and high-frequency electronic devices due to its excellent electrical and thermal properties. However, in practical applications, SiC MOSFET faces transient stresses such as surge current, which may have a significant impact on the reliability of the device. Surge current is usually caused by factors such as instantaneous overload or power supply fluctuation, which may cause physical damage to internal materials and changes in electrical characteristics.

[0003] After surge stress is applied, the static electrical characteristics of SiC MOSFET, especially the three-terminal static resistance, may change. This is because surge stress can cause microstructural changes inside the device, including the generation of defects and aging of materials, which in turn affect the conductive path. By measuring the three-terminal static resistance, important information can be obtained on whether the device fails or performance degrades after experiencing a surge.

[0004] Many methods focus on measuring changes in electrical characteristics after applying surge current stress, including key parameters such as leakage current, threshold voltage, and on-resistance. These electrical characteristics can reflect the performance degradation of the device after experiencing extreme conditions. Some existing methods use high-precision instruments (such as semiconductor parameter analyzers and oscilloscopes) to determine the maximum single surge current. Although these methods are accurate, they are usually costly, time-consuming, and not suitable for rapid evaluation.

[0005] After a SiC MOSFET fails due to a surge, its failure mode and failure mechanism are generally determined through a series of analysis methods such as acoustic scanning, X-ray, unsealing, and SEM. Although the failure location is accurate, it requires high-end analytical instruments, which are costly and time-consuming. The change in static three-terminal resistance can quickly determine the device open circuit, short circuit, burnout, and leakage failure modes, thereby indicating failure mechanisms such as material defects, structural damage, or poor contact. At present, there is little research on device surge current testing and degradation analysis based on three-terminal static resistance measurement. Summary of the invention

[0006] In response to the above technical problems, the present invention aims to quickly analyze the performance changes of SiC MOSFET under extreme stress by applying a stepped single surge current stress combined with three-terminal static resistance measurement, thereby providing a basis for determining the cause of failure.

[0007] The technical solution adopted by the present invention is specifically described as follows:

[0008] A SiC MOSFET failure analysis method based on three-terminal resistance monitoring, characterized in that the three-terminal resistance is the gate-source resistance, drain-source resistance and gate-drain resistance of the SiC MOSFET;

[0009] The method comprises:

[0010] S1. Apply gate bias to the SiC MOSFET to turn off the channel of the device.

[0011] S2. Apply a surge current from the source to the drain of the SiC MOSFET in a single step. After each application, measure and record the three-terminal resistance of the SiC MOSFET (including Rgs, Rsg, Rgd, Rdg, Rds, and Rsd). The surge current increases by 5-10A each time.

[0012] S3. When one or more of the three-terminal resistors of the SiC MOSFET drops below 1,000 ohms after a surge current is applied, the SiC MOSFET is judged to be in a failed state, and the surge current is stopped;

[0013] S4. When it is determined that the SiC MOSFET is in a failed state, determine the failure cause of the SiC MOSFET according to changes in the gate-source resistance, the drain-source resistance, and the gate-drain resistance, wherein the failure cause is at least one of a short circuit between the gate and the source, a short circuit between the drain and the source, and a short circuit between two of the gate, the drain, and the source;

[0014] When the gate-source resistance drops below a thousand ohms, and the gate-drain resistance and drain-source resistance are greater than one hundred megohms, the cause of the failure is determined to be a short circuit between the gate and the source;

[0015] When the drain-source resistance drops below a thousand ohms, and the gate-drain resistance and gate-source resistance are greater than one hundred megohms, the cause of failure is determined to be a short circuit between the drain and source electrodes;

[0016] When the gate-source resistance, drain-source resistance and gate-drain resistance all dropped below kilohms, it was determined that the cause of the failure was the short circuit between the three terminals of the gate, drain and source.

[0017] Preferably, the cause of the gate-source short circuit is at least one of gate oxide layer damage, gate charge capture, leakage current increase, local thermal effect and material defect-induced leakage;

[0018] The cause of the short circuit between the drain and the source is at least one of damage to the body diode, metal migration, thermal stress, increased leakage current and accumulation of drift layer defects;

[0019] The reason for the short circuit between the three terminals of the gate, drain and source is at least one of overheating of the device, burning of the gate aluminum metal and breakdown of the gate oxide layer.

[0020] Preferably, in S1, the three-terminal static resistance of the SiC MOSFET is in the order of hundreds of megohms; the gate bias voltage is -10V to 0V, so that the channel of the SiC MOSFET is in a closed state.

[0021] Preferably, in S2, the surge current pulse width is 1-10 ms, and the duty cycle is less than one thousandth.

[0022] A method for testing the maximum surge current of a SiC MOSFET based on three-terminal resistance monitoring is characterized in that a failure analysis is performed according to the method of the present invention, and after the SiC MOSFET is in a failed state, the intensity of the last surge current applied before the failure is judged to be the maximum surge current of the SiC MOSFET.

[0023] A SiC MOSFET maximum surge current test and failure analysis circuit based on three-terminal resistor monitoring, characterized in that it includes a capacitor charging circuit, a surge current circuit, a drive circuit and a three-terminal resistor detection unit; the capacitors respectively form the capacitor charging circuit and the surge current circuit through a single-pole double-throw switch;

[0024] The capacitor charging loop also includes a first voltage source and a resistor; the surge current loop also includes an inductor connected to the source and drain of the SiC MOSFET.

[0025] Preferably, after the capacitor is charged in the capacitor charging circuit through the first voltage source, the capacitor charging circuit is disconnected and the surge current circuit is closed through a single-pole double-throw switch, so that the capacitor and the inductor construct a sinusoidal oscillation circuit to generate a surge current from the source to the drain of the SiCMOSFET, and the surge current intensity is controlled by controlling the voltage of the first voltage source.

[0026] Preferably, the driving circuit comprises a second voltage source and a first switch, and the source of the SiC MOSFET is connected to the gate of the SiC MOSFET via the first switch and the second voltage source in sequence.

[0027] Preferably, the three-terminal resistance detection unit is connected to the SiC MOSFET via a second switch, and is used to detect the gate-source resistance, drain-source resistance and gate-drain resistance of the SiC MOSFET.

[0028] A SiC MOSFET maximum surge current testing and failure analysis device based on three-terminal resistance monitoring, characterized by comprising the circuit described in the present invention.

[0029] The main advantage of the present invention is that by analyzing the change law of the three-terminal static resistance of the device during the step single surge current test, the maximum single surge current and failure mode of the SiC MOSFET can be effectively determined. The method only needs to design and integrate the resistance detection function, avoiding the use of electronic test instruments such as parameter analyzers and oscilloscopes, thereby significantly reducing the initial workload, and the required equipment is relatively simple and low-cost. At the same time, the present invention helps to understand the failure mechanism of the device more deeply, and provides key support and supplement for the reliability research of SiC MOSFET. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0031] Figure 1 The invention discloses a circuit for testing the maximum surge current and analyzing the failure of a SiC MOSFET based on three-terminal resistance monitoring.

[0032] Among them, V is the first voltage source; R1 is a resistor; S is a single-pole double-throw switch; C is a capacitor; L is an inductor; V1 is the first voltage source; S1 is the first switch; S2 is the second switch. DETAILED DESCRIPTION

[0033] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0035] It can be understood that the terms "first", "second", etc. used in the present application can be used in this article to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element.

[0036] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.

[0037] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0038] Example 1

[0039] The samples under test (DUT) in this embodiment are commercial 1200V SiC MOSFETs produced by manufacturers A, B, C, and D.

[0040] First, the three-terminal resistance of the devices under test was measured. The measurement results showed that the resistance values ​​of all the devices under test were in the order of hundreds of megohms, indicating that the devices were in good condition before stress was applied.

[0041] Then, the rated current size in the product specification is set as the initial surge current size, and a sine wave with a pulse width of 10ms is generated according to the LC oscillation principle. The number of impact rounds is set to 1 round to ensure that only one surge current is applied each time, and the duty cycle is set to less than one thousandth. Next, gradually increase the single surge current intensity of 10A, and measure the three-terminal resistance of the DUT after each single surge current stress is applied, and record the change in resistance value. If the resistance value is still in the hundreds of megohms after applying a single surge current stress, the test process continues until the resistance value is observed to decrease in magnitude, and the device is determined to have failed.

[0042] like Figure 1 As shown, the test circuit includes a capacitor charging circuit, a surge current circuit, a drive circuit and a three-terminal resistance detection unit. Figure 1It can be seen that the main components include a first voltage source V, a resistor R1, a capacitor C, a single-pole double-throw switch S, an inductor L, a second voltage source V1, a first switch S1, a second switch S2, a device under test, and a resistance detection unit. During the charging process, the first voltage source V charges the capacitor C through the resistor R1, the left side of the switch S is closed, and the right side remains disconnected. The second voltage source V1 and the switch S1 are used to provide a bias voltage for the gate of the device under test, so as to test the response of the device to a single surge current under a fixed gate bias voltage. The gate voltage is set according to the actual working condition of the DUT, and is set to -10V in this embodiment. When the capacitor C is fully charged, the switch S1 is closed, the S2 is disconnected, the right side of the switch S is closed, and the charge in the capacitor is released to the device under test SiCMOSFET through the inductor L, forming a single transient surge current. The switch S is thrown to the right side and closed to discharge the capacitor quickly, and the high-amplitude single surge current generated flows through the inductor L and the device under test. The inductor L can adjust the rate of current rise to simulate the sudden stress situation in actual work.

[0043] After the single surge current is applied and the capacitor is discharged, the switches S and S1 are turned off, and the switch S2 is closed. The three-terminal resistance detection unit is used to measure the three resistance values ​​of gate-source, gate-drain, and drain-source. The specific principle is that the three-terminal resistance detection unit applies a known small current to the gate and source, the gate and drain, and the drain and source, respectively, and calculates the values ​​of the three-terminal resistances Rgs, Rsg, Rgd, Rdg, Rds, and Rsd by measuring the voltage drop. These measurement data are used to analyze the changes in resistance of the DUT before and after it is subjected to a single surge current.

[0044] The intensity of the surge current last applied before the failure of DUT A, DUT B, DUT C, and DUT D is recorded as the maximum single surge current, and the three-terminal resistance measured after the device fails is recorded. The data results are shown in Table 1.

[0045] Table 1 Three-terminal resistance of failed devices

[0046]

[0047] By comparing the change in the three-terminal resistance of the DUT after withstanding a single-step surge current, the maximum single-surge current of the DUT can be determined first, and at the same time, the degradation or failure mode of the SiC MOSFET can be effectively judged. Within 10 ms after applying the single-surge current, the direction of the single-surge current is from the source (S) of the DUT to the drain (D). After applying the single-surge current, through the three-terminal resistance detection module, the resistance values of the drain-source terminals (Rds, Rsd) can be measured to be in the order of one hundred thousand ohms to one megohm, and Rsd < Rds, which can judge that there is a leakage channel between the two detected terminals, but the DUT still has a certain blocking ability and the DUT is not completely失效; when the resistance values of Rsd and Rds decrease to below the order of ten thousand ohms, and the difference between the resistance values of Rsd and Rds is very small or equal, the drain-source is in a short-circuit mode, the leakage increases rapidly, the DUT loses its blocking ability, and it is determined that the damage between the source and drain causes failure.

[0048] After the DUT fails, only the resistance values of the gate-source terminals (Rgs, Rsg) are detected to be below one thousand ohms, and when the difference between the resistance values of Rgs and Rsg is very small or equal, the gate-source is in a short-circuit mode, indicating that the gate oxide layer is damaged or there is a problem of source metal melting; when the resistance values of the three terminals of the gate-source-drain are all detected to be below one thousand ohms and the three terminals of the gate-source-drain are in a short-circuit mode showing resistance failure, it can be judged that under the maximum surge current stress, the DUT overheats and burns out inside, resulting in transient failure.

[0049] As can be seen from Table 1, when the gate bias is -10V, after each of DUT A, DUT B, DUT C, and DUT D withstands a single-step surge current increasing by 10A, the maximum single-surge currents of DUT A, DUT B, DUT C, and DUT D are determined to be 140A, 110A, 160A, and 110A respectively.

[0050] As can be seen from Table 1, after DUT A withstands the maximum single-surge current of 140A, both Rgs and Rsg are 1.6Ω, while the resistance values between the drain-source and gate-drain are very large, and the resistance between the gate and the source is significantly reduced. It is judged that the cause of failure is a short circuit between the gate and the source, and the insulating layer is damaged, and the insulation state has been affected; the resistance values between the three terminals of DUT B and DUT C are severely reduced, both dropping below one thousand ohms, indicating that all three terminals are in a short-circuit state. It is judged that the cause of failure is a short circuit between any two of the three terminals of the gate-drain-source; the resistance values of Rds and Rsd of DUTD are both less than one thousand ohms, and the drain-source has a short circuit and loses its blocking ability, while the resistance values between the gate-drain and gate-source are still in the order of one hundred megohms. It is judged that the cause of failure is a short circuit between the drain-source.

[0051] As shown in Table 1, DUT A, DUT B, and DUT C all show a significant decrease in gate-source resistance, indicating that the thermal effect and electric field strength generated by the step single surge current have caused damage to the gate oxide layer; the Rds and Rsd resistance values ​​of DUT B and DUT C have decreased, indicating that the body diode is seriously damaged, which may be caused by metal migration, thermal stress or material defects; the Rgd and Rdg resistance values ​​of DUT B and DUT C have decreased, indicating that the insulation between the gate and the drain is affected, which may be caused by the breakdown of the gate oxide layer between the gate and the drain or material defects; for DUT D, the Rds and Rsd resistance values ​​are both reduced to below the kilohm level and Rsd≈Rds, and the remaining resistance values ​​are very large, indicating that there is a conduction path between the drain and the source, which may be due to the single large step surge current destroying the internal PN junction and causing the device body diode to fail.

[0052] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be equivalent replacement methods and are included in the protection scope of the present invention.

Claims

1. A SiC MOSFET failure analysis method based on three-terminal resistance monitoring, characterized in that: The three-terminal resistor is the gate-source resistance, drain-source resistance and gate-drain resistance of the SiC MOSFET; The method comprises: S1. Apply gate bias to the SiC MOSFET to turn off the channel of the device. S2. Apply a surge current from the source to the drain of the SiC MOSFET in a single step. After each application, measure and record the three-terminal resistance of the SiC MOSFET. The surge current increases by 5-10A each time. S3. When one or more of the three-terminal resistors of the SiC MOSFET drops below 1,000 ohms after a surge current is applied, the SiC MOSFET is judged to be in a failed state, and the surge current is stopped; S4. When it is determined that the SiC MOSFET is in a failed state, determine the failure cause of the SiC MOSFET according to changes in the gate-source resistance, the drain-source resistance, and the gate-drain resistance, wherein the failure cause is at least one of a short circuit between the gate and the source, a short circuit between the drain and the source, and a short circuit between two of the gate, the drain, and the source; When the gate-source resistance drops below a thousand ohms, and the gate-drain resistance and drain-source resistance are greater than one hundred megohms, the cause of the failure is determined to be a short circuit between the gate and the source; When the drain-source resistance drops below a thousand ohms, and the gate-drain resistance and gate-source resistance are greater than one hundred megohms, the cause of failure is determined to be a short circuit between the drain and source electrodes; When the gate-source resistance, drain-source resistance and gate-drain resistance all dropped below kilohms, it was determined that the cause of the failure was the short circuit between the three terminals of the gate, drain and source.

2. A SiC MOSFET failure analysis method based on three-terminal resistance monitoring according to claim 1, characterized in that: The cause of the short circuit between the gate and the source is at least one of damage to the gate oxide layer, gate charge capture, increased leakage current, local thermal effects and leakage caused by material defects; The cause of the short circuit between the drain and the source is at least one of damage to the body diode, metal migration, thermal stress, increased leakage current and accumulation of drift layer defects; The reason for the short circuit between the three terminals of the gate, drain and source is at least one of overheating of the device, burning of the gate aluminum metal and breakdown of the gate oxide layer.

3. A SiC MOSFET failure analysis method based on three-terminal resistance monitoring according to claim 2, characterized in that: In S1, the three-terminal static resistance of the SiC MOSFET is in the order of hundreds of megohms; the gate bias voltage is -10V to 0V, so that the channel of the SiC MOSFET is in a closed state.

4. A SiC MOSFET failure analysis method based on three-terminal resistance monitoring according to claim 3, characterized in that: In S2, the surge current pulse width is 1 to 10 ms, and the duty cycle is less than one thousandth.

5. A SiC MOSFET maximum surge current test method based on three-terminal resistance monitoring, characterized in that: According to the method according to any one of claims 1 to 4, failure analysis is performed, and after the SiC MOSFET is in a failed state, it is determined that the intensity of the last surge current applied before the failure is the maximum surge current of the SiC MOSFET.

6. A SiC MOSFET maximum surge current test and failure analysis circuit based on three-terminal resistance monitoring, characterized in that: It includes a capacitor charging circuit, a surge current circuit, a driving circuit and a three-terminal resistance detection unit; the capacitors form the capacitor charging circuit and the surge current circuit respectively through a single-pole double-throw switch; The capacitor charging loop also includes a first voltage source and a resistor; the surge current loop also includes an inductor connected to the source and drain of the SiC MOSFET.

7. The circuit according to claim 6, characterized in that: After the capacitor is charged in the capacitor charging loop through the first voltage source, the capacitor charging loop is disconnected and the surge current loop is closed through the single-pole double-throw switch, so that the capacitor and the inductor construct a sinusoidal oscillation loop to generate a surge current from the source to the drain of the SiC MOSFET, and the surge current intensity is controlled by controlling the voltage of the first voltage source.

8. The circuit according to claim 7, characterized in that: The driving circuit includes a second voltage source and a first switch, and the source of the SiC MOSFET is connected to the gate of the SiC MOSFET via the first switch and the second voltage source in sequence.

9. The circuit according to claim 8, characterized in that: The three-terminal resistance detection unit is connected to the SiC MOSFET via a second switch, and is used to detect the gate-source resistance, drain-source resistance and gate-drain resistance of the SiC MOSFET.

10. A SiC MOSFET maximum surge current test and failure analysis device based on three-terminal resistance monitoring, characterized in that: Comprising a circuit as claimed in any one of claims 6 to 9.

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