Reduction of thermal warpage offset

Abstract

Methods and structures are provided for maintaining the integrity of a layer deposited on a semiconductor wafer by thermal cycling. Deposition of a second backside layer or cap having an internal stress opposite to that of the first backside layer may be used to reduce warpage offset of the wafer during thermal cycling. The first backside layer may have a tensile internal stress or a compressive internal stress. The second backside layer has an internal stress opposite the first backside layer. Each backside layer may be deposited by a backside deposition device.

Description

Related Applications

[0001] The PCT application form is filed concurrently with this specification as a part of this application. Each application to which this application claims the benefit or priority as identified in the concurrently filed PCT application form is incorporated herein by reference in its entirety and for all purposes. Background Art

[0002] In semiconductor processing, it may be desirable for a wafer to remain substantially flat. However, during normal operation, a wafer may experience wafer warpage. Wafer warpage may result in, for example, an electrostatic chuck failing to properly clamp, a wafer handler failing to hold, and pattern transfer issues during photolithography, among others. Processes have been developed to control wafer warpage by keeping the wafer flat within process tolerances. One process includes depositing a film on the back side of the wafer to counteract any stress that may cause the wafer to warp. While this stress from the deposited back side film may keep the wafer substantially flat, the additional back side material may cause the wafer to further deflect during normal wafer handling and may damage the wafer and / or cause wafer handling issues in subsequent processing operations. This article discusses improvements associated with improving the integrity of the wafer, reducing the likelihood of damage to the wafer, and reducing the risk of wafer handling issues during subsequent wafer processing.

[0003] The background description provided here is for the purpose of generally presenting the context of the present disclosure. The work of the presently designated inventors is neither explicitly nor implicitly admitted to be prior art against the present disclosure to the extent that it is described in this background section and in aspects of the specification that were not determined to be prior art at the time the application was filed. Summary of the invention

[0004] Aspects of the present disclosure relate to methods for processing substrates during electronic device manufacturing. Such methods are characterized by the following operations: (a) depositing one or more front side layers on the front side of the substrate, wherein the one or more front side layers induce warpage in the substrate; (b) depositing a first back side layer on the back side of the substrate, wherein the first back side layer reduces the warpage in the substrate, wherein the first back side layer and the one or more front side layers have a first type of internal stress; (c) depositing a second back side layer over the first back side layer, wherein the second back side layer has a second type of internal stress that is opposite to or neutral to the first type; and (d) after (c), exposing the substrate to a thermal treatment that increases the temperature of the substrate to at least about 600°C.

[0005] In some embodiments, at least one of the one or more front side layers comprises a hard mask. In some embodiments, the one or more front side layers comprises a stack of alternating layers (e.g., about 100 or more). As an example, the stack comprises alternating oxide layers and nitride or polysilicon layers.

[0006] In some cases, the warpage of the substrate is about 300 μm or more, or even about 400 μm or more. In some embodiments, the first type of internal stress is tensile stress and the second type of internal stress is compressive stress. In some cases, the first warpage magnitude produced by the first backside layer when not compensated is greater than the second warpage magnitude produced by the second backside layer when not compensated.

[0007] In certain embodiments, the first backside layer comprises silicon nitride. In certain embodiments, the first backside layer has a thickness of about 0.1 μm to about 5 μm. In certain embodiments, the second backside layer comprises silicon oxide. In certain embodiments, the second backside layer has a thickness of about 0.01 μm to about 1 μm.

[0008] In some applications, the thermal treatment process in (d) is an annealing process. In some applications, the thermal treatment in (d) includes depositing a hard mask on the front side of the substrate.

[0009] Another aspect of the present invention relates to a substrate having the following features: (a) one or more front side layers on the front side of the substrate; (b) a first back side layer on the back side of the substrate, wherein the first back side layer and the one or more front side layers have a first type of internal stress; and (c) a second back side layer above the first back side layer, wherein the second back side layer has a second type of internal stress that is opposite to or neutral to the internal stress.

[0010] In some embodiments, the substrate has a warp of about 300 μm or more or even about 400 μm or more if not compensated by the first backside layer from the one or more frontside layers.

[0011] In some embodiments, at least one of the one or more front side layers of the substrate is a hard mask. In some embodiments, the one or more front side layers include a stack of about 100 or more alternating layers (e.g., alternating oxide layers and nitride or polysilicon layers). In some embodiments, the first type of internal stress is tensile stress and the second type of internal stress is compressive stress. In some embodiments, the first warp amplitude produced by the first back side layer when uncompensated is greater than the second warp amplitude produced by the second back side layer when uncompensated.

[0012] In certain embodiments, the first backside layer of the substrate comprises silicon nitride. In certain embodiments, the first backside layer has a thickness of about 0.1 μm to about 5 μm. In certain embodiments, the second backside layer of the substrate comprises silicon oxide. In certain embodiments, the second backside layer has a thickness of about 0.01 μm to about 1 μm.

[0013] Other aspects of the present disclosure relate to an apparatus for semiconductor processing. Such an apparatus may have the following features: (a) a processing chamber; (b) a substrate support within the processing chamber; (c) a showerhead; (d) a gas source fluidically connected to the showerhead; and (e) a controller. The controller may be configured (e.g., designed or programmed) to cause: (i) receiving a substrate comprising one or more front side layers, the front side layers causing warpage in the substrate; (ii) depositing a first back side layer on the back side of the substrate, the first back side layer reducing the warpage in the substrate, wherein the first back side layer and the one or more front side layers have a first type of internal stress; and (iii) depositing a second back side layer over the first back side layer, wherein the second back side layer has a neutral internal stress or a second type of internal stress opposite to the first type of internal stress.

[0014] In certain embodiments, the warp in the received substrate is about 300 μm or greater or about 400 μm or greater.In certain embodiments, the first backside layer and the second backside layer of the received substrate are deposited by plasma enhanced chemical vapor deposition.

[0015] In some embodiments, at least one of the one or more front side layers or the received substrate is a hard mask. In some embodiments, the one or more front side layers of the received substrate include a stack of about 100 or more alternating layers. As an example, the stack includes alternating oxide layers and nitride or polysilicon layers.

[0016] In some embodiments, the first type of internal stress is tensile stress and the second type of internal stress is compressive stress. In an application, the first backside layer of the received substrate when uncompensated will produce a first warp magnitude greater than the second backside layer when uncompensated will produce a second warp magnitude.

[0017] In certain embodiments, the first backside layer of the received substrate comprises silicon nitride. In certain embodiments, the first backside layer has a thickness of about 0.1 μm to about 5 μm. In certain embodiments, the second backside layer of the received substrate comprises silicon oxide. In certain embodiments, the second backside layer has a thickness of about 0.01 μm to about 1 μm.

[0018] These and other features of the present invention will be described throughout this disclosure, sometimes with reference to the related drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1A and 1B Examples of non-warped and warped semiconductor wafers on an electrostatic chuck are shown.

[0020] FIG. 2A to FIG. 2C An exemplary contour plot of wafer warpage is shown.

[0021] Figures 3A to 3D Cross-sectional views of an exemplary wafer before and after thermal cycling are shown.

[0022] Figures 4A to 4C An exemplary contour plot of wafer warpage is shown.

[0023] Figure 5A and 5B Cross-sectional views of an exemplary wafer before and after thermal cycling are shown.

[0024] Figure 6 is a process flow diagram illustrating certain operations in semiconductor wafer processing.

[0025] Figure 7 is a process flow diagram illustrating certain operations in semiconductor wafer processing.

[0026] Figure 8 An exemplary cross section of a semiconductor wafer during semiconductor processing is shown according to various embodiments.

[0027] Fig. 9 is a process flow diagram illustrating certain operations in semiconductor wafer processing.

[0028] Fig.10 is a process flow diagram illustrating certain operations in semiconductor wafer processing.

[0029] Fig.11A -C is an exemplary cross-sectional schematic diagram of a semiconductor wafer during semiconductor processing according to various embodiments.

[0030] Fig. 12A and 12B A block diagram of an exemplary substrate processing system is shown.

[0031] Fig.13A An exemplary cross section of the edge of the showerhead-base is shown.

[0032] Fig. 13B A top view of an example carrier ring is shown.

[0033] Fig.14 A schematic diagram of an example processing system that may be used to perform the methods described herein is shown. DETAILED DESCRIPTION the term

[0034] The following terms are used throughout this specification:

[0035] The terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially fabricated integrated circuit" may be used interchangeably. One of ordinary skill in the art will appreciate that the term "partially fabricated integrated circuit" may refer to a silicon wafer during any of many stages of integrated circuit fabrication thereon. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, or 300 mm, or 450 mm. Examples of wafer materials include silicon (Si), gallium arsenide (GaAs), and silicon germanium (SiGe). In addition to semiconductor wafers, other workpieces that may utilize the disclosed embodiments include various articles of manufacture, such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, display devices or components, such as backplanes for pixelated display devices, flat panel displays, micromechanical devices, and the like. The workpiece may have many shapes, sizes, and materials.

[0036] As used herein, "semiconductor device manufacturing operations" are operations performed during the manufacture of semiconductor devices. Typically, the entire manufacturing process includes multiple semiconductor device manufacturing operations, each of which is performed in its own unique semiconductor manufacturing tool, such as a plasma reactor, an electroplating tank, a chemical mechanical planarization tool, a wet etching tool, and the like. Categories of semiconductor device manufacturing operations include subtractive processes, such as etching processes and planarization processes, and additive processes, such as deposition processes (e.g., physical vapor deposition, chemical vapor deposition, atomic layer deposition, electrochemical deposition, electroless deposition). In the context of an etching process, a substrate etching process includes a process for etching a mask layer, or more generally includes a process for etching any material layer previously deposited on a substrate surface and / or otherwise left on a substrate surface. Such an etching process can etch a stack of layers in a substrate.

[0037] "Fabrication apparatus" refers to an apparatus in which a manufacturing process is performed. A fabrication apparatus typically has a processing chamber in which a workpiece resides during processing. Typically, when in use, a fabrication apparatus performs one or more semiconductor device fabrication operations. Examples of fabrication apparatus used for semiconductor device fabrication include deposition reactors, such as plating tanks, physical vapor deposition reactors, chemical vapor deposition reactors, and atomic layer deposition reactors, and subtractive process reactors, such as dry etch reactors (e.g., chemical and / or physical etch reactors, wet etch reactors, and ashers.

[0038] As used herein, "wafer warpage" may refer to deformation of a wafer. The deformation may have radial and / or azimuthal components. Examples of types of wafer warpage include a dome shape, a disk shape, and a potato chip shape. Wafer warpage may occur during manufacturing, for example, due to stress on the wafer during deposition of material on the active surface of the wafer substrate. Wafer warpage may occur during various types of manufacturing, such as when depositing a large amount of stack material. Wafer warpage may cause complications in subsequent processing steps. For example, if the amount of warpage is too great, the wafer may not be properly clamped. In addition, if some processing steps (e.g., photolithography) are performed on an overly warped wafer, poor results may be produced.

[0039] Wafer warpage can be measured as the deviation of the average or median distance of the wafer surface to a reference plane. The point of the mid-plane of the wafer can be the center point (e.g., in the case of concave or dome-shaped warpage), or the edge point of the wafer and / or the average edge point of the wafer (e.g., in the case of bow or convex warpage).

[0040] "Warp shift" refers to the change in the amount of wafer warpage during a semiconductor process. A wafer that has undergone a warp shift may retain a specific warp direction, such as a dome shape, a disk shape, etc., but change the magnitude of the warp. In some cases, the warp shift may change the direction of the warp, for example, the wafer may initially be dome-shaped, and after the warp shift occurs, the wafer may have a disk shape. Examples of semiconductor processes that may cause warp shift include material deposition, etching processes, and thermal treatments, such as annealing. Warp shift can be measured in a variety of ways. In some cases, the warp shift is described as a ratio of the final warp to the original wafer warp. The original warp can be set at any point in the process, but unless otherwise stated, the original warp used to measure the warp shift is the warp after the front side layers have been deposited but before any back side layers have been deposited.

[0041] "Thermal cycle" or "thermal process" refers to an operation that subjects a wafer to an elevated temperature for a period of time. Examples of device manufacturing operations that may include thermal cycling include thermal annealing, hard mask formation, material deposition, and etching. In the context of the present invention, thermal cycling is typically performed after the warp compensation backside layer has been deposited. The elevated temperatures experienced during the thermal cycle may be about 650° C. or higher or between about 650° C. and 1100° C. The duration of exposure to the elevated temperature may be any length of time. In some embodiments, the duration is at least about 50 seconds, or at least about 100 seconds, or at least about 200 seconds. Warped wafer

[0042] Semiconductor device manufacturing typically involves depositing a stack of layers on a wafer substrate. Typically, most deposition and other processing to form the device occurs on one side of the substrate, often referred to as the front side or front side of the wafer. As the deposited layers accumulate, they introduce stress into the wafer. Large net compressive or tensile stresses can cause the wafer to warp, which is undesirable.

[0043] Warping can be particularly likely when depositing large amounts of stack material, such as in the case of 3D-NAND devices. When warping is significant, it can have an adverse effect on subsequent processing steps. For example, if the warping is too large, the wafer may not be properly clamped. Figure 1A and 1B A wafer on an electrostatic chuck is shown. Figure 1A Wafer 102 is shown with electrostatic chuck 110. When wafer 102 is substantially flat for the purpose of a particular process operation, for example, having a warp of about 100 um or less, then the wafer may be properly clamped, thereby securing the wafer for subsequent processing steps. Figure 1B A warped wafer 104 is shown on an electrostatic chuck 110. When the warp is significant, the wafer may not be properly secured to the electrostatic chuck. Wafer warpage may cause other problems. For example, certain processing steps (e.g., photolithography) are very precise and produce poor results if the wafer is not substantially flat. This problem may manifest as photolithography defocus.

[0044] An exemplary stack that may cause these problems is a stack having alternating oxide layers and nitride layers (e.g., silicon oxide / silicon nitride / silicon oxide / silicon nitride, etc.). Another example of a type of stack that may cause warpage includes alternating oxide layers and polysilicon layers (e.g., silicon oxide / polysilicon / silicon oxide / polysilicon, etc.). Other examples of potentially problematic stack materials include, but are not limited to, tungsten and titanium nitride.

[0045] The materials in the stack may be deposited by chemical vapor deposition (CVD) techniques, such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), or by direct metal deposition (DMD), etc. These examples are not intended to be limiting. Certain disclosed embodiments may be useful whenever wafer stress and / or warpage is caused by the presence of materials on the front side of the wafer.

[0046] The front side stack can be deposited to any number of layers and thicknesses. In a typical example, the stack includes between about 32-72 layers and has a total thickness of about 2 μm to about 4 μm. The stress caused by the stack in the wafer may be about -500 MPa to about +500 MPa, resulting in a warpage of about 200 μm to about 400 μm (for 300 mm wafers) and even greater in some cases. However, modern IC manufacturing technology may produce substrates with front side layers with much higher internal stress than existing nodes. The front side may have a larger stack, for example, the stack may be more than 1000 layers. In another example, the reduced etching selectivity causes the mask to be thicker. These stacks may have a thickness of about 4 μm to 12 μm.

[0047] A variety of techniques have been designed to combat warpage. When warpage is more severe, the deposition process can be adjusted to reduce or offset the internal stress in the deposited layer. However, any such adjustments should not interfere with the process requirements of the manufacturing equipment. A commonly used technique to counteract warpage is to deposit a film on the back side of the wafer.

[0048] Backside deposition can form a high stress film. If the backside layer has the same type of internal stress (tensile or compressive) as the internal stress generated on the front side and is comparable in magnitude, the backside film effectively counteracts and corrects the warpage.

[0049] Examples of backside films used to counteract warpage include the following: amorphous silicon, silicon oxide, silicon nitride, and silicon oxynitride. Current backside films have high internal stress and can relieve the stress exerted on the wafer by the front side layer, thereby reducing or eliminating wafer warpage. Generally speaking, the backside layer is made of a film with high stress.

[0050] Until relatively recently, the backside film thickness was relatively thin (e.g., <2um) because the warpage caused by depositing materials on the front side was relatively modest. Therefore, downstream processes at prior art nodes generally do not encounter the problems that the embodiments herein are intended to solve. However, modern IC manufacturing techniques may produce substrates with more severe warpage of the front side layers than prior art nodes. For example, some modern processes have limited etch selectivity between the hard mask and the etched material but still use thick hard mask layers in operations that etch deep trenches or vias. In another example, the front side stack has increased in number of layers. For example, in prior art nodes, the stack may be about 32 to about 72 layers. Today, the stack may have hundreds or even thousands of layers, increasing the thickness and internal stress of the front side layers.

[0051] As the magnitude of wafer warpage increases, a thicker backside film must be deposited to compensate for the wafer warpage. This leads to certain problems. For example, when the wafer undergoes subsequent thermal cycles, the wafer warpage compensation layer on the backside may experience significant warpage excursions. For thicker backside layers, the warpage excursions during thermal cycling may be larger. For example, the warpage excursion may be about 30% or even up to about 60% of the original warpage. Due to such large warpage excursions, cracks may occur in the deposited layers on the wafer. Moreover, even if cracks are not caused, the warpage excursion may cause new warpage in the wafer, hindering downstream processing.

[0052] Figures 2A-2C Contour graphs of wafer warpage 202 after different processing events are shown. These graphs illustrate the challenges of warpage excursions during processing. Figure 2A FIG. 2 shows the warpage of a wafer after one or more front side layers have been deposited. The front side layers have internal stresses, such as tensile internal stresses or compressive internal stresses. The internal stresses cause the wafer to warp, such as Figure 2A In the example shown, the wafer warp 201 is dome-shaped.

[0053] Figure 2B The wafer is shown after the backside layer is deposited onto the wafer. In the illustrated embodiment, the backside layer has the same type of internal stress as the internal stress of the frontside layer, for example, if the frontside layer has tensile internal stress, then the backside layer also has tensile internal stress. By having the same type of internal stress, wafer warpage 201 is reduced or eliminated. In the embodiment shown, the backside layer has the same type of internal stress as the frontside layer, for example, if the frontside layer has tensile internal stress, then the backside layer also has tensile internal stress. By having the same type of internal stress, wafer warpage 201 is reduced or eliminated. Figure 2B In the ideal case shown, in preparation for the subsequent warpage shift, the backside layer is thick enough that the warpage direction changes, causing the wafer to move from Figure 2A The dome shape in Figure 2B In the depicted example, the magnitude of the warping from the backside layers is slightly greater than the warping from the frontside layers. Therefore, in some cases, such as Figure 2B As depicted in , the backside layers overcompensate for the warpage caused by the frontside layers. This is probably due to the expected effects of subsequent thermal cycling.

[0054] Figure 2C 2 shows a wafer 202 after undergoing a thermal cycle (e.g., annealing). The thermal cycle causes a warpage shift in the wafer 202. As shown, Figure 2B The wafer in has a disk-shaped warpage, and after the annealing process, as Figure 2C As shown, the wafer is substantially flat. In some embodiments, discussed in more detail below, warpage excursions during thermal cycling may cause cracking of the front-side layer, the back-side layer, or both the front-side layer and the back-side layer.

[0055] Figures 3A to 3DTwo different warped wafers (wafer 202 and wafer 302) are shown before and after thermal cycling. Each figure shows a small section of the wafer and a profile of the entire wafer. The profiles are indicated by reference numerals 205 and 305. Figure 3A and 3B As shown, the wafer 202 has a main structure 203 (e.g., a single crystal silicon substrate), a front side layer 204, and a back side layer 206. Similarly, as shown in FIG. Figure 3C and 3D As shown, wafer 302 has a main structure 303 (eg, a single crystal silicon substrate), a front side layer 304 , and a back side layer 306 .

[0056] Figure 3A and 3B FIG. 4 shows a wafer 202 in which the front side layer 204 has a moderate effect on the warpage (eg, the front side layer 204 is relatively thin), while FIG. Figure 3C and 3D Wafer 302 is shown with front side layers 304 having a more pronounced warpage effect. Figure 3A and Figure 3C 2 and 302 before thermal cycling. As shown in the contour plot 205, the wafer 202 with the thinner front side layer 204 is warped ( Figure 3A ) is not as warped as the wafer 302 having a thicker front side layer ( Figure 3C )obvious.

[0057] When the wafer 302 undergoes thermal cycling, the wafer may experience warpage excursions. Figure 3B As shown in the profile graph 205 of FIG. 2 , the warpage of the wafer 202 is reduced. The warpage excursion may exert additional stress on each of the wafer 202, the front-side layer 204, and the back-side layer 206. If the warpage excursion is below a defined threshold or tolerance for a particular process (e.g., about 100 μm or less), the warpage may be manageable (e.g., the wafer can be handled without any problems), and the wafer 202, the front-side layer, the back-side layer 204, and the back-side layer 206 may remain intact without any cracks, as shown in FIG. Figure 3B shown.

[0058] Figure 3C and 3D Shown with Figure 3A and 3B The wafer in FIG. 300 has a more pronounced warpage than the wafer 302 having the front side layer 304 (eg, the front side layer 304 is relatively thick). In the example shown, Figure 3C The warpage of the wafer 302 is greater than Figure 3A The warpage of the wafer 202 in FIG.

[0059] like Figure 3DAs shown in the example in , when the wafer 302 undergoes thermal cycling, the wafer may experience significant warpage excursions. In this example, the wafer experiences relatively large warpage excursions, such as about 40 μm or greater. The warpage excursions caused by thermal cycling may cause one of the layers to crack, damage the wafer 302 and / or introduce wafer handling problems in subsequent process operations. In the example shown, the backside layer 306 has cracks inside. In particular, when the tensile backside layer has a warpage value above a certain threshold, thermal cycling may cause cracks in the tensile backside layer. In some cases, no cracks are observed in the compressive or neutral backside layers.

[0060] Disclosed herein are methods, systems, and techniques for maintaining the integrity of each deposited layer (particularly backside layers) on a wafer during thermal cycling. In particular, a wafer may have a second backside layer deposited on a first backside layer. By selecting the properties of the second backside layer, such as the type of internal stress (e.g., compressive or neutral versus tensile) and thickness, the second backside layer can reduce the warpage offset during thermal cycling and reduce the likelihood of cracks forming on the deposited layer. The second backside layer is sometimes referred to herein as a "cap." A cap is a backside layer deposited on another backside layer that has an internal stress opposite to that of the previous backside layer. The cap can reduce the warpage offset of the wafer during thermal cycling and reduce the likelihood of layer cracking that may occur due to the warpage offset.

[0061] The first backside layer deposited is used to offset the wafer warpage caused by the frontside layer deposited on the wafer. When the frontside layer has tensile internal stress, the first backside layer may also have tensile internal stress. Similarly, when the frontside layer has compressive internal stress, the first backside layer may also have compressive internal stress. The second backside layer or cap is deposited on the first backside layer and has a stress that offsets the stress of the first backside layer. Since both layers are located on the same side (backside) of the wafer, these layers are of opposite types. For example, when the first backside layer is a tensile layer, the second backside layer is a compressive layer. In some embodiments, the magnitude of the internal stress of the second backside layer is less than the magnitude of the internal stress of the first backside layer. For example, the magnitude of the internal stress of the second backside layer may be about 20% or less of the magnitude of the internal stress of the first backside layer. In some embodiments, the magnitude of the warpage caused by the second backside layer is less than the magnitude of the warpage caused by the first backside layer. By having the first backside layer and the second backside layer have opposite internal stress types, the wafer experiences a smaller warpage excursion during thermal cycling, thereby reducing the possibility of cracking of any layer. In some embodiments, the cover or second backside layer has a neutral internal stress: that is, the internal stress is neither tensile nor compressive.

[0062] Figures 4A-4C A profile diagram of the warpage 401 of a wafer having a second backside layer after different processing events is shown. Figure 4AWafer warpage 401 is shown after the front side layers (not shown) have been deposited. The front side layers have internal stresses that cause the wafer to warp.

[0063] Figure 4B Wafer warpage 401 is shown after two backside layers (not shown) (a first backside layer and a second backside layer) are deposited onto the wafer. The first backside layer is deposited closer to the wafer and has the same type of internal stress as the internal stress of the front side layer. The second backside layer is deposited on the first backside layer and has the opposite type of internal stress as the front side layer. For example, if the front side layer has tensile internal stress, the first backside layer has tensile internal stress and the second backside layer has compressive internal stress. The first backside layer counteracts the wafer warpage caused by the front side layer. The second backside layer may increase the wafer warpage caused by the front side layer. Each backside layer can be selected so that the wafer warpage 401 is minimized. As shown in FIG. Figure 4B As shown, the backside layers are selected so that after deposition of each layer, the wafer warpage 401 is substantially flat.

[0064] Figure 4C The wafer warpage 401 after exposure to thermal cycling is shown. Figure 2C As shown in , thermal cycling causes a warpage shift in the wafer 4. However, by adding a second backside layer having an internal stress that counteracts the stress induced by the first backside layer, the warpage shift is reduced. In some cases, such as Figure 4C As shown in the example of , there is no warpage offset. Therefore, after the wafer undergoes thermal cycling, the wafer warpage 401 remains substantially flat.

[0065] Figure 5A and 5B Wafer 502 is shown before and after thermal cycling. Wafer 502 has a main structure 503 (e.g., a single crystal silicon substrate), a front side layer 504, a first back side layer 506, and a second back side layer 508. Each figure shows a cross section of a small portion of wafer 502 and an outline view of wafer 502. The outline view is indicated by reference numeral 505.

[0066] Figure 5A and 5B The front side layer 504 and Figure 3C and 3D 5, however, the wafer 502 has two backside layers, a first backside layer 506 and a second backside layer 508 (cap). Similar to Figures 4A to 4CIn the examples, the front side layer 504 has a first type of internal stress (tensile or compressive), the first back side layer 506 has the same type of internal stress, and the second back side layer 508 has an internal stress opposite to the first type of internal stress. In the first example, the front side layer 504 has a tensile internal stress, the first back side layer 506 has a tensile internal stress, and the second back side 508 has a compressive internal stress. In the second example, the front side layer 504 has a compressive internal stress, the first back side layer 506 has a compressive internal stress, and the second back side 508 has a tensile internal stress.

[0067] Figure 5B Wafer 502 is shown after thermal cycling. As shown in profile plot 505, there is no warpage shift after thermal cycling. In some embodiments, thermal cycling may cause minimal warpage shift, such as about 10 μm or less. Although there is more significant warpage caused by the front side layers, similar to Figure 3C and 3D 304 in the wafer 504, but not the front side layer 504, the first back side layer 506 or the second back side layer 508. By making the two back side layers each have an opposite type of stress compared to the other, for the wafer 5 with a thick front side layer, the warpage excursion can be reduced during thermal cycling, thereby reducing the occurrence of cracking on any layer.

[0068] As described above, wafer warpage may be caused by front-side processing. In some embodiments, the front-side processing may deposit a material or material stack with internal stress (compressive stress or tensile stress). The material stack may be a multilayer stack. In some embodiments, the multilayer stack may have about 100 layers or more. In some embodiments, the multilayer stack may have about 500 layers or more. In some embodiments, the multilayer stack may have about 1000 layers or more. The internal stress of the deposited material or material stack may have a size of 0 MPa to about 500 MPa. The stress may be tensile stress or compressive stress. The stress may cause significant wafer warpage. For example, the wafer may have a wafer warpage of about 150 μm or more (e.g., about 300 μm or more, about 400 μm or more). An exemplary stack that may cause these problems is a stack having alternating oxide layers and nitride layers (e.g., silicon oxide / silicon nitride / silicon oxide / silicon nitride, etc.). Another example of a type of stack that may cause warping includes alternating oxide layers and polysilicon layers (e.g., silicon oxide / polysilicon / silicon oxide / polysilicon, etc.). Other examples of stack materials that may be problematic include, but are not limited to, tungsten and titanium nitride. The materials in the stack may be deposited by chemical vapor deposition techniques, such as PECVD, LPCVD, MOCVD, ALD, PEALD, or DMD, etc. These examples are not intended to be limiting.

[0069] Another cause of wafer warpage may be front side processing using a thick hard mask with limited etch selectivity. In these embodiments, at least one of the one or more front side layers is a hard mask. The thick hard mask may have internal stresses similar to those described above, for example, having a magnitude of 0 MPa to about 500 MPa. The stress induced by the hard mask may be tensile stress or compressive stress. The thick hard mask may cause the wafer to have significant wafer warpage, for example, about 150 μm or more.

[0070] The backside layer thickness is generally proportional to the wafer warpage. Larger wafer warpage values ​​require thicker backside compensation layers. Wafers with wafer warpage of about 300 μm or greater (e.g., about 400 μm or greater) may require a backside film that is so thick that it may be susceptible to cracking. The backside film may have an internal stress that can offset the internal stress from the frontside layer. The backside film may be deposited using CVD, PECVD, ALD, PEALD, or epitaxial growth processes. The backside film may be deposited in a backside deposition apparatus.

[0071] To counteract wafer warpage caused by the front side layer having internal tensile forces, a stretch film may be used for the backside film. The stretch film may be formed using specific materials and / or processing conditions. Exemplary materials for making the stretch film include silicon nitride (SiN), silicon oxynitride, and polymer layers. The stretch film may be deposited using CVD or PECVD techniques.

[0072] To counteract wafer warpage caused by the front layer having internal compressive forces, a compression film can be used for the back film. The compression film can be formed using specific materials and / or processing conditions. Exemplary materials for making the compression film include silicon oxide (SiO x ), silicon nitride, aluminum oxide, aluminum nitride and polysilicon. Compressive films can be deposited using CVD or PECVD techniques.

[0073] As explained, during wafer processing, the wafer may be subjected to thermal cycling. Thermal cycling subjects the wafer to elevated temperatures. It may be caused by any of a variety of process operations. Thermal cycling may cause a warpage excursion in the wafer. In general, a wafer with a large warpage may experience a relatively large warpage excursion. A large warpage excursion may increase the probability of cracking of a deposited layer (e.g., a backside layer) on the wafer. An example of a thermal cycle is annealing of the wafer. Another example of a thermal cycle is depositing a material such as a hard mask on the front side of the wafer. For example, when deposition is performed at a temperature above about 650° C. or above about 850° C., a thermal cycle may result. In another example, thermal annealing may subject the wafer to a thermal cycle, such as at a temperature up to about 1100° C.

[0074] Figure 6 A first example process utilizing deposition of a first backside layer having a cap is shown. Figure 6Beginning in operation 610, one or more front side layers having a first type of internal stress (tensile or compressive) are deposited on a wafer. The internal stress from the front side layer may cause the wafer to warp. In some embodiments, the front side layer may have tensile internal stress. In some embodiments, the front side layer may have compressive internal stress. In some embodiments, the wafer warps by about 300 μm or more, such as about 400 μm or more.

[0075] Once the front side layer is deposited onto the wafer, a first back side layer having a first type of internal stress is deposited onto the wafer in operation 620. In other words, the internal stress of the back side layer is the same type of internal stress as the front side layer deposited in operation 610. For example, if the front side layer deposited in operation 610 has a tensile internal stress, the first back side layer deposited also has a tensile internal stress. In another example, if the front side layer deposited in operation 610 has a compressive internal stress, the first back side layer deposited also has a compressive internal stress. In some embodiments, the magnitude of the internal stress of the first back side layer deposited may be approximately the same as the magnitude of the internal stress of the deposited front side layer. In some embodiments, the magnitude of the internal stress of the first back side layer deposited may be greater than the magnitude of the internal stress deposited on the back side layer. By depositing a back side layer having an internal stress equal to or greater than the internal stress of the front side layer, the back side layer counteracts the warpage that may be caused by the front side layer. The amount of warpage in the compensated wafer depends on the requirements of the process. Typically, the warpage compensation film can control the wafer warpage to a near overall neutral stress. In some embodiments, the warpage of the wafer is reduced such that the warpage of the wafer is about 200 μm or less. In some embodiments, the wafer may be substantially flat, i.e., the wafer has a warpage of about 150 μm or less. In some embodiments, the warpage of the wafer may change direction, for example, the warpage changes from a dome shape to a disk shape.

[0076] The first backside layer may be deposited using CVD, PECVD, ALD, epitaxy, PVD, or other deposition processes. The first backside layer may be deposited using a dedicated backside deposition apparatus. In some embodiments, the wafer switches chambers between operations 610 and 620. The backside deposition apparatus may be a deposition apparatus different from the apparatus used to deposit the one or more frontside layers.

[0077] In operation 630, a second backside layer or cap is deposited on the first backside layer. The second backside layer has a second type of internal stress. The second type of internal stress is different from the first type of internal stress in the front side layer and the first backside layer. For example, if the first type of stress is tensile stress, the second type of stress is compressive stress. In this example, both the front side layer and the first backside layer have tensile internal stress, while the second backside layer has compressive internal stress. In a second example, the first type of stress is compressive stress, so the second type of stress is tensile stress. In a second example, both the front side layer and the first backside layer have compressive internal stress, while the second backside layer has tensile internal stress. The magnitude of the warpage caused by the second backside layer may be less than the magnitude of the warpage caused by the first backside layer, for example, about 50% or less, about 30% or less, about 20% or less, or about 10% or less. The warpage caused by the second backside layer and the first backside layer may be the sum of the individual warpages caused. In some embodiments, the combined backside layer warpage magnitude may be about the same as the warpage magnitude of the one or more frontside layers. In some embodiments, the warpage contributions of all frontside layers and backside layers may be combined such that the total warpage of the wafer is minimal (i.e., less than 100 μm). For example, the frontside layer may cause a tensile warpage of about 400 μm, while the first backside layer may cause a tensile warpage of about 450 μm. In this example, the second backside layer may cause a compressive warpage of about 50 μm.

[0078] Note that referring to the warpage values ​​caused or contributed by each backside layer assumes that the other layers do not compensate for the warpage. For example, when referring to the magnitude of the warpage caused by the first backside layer, we assume that this is the warpage that would occur on the substrate if the other layers were not present (e.g., without the frontside layer). The magnitude of the warpage caused by a layer depends on the internal stress of the material in the layer and the thickness of the layer.

[0079] In some embodiments, the magnitude of the warpage value produced by the first backside layer may be greater than the magnitude of the warpage value produced by the one or more front side layers. In some embodiments, the magnitude of the warpage value produced by the first backside layer may be greater than the magnitude of the warpage value produced by the second backside layer.

[0080] return Figure 6 , the second backside layer can be deposited in the same apparatus used to deposit the first backside layer in operation 620. In some embodiments, the wafer can stay in the same station for the first backside deposition in operation 620 and the second backside deposition in operation 610.

[0081] In operation 640, the wafer is exposed to a thermal cycle. For example, the semiconductor substrate may be exposed to a temperature of about 650 to 1100° C. The thermal cycle may cause the wafer to experience a warp excursion. However, the second backside layer may minimize the amount of warp excursion experienced by the wafer. In some embodiments, the warp excursion after deposition of the second backside layer is less than about 50% or less than about 10% of the original wafer bow.

[0082] Figure 7 A second exemplary process using multiple backside layers to prevent layer cracking and / or other warpage related issues during thermal cycling is shown. Figure 7 Beginning in operation 710, one or more front-side layers having a first type of internal stress (tensile or compressive) are deposited on a wafer. The internal stress from the front-side layer causes the wafer to warp. As used herein, a first type of internal stress refers to an internal stress that can be tensile stress or compressive stress. A second type of internal stress refers to an internal stress that is not a tensile stress or a compressive stress of the first type of stress, for example, if the first type of internal stress is a tensile stress, the second type of stress is a compressive stress.

[0083] Once the front-side layer is deposited on the wafer, a first back-side layer having a first type of internal stress is deposited on the wafer in operation 720. The internal stress of the back-side layer is the same type of internal stress as the front-side layer deposited in operation 710. The internal stress of the first back-side layer counteracts the internal stress from the front-side layer and can help reduce wafer warpage.

[0084] In operation 730, a second backside layer is deposited on the first backside layer. The second backside layer has a second type of internal stress that is neutral or opposite to the internal stress of the front side layer and the first backside layer. As discussed above in operation 630, the second backside layer can act as a cap for the first backside layer. The second backside layer can help reduce the amount of warpage caused by thermal cycling and reduce the chance of any layer cracking.

[0085] In operation 740, a third backside layer is deposited onto the second backside layer. The third backside layer has a first type of internal stress. In other words, the third backside layer has a stress that is the same as the stress of the front side layer and the first backside layer but opposite to the stress of the second backside layer. Similar to the first backside layer, the internal stress of the third backside layer counteracts the stress introduced by the front side layer.

[0086] After depositing the third backside layer, an optional operation of depositing a fourth backside layer on the third backside layer may be performed in operation 750. The fourth backside layer has a second type of internal stress and may serve as a cap for the third backside layer. Similar to the second backside layer deposited in operation 730, the fourth backside layer may serve as a cap for the third backside layer and reduce the amount of warpage offset caused by thermal cycling and reduce the chance of any layer cracking. In some embodiments, this operation is not performed and the third backside layer is the outermost layer on the backside of the wafer.

[0087] In a first example, the first type of internal stress is tensile stress and the second type of internal stress is compressive stress. In this example, the front side layer, the first back side layer and the third back side layer have tensile internal stress, while the second back side layer and the fourth back side layer (if deposited) have compressive internal stress. For example, the first back side layer may have silicon nitride and the second back side layer may have silicon oxide. In this example, the third back side layer may also have silicon nitride and the fourth back side layer may have silicon oxide.

[0088] In a second example, the first type of internal stress is compressive stress, and the second type of internal stress is tensile stress. In this example, the front side layer, the first back side layer, and the third back side layer have compressive internal stress, while the second back side layer and the fourth back side layer (if deposited) have tensile internal stress. For example, the first back side layer may have silicon oxide, and the second back side layer may have silicon nitride. In this example, the third back side layer may also have silicon oxide, and the fourth back side layer may have silicon nitride.

[0089] The magnitude of the warpage caused by each layer can be controlled to control the overall warpage of the substrate. For example, the stress magnitude from the sum of the deposited backside layers can be equal to the stress magnitude of the frontside layers. When the net difference in the amount of warpage from the frontside layers and the amount of warpage from the deposited backside layers is relatively low (e.g., about 0 to 30% difference), the overall warpage of the wafer may be minimal or acceptable for further processing.

[0090] In each of the backside deposition operations 720-750, each deposition layer can be deposited by a backside deposition device. In some embodiments, the wafer can stay in the same chamber for operations 720-750. In some embodiments, the wafer can switch chambers between operations 710 and 720. The backside deposition device can be a deposition device different from the device used to deposit the one or more front side layers. For example, in operation 710, the wafer can be located in a first chamber for depositing the front side layer, and in operations 720-740, the wafer can be moved to a second chamber for depositing each backside layer.

[0091] In operation 760, the wafer is exposed to a thermal cycle similar to that described above. Figure 6 The thermal cycle described in operation 640 of . The thermal cycle may cause the wafer to experience a warpage shift. However, the second backside layer and the fourth backside layer (if deposited) may minimize the amount of warpage shift experienced by the wafer during the thermal cycle. In some embodiments, the warpage shift may be less than about 10% of the original warpage.

[0092] Figure 8 Shows the experience Figure 7802 after an exemplary process of the present invention. Wafer 802 has a main structure 803 (e.g., a single crystal silicon substrate). A front side layer 804 is deposited on the front side of the main structure 803. The front side layer 804 has a first type of internal stress. The first type of internal stress can be tensile internal stress or compressive internal stress. A first back side layer 806 is deposited on the back side of the main structure 803. The first back side layer 806 has a first type of internal stress, for example, the same internal stress as the front side layer. A second back side layer 808 is deposited on the first back side layer 806. The second back side layer 808 has a second type of internal stress. The second type of internal stress is tensile internal stress or compressive internal stress and is opposite to the first type of stress, for example, if the first type of stress is tensile internal stress, the second type of stress is compressive internal stress. The second back side layer 808 warps about 20% or less of the warpage of the first back side layer. A third back side layer 816 is deposited on the second back side layer 808. The third backside layer 816 has a first type of internal stress. The fourth backside layer 818 is deposited on the third backside layer 816. The second backside layer 818 has a second type of internal stress.

[0093] In the first example, the first type of stress is tensile internal stress, and the second type of stress is compressive internal stress. In this example, the front side layer 804, the first back side layer 806, and the third back side layer 816 have tensile internal stress. The second back side layer 808 and the fourth back side layer 8018 have compressive internal stress. In the second example, the first type of stress is compressive internal stress, and the second type of stress is tensile internal stress. In this example, the front side layer 804, the first back side layer 806, and the third back side layer 816 have compressive internal stress. The second back side layer 808 and the fourth back side layer 8018 have tensile internal stress.

[0094] As discussed above, the internal stress of the front side layer 804 may cause the wafer to warp. The internal stress of the back side layer may counteract the internal stress of the front side layer 804. In order to minimize the wafer warp, the internal stress of the back side layer may be approximately equal to the internal stress of the front side layer 804. Therefore, if the front side layer 804 has a tensile warp of about 400 μm, the back side layer may have a total tensile warp of about 400 μm. In the first example where the front side layer 804 has a warp of 400 μm, the first back side layer 806 and the third back side layer 816 may each have a tensile warp of about 250 μm, and the second back side layer 808 and the fourth back side layer 818 may each have a compressive warp of about 50 μm. The tensile warp of the first back side layer 806 and the second back side layer 808 has a tensile warp of about 500 MPa in total. The compressive warpage of the second backside layer 808 and the fourth backside layer 818 reduces the tensile warpage from the first backside layer 806 and the third backside layer 816. Therefore, the 500 μm tensile warpage is reduced by about 100 μm (compressive warpage from the second backside layer 808 and 50 μm compressive warpage from the fourth backside layer 818), leaving about 400 μm tensile warpage contributed by the backside layers. The 400 μm tensile internal warpage from the frontside layer 804 and the 400 μm tensile internal warpage from the backside layers can offset each other and minimize any potential wafer warpage.

[0095] Fig. 9 Another example process using multiple backside layers to prevent layer cracking during thermal cycling is shown. Fig. 9 One or more front-side layers having a first type of intrinsic stress (tensile or compressive) are deposited on a wafer beginning in operation 910. The intrinsic stress from the front-side layers may cause the wafer to warp.

[0096] Once the front-side layer is deposited on the wafer, a first back-side layer having a first type of internal stress is deposited on the wafer in operation 920. The internal stress of the first back-side layer is the same type of internal stress as the front-side layer deposited in operation 910. The internal stress of the first back-side layer can be used to offset the internal stress of the front-side layer deposited in operation 910.

[0097] In operation 930, a second backside layer is deposited on the first backside layer. The second backside layer has a second type of internal stress that is opposite to the internal stress of the front side layer and the first backside layer. Similar to the above discussion, the second backside layer can act as a cap for the first backside layer. The second backside layer can help reduce the amount of warpage caused by thermal cycling and reduce the chance of any layer cracking.

[0098] In operation 940, a wafer having one or more front side layers, a first back side layer, and a second back side layer is exposed to a thermal cycle. The thermal cycle may cause the wafer to experience a warpage shift. However, the second back side layer may minimize the warpage shift experienced by the wafer. In some embodiments, the warpage shift may be less than about 20% of the original warpage.

[0099] In operation 950, a second front side layer is deposited on the initial front side layer. The second front side layer may have a first type of internal stress or a second type of internal stress. The internal stress from the second front side layer may cause the wafer to warp.

[0100] In operation 960, a third backside layer is deposited on the second backside layer. The third backside layer has the same type of internal stress as the second frontside layer deposited in this prior operation. For example, if the second frontside layer has a first type of internal stress, the third backside layer has the first type of internal stress. The third backside layer counteracts the warping caused by the second frontside layer.

[0101] In operation 970, a fourth backside layer is optionally deposited onto the third backside layer. The fourth backside layer has an internal stress that is different from the internal stress of the third backside layer. For example, if the second front side layer and the third backside layer have a first type of internal stress, the fourth backside layer has a second type of internal stress. In one example, if the front side layer has a tensile internal stress, the third backside layer has a tensile internal stress. In this example, the fourth backside layer will have a compressive internal stress.

[0102] The wafer is exposed to a thermal cycle in operation 980. The thermal cycle may cause the wafer to experience a warpage excursion. The fourth backside layer may minimize the amount of warpage excursion experienced by the wafer, thereby reducing the chance of cracking of deposited layers on the wafer due to the thermal cycle.

[0103] Fig.10 Another exemplary process using multiple backside layers to prevent layer cracking during thermal cycling is shown. Fig.10 One or more front-side layers having a first type of intrinsic stress (tensile or compressive) are deposited on a wafer beginning in operation 910, similar to that described above in operation 610. The intrinsic stress from the front-side layers may cause the wafer to warp.

[0104] Once the front-side layer is deposited on the wafer, a first back-side layer having a first type of internal stress is deposited on the wafer in operation 1020. The internal stress of the first back-side layer is the same type of internal stress as the front-side layer deposited in operation 1010. The internal stress of the first back-side layer can be used to offset the internal stress of the front-side layer deposited in operation 1010.

[0105] In operation 1030, a second backside layer is deposited on the first backside layer. The second backside layer has a second type of internal stress that is neutral or opposite to the internal stress of the front side layer and the first backside layer. Similar to the above discussion, the second backside layer can act as a cap for the first backside layer. The second backside layer can help reduce the amount of warpage caused by thermal cycling and reduce the chance of any layer cracking.

[0106] In operation 1040, the wafer is exposed to a thermal cycle. The thermal cycle may cause the wafer to experience a warpage shift. However, the second backside layer may minimize the amount of warpage shift experienced by the wafer. In some embodiments, the warpage shift may be less than 20% of the original warpage.

[0107] In operation 1050, the second backside layer is removed. As shown, the second backside layer can be used to control the warpage offset during thermal cycling. Once the thermal cycle is completed, the second backside layer can be removed before further processing of the wafer. In some embodiments, the entire second backside layer is removed so that the exposed surface on the backside is the first backside layer deposited in operation 1020. In some embodiments, a portion of the backside layer is removed.

[0108] In operation 1060, a second front side layer is deposited on the initial front side layer. The second front side layer may have a first type of internal stress or a second type of internal stress. The internal stress from the second front side layer may cause the wafer to warp.

[0109] In operation 1070, a third backside layer is deposited on the first backside layer. The third backside has the same type of internal stress as the second frontside layer deposited in operation 1060. For example, if the second frontside layer has a first type of internal stress, the third backside layer has the first type of internal stress. The third backside layer counteracts the warping caused by the second frontside layer.

[0110] After depositing the third backside layer, an optional operation of depositing a fourth backside layer on the third backside layer may be performed in operation 1070. The fourth backside layer has an internal stress that is neutral or opposite to the internal stress deposited in operation 1060. For example, if the second front side layer and the third backside layer have a first type of internal stress, the fourth backside layer has a second type of internal stress. Similar to the second backside layer deposited in operation 1030, the fourth backside layer may act as a cap for the third backside layer and reduce the amount of warpage offset due to thermal cycling and reduce the chance of any layer cracking. In some embodiments, this operation is not performed and the third backside layer is the outermost layer on the backside of the wafer.

[0111] The wafer is exposed to a thermal cycle in operation 1080. The thermal cycle may cause the wafer to experience a warpage excursion. If a fourth backside layer is deposited, the fourth backside layer may minimize the amount of warpage excursion experienced by the wafer, thereby reducing the chance of cracking of the deposited layer on the wafer due to the thermal cycle.

[0112] Figures 11A-11C Shows the Fig.10 11. Example cross sections of wafer 1102 after different operations of the example process. Fig.11A A cross section of a wafer 1102 after depositing a second backside layer in operation 1030 is shown. The wafer 1102 has a main structure 1103 (e.g., a single crystal silicon substrate). A frontside layer 1104 is deposited on the front side of the main structure 1103. The frontside layer 1104 has a first type of internal stress. A first backside layer 1106 is deposited on the back side of the main structure 1103. The first backside layer 1106 has a first type of internal stress, such as the same internal stress as the frontside layer. A second backside layer 1108 is deposited on the first backside layer 1106. The second backside layer 1108 has a second type of internal stress. The second type of internal stress is neutral or opposite to the first type of stress, for example, if the first type of stress is a tensile internal stress, the second type of stress may be a compressive internal stress.

[0113] Fig. 11B Wafer 1102 is shown after at least a portion of the second backside layer is removed in operation 1050. In the illustrated embodiment, the removal Fig.11A After removing the second backside layer, the wafer 1102 has a main structure 1103 with a frontside layer 1104 and a first backside layer 1106. The remaining layers all have a first type of internal stress, which counteracts the internal stress of other layers, thereby reducing wafer warpage.

[0114] Fig. 11C Wafer 1102 is shown after a fourth backside layer is deposited in operation 1070. On frontside layer 1104 is second frontside layer 1114. Third backside layer 1116 is deposited on first backside layer 1106. Third backside layer 1116 has the same internal stress as second frontside layer 1114. Fourth backside layer 1118 is located on third backside layer 1116. Fourth backside layer has a neutral internal stress or an opposite internal stress to third backside layer 1116 and reduces warpage excursion during thermal cycling.

[0115] In the first example, the first type of stress is tensile internal stress, and the second type of stress is compressive internal stress. In this example, the front side layer 1104, the second front side layer 1114, the first back side layer 1106, and the third back side layer 1116 may have tensile internal stress. The fourth back side layer 1118 may have compressive internal stress. In the second example, the first type of stress is compressive internal stress, and the second type of stress is tensile internal stress. In this example, the front side layer 1104, the second front side layer 1114, the first back side layer 1106, and the third back side layer 1116 have compressive internal stress. The fourth back side layer 1118 has tensile internal stress. Device

[0116] Fig. 12A 1 is a block diagram of a substrate processing system 1200 for performing processing on a wafer 1202 (also referred to as a wafer) according to some embodiments. As shown, the substrate processing system may include a chamber 1234. A central column may be configured to support a pedestal while a top surface of the wafer 1202 is being processed (e.g., a film is being formed on the top surface of the wafer 1202 or on the back side of the wafer 1202). According to some embodiments disclosed herein, the pedestal may be referred to as a showerhead pedestal ("ShoPed") 1206. A showerhead 1236 may be disposed above the showerhead 1206.

[0117] In some embodiments, the showerhead 1236 can be electrically coupled to a power supply 1238 via a matching network 1240. The power supply 1238 can be controlled by a control module 1242, such as a controller. In some embodiments, power can be provided to the showerhead 1206 instead of the showerhead 1236. The control module 1242 can be configured to operate the substrate processing system 1232 by executing process inputs and controls for a particular process recipe. Depending on whether the top surface of the wafer 1202 is receiving a deposited film or whether the bottom surface of the wafer 1202 is receiving a deposited film, the controller module 1242 can set a number of operational inputs for the process recipe, such as power levels, timing parameters, process gases, mechanical movement of the wafer 1202, and / or the height of the wafer 1202 relative to the showerhead 1206.

[0118] In some embodiments, the center column may also include lift pins that are controlled by a lift pin controller. These lift pins may be used to lift the wafer 1202 from the nozzle holder 1206 to allow an end effector (not shown) to pick up the wafer and lower the wafer 1202 after the wafer 1202 is placed by the end effector. The end effector may also place the wafer 1202 over the spacer 1244. As will be described below, the spacer 1244 may be sized to provide a controlled separation of the wafer 1202 between the top surface of the nozzle 1236 (facing the wafer) and the top surface of the nozzle holder 1206 (facing the wafer).

[0119] In some embodiments, the substrate processing system 1232 can further include a first gas manifold 1246 connected to a first gas source 1248 (e.g., a gas chemical and / or an inert gas supplied from a facility). Depending on the process being performed above the top surface of the wafer 1202, the control module 1242 can control the delivery of the first gas source 1248 through the first gas manifold 1246. The selected gas can then flow into the showerhead 1236 and be distributed in the volume of space defined between the surface of the showerhead 1236 facing the wafer 1202 when the wafer is positioned above the susceptor.

[0120] In some embodiments, the substrate processing system 1232 can further include a second gas manifold 1250 connected to a second gas source 1252 (e.g., a gas chemical and / or an inert gas supplied from a facility). Depending on the process being performed above the bottom surface of the wafer 1202, the control module 1242 can control the delivery of the second gas source 1252 through the second gas manifold 1250. The selected gas can then flow into the showerhead 1236 and be distributed in the volume of space defined between the surface of the showerhead 1206 facing the lower surface or underside (backside) of the wafer 1202 when the wafer is placed over the spacer 1244. The spacer 1244 can provide separation that optimizes deposition on the lower surface of the wafer 1202 and reduces deposition above the top surface of the wafer 1202. In some embodiments, when the deposition target is the lower surface of wafer 1202, an inert gas may flow over the top surface of wafer 1202 via showerhead 1236, which may push reactant gas away from the top surface and enable reactant gas provided from showerhead 1206 to be directed to the lower surface of wafer 1202.

[0121] Further, the gases may be premixed or not. Appropriate valves and mass flow control mechanisms may be employed to ensure that the correct gases are delivered during the deposition and plasma treatment phases of the process. The process gases may exit the chamber 1234 via an outlet. A vacuum pump (e.g., a single or two-stage mechanical dry pump and / or a turbomolecular pump) may pump the process gases out and maintain an appropriate low pressure within the reactor through a closed loop flow restriction device (e.g., a throttle valve or a pendulum valve).

[0122] In some embodiments, the carrier ring 1254 may surround an outer region of the nozzle seat 1206. When the top surface of the wafer 1202 is being processed, for example, when a material is being deposited thereon, the carrier ring 1254 may be configured to be located above a carrier ring support area that is stepped downward from a wafer support area in the center of the nozzle seat 1206. The top surface of the carrier ring 1254 is generally coplanar with the top surface of the wafer 1202. The carrier ring 1254 may include an outer edge side (e.g., an outer radius) of its disk structure and a wafer edge side (e.g., an inner radius) of its disk structure that is closest to where the wafer 1202 is located. The carrier ring 1254 may be associated with an inner diameter (ID). The ID may extend to the inner periphery of the carrier ring and generally surround the substrate (e.g., wafer 1202) in the processing chamber. The wafer edge side of the carrier ring 1254 may also include a plurality of contact support structures or "tabs" that may be configured to elevate the wafer 1202 when the carrier ring 1254 is held by the spacer 1244. The carry ring 1254 may include a plurality of tabs, the number of which is selected from a range that supports the wafer 1202 during processing. Additional details regarding the tab embodiments are as follows.

[0123] Fig. 12B1 is a block diagram illustrating another substrate handling system 1232 for performing processing on a wafer 1202 according to some embodiments. In some embodiments, spoke forks 1256 may be used to elevate and maintain a carry ring 1254 at its process height, e.g., to allow deposition on the lower surface (backside) of the wafer 1202. Thus, the carry ring 1254 may be lifted along with the wafer 1202. In some implementations, the carry ring 1254 may be rotated to another station, e.g., in a multi-station system.

[0124] Broadly, embodiments disclosed herein are systems for depositing PECVD films on selected sides (front and / or back) of a wafer by dynamic control. Some embodiments may include dual gas flow electrodes for defining a capacitively coupled PECVD system. The system may include a gas flow showerhead (e.g., showerhead 1236) and a showerhead 126. In some embodiments, the gas flow base (i.e., showerhead) is a combination of a showerhead and a pedestal that performs deposition on the back side of the wafer. The electrode geometry combines features of the showerhead (e.g., gas mixing plenum, holes, hole patterns, anti-gas spray baffles) and features of the pedestal. Examples of pedestal features include embedded controlled heaters, wafer lifting mechanisms, the ability to hold a plasma suppression ring, and movability. This enables transfer of wafers and handling of gases to be performed with or without RF power from the pedestal.

[0125] In some embodiments, the system may have a wafer lift mechanism that tightly controls the parallelism of the substrate relative to the electrodes. In one example, this can be achieved by setting the lift mechanism (e.g., a spindle or lift pin mechanism) parallel to the two electrodes and controlling manufacturing tolerances. In another example, the lift can be achieved by raising the wafer lift component. This option may not allow for dynamic control of the side where deposition is performed.

[0126] In some configurations, the lift mechanism may allow for dynamic control of substrate position during processing (before plasma, during plasma, after plasma) to control the side of deposition, the profile of deposition, and deposited film properties. The system may further allow for selective activation / deactivation of the side of reactant flow. One side may flow reactants and the other side may flow inert gas to suppress deposition and plasma.

[0127] In some embodiments, the gap between the sides of the wafer where plasma / deposition is not desired can be strictly controlled. The distance can be controlled to suppress plasma. If the distance is not controlled, the wafer may be susceptible to plasma damage. For example, the system may allow a minimum gap of about 2 mm to about 0.5 mm, and in another embodiment about 1 mm to about 0.05 mm (limited by wafer warpage), and such a gap can be controlled. The gap can be controlled according to process conditions.

[0128] In some embodiments, the gas flow base (i.e., nozzle base) can achieve, but is not limited to: (a) thermal stabilization of the wafer to the processing temperature before processing; (b) selective design of the hole pattern on the nozzle base to selectively deposit films on different areas of the back side of the wafer; (c) replaceable rings can be attached to achieve appropriate plasma confinement and hole pattern; (d) stable wafer transfer mechanism within the chamber for transferring the wafer out to another chamber or wafer boat - such as lift pins, RF coupling features, minimum contact arrays; (e) implementation of gas mixing features, such as internal gas chambers, baffles, and manifold pipeline openings; and (f) providing compartments in the gas flow base (i.e., nozzle base) to enable selective gas flow to different areas of the back side of the wafer, and control the flow rate through flow controllers and / or multiple gas chambers.

[0129] In another embodiment, dynamic gap control using a wafer lift mechanism is achieved: (a) controlling the distance from the deposition or reactant flow electrode to the side or middle of the wafer where deposition is desired so that deposition can be performed on both sides; and (b) a lift mechanism for dynamically controlling the distance during the process (before plasma, during plasma, after plasma) to control the side of deposition, deposition profile, and deposited film properties. In another embodiment, for deposition modes used to deposit on the back side of the wafer, film edge exclusion control is highly desirable to avoid overlay issues associated with lithography. The lift mechanism used in this system is accomplished by a carrier ring 124 that has design features for shielding deposition on the edge. This specifies edge exclusion control through the design and shape of the carrier ring.

[0130] Fig.13A A cross-sectional view of an edge region of the nozzle seat 1206 is shown. This view provides a cross-sectional representation of the carrier ring 1254, which has a carrier ring inner radius 1254a and a carrier ring outer radius 1254b. In some embodiments, the carrier ring 1254 includes a support extension 1254c that extends below the substantially flat surface of the carrier ring 1254.

[0131] The support extension 1254c is configured to fit and be located within a support surface defined in the top surface of the spacer 1244. The support surface provides a complementary mating surface to the support extension 1254c, thereby preventing the carrier ring 1254 from sliding or moving when supported by the spacer 1244. Fig. 13B Three spacers 1244 are shown in FIG. 1 , but it is contemplated that any number of spacers may be provided so long as the carrier ring can be supported substantially parallel to the surface of the nozzle holder 1206 and the spacing is defined to support the wafer 1202 in a spaced relationship with the top surface of the pedestal 1206.

[0132] It is further shown that the top surface of the nozzle seat 1206 will include a hole pattern 1206a distributed across the surface to provide uniform distribution and output of gas during operation. In one embodiment, the hole pattern 1206a is distributed into a plurality of concentric rings starting at the center of the top surface of the nozzle seat 1206 and extending to the outer periphery of the nozzle seat 1206. At least one hole pattern 1206a is disposed at an edge hole region 1207 of the hole pattern, and the orifices defined in the edge hole region 1207 are preferably angled to provide gas non-perpendicular to the nozzle seat 1206 surface.

[0133] In one example, the angle or tilt of the orifices in the edge hole region 1207 is defined to be tilted or angled away from the center of the nozzle holder 106. In one embodiment, the angle is approximately 45° from horizontal. In other embodiments, the angle can vary from 20° from horizontal to approximately 80° from horizontal. In one embodiment, by providing angled orifices in the edge hole region 1207, additional distribution of process gases can be provided during deposition on the back side of the wafer 1202. In one embodiment, the remaining orifices 1206d of the hole pattern 1206a are oriented substantially perpendicular to the nozzle holder 106 surface and pointed toward the underside of the wafer 1202.

[0134] Fig. 13B It is shown that when the wafer 1202 is held by the carry ring 1254, the edge of the wafer 1202 will be located on an edge region closer to the carry ring inner radius 1254a of the carry ring 1254. When positioned using the spacer 1244, the surface of the showerhead 1236 facing the top surface of the wafer 1202 can be substantially close to prevent deposition during a mode in which deposition is performed on the back side of the wafer 1202.

[0135] For example, the distance between the top of the wafer 1202 and the surface of the showerhead 1236 is preferably between about 2 mm and about 0.5 mm, and in some embodiments about 1 mm to about 0.5 mm, depending on the wafer warpage. That is, if the wafer is significantly warped, the spacing will be about 0.5 mm or more. If the wafer has not been significantly warped, the spacing may be less than about 0.5 mm. In one embodiment, it is preferred that when a material layer is being deposited on the back side of the substrate, the spacing is minimized to prevent deposition on the top side of the substrate. In some embodiments, the showerhead 1236 is configured to supply an inert gas flow over the top side of the wafer 1202 during deposition on the back side of the substrate and supplying deposition gas through the showerhead 1206.

[0136] Any suitable chamber may be used to implement the disclosed embodiments. Exemplary deposition apparatus include various systems, such as the and Max, or any of a variety of other commercially available processing systems.

[0137] In some embodiments, the first deposition may be performed at a first station, which is one of two, five, or even more deposition stations located within a single deposition chamber. Thus, for example, hydrogen (H2) and tungsten hexafluoride (WF6) may be directed to the surface of the semiconductor substrate in alternating pulses at the first station using a separate gas supply system that creates a localized atmosphere at the substrate surface. Another station may be used for NF3 treatment, and a third and / or fourth station for subsequent ALD bulk fill.

[0138] Fig.14 Schematic diagram of a processing system suitable for performing a deposition process according to an embodiment. System 1400 includes a transfer module 1403. Transfer module 1403 provides a clean, pressurized environment to minimize the risk of contamination of the substrate being processed when it is moved between the various reactor modules. Mounted on transfer module 1403 is a multi-station reactor 1409 capable of performing ALD, treatment, and CVD according to various embodiments. Multi-station reactor 1409 may include a plurality of stations 1411, 1413, 1415, and 1417, which may perform operations sequentially according to the disclosed embodiments. For example, multi-station reactor 1409 may be configured such that station 1411 performs front side deposition using a precursor and a reducing agent, station 1413 performs ALD bulk deposition of a conformal layer using a reducing agent, station 1415 performs a NF3 treatment operation, and station 1417 may perform a bulk ALD fill after treatment using a reducing agent.

[0139] The station may include a heated pedestal or substrate support, one or more gas inlets or showerheads, or a distribution plate.

[0140] return Fig.14 , one or more single-station or multi-station modules 1407 capable of performing plasma or chemical (non-plasma) pre-cleaning, other deposition operations, or etching operations may also be mounted on the transfer module 1403. The modules may also be used for various processes, for example, to prepare substrates for deposition processes. The system 1400 also includes one or more wafer source modules 1401, where wafers are stored before and after processing. An atmospheric robot (not shown) in the atmospheric transfer chamber 1419 may first move the wafers from the source module 1401 to the load lock 1421. The wafer transfer device (typically a robot arm unit) in the transfer module 1403 moves the wafers from the load lock 1421 to the modules mounted on the transfer module 1403 and moves the wafers between these modules.

[0141] In various embodiments, a system controller 1442 is used to control process conditions during deposition. The controller 1442 will typically include one or more memory devices and one or more processors. The processor may include a CPU or computer, analog and / or digital input / output connections, a stepper motor controller board, etc.

[0142] The controller 1442 can control all activities of the deposition apparatus. The system controller 1442 runs system control software, which includes instruction sets for controlling timing, gas mixture, chamber pressure, chamber temperature, wafer temperature, radio frequency (RF) power level, wafer chuck or pedestal position, and other parameters of a particular process. In some embodiments, other computer programs stored on a memory device associated with the controller 1442 may be used.

[0143] Typically, there will be a user interface associated with the controller 1442. The user interface may include a display screen, a graphical software display of the device and / or process conditions, and a user input device such as a pointing device, keyboard, touch screen, microphone, or the like.

[0144] The system control logic may be configured in any suitable manner. In general, the logic may be designed or configured in hardware and / or software. The instructions for controlling the drive circuit may be hard-coded or provided as software. The instructions may be provided by "programming". Such programming is understood to include any form of logic including hard-coded logic in digital signal processors, application specific integrated circuits, and other devices having specific algorithms implemented as hardware. Programming is also understood to include software or firmware instructions that can be executed on a general purpose processor. The system control software may be encoded in any suitable computer readable programming language.

[0145] The computer program code for controlling the germanium-containing reducing agent pulses, hydrogen gas flow, and tungsten-containing precursor pulses and other processes in the process sequence can be written in any conventional computer-readable programming language: for example, assembly language, C, C++, Pascal, Fortran, or others. The compiled object code or script is executed by the processor to perform the tasks identified in the program. As also indicated, the program code can be hard-coded.

[0146] Controller parameters relate to process conditions such as, for example, process gas composition and flow rate, temperature, pressure, cooling gas pressure, substrate temperature and chamber wall temperature. These parameters are provided to the user in the form of a recipe and can be input using a user interface.

[0147] Signals for monitoring the process may be provided through analog and / or digital input connections of the system controller 1442. Signals for controlling the process may be output through analog and digital output connections of the apparatus 1400.

[0148] The system software may be designed or configured in different ways. For example, multiple chamber component subroutines or control objects may be written to control the operation of chamber components required to perform a deposition process according to the disclosed embodiments. Examples of programs or program segments for this purpose include substrate positioning code, process gas control code, pressure control code, and heater control code.

[0149] In some embodiments, the system controller 1442 is part of a system, which can be part of the above-described embodiments. Such a system includes a semiconductor processing device, which includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems can be integrated with electronic devices to control the operation of these systems before, during, or after the processing of semiconductor wafers or substrates. The electronic device can be referred to as a "controller" that can control various components or sub-parts of one or more systems. Depending on the processing requirements and / or the type of system, the system controller 1442 can be programmed to control any of the processes disclosed in the present invention, including controlling the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings in some systems, RF matching circuit settings, frequency settings, flow rate settings, plasma pulse frequency settings, fluid delivery settings, position and operation settings, wafer entry and exit tools and other delivery tools and / or delivery of load locks connected to a specific system or interfaced with the system.

[0150] Broadly speaking, a controller can be defined as an electronic device with various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, can perform cleaning operations, can perform endpoint measurements, etc. The integrated circuit may include a chip storing program instructions in the form of firmware, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions delivered to a controller or system in the form of various different settings (or program files), and different settings (or program files) define operating parameters for performing specific processes on or for semiconductor wafers. In some embodiments, the operating parameters may be a part of a recipe defined by a process engineer to complete one or more processing steps in the manufacturing process of one or more (kinds) layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or bare chips of a wafer.

[0151] In some embodiments, the system controller 1442 can be a part of or coupled to a computer that is integrated with the system, coupled, or connected to the system or a combination thereof through a network. For example, the system controller 1442 can be in the "cloud" or all or part of a wafer factory (fab) main computer system, which can allow remote access to wafer processing. The computer can enable remote access to the system to monitor the current progress of the manufacturing operation, check the history of past manufacturing operations, check the trends or performance standards of multiple manufacturing operations, change the parameters of the current processing, set the processing steps to follow the current processing or start a new process. In some embodiments, a remote computer (e.g., a server) can provide a process recipe to the system through a network, which can include a local network or the Internet. The remote computer can include a user interface that allows input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify the parameters of each processing step to be performed during one or more operations. It should be understood that these parameters can be for the type of process to be performed and the type of tool, and the controller is configured to connect or control the tool type. Thus, as described above, the controller may be distributed, for example, by including one or more discrete controllers that are networked together and work toward a common goal (e.g., the process and control described herein). An example of a distributed controller for these purposes would be one or more integrated circuits within the room that communicate with one or more remote integrated circuits (e.g., at the platform level or as part of a remote computer), which combine to control the process within the room.

[0152] Exemplary systems may include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, chamfer edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, CVD chambers or modules, ALD chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that may be associated with or used in the preparation and / or manufacture of semiconductor wafers.

[0153] As described above, depending on one or more process steps to be performed by the tool, the controller can communicate with one or more other tool circuits or modules, other tool components, combination tools, other tool interfaces, adjacent tools, adjacent tools, tools located throughout the factory, a host computer, another controller, or tools used in material handling to move containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing facility.

[0154] The system controller 1442 may include different programs. The substrate positioning program may include program code for controlling chamber components that are used to load the substrate onto a pedestal or chuck and control the spacing between the substrate and other components of the chamber, such as a gas inlet and / or a target. The process gas control program may include code for controlling gas composition, flow rate, pulse time, and optionally for flowing gas into the chamber to stabilize the pressure in the chamber before deposition. The pressure control program may include code for controlling the pressure in the chamber by adjusting, for example, a throttle valve in an exhaust system in the chamber. The heater control program may include code for controlling the current of a heating unit used to heat the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas, such as helium, to a wafer chuck.

[0155] Examples of chamber sensors that can be monitored during deposition include mass flow controllers, pressure sensors such as manometers, and thermocouples located in the pedestal or chuck. Appropriately programmed feedback and control algorithms can be used with data from these sensors to maintain desired process conditions.

[0156] The foregoing describes implementations of the present invention as implemented in a single-chamber or multi-chamber semiconductor processing tool. The apparatus and processes described herein can be used in conjunction with a lithography patterning tool or process, for example, to prepare or manufacture semiconductor devices, displays, LEDs, photovoltaic panels, etc. Typically, although not necessarily, these tools / processes will be used or operated together in a common manufacturing facility. Photolithographic patterning of films typically includes some or all of the following steps, each of which enables multiple available tools: (1) coating a workpiece, i.e., a substrate, with photoresist using a spin coating or spray coating tool; (2) curing the photoresist using a hot plate or oven or a UV curing tool; (3) exposing the photoresist to visible light or UV light or X-rays using a tool such as a wafer stepper; (4) developing the resist to selectively remove the resist and thereby pattern it using a tool such as a wet cleaning station; (5) transferring the resist pattern to an underlying film or workpiece by using a dry or plasma assisted etching tool; and (6) removing the resist using a tool such as a radio frequency or microwave plasma resist stripper. in conclusion

[0157] Although the above embodiments have been described in detail to a certain extent for the purpose of clear understanding, it is apparent that certain variations and modifications may be implemented within the scope of the appended claims. It should be noted that there are many alternatives to the processes, systems, and equipment of the embodiments of the present invention. Therefore, the embodiments of the present invention should be considered illustrative rather than restrictive, and these embodiments are not limited to the details given herein.

Claims

1. A method for processing a substrate during electronic device manufacturing, the method comprising: (a) depositing one or more front side layers on the front side of the substrate, wherein the one or more front side layers induce warpage in the substrate; (b) depositing a first backside layer on the backside of the substrate, wherein the first backside layer reduces the warpage in the substrate, wherein the first backside layer and the one or more frontside layers have a first type of intrinsic stress; (c) depositing a second backside layer over the first backside layer, wherein the second backside layer has a second type of internal stress that is opposite to or neutral to the first type; and (d) After (c), exposing the substrate to a thermal treatment that increases the temperature of the substrate to at least about 600°C. 2 . The method of claim 1 , wherein the warpage of the substrate is about 300 μm or more. The method of claim 1 , wherein the warpage of the substrate is about 400 μm or more. The method of claim 1 , wherein at least one of the one or more front-side layers comprises a hard mask.

5. The method of claim 1, wherein the one or more front-side layers comprise a stack of about 100 or more alternating layers. The method of claim 5 , wherein the stack comprises alternating oxide layers and nitride or polysilicon layers.

7. The method of claim 1, wherein the internal stress of the first type is a tensile stress and the internal stress of the second type is a compressive stress. 8 . The method of claim 1 , wherein a first warping amplitude generated by the first backside layer when not compensated is greater than a second warping amplitude generated by the second backside layer when not compensated.

9. The method of claim 1, wherein the first backside layer comprises silicon nitride. 10 . The method of claim 1 , wherein the first backside layer has a thickness of about 0.1 μm to about 5 μm. The method of claim 1 , wherein the second backside layer comprises silicon oxide. 12 . The method of claim 1 , wherein the second backside layer has a thickness of about 0.01 μm to about 1 μm.

13. The method according to claim 1, wherein the heat treatment in (d) is an annealing process.

14. The method of claim 1, wherein the thermal processing in (d) comprises depositing a hard mask on the front side of the substrate.

15. A substrate comprising: (a) one or more front-side layers on the front side of the substrate; (b) a first backside layer on the backside of the substrate, wherein the first backside layer and the one or more frontside layers have a first type of internal stress; as well as (c) a second backside layer over the first backside layer, wherein the second backside layer has a second type of internal stress that is opposite to or neutral to the internal stress.

16. An apparatus for semiconductor processing, the apparatus comprising: Processing room; a substrate support within the processing chamber; Sprinklers; a gas source in fluid connection with the showerhead; as well as A controller configured to cause: (i) receiving a substrate comprising one or more front-side layers, the front-side layers inducing warpage in the substrate; (ii) depositing a first backside layer on the backside of the substrate, the first backside layer reducing warpage in the substrate, wherein the first backside layer and the one or more frontside layers have a first type of intrinsic stress; as well as (iii) depositing a second backside layer over the first backside layer, wherein the second backside layer has a neutral internal stress or a second type of internal stress opposite to the first type of internal stress.

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