Power supply switching device, vehicle control device, and power supply switching method

Abstract

A power supply switching device according to one embodiment of the present invention is provided with a first semiconductor switch connected to a first power supply, a second semiconductor switch connected to a second power supply, and a switch control device for controlling the drive voltages of the first semiconductor switch and the second semiconductor switch. When one of the first power supply and the second power supply is switched to the other power supply, the switch control device sets an intermediate state in which the semiconductor switch connected to the power supply on the power supply side after switching is kept in an unsaturated state. The holding time of the intermediate state is changed according to the voltage difference between the voltages output by the first power supply and the second power supply.

Description

Technical Field

[0001] The present invention relates to a power switching device, a vehicle control device and a power switching method, and in particular to a technology for protecting a switching circuit of a power supply during power supply. Background Art

[0002] In recent years, with the development of electric vehicles and autonomous driving in automobiles, the electrification of existing components such as hydraulic and mechanical systems is developing. As a result, in the on-board power supply system, it is required to reduce the wiring harness used for power supply, and to make the power supply system highly reliable (redundant) and efficient. In the past, in the on-board power supply system, the power supply was controlled by mechanical switches such as relays and fuses, but in recent years, the application of power control systems using semiconductor switches has become widespread. Semiconductor switches have a faster switching speed than relays, and can avoid instantaneous power supply interruption when switching power sources. In addition, semiconductor switches do not have mechanical contacts, so they have higher durability and the restrictions on the number of switching times are greatly relaxed.

[0003] As prior art of power supply systems using such semiconductor switches, there are Patent Documents 1 and 2. Patent Document 1 discloses a protection technology for suppressing reverse flow of current from a second power supply to a first power supply without increasing the size and cost of a control circuit.

[0004] In addition, patent document 2 includes a first switch pair for selectively connecting a first power supply node to an output node, a second switch pair for selectively connecting a second power supply node to an output node, and a switch control circuit, and the switch control circuit operates so that only one of the first power supply node and the second power supply node is connected to the output node at any time. Prior art literature Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2022-061736 Patent Document 2: Japanese Patent Publication No. 2019-514328 Summary of the invention Technical problem to be solved by the invention

[0006] According to the technology described in Patent Document 1, the main power supply is cut off when the main power supply fails to prevent the current from flowing back from the auxiliary power supply to the main power supply. In this technology, the switching action is only performed when the main power supply fails, and the main power supply and the auxiliary power supply cannot be used for selective power supply during normal use.

[0007] According to the technology described in Patent Document 2, the first power supply and the second power supply can be selectively connected to the output node. However, this technology is configured so that only one of the first power supply and the second power supply is connected to the output node, so a temporary power cut may occur when the power supply is switched. In addition, when the power supply voltages of the first power supply and the second power supply differ due to individual differences, degradation, etc. of the power supplies, an overcurrent flows through the semiconductor switch due to the surge current and discharge current during switching, and the semiconductor switch may be damaged. In addition, the surge current during switching varies according to the current capacity of the connected load, so it is usually necessary to estimate the maximum current under the worst condition that all connected loads are in an operating state, and it is necessary to select a semiconductor switch that meets this condition. Therefore, the cost of the semiconductor switch increases.

[0008] In view of the above circumstances, a method is required for suppressing damage to a semiconductor switch even when there is a difference in output voltage between a first power source and a second power source. Technical means for solving technical problems

[0009] In order to solve the above-mentioned problem, a power switching device of one embodiment of the present invention includes: a first semiconductor switch arranged between a first power supply source for supplying power to a load device and the load device; a second semiconductor switch arranged between a second power supply source for supplying power to the load device and the load device; and a switch control device for controlling the driving voltage of the first semiconductor switch and the second semiconductor switch. When switching from one power supply to the other between the first power supply and the second power supply, the switch control device is configured to maintain the semiconductor switch of the power supply connected to the power supply side after switching in an intermediate state of a non-saturated state, and to change the holding time of the intermediate state according to the voltage difference between the voltages output by the first power supply and the second power supply. Effects of the Invention

[0010] According to at least one embodiment of the present invention, the holding time of the intermediate state of the semiconductor switch of the power supply source connected to the power supply side after switching is changed according to the difference in output voltage output by the first power supply and the second power supply. Thus, even when there is a difference in output voltage between the first power supply and the second power supply, damage to the semiconductor switch caused by overcurrent can be suppressed. Technical problems, structures and effects other than those described above will be further clarified through the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 1 is a schematic diagram showing an example in which a plurality of power supplies are connected to a vehicle control device mounted on a vehicle. Figure 2 This is a diagram showing a configuration example of a power supply switching device according to Embodiment 1 of the present invention. Figure 3 This is a diagram showing an operation example of the power supply switching device according to the first embodiment of the present invention. Figure 4 This is a diagram showing a configuration example of a power supply switching device according to Embodiment 2 of the present invention. Figure 5 This is a diagram for explaining a method of estimating an inrush current during power supply switching using load information in a power supply switching device according to Embodiment 2 of the present invention. Figure 6 This is a diagram showing an operation example of the power supply switching device according to the second embodiment of the present invention. Figure 7 This is a diagram showing a configuration example of a power supply switching device according to Embodiment 3 of the present invention. Figure 8 This is a diagram showing a configuration example of a power supply switching device according to a fourth embodiment of the present invention. Fig. 9 It is a diagram showing an operation example of the power supply switching device according to the fourth embodiment of the present invention. Fig.10 This is a diagram for explaining the effect of providing an overlap period for the gate voltages of the first semiconductor switch and the second semiconductor switch in the power supply switching device according to the fourth embodiment of the present invention. Fig.11 This is a diagram showing a configuration example of a power supply switching device according to a fifth embodiment of the present invention. Fig.12 This is a diagram showing a first configuration example for turning on a semiconductor switch of a power supply switching device according to a sixth embodiment of the present invention. Fig.13 This is a diagram showing an operation example of a semiconductor switch in the first configuration example of the power supply switching device according to the sixth embodiment of the present invention. Fig.14 This is a diagram showing a second configuration example for turning on the semiconductor switch of the power supply switching device according to the sixth embodiment of the present invention. Fig.15 This is a diagram showing an operation example of a semiconductor switch in the second configuration example of the power supply switching device according to the sixth embodiment of the present invention. Fig.16 This is a diagram showing a third configuration example for turning on the semiconductor switch of the power supply switching device according to the sixth embodiment of the present invention. Fig.17 This is a diagram showing an operation example of a semiconductor switch in the third configuration example of the power supply switching device according to the sixth embodiment of the present invention. Fig.18 This is a block diagram showing a hardware configuration example of a computer included in the power supply switching device according to each embodiment of the present invention. DETAILED DESCRIPTION

[0012] Hereinafter, examples of methods for implementing the present invention (hereinafter referred to as "implementation methods") will be described with reference to the accompanying drawings. In this specification and the accompanying drawings, the same constituent elements or constituent elements of components having substantially the same functions are marked with the same reference numerals, and repeated descriptions are omitted. In addition, when there are multiple constituent elements having the same or equivalent functions, different subscripts are sometimes added to the same reference numeral for description. In addition, when there is no need to distinguish the above-mentioned multiple constituent elements, the subscripts are sometimes omitted for description.

[0013] <Implementation Method 1> First, refer to Figure 1 An example of a vehicle including a power source switching device for switching a plurality of power sources will be described. Figure 1 is a schematic diagram showing an example in which a plurality of power sources are connected to a vehicle control device mounted on a vehicle. Figure 1 As shown, the vehicle 100 is configured to include a vehicle control device 110, sensors 120, actuators 130, a first power supply ("first power supply" in the figure) 2a, and a second power supply ("second power supply" in the figure). The vehicle control device 110 is connected to the sensors 120, the actuators 130, the first power supply 2a, and the second power supply 2b, respectively.

[0014] The vehicle control device 110 includes a power switching device 1 and a controller 111. The controller 111 receives a detection signal from the sensor 120 via a signal line d1, and sends a control signal to the actuator 130 via a control line s1 to control the vehicle 100. The controller 111 analyzes the detection signal received from the sensor 120, generates a control signal based on the analysis result, and controls the operation of the actuator 130. The controller 111 can be configured using an ECU (Electronic Control Unit), for example. The sensor 120 and the actuator 130 are load devices that consume power provided by the first power supply 2a or the second power supply 2b.

[0015] The power switching device 1 switches the power supply between the first power supply 2a and the second power supply 2b based on the power supply voltages of the first power supply 2a and the second power supply 2b. The power switching device 1 is powered from the first power supply 2a via the power line p1, and powered from the second power supply 2b via the power line p2. Then, the power switching device 1 supplies the power received from the first power supply 2a or the second power supply 2b to the sensor 120 via the power line p3, and supplies the power received from the first power supply 2a or the second power supply 2b to the actuator 130 via the power line p4.

[0016] Figure 1In the illustrated example, the power switching device 1 is described as being built into the vehicle control device 110, but the power switching device 1 may be separated from the vehicle control device 110. In addition, the power switching device 1 may be configured to be controllable by the controller 111. For example, a terminal used by a mechanic or the like may be connected to the controller 111, and the controller 111 may control the on / off of the first semiconductor switch 3a and the second semiconductor switch 3b based on instructions from the terminal.

[0017] Next, the configuration of the power supply switching device 1 according to the first embodiment of the present invention will be described with reference to the drawings. Figure 2 1 is a diagram showing a configuration example of a power switching device 1 according to Embodiment 1 of the present invention. The power switching device 1 is connected to a first power supply 2a and a second power supply 2b. For example, the first power supply 2a and the second power supply 2b are connected to a power converter such as a vehicle battery or a DC / DC converter. The power switching device 1 includes a first semiconductor switch 3a, a second semiconductor switch 3b, and a switch control device 5.

[0018] A first semiconductor switch 3a is provided between a first power supply source 2a that supplies power to load devices 4a to 4c and the load devices 4a to 4c. Power from the first power supply source 2a is supplied to a plurality of load devices 4a to 4c via the first semiconductor switch 3a. For example, the first semiconductor switch 3a is formed by a field effect transistor M. The field effect transistor M of the first semiconductor switch 3a is connected so that a body diode (also referred to as a "parasitic diode") formed between its drain and source is in the opposite direction relative to the power supply direction from the first power supply source 2a. That is, the anode side of the body diode is connected to the source of the field effect transistor M, and the cathode side is connected to the drain of the field effect transistor M.

[0019] A second semiconductor switch 3b is provided between the second power supply source 2b that supplies power to the load devices 4a to 4c and the load devices 4a to 4c. The power from the second power supply source 2b is supplied to the plurality of load devices 4a to 4c via the second semiconductor switch 3b. For example, the second semiconductor switch 3b is formed by a field effect transistor M. The field effect transistor M of the second semiconductor switch 3b is connected so that the body diode formed between the drain and the source thereof is in the opposite direction to the power supply direction from the second power supply source 2b. That is, the anode side of the body diode is connected to the source of the field effect transistor M, and the cathode side is connected to the drain of the field effect transistor M.

[0020] The load devices 4a to 4c are configured to control the first semiconductor switch 3a and the second semiconductor switch 3b so as to be powered from either the first power supply source 2a or the second power supply source 2b. The output end of the first semiconductor switch 3a is electrically connected to the output end of the second semiconductor switch 3b, and the plurality of load devices 4a to 4c are connected to the output ends.

[0021] The load devices 4a to 4c include actuators 130 such as motors or solenoids and sensors 120 such as cameras mounted on the vehicle 100. In addition, in the present embodiment, the number of connected load devices is set to three, but it is not limited thereto, and a plurality of load devices of two or more may be connected. In the following description, when there is no need to distinguish between the load devices 4a to 4c, they are described as "load devices 4".

[0022] The switch control device 5 outputs a control signal (gate voltage) to the first semiconductor switch 3 a and the second semiconductor switch 3 b to switch power supply. The switch control device 5 includes a voltage comparator 7 and a gate voltage control circuit 6 .

[0023] The voltage comparator 7 monitors the voltage Va output from the first power supply source 2 a and the voltage Vb output from the second power supply source 2 b and detects a voltage difference Vd (=Va−Vb). The voltage difference Vd is output to the gate voltage control circuit 6 .

[0024] The gate voltage control circuit 6 generates and outputs a gate voltage Vga of the field effect transistor M as the first semiconductor switch 3a and a gate voltage Vgb of the field effect transistor M as the second semiconductor switch 3b based on the voltage difference Vd. When the gate voltage Vga of the first semiconductor switch 3a is at a high level, the first semiconductor switch 3a is turned on. When the gate voltage Vgb of the second semiconductor switch 3b is at a high level, the second semiconductor switch 3b is turned on. In the following description, the first semiconductor switch 3a and the second semiconductor switch 3b are referred to as "semiconductor switch 3" when it is not necessary to distinguish between them.

[0025] Figure 2 In the embodiment, the field effect transistor M uses an N-channel MOS field effect transistor, but a P-channel MOS field effect transistor or other field effect transistors may also be used. Alternatively, a bipolar transistor may be used to form the semiconductor switch 3.

[0026] Next, use Figure 3 An operation example of the power supply switching device 1 according to the present embodiment will be described. Figure 3 1 is a diagram showing an operation example of the power supply switching device 1 . Figure 3 The upper part shows the voltage distribution of the gate voltage Vga when the first power supply source 2a is switched to the second power supply source 2b. Figure 3 The middle part shows the voltage distribution of the gate voltage Vgb. Figure 3 The lower portion shows the current I2 flowing through the second semiconductor switch 3b. Figure 3 , the horizontal axis represents time t.

[0027] The voltages Va and Vb outputted by the first power supply 2a and the second power supply 2b vary due to individual differences in the vehicle battery and DC / DC converter, the charging state, the wiring length, and the degradation of the vehicle battery or the power wiring, etc. The following example is described: Assuming that the voltage Va of the first power supply 2a is 13V and the voltage Vb of the second power supply 2b is 14V, the first power supply 2a with a lower output voltage is switched to the second power supply 2b with a higher output voltage.

[0028] like Figure 3 As shown, when power is supplied from the first power supply source 2a to the load devices 4a to 4c (first power supply S1), the gate voltage Vga of the first semiconductor switch 3a is high, and the gate voltage Vga of the second semiconductor switch 3b is low.

[0029] When the power supply source is switched from the first power supply state S1 to the second power supply source 2b, the gate voltage control circuit 6 first sets the gate voltage Vga of the first semiconductor switch 3a to a low level. Then, the gate voltage control circuit 6 simultaneously or after the gate voltage Vgb of the second semiconductor switch 3b starts to rise, raises the gate voltage Vgb to an intermediate voltage Vm between a low level and a high level, and maintains the intermediate voltage Vm during the holding time Tm (intermediate state S2).

[0030] In addition, the gate voltage control circuit 6 needs a certain time (rise time) to raise the gate voltage from the low level to the intermediate voltage Vm. Therefore, it can be said that the time that the gate voltage actually remains at the intermediate voltage Vm is longer than Figure 3 The holding time Tm shown in FIG. 1 is shorter than the time during which the gate voltage is held at a constant value of the intermediate voltage Vm. However, the rising time is shorter than the time during which the gate voltage is held at a constant value of the intermediate voltage Vm. Therefore, the holding time Tm is set to the period from the start of the gate voltage rising to the start of the rise to the next voltage level. For example, the next voltage level is Figure 3 The high level is described later. Fig.13 The middle voltage is the second stage.

[0031] Thereafter, the gate voltage control circuit 6 raises the gate voltage Vgb of the second semiconductor switch 3b to a high level, thereby completely switching the power supply from the first power supply 2a to the second power supply 2b (second power supply S3).

[0032] Therefore, in this embodiment, the voltage levels of the gate voltages Vga and Vgb have three states: a high level, a low level, and an intermediate voltage. The high level refers to a voltage at which the on-resistance of the field effect transistors serving as the first semiconductor switch 3a and the second semiconductor switch 3b is the minimum, for example, a voltage at which the gate-source voltage is 10V or more. The low level refers to a voltage at which the output characteristic (I D -V DS The intermediate voltage is the voltage in the cut-off region of the field effect transistor output characteristic, for example, the voltage at which the gate-source voltage is 0 V. The intermediate voltage is the voltage at which the output characteristic of the field effect transistor is in the non-saturation region, and is the voltage at which the source-drain resistance changes according to the gate voltage.

[0033] The holding time Tm is dynamically set according to the voltage difference Vd between the voltages outputted by the first power supply 2a and the second power supply 2b. When the voltage difference Vd is small, the holding time Tm is shortened, and when the voltage difference Vd is large, the holding time Tm is extended. That is, the gate voltage control circuit 6 changes the holding time Tm in a direction longer than a preset reference time when the voltage difference Vd is larger than a predetermined value, and changes the holding time Tm in a direction shorter than the reference time when the voltage difference Vd is less than a predetermined value.

[0034] In this embodiment, the state where the gate voltage of the semiconductor switch is a voltage between a low level and a high level is set as an "intermediate state". Figure 3 As shown by the thin solid line in the middle of , the voltage distribution of the gate voltage Vgb rising from a low level to a high level is fixed in the intermediate state. The holding time is the time used to limit the surge current flowing through the semiconductor switch when the power supply is switched, and it can also be called the "current limit time".

[0035] When switching to a power supply with a different voltage value, such as from the first power supply 2a (voltage Va=13V) to the second power supply 2b (voltage Vb=14V) shown in this embodiment, a surge current corresponding to the voltage difference Vd between the two power supplies is generated. In the conventional structure, a large surge current exceeding the allowable current indicated by the single-dot chain line flows through the second semiconductor switch 3b.

[0036] In the structure of this embodiment, the current I2 flowing through the second semiconductor switch 3b when switching from the intermediate state S2 to the second power supply S3 is described. Figure 3 As shown in the lower part, when the gate voltage Vgb of the second semiconductor switch 3b rises to the intermediate voltage Vm, the first peak current flows. Thereafter, when the gate voltage Vgb rises to a high level after the first peak current decreases, the second peak current flows.

[0037] Thus, in the present embodiment, the gate voltage Vgb of the second semiconductor switch 3b is increased from a low level to a high level in a stepwise manner, rather than from a low level to a high level all at once, so that the peak current can be dispersed so that the current I2 (peak current) flowing through the second semiconductor switch 3b does not exceed the allowable current when the power source is switched. In addition, in the present embodiment, the power source can be changed according to the voltage difference Vd between the output voltages of the first power source 2a and the second power source 2b, so the power source can be switched so as not to exceed the allowable current. In the past, when the power source is switched, a structure for changing the holding time Tm of the intermediate voltage Vm according to the voltage difference Vd in the intermediate state may not be included. Therefore, in the past, when the voltage difference Vd becomes larger, the peak current of the semiconductor switch may increase accordingly and exceed the allowable current, but according to the present embodiment, this problem is solved.

[0038] As described above, the power switching device (power switching device 1) involved in embodiment 1 includes: a first semiconductor switch (first semiconductor switch 3a) provided between a first power supply (first power supply 2a) for supplying power to a load device (4a~4c) and the load device; a second semiconductor switch (second semiconductor switch 3b) provided between a second power supply (second power supply 2b) for supplying power to the load device and the load device; and a switch control device (switch control device 5) for controlling the driving voltage of the first semiconductor switch and the second semiconductor switch. When switching from one power supply to the other between the first power supply and the second power supply, the switch control device is configured to maintain the semiconductor switch (second semiconductor switch 3b) of the power supply (for example, the second power supply 2b) connected to the power supply side after switching in an intermediate state of a non-saturated state, and to change the holding time (holding time Tm) of the intermediate state according to the voltage difference (voltage difference Vd) between the voltages output by the first power supply and the second power supply.

[0039] According to the present embodiment of the above structure, the holding time (current limiting time) of the intermediate state of the semiconductor switch of the power supply connected to the power supply side after switching is changed according to the voltage difference between the output voltages of the first power supply and the second power supply. Thus, even when there is a difference in the output voltages of the first power supply and the second power supply, damage to the semiconductor switch caused by overcurrent can be suppressed, and the power supply can be switched smoothly without cutting off the power supply.

[0040] <Implementation Method 2> Next, the power switching device according to Embodiment 2 is described. Embodiment 2 is an example in which the first semiconductor switch 3a and the second semiconductor switch 3b are controlled in consideration of information (load information) of the load device 4 in addition to the voltage difference Vd between the output voltages of the first power supply source 2a and the second power supply source 2b. Hereinafter, the power switching device according to Embodiment 2 is described with a focus on the differences from Embodiment 1.

[0041] First, use Figure 4 The structure of the power supply switching device according to this embodiment will be described. Figure 4 1 is a diagram showing a configuration example of a power switching device 1A according to the present embodiment. The power switching device 1A includes a switch control device 5A in place of the switch control device 5 of the power switching device 1 according to Embodiment 1. That is, the power switching device 1A includes a first semiconductor switch 3a, a second semiconductor switch 3b, and a switch control device 5A.

[0042] The switch control device 5A outputs a control signal to the first semiconductor switch 3a and the second semiconductor switch 3b to switch the power supply. The switch control device 5A includes a voltage comparator 7, a gate voltage control circuit 6A, and a load information 8A.

[0043] The gate voltage control circuit 6A generates and outputs the gate voltage Vga of the first semiconductor switch 3a (field effect transistor M) and the gate voltage Vgb of the second semiconductor switch 3b (field effect transistor M) based on the voltage difference Vd output by the voltage comparator 7. In addition, the gate voltage control circuit 6A generates and outputs the gate voltage Vga and the gate voltage Vgb based on the load information 8A based on the equivalent resistance and equivalent electrostatic capacitance of the load devices 4a to 4c. The load information 8A is stored in a memory or the like. The gate voltage control circuit 6A generates the gate voltage Vga and the gate voltage Vgb by referring to the memory storing the load information 8A.

[0044] The present embodiment is characterized in that, in addition to the voltage difference Vd, a gate voltage Vga and a gate voltage Vgb are generated and outputted according to the load information 8A. Figure 4 As shown, the load information 8A is a parameter based on the equivalent circuit model of the load devices 4a to 4c. The load devices 4a to 4c can be represented by an equivalent circuit of equivalent resistance and equivalent electrostatic capacitance as shown in the figure. The load information 8A is information based on the equivalent resistance and equivalent electrostatic capacitance of the above-mentioned multiple load devices 4a to 4c. In this embodiment, it is preferred that the information representing the electrical characteristics of the load device includes at least equivalent resistance and equivalent electrostatic capacitance. For example, as electrical characteristics, the resistance and electrostatic capacitance of the load device 4 are exemplified, but the reactance component can also be considered.

[0045] For example, the load device 4a is represented by an equivalent resistance R L 1 is an equivalent circuit formed by connecting the equivalent electrostatic capacitance C1 and the equivalent resistance Rs1 in parallel with each other in series. Similarly, the load device 4b is represented by the equivalent resistance R L 2 is an equivalent circuit formed by connecting the equivalent electrostatic capacitance C2 and the equivalent resistance Rs2 connected in series in parallel. L 3 is an equivalent circuit formed by connecting the equivalent electrostatic capacitance C3 and the equivalent resistance Rs3 connected in series in parallel. One end side of the equivalent circuit of the load devices 4a to 4c is connected to the power supply line, and the other end is grounded.

[0046] In this embodiment, use Figure 5 and Figure 6 An example of a procedure for determining the gate voltage distribution based on the load information 8A described above will be described. Figure 5 This is an explanatory diagram regarding a method of estimating an inrush current at the time of power supply switching using the load information 8A in the power supply switching device 1A. Figure 5 In FIG. 1 , the vertical axis represents the current I2 flowing through the second semiconductor switch 3b, and the horizontal axis represents the time t. For example, when switching from the first power supply source 2a to the second power supply source 2b, the current I2 flowing through the second semiconductor switch 3b can be predicted by the following equation (1).

[0047] [Mathematical formula 1]

[0048] Here, "i c " is the charging current of the electrostatic capacitor in the current I2 flowing through the second semiconductor switch 3b. "i R " is the current of the DC component of the current I2 flowing through the second semiconductor switch 3b. "t" is the time elapsed from the moment when the gate voltage Vgb is applied to the second semiconductor switch 3b. "Vd" is the voltage difference between the voltages output by the first power supply 2a and the second power supply 2b (hereinafter also referred to as "power supply voltage difference"), and "Rs" is the resistance of the equivalent electrostatic capacitance connected in series to each load device 4 ( Figure 4 "Vb" is the output voltage of the second power supply 2b, "Rs1 to Rs3" is the parallel composite resistance, "C" is the parallel composite capacitance of the equivalent electrostatic capacitance (C1 to C3) of each load device 4. L ” is the equivalent resistance (R L 1~R L 3) Parallel synthetic resistance.

[0049] Based on the above formula (1), the peak current of the surge current flowing through the second semiconductor switch 3b when the power supply is switched is estimated. When the peak current exceeds the allowable current, the value of the source-drain resistance Rsd is calculated using the following formula (2) taking into account the source-drain resistance Rsd of the second semiconductor switch 3b so as not to exceed the allowable current.

[0050] [Mathematical formula 2]

[0051] After the source-drain resistance Rsd is calculated according to equation (2), the gate voltage Vgb at which the source-drain resistance becomes Rsd is determined according to the electrical characteristics of the field effect transistor M constituting the second semiconductor switch 3b. The gate voltage Vgb can be calculated using, for example, the drain current-gate-source voltage characteristic (Id-V GS The gate voltage Vgb value determined here is the intermediate voltage value in the intermediate state of the present invention ( Figure 6 The intermediate voltage Vm).

[0052] Next, use Figure 6 An operation example of the power supply switching device 1B according to the present embodiment will be described. Figure 6 1B is a diagram showing an operation example of the power supply switching device 1B. Figure 6 The upper part shows the voltage distribution of the gate voltage Vgb generated by the gate voltage control circuit 6, Figure 6 The lower part shows the current I2 of the second semiconductor switch 3b. Figure 5 , the horizontal axis represents time t.

[0053] First, after the power supply is switched, the gate voltage control circuit 6 raises the gate voltage Vgb from the Lw level to the intermediate voltage Vm determined above. The holding time Tm at the intermediate voltage Vm is determined by the following formula (3) based on the equivalent resistance Rs of the load device 4, the equivalent electrostatic capacitance C, and the source-drain resistance Rsd of the field effect transistor.

[0054] [Mathematical formula 3] Tm=k C(R s +R sd )····(3)

[0055] In formula (3), "k" is a constant. After the gate voltage Vgb is maintained in the intermediate state for the holding time Tm, if the gate voltage Vgb is raised to a high level, the second semiconductor switch 3b is completely turned on. In the current I2 under this voltage distribution, the first peak current flows when the gate voltage Vgb is switched to the intermediate voltage Vm, and then the second peak current flows when it becomes a high level. According to this embodiment, the peak current is dispersed into the first peak current and the second peak current according to the voltage difference Vd and the electrical characteristics of the load device 4, so that switching can be performed so that the peak current does not exceed the allowable current.

[0056] In the present embodiment, as described above, an example of determining the holding time Tm based on the equivalent resistance and the equivalent electrostatic capacitance is shown, but the holding time Tm can also be optimized by multiplying the time constant (=C(Rs+Rsd)) of the formula (3) by a predetermined coefficient k. That is, the rising curve (rising speed) of the gate voltage Vgd can be changed according to the value of k to change the holding time Tm. For example, if the second peak current value of the current I2 has a margin to the allowable current, it can be set to k<1 to set the holding time Tm to a time shorter than the time constant. If the peak current value has no margin, it can be set to k>1 to set the holding time Tm to a time longer than the time constant. That is, the gate voltage Vgb can be optimized using the source-drain resistance Rsd and the holding time Tm of the field effect transistor M of the second semiconductor switch 3b as parameters.

[0057] In addition, in this embodiment, an example is shown in which the value of the gate voltage Vgb (intermediate voltage Vm) maintained in the intermediate state is one, but a plurality of voltage values ​​may be set, and the gate voltage Vgb may be increased in a plurality of step voltages of two or more stages. These voltage distributions are design parameters and are appropriately set according to the characteristics of the semiconductor switch 3, the load device 4, etc.

[0058] As described above, the switch control device in the second embodiment (switch control device 5A) is configured to change the holding time Tm of the intermediate state based on the voltage difference Vd between the voltages output by the first power supply source 2a and the second power supply source 2b and the information indicating the electrical characteristics of the load devices 4a to 4c (load information 8A).

[0059] According to the present embodiment of the above-described structure, the gate voltage control circuit 6 sets the voltage distribution of the gate voltage of the semiconductor switch 3 based on the information of the load device 4 (load information 8A) in addition to the voltage difference Vd. By adopting such a structure, even if the addition or update of the load device 4 causes a change in the surge current at the time of power switching, the failure and degradation of the semiconductor switch 3 caused by the surge current can be suppressed by changing the load information 8A. That is, it is possible to cope with the change of the load device 4 without replacing the semiconductor switch 3. For example, even if the number of connected loads or the current capacity changes due to a later increase, it is not necessary to replace the semiconductor switch 3, and it can be dealt with by correcting the software.

[0060] In addition, in this embodiment, the equivalent resistance and equivalent electrostatic capacitance of the load device 4 are shown as the load information 8A, but the present invention is not limited thereto. For example, the following method can be adopted: the intermediate voltage Vm and the holding time Tm predetermined according to the characteristics of the surge current flowing through the semiconductor switch 3 are stored in the memory as the load information 8A. That is, as long as the load information 8A is information that can appropriately change the parameters (Tm, Vm) that determine the voltage distribution of the gate voltage according to the electrical characteristics of the connected load device 4, and can change the voltage distribution of the gate voltage and the holding time of the intermediate state, the effect of the present invention can be obtained.

[0061] <Implementation Method 3> Next, a description will be given of a power supply switching device according to Embodiment 3. Embodiment 3 is an example in which a gate voltage of a semiconductor switch 3 is controlled based on information indicating electrical characteristics of a load device 4 in an energized state among a plurality of load devices 4 .

[0062] use Figure 7 The structure of the power supply switching device according to this embodiment will be described. Figure 7 1B is a diagram showing a configuration example of a power switching device 1B according to the present embodiment. The power switching device 1B has a basic configuration of the power switching device 1A according to the second embodiment, and the power switching device 1B will be described mainly with respect to the differences from the second embodiment.

[0063] The power switching device 1B includes a switch control device 5B in place of the switch control device 5A of the power switching device 1 according to Embodiment 2. That is, the power switching device 1B includes a first semiconductor switch 3a, a second semiconductor switch 3b, and a switch control device 5B. The switch control device 5B includes a voltage comparator 7, a gate voltage control circuit 6B, and a load information 8A.

[0064] In addition to the structure of Embodiment 2, this embodiment further includes load switches 9a to 9c provided on the power supply lines of the load devices 4a to 4c, and a load switch control device 10 for controlling the on / off of the load switches 9a to 9c based on external commands. The load switch control device 10 may be built into Figure 1 The controller 111 of the vehicle control device 110 shown in FIG.

[0065] In addition, the electronic control unit (ECU) of the power management system inputs a load switch switching instruction to the switch control device 5B. For example, load switches 9a to 9c are switched by detecting a failure (or a sign of failure) of the load device 4 to stop using the load device 4 or restrict its function.

[0066] As a load switch, in addition to a semiconductor switch using a field effect transistor, a mechanical switch such as a relay can also be used. The power supply to the load devices 4a to 4c is controlled by the load switches 9a to 9c. In the following description, when there is no need to distinguish between the load switches 9a to 9c, they are recorded as "load switch 9".

[0067] The load information 8A is information based on the equivalent resistance and equivalent electrostatic capacitance of the load devices 4a to 4c. However, the load information 8A of the present embodiment is updated based on the switching information of the load switches 9a to 9c notified from the load switch control device 10 ("switch information" in the figure), that is, the information of the load devices 4a to 4c connected (energized) to the power line.

[0068] In addition, the load information 8A may include information indicating the electrical characteristics of all the load devices 4a to 4c, and based on the switch information, the load information 8A may be updated according to the electrical characteristics (electrical characteristics of the equivalent circuit model) of the driven load device 4 and stored in the memory.

[0069] The gate voltage control circuit 6B has the same function as the gate voltage control circuit 6A in Embodiment 2. The gate voltage control circuit 6B generates the gate voltage Vga and the gate voltage Vgb by the same method as in Embodiment 2, referring to the memory storing the load information 8A.

[0070] In addition, when the load information 8A registers information indicating the electrical characteristics of the load devices 4a to 4c, the gate voltage control circuit 6B can extract only the electrical characteristics information of the energized load device 4 from the load information 8A based on the switch information, and generate the gate voltage based on the extracted electrical characteristics information of the load device 4. The gate voltage control circuit 6B can obtain the switch information before the power supply is switched by periodically communicating with the load switch control device 10. For example, Figure 7 In the embodiment, only the load switch 9a is energized, and the load device 4a is connected to the power supply line and driven. The gate voltage control circuit 6B generates a gate voltage based on the load information 8A based on the electrical characteristics of the load device 4a.

[0071] The surge current flowing through the semiconductor switch 3 during power switching is determined by the load device 4 in the driving state. Therefore, according to the present embodiment, the surge current flowing through the semiconductor switch 3 during power switching can be estimated more accurately, and an optimal gate voltage can be generated.

[0072] In addition, before switching from one power supply source to another, the switch control device 5B can stop the power supply to any one of the multiple load devices 4a~4c, and the switch control device 5B can also change the holding time Tm of the intermediate state according to the information representing the electrical characteristics of the load device 4 in the power-on state among the multiple load devices 4 (for example, equivalent resistance and equivalent electrostatic capacitance). For example, the multiple load devices 4 are pre-classified into important equipment and non-important equipment, and the non-important equipment is stopped when the power is switched. In this way, the number of load devices 4 connected when the power is switched can be reduced, and the surge current flowing through the semiconductor switch 3 when the power is switched can be reduced. For example, important equipment is a load device such as brake lights, headlights, wipers, etc. that is crucial to the safe driving of the car. Non-important equipment is a load device such as audio, air conditioning, electric windows, etc. that does not hinder the safe driving of the car even if it is temporarily stopped.

[0073] Then, after the power supply is switched, the load switch control device 10 supplies power to the load device 4 to which the power supply has been stopped. At this time, the load switch control device 10 energizes the load switch 9 connected to the load device 4 to which the power supply has been stopped, within the range not exceeding the allowable current of the semiconductor switch 3, to drive the corresponding load device 4. For example, the load switch control device 10 may drive the multiple stopped load devices 4 in sequence rather than simultaneously. Alternatively, the load switch control device 10 may not start the load devices 4 with larger surge currents (equivalent electrostatic capacitance) at the same time, so as not to exceed the allowable current of the semiconductor switch 3. In other words, as long as it does not exceed the allowable current of the semiconductor switch 3, multiple load devices 4 can be powered on at the same time.

[0074] As described above, the switch control device (switch control device 5B) in the third embodiment is configured to change the intermediate state holding time Tm based on the information (load information 8A) indicating the electrical characteristics of the load devices in the energized state among the plurality of load devices 4a to 4c.

[0075] According to the present embodiment of the above structure, the holding time of the intermediate state of the semiconductor switch of the power supply connected to the power supply side after switching is changed according to the voltage difference between the output voltages of the first power supply and the second power supply, and the connected load device. Thus, even if the difference between the output voltages of the first power supply and the second power supply changes, damage to the semiconductor switch caused by overcurrent can be suppressed, and the power supply can be smoothly switched without cutting off the power supply. In addition, it is not necessary to design under the worst conditions of the current capacity of the load device connected to the power supply switching device, so the cost of the semiconductor switch can be reduced.

[0076] <Implementation Method 4> Next, a power supply switching device according to Embodiment 4 is described. Embodiment 4 is an example of preventing a reverse current from the load device 4 to the first power supply source 2a and the second power supply source 2b and a through current from flowing between the first power supply source 2a and the second power supply source 2b.

[0077] First, use Figure 8 The structure of the power supply switching device according to this embodiment will be described. Figure 8 1 is a diagram showing a configuration example of a power switching device 1C according to the present embodiment. The power switching device 1C is based on the power switching device 1A according to the second embodiment, and the power switching device 1C is described mainly with the differences from the second embodiment as the focus. The power switching device 1C differs most from the power switching device 1A according to the second embodiment in that the power switching device 1C includes a first semiconductor switch 3c and a second semiconductor switch 3d instead of the first semiconductor switch 3a and the second semiconductor switch 3b.

[0078] The power switching device 1C includes a first semiconductor switch 3c, a second semiconductor switch 3d, and a switch control device 5C. The power from the first power supply source 2a is supplied to a plurality of load devices 4a to 4c via the first semiconductor switch 3c. The first semiconductor switch 3c is composed of a plurality of field effect transistors M1 and M2, and the field effect transistor M1 and the field effect transistor M2 are connected in series so that their body diodes are in opposite directions.

[0079] The power from the second power supply source 2b is supplied to the plurality of load devices 4a to 4c via the second semiconductor switch 3d. The second semiconductor switch 3d is composed of a plurality of field effect transistors M3 and M4 connected in series so that their body diodes are in opposite directions.

[0080] The switch control device 5C outputs control signals (gate voltages) to the field effect transistors M1 and M2 of the first semiconductor switch 3c and the field effect transistors M3 and M4 of the second semiconductor switch 3d to switch power supply. The switch control device 5C includes a voltage comparator 7, a gate voltage control circuit 6C, and a load information 8A.

[0081] The gate voltage control circuit 6C generates and outputs a gate voltage Vga1 of the field effect transistor M1 as the first semiconductor switch 3c and a gate voltage Vga2 of the field effect transistor M2 according to the voltage difference Vd between the output voltages of the first power supply source 2a and the second power supply source 2b detected by the voltage comparator 7. In addition, the gate voltage control circuit 6C generates and outputs a gate voltage Vgb1 of the field effect transistor M3 as the second semiconductor switch 3d and a gate voltage Vgb2 of the field effect transistor M4 according to the voltage difference Vd.

[0082] Furthermore, the gate voltage control circuit 6C can generate and output gate voltages Vga1 and Vga2 and gate voltages Vgb1 and Vgb2 based on load information 8A based on equivalent resistance and equivalent capacitance of the load devices 4a to 4c in addition to the voltage difference Vd.

[0083] In this embodiment, if Figure 8 As shown, in each of the first semiconductor switch 3c and the second semiconductor switch 3d, two field effect transistors are connected back-to-back. The back-to-back connection is a connection method in which the body diodes of the two field effect transistors are connected in series relative to each other. As a result, the reverse current from the load device 4 side to the first power supply source 2a and the second power supply source 2b and the through current in the first power supply source 2a and the second power supply source 2b can be cut off.

[0084] Next, use Fig. 9 An operation example of the power supply switching device 1C according to the present embodiment will be described. Fig. 9 1C is a diagram showing an example of gate voltages Vga1 and Vga2 and gate voltages Vgb1 and Vgb2 generated by the gate voltage control circuit 6C as an operation example of the power supply switching device 1C. Fig. 9 The upper part shows the voltage distribution of gate voltages Vga1 and Vga2 when the first power supply source 2a is switched to the second power supply source 2b. Fig. 9 The middle part shows the voltage distribution of gate voltages Vgb1 and Vgb2. Fig. 9 The lower part shows the current I2 flowing through the second semiconductor switch 3d. Fig. 9 , the horizontal axis represents time t.

[0085] In this embodiment, similar to the first embodiment, the following example is described: assuming that the voltage Va of the first power supply 2a is 13V and the voltage Vb of the second power supply 2b is 14V, the output voltage is switched from the first power supply 2a having a lower output voltage to the second power supply 2b having a higher output voltage.

[0086] like Fig. 9 As shown, when power is supplied from the first power supply source 2a to the load devices 4a to 4c (first power supply S1), the gate voltages Vga1 and Vga2 of the first semiconductor switch 3c are at a high level, and the gate voltages Vgb1 and Vgb2 of the second semiconductor switch 3d are at a low level.

[0087] When the power supply source is switched from the first power supply S1 to the second power supply source 2 b , the gate voltage control circuit 6C first sets the gate voltages Vga1 and Vga2 of the first semiconductor switch 3 c to a low level.

[0088] Here, the gate voltage control circuit 6C increases the gate voltage Vgb1 of the second semiconductor switch 3d to the intermediate voltage Vm just before the gate voltages Vga1 and Vga2 become low level. Fig. 9 As shown in the middle, in this embodiment, an overlap period Po is provided, and during the overlap period Po, the gate voltage Vga1 and the gate voltage Vgb1 are simultaneously set to a voltage greater than the low level. When the gate voltage control circuit 6C of the switch control device 5C switches from one power supply source to another power supply source during the overlap period Po, before cutting off the power supply of one side, the field effect transistor (for example, the field effect transistor M3) of the other side is set to an intermediate state. The effect of the overlap period will be described later. The gate voltage control circuit 6C maintains the gate voltage Vgb1 at the intermediate voltage Vm during the holding time Tm (intermediate state S2).

[0089] Then, the gate voltage control circuit 6C raises the gate voltage Vgb1 from the intermediate voltage Vm to a high level, and then raises the gate voltage Vgb2 from a low level to a high level. Thus, the power supply is completely switched from the first power supply 2a to the second power supply 2b (second power supply S3).

[0090] As in the first embodiment, the holding time Tm is dynamically set according to the voltage difference Vd between the voltages outputted by the first power supply 2a and the second power supply 2b. When the voltage difference Vd between the output voltages of the first power supply 2a and the second power supply 2b is small, the holding time Tm is shortened, and when the voltage difference Vd is large, the holding time Tm is extended. In the present embodiment, the state in which the gate voltage Vgb1 of the field effect transistor M3 of the second semiconductor switch 3d is a voltage between a low level and a high level is set as an "intermediate state".

[0091] By the power switching control as described above, Fig. 9 The current I2 at the bottom shows the current flowing through the second semiconductor switch 3d. Time t0 is the timing when the gate voltage Vgb1 starts to rise from a low level. When the gate voltage Vgb1 rises to the intermediate voltage Vm (time t1), the first peak current flows, and then, after the first peak current decreases, when the gate voltage Vgb1 rises to a high level (time t2), the second peak current flows. Next, when the gate voltage Vgb2 rises to a high level (time t3), the third peak current flows. When both the gate voltages Vgb1 and Vgb2 become high levels (time t4), the power supply is completely switched to the second power supply 2b.

[0092] As described above, in the switch control device (switch control device 5C) in embodiment 4, when switching from one power supply source to another power supply source, a field effect transistor (for example, field effect transistor M3) whose body diode is on the opposite side with respect to the power supply direction is set to be maintained in an intermediate state of a non-saturated state, and the holding time Tm of the intermediate state is changed according to the voltage difference Vd between the voltages output by the first power supply source 2a and the second power supply source 2b.

[0093] Furthermore, in the switch control device (switch control device 5C) according to the present embodiment, when switching from one power supply source to another power supply source, an intermediate state in which a field effect transistor (for example, field effect transistor M3) whose body diode is on the opposite side with respect to the power supply direction is maintained in a non-saturated state may be provided, and the holding time Tm of the intermediate state may be changed according to the information indicating the electrical characteristics of the load devices 4a to 4c. Alternatively, the holding time Tm of the intermediate state may be changed according to the voltage difference Vd and the information indicating the electrical characteristics of the load devices 4a to 4c.

[0094] Thus, in this embodiment, the peak current can be dispersed so that the current I2 (peak current) flowing through the second semiconductor switch 3d does not exceed the allowable current shown by the dotted line. In addition, in this embodiment, the power supply source can be changed according to the voltage difference Vd between the output voltages of the first power supply source 2a and the second power supply source 2b, so the power supply source can be switched so that the allowable current does not exceed.

[0095] Here, use Fig.10 The effect of providing the overlap period Po for the gate voltages Vga1 and Vgb1 of the first semiconductor switch 3c and the second semiconductor switch 3d will be described.

[0096] Fig.10 This is an explanatory diagram regarding the effect of providing the overlap period Po with respect to the gate voltage Vga1 of the first semiconductor switch 3 c and the gate voltage Vgb1 of the second semiconductor switch 3 d. Fig.10In the example of FIG. 1 , the operating states of the field effect transistors M1 to M4 constituting each of the first semiconductor switch 3c and the second semiconductor switch 3d are shown when switching from the first power supply source 2a to the second power supply source 2b.

[0097] like Fig.10 As shown, when power is supplied from the first power supply source 2a to the load devices 4a to 4c (first power supply S1), the field effect transistors M1 and M2 of the first semiconductor switch 3c are in the on state, and the field effect transistors M3 and M4 of the second semiconductor switch 3d are in the off state. Conversely, when power is supplied from the second power supply source 2b to the load devices 4a to 4c (second power supply S3), the field effect transistors M1 and M2 of the first semiconductor switch 3c are in the off state, and the field effect transistors M3 and M4 of the second semiconductor switch 3d are in the on state.

[0098] In the overlap period Po, the field effect transistors M1 and M3 are in the on state, and the field effect transistors M2 and M4 are in the off state. That is, the field effect transistors M2 and M4 are in a state where current flows through their body diodes, and form a diode parallel circuit.

[0099] Thus, in this embodiment, the switching operation can be performed without cutting off the power supply during the power switching. In addition, in this embodiment, since any individual diode is reversely connected between the first power supply 2a and the second power supply 2b, the through current between the first power supply 2a and the second power supply 2b can be cut off.

[0100] In addition, in this embodiment, the holding time Tm and the intermediate voltage Vm are set based on the voltage difference Vd between the output voltages of the first power supply source 2a and the second power supply source 2b, but these parameters can be set based on the voltage difference Vd and the load information 8A as in the second embodiment. In addition, the power supply switching device 1C involved in this embodiment can also be combined with the third embodiment that uses the information of the load device 4 in the energized state among the plurality of load devices 4.

[0101] The overlap period Po is described in this embodiment, but the overlap period is not a necessary structure in this embodiment. However, the structure of setting the overlap period Po for the gate voltage between the first semiconductor switch 3c and the second semiconductor switch 3d in the power switching device 1C cannot be applied to the first to third embodiments. This is because in the first to third embodiments, the reverse connection structure based on two field effect transistors such as the first semiconductor switch 3c and the second semiconductor switch 3d does not exist. Therefore, in the first to third embodiments, if the overlap period is set for the gate voltage of the first semiconductor switch 3a and the second semiconductor switch 3b, the through current flows between the first power supply 2a and the second power supply 2b.

[0102] <Implementation method 5> Next, a power switching device according to Embodiment 5 is described. Embodiment 5 is an example in which a power switching device that forms a diode parallel circuit during power switching has a structure for suppressing an increase in voltage drop and power loss due to a forward voltage of a body diode.

[0103] use Fig.11 The structure of the power supply switching device according to this embodiment will be described. Fig.11 1 is a diagram showing a configuration example of a power switching device 1D according to this embodiment. The power switching device 1D is based on the power switching device 1C according to Embodiment 4, and the power switching device 1D is described mainly with the differences from Embodiment 4. The biggest difference between the power switching device 1D and the power switching device 1C according to Embodiment 4 is that the power switching device 1D is provided with ideal diode control circuits 11a and 11b.

[0104] The power switching device 1D includes a first semiconductor switch 3e, a second semiconductor switch 3f, and a switch control device 5D. The power from the first power supply source 2a is supplied to a plurality of load devices 4a to 4c via the first semiconductor switch 3e. The first semiconductor switch 3e is configured by reversely connecting a field effect transistor M1 and a field effect transistor M2, similarly to the first semiconductor switch 3c in the fourth embodiment. However, the gate voltage of the field effect transistor M2 is input from the ideal diode control circuit 11a, which is different from the fourth embodiment.

[0105] The power from the second power supply source 2b is supplied to the plurality of load devices 4a to 4c via the second semiconductor switch 3f. The second semiconductor switch 3f is configured by reversely connecting the field effect transistor M3 and the field effect transistor M4, similarly to the second semiconductor switch 3d in the fourth embodiment. However, the gate voltage of the field effect transistor M4 is input from the ideal diode control circuit 11b, which is different from the fourth embodiment.

[0106] The switch control device 5D outputs a control signal (gate voltage) to the field effect transistor M1 of the first semiconductor switch 3e and the field effect transistor M3 of the second semiconductor switch 3f to switch the power supply. The switch control device 5D includes a voltage comparator 7, a gate voltage control circuit 6A, and load information 8A. The switch control device 5D can have the same structure as the switch control device 5A in the second embodiment. In addition, the switch control device 5D can have the same structure as the switch control device 5 in the first embodiment without referring to the load information 8.

[0107] The gate voltage control circuit 6A generates and outputs a gate voltage Vga1 of the field effect transistor M1 as the first semiconductor switch 3e and a gate voltage Vgb1 of the field effect transistor M3 as the second semiconductor switch 3f based on the voltage difference Vd between the output voltages of the first power supply source 2a and the second power supply source 2b detected by the voltage comparator 7. In addition to the voltage difference Vd, the gate voltage control circuit 6A can also generate and output the gate voltage Vga1 of the field effect transistor M1 and the gate voltage Vgb1 of the field effect transistor M3 based on load information 8A based on equivalent resistance and equivalent electrostatic capacitance of the load devices 4a to 4c.

[0108] Fig.11 In the first semiconductor switch 3e, the gate voltage Vga2 of the field effect transistor M2 is controlled by the ideal diode control circuit 11a. In addition, in the second semiconductor switch 3f, the gate voltage Vgb2 of the field effect transistor M4 is controlled by the ideal diode control circuit 11b.

[0109] The ideal diode control circuit 11 a includes operational amplifiers 12 a and 13 a for detecting the direction of current based on the drain voltage and source voltage of the field effect transistor M2 , and a transistor 14 a for adjusting the gate voltage Vga2 based on the outputs of the operational amplifiers 12 a and 13 a . The description of power supply to the operational amplifiers 12a and 13a is omitted. Fig.11 In the example of , a bipolar transistor is used for transistor 14a, but the invention is not limited to this example.

[0110] When the current flowing through the field effect transistor M2 is in the reverse direction (in the reverse direction relative to the body diode), the operational amplifier 12a outputs a high-level signal to the gate of the transistor 14a. For example, when the second semiconductor switch 3f is in the on state and the output voltage of the second power supply 2b is higher than that of the first power supply 2a, the current flowing through the field effect transistor M2 becomes in the reverse direction. When the current flowing through the field effect transistor M2 becomes in the reverse direction, the operational amplifier 12a turns on the transistor 14a and pulls down the gate voltage Vga2 to immediately turn off the field effect transistor M2.

[0111] When the current flowing through the field effect transistor M2 is in the forward direction (in the forward direction relative to the body diode), the operational amplifier 13a outputs a high-level signal to the gate of the field effect transistor M2. When the current flowing through the field effect transistor M2 becomes in the forward direction through the boosted power supply operation, the operational amplifier 13a sets the gate voltage Vga2 to a high level to energize the field effect transistor M2.

[0112] The ideal diode control circuit 11a has a structure that allows a diode operation with a suppressed voltage drop. The ideal diode control circuit 11b has a similar structure.

[0113] The ideal diode control circuit 11b includes operational amplifiers 12b and 13b for detecting the current direction based on the drain voltage and source voltage of the field effect transistor M4, and a transistor 14b for adjusting the gate voltage Vgb2 based on the outputs of the operational amplifiers 12b and 13b.

[0114] When the current flowing through the field effect transistor Mf is in the reverse direction (in the reverse direction relative to the body diode), the operational amplifier 12b outputs a high-level signal to the gate of the transistor 14b. For example, when the first semiconductor switch 3e is in the on state and the output voltage of the first power supply 2a is higher than that of the second power supply 2b, the current flowing through the field effect transistor M4 becomes in the reverse direction. When the current flowing through the field effect transistor M4 becomes in the reverse direction, the operational amplifier 12b turns on the transistor 14b and pulls down the gate voltage Vgb2 to immediately turn off the field effect transistor M4.

[0115] When the current flowing through the field effect transistor M4 is in the forward direction (in the forward direction relative to the body diode), the operational amplifier 13b outputs a high-level signal to the gate of the field effect transistor M4. When the boosted power supply is activated and the current flowing through the field effect transistor M4 becomes in the forward direction, the operational amplifier 13b sets the gate voltage Vgb2 to a high level to energize the field effect transistor M4.

[0116] As described above, in the power switching device (power switching device 1D) involved in embodiment 5, the switch control device (switch control device 5D) turns off the field effect transistors (field effect transistors M2, M4) when the current flowing through the field effect transistors whose body diodes are in the forward direction relative to the power supply direction (for example, field effect transistor M2) among multiple field effect transistors constituting a semiconductor switch connected to one power supply source and the field effect transistors whose body diodes are in the forward direction relative to the power supply direction (for example, field effect transistors M2, M4) among multiple field effect transistors (for example, field effect transistor M4) constituting a semiconductor switch connected to another power supply source becomes in the reverse direction relative to the output supply direction.

[0117] In the fourth embodiment, the body diodes of the field effect transistors M2 and M4 are used to form a diode parallel circuit when the power source is switched, but in the case of this structure, there is a problem of increased voltage drop and power loss due to the forward voltage of the body diode. In the present embodiment, a field effect transistor with a small on-resistance is used to form the same function as a diode, thereby preventing damage caused by the through current between the first power supply 2a and the second power supply 2b, and suppressing voltage drop and power loss.

[0118] <Implementation Method 6> Next, the power switching device according to Embodiment 6 is described. In Embodiments 1 and 2, examples are shown in which the gate voltage Vga and the gate voltage Vgb are controlled by setting a two-stage voltage distribution during which the voltage is maintained at an intermediate voltage when the first semiconductor switch 3a and the second semiconductor switch 3b are turned on, but the present invention is not limited thereto. For example, the structure for turning on the first semiconductor switch 3 may be the first structure example to the third structure example shown below.

[0119] (First structural example for turning on a semiconductor switch) First, use Fig.12 and Fig.13 A first configuration for turning on the semiconductor switch 3 will be described. The first configuration is an example in which a gate voltage generated by a voltage source is increased in three or more steps based on a voltage profile.

[0120] Fig.12 1 is a diagram showing a first configuration example for turning on the semiconductor switch 3 of the power supply switching device according to the present embodiment. In the first configuration example, the field effect transistor M of the semiconductor switch 3 is turned on based on the gate voltage generated by the voltage source 15, thereby supplying the power of the power supply source 2 to the load device 4.

[0121] Fig.13 It is a diagram showing an operation example of the semiconductor switch 3 in the first configuration example of the power supply switching device according to the present embodiment. Fig.13 In FIG. 1 , the vertical axis represents the gate voltage of the field effect transistor M, and the horizontal axis represents the time t. Fig.13 , an example of a voltage distribution that increases in three stages via a first intermediate state S21 and a second intermediate state S22 when the gate voltage increases from a low level to a high level is shown. Fig.13 , an example is also shown in which the gate voltage (intermediate voltage) is maintained at a higher value as shown by the dotted line in the first intermediate state S21 and the second intermediate state S22. In addition, not only the value of the intermediate voltage in the first intermediate state S21 and the second intermediate state S22, but also the holding time Tm in the first intermediate state S21 and the second intermediate state S22 can be appropriately changed.

[0122] (Second structural example for turning on a semiconductor switch) Next, use Fig.14 and Fig.15 Next, a second structure for turning on the semiconductor switch 3 is described. The second structure is an example in which the gate voltage is controlled by a current source using a resistance component and an electrostatic capacitance component of an external circuit connected to the gate of the field effect transistor.

[0123] Fig.14 1 is a diagram showing a second structural example for turning on the semiconductor switch 3 of the power supply switching device involved in the present embodiment. In the second structural example, the current source 16 is connected to the gate of the field effect transistor M of the semiconductor switch 3 via the resistor 17. In addition, one end of the capacitor 18 is connected to the connection midpoint between the gate of the field effect transistor M and the resistor 17, and the other end of the capacitor 18 is grounded. The resistor 17 and the capacitor 18 constitute a so-called CR circuit. The current output from the current source 16 is input to the gate through the CR circuit, and the field effect transistor M of the semiconductor switch 3 becomes conductive, thereby supplying the power of the power supply source 2 to the load device 4. The CR circuit can be used to adjust the value of the gate voltage (intermediate voltage) and the holding time Tm in the intermediate state.

[0124] Fig.15 FIG. 2 is a diagram showing an operation example of the semiconductor switch 3 in the second configuration example of the power supply switching device according to the present embodiment. Fig.15 As shown, by adjusting the time constant of the CR circuit, the speed at which the gate voltage rises from a low level to a high level (equivalent to the holding time Tm) can be changed. For example, by reducing the time constant of the CR circuit, the rise of the gate voltage can be accelerated to shorten the intermediate state (holding time Tm). In addition, if the amount of current provided by the current source 16 is increased, the gate voltage rises to a high level more quickly. That is, the holding time Tm in which the gate voltage is within the range of the intermediate voltage (intermediate state) can be adjusted by the amount of current provided by the current source 16. In this case, the gate voltage in the intermediate state will not be maintained at a constant value like the intermediate voltage Vm mentioned above.

[0125] (Third structural example for turning on a semiconductor switch) Next, use Fig.16 and Fig.17 Next, the third structure for turning on the semiconductor switch 3 is described. The third structure is an example in which a PWM (Pulse Width Modulation) generator is provided and a PWM waveform is input to the gate as an intermediate state. In this structure, the semiconductor switch can also be provided with an intermediate state, and the same effect as the above structure example can be obtained.

[0126] Fig.16 1 is a diagram showing a third configuration example for turning on the semiconductor switch 3 of the power supply switching device according to the present embodiment. Fig.16 The third structural example shown is constituted by Fig.12 The voltage source 15 is replaced by a PWM generator 19. In the third structural example, the field effect transistor M of the semiconductor switch 3 becomes conductive based on the PWM signal output by the PWM generator 19, thereby supplying the power of the power supply source 2 to the load device 4. At this time, the intermediate state (intermediate voltage) of the gate voltage is generated by controlling the duty ratio of the PWM signal.

[0127] Fig.17 1 is a diagram showing an operation example of the semiconductor switch 3 in the third configuration example of the power switching device according to the present embodiment. By controlling the duty ratio of the PWM signal, the gate voltage in the intermediate state (equivalent to the intermediate voltage Vm) can be adjusted. For example, by setting the duty ratio of the PWM signal to be constant, the gate voltage is maintained at the intermediate voltage Vm. In addition, the application time of the PWM signal (the repetition period of the low level and the high level) is equivalent to the holding time Tm of the intermediate state.

[0128] [Computer hardware structure] Next, with respect to the hardware configuration of the computer included in the power switching device in each of the above-mentioned embodiments, refer to Fig.18 To explain.

[0129] Fig.18 It is a block diagram showing a hardware configuration example of a computer included in the power supply switching device according to each embodiment. Fig.18 The computer 20 shown is hardware used as a so-called computer.

[0130] The computer 20 includes a CPU (Central Processing Unit) 21, a ROM (Read Only Memory) 22, a RAM (Random Access Memory) 23, a nonvolatile memory 26, and a network interface 27, which are respectively connected to a bus.

[0131] The CPU 21 is an example of a processor as an arithmetic device. The ROM 22 and the RAM 23 are examples of memories. For example, the load information 8A is stored in the ROM 22 or the nonvolatile memory 26 .

[0132] The nonvolatile memory 26 is a nonvolatile storage element having a larger capacity than the memory. A program for realizing the functions of the power switching device involved in each embodiment of the present invention is stored in the nonvolatile memory 26. The nonvolatile memory 26 is an example of a computer-readable non-temporary recording medium. In addition, the program can also be stored in the ROM 22.

[0133] The network interface 27 is constituted by a communication device, etc., which controls communication with other devices (for example, ECU) via a communication line, a network such as CAN, etc. The network interface 27 is an example of an input / output device.

[0134] in addition, Fig.18 In the above description, an example of the hardware configuration of a computer included in the power supply switching device is described, but the hardware configuration of a computer included in the controller 111 can also be set to the same configuration.

[0135] In addition, the present invention is not limited to the above-mentioned embodiment examples, and various other application examples and modified examples can be obtained as long as they do not deviate from the main points of the present invention described in the claims. For example, the above-mentioned embodiment describes its structure in detail and specifically in order to easily understand the present invention, and is not limited to an embodiment having all the described constituent elements. In addition, a part of the structure of a certain embodiment can be replaced with constituent elements of other embodiments. In addition, constituent elements of other embodiments can be added to the structure of a certain embodiment. In addition, other constituent elements can be added, replaced or deleted to a part of the structure of each embodiment.

[0136] In addition, the above-mentioned components, functions, processing units, etc. may be partially or entirely implemented by hardware, for example, by integrated circuit design, etc. As hardware, a general processor device such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit) may be used.

[0137] In addition, in the above-mentioned embodiment, the control lines and information lines necessary for explanation are shown, but it is not limited to showing all the control lines and information lines necessary for the product. In fact, it can be considered that almost all the structural elements are connected to each other. Description of symbols

[0138] 1. 1A~1D power switching device 2a 1st power supply 2b Second power supply 3Semiconductor switch 3a, 3c, 3e: 1st semiconductor switch 3b, 3d, 3f: Second semiconductor switch 4. 4a~4c Load Devices 5. 5A~5D switch control device 6, 6A, 6C gate voltage control circuit 7 Voltage Comparator 8A Load Information 9a~9c load switch 10 Load switch control device 11a, 11b Ideal diode control circuit 12a, 12b, 13a, 13b operational amplifiers 14a, 14b transistors 15 Voltage Source 16 Current Source 19 PWM Generator 100 Vehicles 110 Vehicle Control Device 120 Sensors 130 Actuator Class.

Claims

1. A power switching device, comprising: a first semiconductor switch disposed between a first power supply source for supplying power to a load device and the load device; a second semiconductor switch provided between a second power supply source for supplying power to the load device and the load device; and a switch control device for controlling a driving voltage of the first semiconductor switch and the second semiconductor switch, wherein the power supply switching device is characterized in that: When switching from one power supply to the other of the first power supply and the second power supply, the switch control device is configured to maintain the semiconductor switch of the power supply connected to the power supply side after switching in an intermediate state of a non-saturated state, and to change the holding time of the intermediate state according to the voltage difference between the voltages output by the first power supply and the second power supply.

2. The power switching device according to claim 1, wherein: The switch control device changes the holding time in a direction longer than a reference time when the voltage difference is larger than a predetermined value, and changes the holding time in a direction shorter than the reference time when the voltage difference is less than a predetermined value.

3. The power switching device according to claim 2, wherein: The switch control device changes a holding time of the intermediate state based on the voltage difference and information indicating an electrical characteristic of the load device.

4. The power switching device according to claim 3, characterized in that: An output end of the first semiconductor switch and an output end of the second semiconductor switch are electrically connected, and a plurality of load devices are connected to the output ends.

5. The power switching device according to claim 4, characterized in that: The switch control device changes the holding time of the intermediate state based on information indicating electrical characteristics of a load device in an energized state among the plurality of load devices.

6. The power switching device according to claim 5, characterized in that: Before the switch control device switches from one power supply source to another power supply source, the power supply to any load device among the plurality of load devices is stopped; The switch control device changes the holding time of the intermediate state based on information indicating electrical characteristics of a load device in an energized state among the plurality of load devices.

7. The power switching device according to claim 1, wherein: The first semiconductor switch and the second semiconductor switch are each formed by connecting a plurality of field effect transistors in series so that the body diodes are in reverse direction. When switching from one power supply source to another, the switch control device is configured to maintain the field effect transistor whose body diode is on the opposite side with respect to the power supply direction in an intermediate state of a non-saturated state, and to change the holding time of the intermediate state according to the voltage difference between the voltages output by the first power supply source and the second power supply source.

8. The power switching device according to claim 7, wherein: When switching from one power supply source to another, the switch control device is set to maintain an intermediate state of the field effect transistor in which the body diode is on the opposite side with respect to the power supply direction in a non-saturated state, and changes the holding time of the intermediate state according to information representing the electrical characteristics of the load device.

9. The power switching device according to claim 7 or 8, characterized in that: When switching from one power supply source to another power supply source, the switch control device sets the field effect transistor of the other power supply source to an intermediate state before the power supply of one power supply source is cut off.

10. The power switching device according to claim 7 or 8, characterized in that: The switch control device is configured such that, when the current flowing through a field effect transistor whose body diode is in a forward direction with respect to the power supply direction among a plurality of field effect transistors constituting a semiconductor switch connected to one power supply source and a field effect transistor whose body diode is in a forward direction with respect to the power supply direction among a plurality of field effect transistors constituting a semiconductor switch connected to another power supply source becomes in a reverse direction with respect to the output supply direction, The field effect transistor is turned off.

11. The power switching device according to claim 3 or 8, characterized in that: The information indicating the electrical characteristics of the load device includes at least equivalent resistance and equivalent electrostatic capacitance.

12. A vehicle control device, comprising a controller for controlling a vehicle, and a power switching device, wherein the vehicle control device is characterized in that: The power switching device includes: a first semiconductor switch provided between a first power supply source for supplying power to a load device provided in the vehicle and the load device; a second semiconductor switch provided between a second power supply source for supplying power to the load device and the load device; and a switch control device for controlling a driving voltage of the first semiconductor switch and the second semiconductor switch. When switching from one power supply to the other of the first power supply and the second power supply, the switch control device is configured to maintain the semiconductor switch of the power supply connected to the power supply side after switching in an intermediate state of a non-saturated state, and to change the holding time of the intermediate state according to the voltage difference between the voltages output by the first power supply and the second power supply.

13. A power switching method, which is a power switching method performed by a power switching device, the power switching device comprising: a first semiconductor switch disposed between a first power supply source for supplying power to a load device and the load device; A second semiconductor switch provided between a second power supply source for supplying power to the load device and the load device; and a switch control device for controlling a driving voltage of the first semiconductor switch and the second semiconductor switch, wherein the power supply switching method is characterized in that: In the switch control device, when switching from one of the first power supply source and the second power supply source to the other power supply source, the semiconductor switch connected to the power supply source on the power supply side after switching is maintained in an intermediate state of a non-saturated state, and a voltage difference between the voltages output by the first power supply source and the second power supply source is detected, The holding time of the intermediate state is changed according to the voltage difference.

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