MEMS inertial chip and preparation method thereof

Abstract

The invention relates to the technical field of inertial devices, and provides an MEMS inertial chip which comprises an ASIC wafer and an MEMS inertial device and further comprises a TEC, the TEC, the ASIC wafer and the MEMS inertial device are sequentially arranged in a laminated mode, the MEMS inertial device comprises a cover body and a movable unit, and the ASIC wafer and the cover body are matched to seal the movable unit. The invention also provides a preparation method of the MEMS inertial chip. The ASIC wafer serves as the lower cover of the MEMS inertial device, mechanical protection and sealing of the movable unit of the MEMS inertial device can be achieved through bonding, a lower cover structure does not need to be independently and additionally prepared, the technology is effectively simplified, and meanwhile the size and the volume of an integrated chip are effectively reduced. The MEMS inertial device and the TEC are integrated, the temperature environment on the periphery of the device can be effectively controlled, the temperature effect of the device is reduced, the change of parameters such as scale factors and zero offset of the device along with the temperature is reduced, and the performance of the device is further improved.

Description

Technical Field

[0001] The present invention relates to the technical field of inertial devices, and in particular to a MEMS inertial chip and a preparation method thereof. Background Art

[0002] Inertial devices include accelerometers and gyroscopes and their various combinations. Accelerometers are used to measure the acceleration of an object, and gyroscopes are used to measure the angular velocity of an object. The comprehensive test of acceleration and angular velocity can clearly characterize the motion state of the object to be tested. Accurate measurement of acceleration and angular velocity requires a stable environment around the device, such as stable temperature. Temperature changes will affect the performance of the device.

[0003] The existing packaging methods of MEMS inertial meter head units and ASIC units are all prepared separately and then packaged in a decentralized manner, without a temperature control module. The overall volume of the decentralized packaged inertial device is large, and the space utilization rate is not high; the decentralized packaging has low efficiency; the decentralized packaging has different process consistency between different batches; the lack of a temperature control module makes the temperature effect of the device too large, affecting the performance and stability of the chip. Summary of the invention

[0004] The object of the present invention is to provide a MEMS inertial chip and a method for preparing the same, which can at least solve some of the defects in the prior art.

[0005] To achieve the above-mentioned purpose, an embodiment of the present invention provides the following technical solution: a MEMS inertial chip, comprising an ASIC wafer and a MEMS inertial device, and also comprising a TEC, wherein the TEC, the ASIC wafer and the MEMS inertial device are stacked in sequence, the MEMS inertial device comprises a cover body and an active unit, and the ASIC wafer and the cover body cooperate to seal the active unit.

[0006] Furthermore, the ASIC wafer is provided with a plurality of signal lead-out terminals, and the MEMS inertial device is bonded to at least part of the signal lead-out terminals on the ASIC wafer.

[0007] Furthermore, the TEC and the ASIC wafer both have signal lead-out through holes, the signal lead-out through holes are filled with metal, the signal lead-out through holes of the TEC are aligned with the signal lead-out through holes of the ASIC wafer, and the metal in the signal lead-out through holes of the TEC is bonded to the metal in the corresponding signal lead-out through holes of the ASIC wafer.

[0008] Furthermore, the TEC is provided with one or more layers of PN junctions, each layer of the PN junctions having a P-type doping layer and a plurality of N-type doping points; wherein the P-type doping layer has a plurality of the N-type doping points, and the N-type doping points are arranged at intervals.

[0009] Furthermore, a PN junction is provided in the TEC, and the PN junction has a plurality of P-type doping points and a plurality of N-type doping points, and each of the P-type doping points and each of the N-type doping points are provided in one-to-one correspondence.

[0010] Furthermore, an insulating layer is applied on the ASIC wafer, and a plurality of metal layers electrically connected to the ASIC wafer are provided in the insulating layer, and the metal layers are arranged at intervals, and the signal lead-out terminals are located on the metal layers.

[0011] Furthermore, the cover is disposed on the movable unit through an insulating member; or an edge of the cover extends to an insulating portion of the ASIC wafer.

[0012] The embodiment of the present invention provides another technical solution: a method for preparing a MEMS inertial chip, comprising the following steps:

[0013] S1, manufacturing a TEC, an ASIC wafer and a MEMS inertial device, wherein the MEMS inertial device has a cover and an active unit;

[0014] S2, bonding the ASIC wafer to the TEC along the chip thickness direction, bonding the MEMS inertial device to the ASIC wafer, and the ASIC wafer and the cover body cooperate to seal the active unit;

[0015] S3, making signal lead-out wires to lead out signals from the MEMS inertial device, the ASIC wafer, and the TEC.

[0016] Further, the preparation method of the TEC is:

[0017] Making a P-type doping layer and making a plurality of N-type doping points on the P-type doping layer, wherein the N-type doping points are arranged at intervals, and the P-type doping layer and the N-type doping points form a PN junction layer; making an insulating layer above the PN junction layer;

[0018] Repeat the above steps X times on the insulating layer, where X≥1, to conduct at least one PN junction layer and electrically connect it to the signal lead-out line.

[0019] Further, the preparation method of the TEC is:

[0020] Making a plurality of P-type doping points, wherein the P-type doping points are arranged at intervals, and making an N-type doping point next to each of the P-type doping points, wherein adjacent P-type doping points and N-type doping points form a PN junction;

[0021] Each of the PN junctions is turned on, and at least one of the PN junctions is electrically connected to the signal lead line.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] 1. As the lower cover of the MEMS inertial device, the ASIC wafer can achieve mechanical protection and sealing of the active unit of the MEMS inertial device through bonding, without the need to prepare a separate lower cover structure, effectively simplifying the process and effectively reducing the size and volume of the integrated chip.

[0024] 2. Integrating MEMS inertial devices with TEC effectively controls the temperature environment around the device, reduces the changes in device parameters such as scale factor and zero bias with temperature, and thus improves device performance.

[0025] 3. By designing an array PN junction in TEC, the total number of PN junctions can be increased, thereby increasing the cooling capacity of the refrigerator.

[0026] 4. MEMS inertial devices, ASIC wafers and TEC are integrated through bonding and directly interconnected by metal layers, which reduces the distance between interconnection leads and effectively reduces the chip area. At the same time, direct metal layer interconnection has higher reliability.

[0027] 5. MEMS inertial devices, ASIC wafers and TEC all use semiconductor processes, which are compatible with each other and can be mass-produced. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of a first form of a MEMS inertial chip provided by an embodiment of the present invention;

[0029] Figure 2 A schematic diagram of a second form of a MEMS inertial chip provided by an embodiment of the present invention;

[0030] Figure 3 A schematic diagram of a third form of a MEMS inertial chip provided by an embodiment of the present invention;

[0031] Figure 4 A schematic diagram of a fourth form of a MEMS inertial chip provided by an embodiment of the present invention;

[0032] Figure 5 A schematic diagram of the manufacturing process of a TEC of a MEMS inertial chip provided in an embodiment of the present invention;

[0033] Figure 6 A schematic diagram of another TEC manufacturing process of a MEMS inertial chip provided in an embodiment of the present invention;

[0034] Figure 7 for Figure 1Schematic diagram of the manufacturing process of the MEMS inertial chip (showing the first step, the second step and the third step);

[0035] Figure 8 for Figure 1 Schematic diagram of the manufacturing process of the MEMS inertial chip (showing the fourth step, the fifth step and the sixth step);

[0036] Fig. 9 for Figure 1 Schematic diagram of the manufacturing process of the MEMS inertial chip (showing the seventh and eighth steps). DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] See also Figure 1 , Figure 2 , Figure 3 and Figure 4 The embodiment of the present invention provides a MEMS inertial chip, including an ASIC wafer 2 and a MEMS inertial device 3, wherein the MEMS inertial device 3 includes a cover body and an active unit, and the ASIC wafer 2 is provided with a plurality of signal lead-out terminals, and the MEMS inertial device 3 is bonded to at least part of the signal lead-out terminals on the ASIC wafer 2, and the ASIC wafer 2 and the cover body cooperate to seal the active unit. In this embodiment, secondary wiring is performed on the prepared ASIC wafer 2, and the signal lead-out method is flexible. At the same time, the ASIC (integrated circuit) wafer serves as the lower cover of the MEMS inertial device 3. After bonding, the mechanical protection and sealing of the active unit of the MEMS inertial device 3 can be achieved, and there is no need to prepare a lower cover structure separately, which can effectively simplify the process and effectively reduce the size and volume of the integrated chip. Preferably, the chip further comprises a TEC (semiconductor refrigerator) wafer, wherein the TEC1, the ASIC wafer 2 and the MEMS inertial device 3 are sequentially stacked, and the ASIC wafer 2 is bonded to the TEC1. The MEMS inertial device 3 is integrated with the TEC1, which can effectively control the temperature environment around the device, reduce the changes of the device's parameters such as the scale factor and zero bias with temperature, and thus improve the performance of the device.

[0039] As an optimization solution of the embodiment of the present invention, please refer to Figure 1 , Figure 2 , Figure 3 and Figure 4TEC1 and MEMS inertial device 3 may have different forms. MEMS inertial device 3 may include accelerometer 30 and gyroscope 31. Figure 1 As shown, the cover body of the MEMS inertial device 3 is consistent with the size of the active unit, and is matched with the insulating member (i.e. Figure 8 The device insulating layer 402 in the fifth step of the invention is used to seal the active unit of the accelerometer and the active unit of the gyroscope. At this time, a cover can be used. The design of the PN junction in TEC1 is as follows: the TEC is provided with one or more layers of PN junctions, each layer of the PN junction has a P-type doping layer and a plurality of N-type doping points; wherein the P-type doping layer has a plurality of the N-type doping points, and each of the N-type doping points is arranged at intervals. Figure 2 As shown, the edge of the cover body used by the MEMS inertial device 3 extends to the insulating portion of the ASIC wafer 2 (ie Figure 7 The insulating layer 301 of the secondary wiring in the second step is used to seal the active unit of the accelerometer and the active unit of the gyroscope. At this time, a cover body can be used. The design of the PN junction in TEC1 is the same as Figure 1 The same. Figure 3 As shown, the MEMS inertial device 3 and Figure 1 The design of the PN junction in TEC1 is consistent with the design of the PN junction in TEC1: the TEC is provided with a PN junction, the PN junction has a plurality of P-type doping points and a plurality of N-type doping points, and each of the P-type doping points and each of the N-type doping points are arranged in a one-to-one correspondence. Figure 4 As shown, the MEMS inertial device 3 has two covers, one of which cooperates with the ASIC wafer 2 to seal the active unit of the accelerometer, and the other covers cooperates with the ASIC wafer 2 to seal the active unit of the gyroscope. The design of the PN junction in TEC1 is similar to Figure 3 of consistency.

[0040] As an optimization solution of the embodiment of the present invention, please refer to Figure 1 , Figure 2 , Figure 3 and Figure 4 , the TEC1 and the ASIC wafer 2 both have signal lead-out holes, the signal lead-out holes are filled with metal, the signal lead-out holes of the TEC1 are aligned with the signal lead-out holes of the ASIC wafer 2, and the metal in the signal lead-out holes of the TEC1 is bonded with the metal in the corresponding signal lead-out holes of the ASIC wafer 2, so as to realize the electrical connection and conduction between the ASIC wafer 2 and the TEC1. In this embodiment, by designing vertical signal lead-out holes and then filling the holes with metal for conduction, the distance between interconnection leads can be reduced, effectively reducing the chip area, and at the same time, the direct interconnection of metal layers has higher reliability.

[0041] As an optimization solution of the embodiment of the present invention, please refer to Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 7 , Figure 8 and Fig. 9 An insulating layer is applied on the ASIC wafer 2, and a plurality of metal layers electrically connected to the ASIC wafer 2 are provided in the insulating layer, and the metal layers are arranged at intervals, and the signal lead-out terminal is located on the metal layer. In this embodiment, secondary wiring is performed on the ASIC wafer 2, and the secondary wiring includes an insulating layer 301 and a metal layer 302, so that the signal lead-out terminal can be easily set.

[0042] As an optimization solution of the embodiment of the present invention, please refer to Figure 7 , Figure 8 and Fig. 9 The chip further includes a signal lead-out line for leading out the signals of the MEMS inertial device 3, the ASIC wafer 2 and the TEC1. Preferably, the signal lead-out line is arranged on the ASIC wafer 2. In this embodiment, the signal lead-out line is a metal bonding wire 501, and the metal bonding wire 501 is used for signal lead-out. After bonding, electrical conduction between the MEMS inertial device 3, the ASIC wafer 2 and the TEC1 can be achieved, and the signals of the three can be longitudinally led out simultaneously on the surface of the ASIC wafer 2.

[0043] See also Figures 1 to 9The embodiment of the present invention provides a method for preparing a MEMS inertial chip, comprising the following steps: S1, manufacturing TEC1, ASIC wafer 2 and MEMS inertial device 3, wherein the MEMS inertial device 3 has a cover and an active unit; S2, bonding the ASIC wafer 2 to the TEC1 along the thickness direction of the chip, bonding the MEMS inertial device 3 to the ASIC wafer 2, wherein the ASIC wafer 2 and the cover cooperate to seal the active unit; S3, manufacturing signal lead wires to lead out the signals of the MEMS inertial device 3, the ASIC wafer 2 and the TEC1. In this embodiment, secondary wiring is performed on the prepared ASIC wafer 2, and the signal lead-out method is flexible. At the same time, the ASIC wafer 2 serves as the lower cover of the MEMS inertial device 3. After bonding, the mechanical protection and sealing of the active unit of the MEMS inertial device 3 can be achieved, and there is no need to prepare the lower cover structure separately, which can effectively simplify the process and effectively reduce the size and volume of the integrated chip. Integrating the MEMS inertial device 3 with TEC1 can effectively control the temperature environment around the device, reduce the temperature effect of the device (reduce the change of scale factor, zero bias, etc. with temperature), and improve the performance of the device. The MEMS inertial device 3, ASIC wafer 2 and TEC1 are integrated by bonding, and the metal layer is directly interconnected, which reduces the distance between the interconnection leads, effectively reduces the chip area, and the direct metal layer interconnection has higher reliability. The MEMS inertial device 3, ASIC wafer 2 and TEC1 all use semiconductor processes, which are compatible with each other and can be mass-produced.

[0044] like Figure 5 As shown, one of the preparation methods of TEC1 is shown:

[0045] Making a P-type doping layer and making a plurality of N-type doping points on the P-type doping layer, wherein the N-type doping points are arranged at intervals, and the P-type doping layer and the N-type doping points form a PN junction layer; making an insulating layer above the PN junction layer;

[0046] Repeat the above steps X times on the insulating layer. When X is 1, it is in the form of a single PN junction. When X is greater than 1, it is in the form of multiple PN junctions. Adjacent PN junction layers are turned on, and at least one PN junction layer is electrically connected to the signal lead line.

[0047] The above methods are as follows:

[0048] S101, depositing an oxide layer 101 and a first metal heat sink 102 on a substrate 100 in sequence, wherein the oxide layer 101 is used for insulation between the first metal heat sink 102 and the substrate 100;

[0049] S102, manufacturing a first P-type doped layer 103 and a first insulating layer a on the first metal heat sink 102, wherein the first P-type doped layer 3 and the first insulating layer a are arranged side by side, and the upper surface of the first insulating layer a is flush with the upper surface of the first P-type doped layer 103, and the first insulating layer a is used as insulation for the region;

[0050] S103, then forming a plurality of first N-type doping points 104 on the first P-type doping layer 103, wherein the first N-type doping points 104 are arranged at intervals;

[0051] S104, forming a second insulating layer b on the first N-type doping point, wherein the second insulating layer completely covers the first N-type doping point and the first P-type doping layer 103, and opening a window on the second insulating layer b to form an interconnection metal 105, wherein the interconnection metal 105 is electrically connected to the first P-type doping layer 103; the second insulating layer b is also used for insulation, and the first P-type doping layer 103 and the first N-type doping point 104 form a first-layer PN junction;

[0052] S105, continue to form a second P-type doped layer 106, the second P-type doped layer 106 covers a portion of the second insulating layer b and is conductively connected to the interconnect metal 105, and form a third insulating layer c on a portion of the second insulating layer b that is not covered, and make the surface of the third insulating layer c flush with the surface of the second P-type doped layer 106;

[0053] S106, forming a plurality of second N-type doping points 107 on the second P-type doping layer 106, wherein the second N-type doping points 107 are arranged at intervals; forming a fourth insulating layer d, wherein a portion of the fourth insulating layer d extends into the intervals between the second N-type doping points 107 and another portion of the fourth insulating layer d covers the third insulating layer c, and the fourth insulating layer d is made to have the same height as the second N-type doping points 107, and the third insulating layer is also used for insulation, the second P-type doping layer 106 and the second N-type doping points 107 form a second layer of PN junctions, and the first layer of PN junctions and the second layer of PN junctions are connected in series through the interconnecting metal 105, thereby increasing the total number of PN junctions and increasing the cooling capacity of the refrigerator;

[0054] S107, continue to make a second metal heat sink 108, the second metal heat sink 108 covers each of the second N-type doping points 107; make a fifth insulating layer e, the fifth insulating layer completely covers the second metal heat sink;

[0055] S108, making a first signal lead-out through hole and a second signal lead-out through hole; along the depth direction of the fifth insulating layer e, penetrating the fifth insulating layer e to form a first signal lead-out through hole 109, the first signal lead-out through hole 109 is connected to the second metal heat sink 108, and the first signal lead-out through hole 109 is filled with metal; along the depth direction of the fifth insulating layer e, penetrating the fifth insulating layer e, the fourth insulating layer d, the third insulating layer c, the second insulating layer b and the first insulating layer a in sequence to form The second signal lead-out through hole 110 is connected to the first metal heat sink 102, and metal is filled in the second signal lead-out through hole 110. The first signal lead-out through hole 109 leads out signals from the series-connected N-type doping points, and the second signal lead-out through hole 110 leads out signals from the series-connected P-type doping layers. The first metal heat sink 102 and the second metal heat sink 108 not only serve as heat sinks, but also connect the first and second PN junction arrays in series in the plane, respectively, to increase the number of PN junctions and the cooling capacity.

[0056] like Figure 6 As shown, another method for preparing TEC1 is as follows:

[0057] First, a plurality of P-type doping points are made, each of which is arranged at intervals, and an N-type doping point is made next to each of the P-type doping points, and adjacent P-type doping points and N-type doping points form a PN junction; then, each of the PN junctions is turned on, and at least one of the PN junctions is electrically connected to the signal lead line.

[0058] The above methods are as follows:

[0059] S111, depositing an oxide layer 101 and a first metal heat sink 102 on the substrate 100 in sequence, wherein the oxide layer 101 is used for insulation between the first metal heat sink 102 and the substrate 100;

[0060] S112, manufacturing a plurality of first interconnection metals 111 on the first metal heat sink 102, wherein the first interconnection metals 111 are arranged at intervals; manufacturing a first insulating layer a, wherein the first insulating layer a extends into the intervals between the first interconnection metals 111, and the first insulating layer a is used for insulation;

[0061] S113, continue to make a plurality of P-type doping points 103, each of the P-type doping points 103 is arranged at intervals, part of the P-type doping points 103 is arranged on the first insulating layer a, and another part of the P-type doping points 103 is arranged on the first interconnect metal 111; make a second insulating layer b, part of the second insulating layer b extends into the intervals between the P-type doping points 103 and another part of the second insulating layer b covers the first insulating layer a;

[0062] S114, making an N-type doping point 104 next to each of the P-type doping points 103, the adjacent P-type doping points 103 and the N-type doping points 104 form a PN junction, and an oxide layer exists between different PN junctions for insulation;

[0063] S115, forming a second interconnection metal 112 on a portion of the N-type doped points 104, wherein the portion of the N-type doped points 104 is the N-type doped points 104 corresponding to the P-type doped points 103 without the first interconnection metal 111; forming a third insulating layer c, wherein a portion of the third insulating layer c extends into the gap between each of the second interconnection metals 112 and another portion of the third insulating layer c covers the second insulating layer b;

[0064] S116, continue to make a second metal heat sink 108, the second metal heat sink 108 covers the third insulating layer c and each of the second interconnecting metals 112; make a fourth insulating layer d, part of the fourth insulating layer d covers the second metal heat sink 108 and another part of the fourth insulating layer d covers the third insulating layer c, the N-type doping point 104 is connected to the second metal heat sink 108 through the interconnecting metal 112, and all PN junctions are connected in series through the PN junction and the first interconnecting metal 111 and the second interconnecting metal 112, so as to increase the total number of PN junctions and increase the cooling capacity of the refrigerator;

[0065] S117, further manufacturing a fifth insulating layer e, wherein a portion of the fifth insulating layer e covers the second metal heat sink 112, and another portion of the fifth insulating layer e covers the fourth insulating layer d; along the depth direction of the fifth insulating layer e, sequentially penetrating the fifth insulating layer e, the fourth insulating layer d and the third insulating layer c to form a first signal lead-out through hole 109 and a second signal lead-out through hole 110, wherein the first signal lead-out through hole 109 and the second signal lead-out through hole 110 are arranged at intervals, and the first signal lead-out through hole 109 connects the second metal heat sink 112 and one of the first signal lead-out through holes 109 and 110. The N-type doping point 104, the second signal lead-out through hole 110 is connected to the P-type doping point 103 corresponding to the N-type doping point 104, the first signal lead-out through hole 109 and the second signal lead-out through hole 110 are both filled with metal, the first signal lead-out through hole 109 leads the signal of the series-connected N-type doping point 104, and the second signal lead-out through hole 110 leads the signal of the series-connected P-type doping point 103, the first metal heat sink 102 and the second metal heat sink 108 not only serve as heat sinks, but also connect the PN junction arrays in series respectively, thereby increasing the number of PN junctions and increasing the cooling capacity.

[0066] See also Figure 7 , Figure 8 and Fig. 9 ,for Figure 1The specific preparation method of the MEMS inertial chip shown is based on the above embodiments:

[0067] (1) Use Figure 5 The prepared TEC1 has a longitudinal signal lead-out hole, namely Figure 5 A first signal lead-out through hole 109 and a second signal lead-out through hole 110;

[0068] (2) Perform secondary wiring on the upper surface of the ASIC wafer 2 to obtain Figure 7 The insulating layer 301 and the metal layer 302 shown in FIG. 1 are used to perform secondary wiring inside the ASIC wafer 2 to obtain the following Figure 7 The signal lead-out through hole 204 and the signal lead-out through hole 205 are shown, both of which are filled with metal for conducting electricity, and the two through holes penetrate the substrate 201 and the insulating layer 203 of the ASIC wafer 2, and the two through holes are connected to the electrical traces in the ASIC wafer 2;

[0069] (3) Align TEC1 with ASIC wafer 2, and then align the signal lead-out through hole of TEC with the signal lead-out through hole of ASIC;

[0070] (4) Bonding TEC1 to ASIC wafer 2;

[0071] (5) Processing and preparing a MEMS inertial device 3, wherein the MEMS inertial device 3 includes a cover 401, a device insulating layer 402, an active unit 403, and a device metal layer 404, wherein the active unit 403 is divided according to the selected inertial device. For example, when an accelerometer and a gyroscope are used, the active unit 403 can be an active unit of the accelerometer and an active unit of the gyroscope;

[0072] (6) Aligning the MEMS inertial device 3 with the bonded ASIC wafer 2 and TEC1;

[0073] (7) After alignment is completed, the MEMS inertial device 3 is bonded to the already bonded ASIC wafer 2 and TEC1, that is, the device metal layer 404 is bonded to the metal layer 302 of the ASIC wafer 2. After bonding, a metal direct interconnection with a shorter interconnection distance and higher reliability is formed between the three-layer structure. The ASIC wafer 2 serves as the lower cover of the movable unit of the MEMS inertial device 3. There is no need to make an additional lower cover. After bonding, the mechanical protection and sealing of the movable unit of the MEMS inertial device 3 can be achieved;

[0074] (8) Metal bonding wires 501 are provided for signal extraction. Electrical conduction among the MEMS inertial device 3, the ASIC device, and the TEC is achieved through bonding. The signals of the three can be simultaneously extracted longitudinally on the surface of the ASIC wafer 2.

[0075] It should be noted that the above content is only for Figure 1 The preparation method of the MEMS inertial chip shown is described in detail. Figure 2 , Figure 3 and Figure 4 The specific preparation method of the MEMS inertial chip shown can refer to the above embodiments and will not be repeated here.

[0076] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A MEMS inertial chip, comprising an ASIC wafer and a MEMS inertial device, characterized in that: It also includes TEC. The TEC, the ASIC wafer and the MEMS inertial device are stacked in sequence. The MEMS inertial device includes a cover body and an active unit. The ASIC wafer and the cover body cooperate to seal the active unit.

2. The MEMS inertial chip according to claim 1, characterized in that: The ASIC wafer is provided with a plurality of signal lead-out terminals, and the MEMS inertial device is bonded to at least part of the signal lead-out terminals on the ASIC wafer.

3. The MEMS inertial chip according to claim 1, characterized in that: The TEC and the ASIC wafer both have signal lead-out through holes, the signal lead-out through holes are filled with metal, the signal lead-out through holes of the TEC are aligned with the signal lead-out through holes of the ASIC wafer, and the metal in the signal lead-out through holes of the TEC is bonded to the metal in the corresponding signal lead-out through holes of the ASIC wafer.

4. The MEMS inertial chip according to claim 1, characterized in that: The TEC is provided with one or more layers of PN junctions, each of which has a P-type doping layer and a plurality of N-type doping points; wherein the P-type doping layer has a plurality of N-type doping points, and the N-type doping points are arranged at intervals.

5. The MEMS inertial chip according to claim 1, characterized in that: A PN junction is provided in the TEC, and the PN junction has a plurality of P-type doping points and a plurality of N-type doping points, and each of the P-type doping points and each of the N-type doping points are arranged in a one-to-one correspondence.

6. The MEMS inertial chip according to claim 1, characterized in that: An insulating layer is applied on the ASIC wafer, and a plurality of metal layers electrically connected to the ASIC wafer are arranged in the insulating layer. The metal layers are arranged at intervals, and the signal lead-out terminals are located on the metal layers.

7. The MEMS inertial chip according to claim 1, characterized in that: The cover is arranged on the movable unit through an insulating member; or the edge of the cover extends to the insulating part of the ASIC wafer.

8. A method for preparing a MEMS inertial chip, characterized in that: The steps include: S1, manufacturing a TEC, an ASIC wafer and a MEMS inertial device, wherein the MEMS inertial device has a cover and an active unit; S2, bonding the ASIC wafer to the TEC, bonding the MEMS inertial device to the ASIC wafer, and the ASIC wafer and the cover cooperate to seal the active unit; S3, making signal lead-out wires to lead out signals from the MEMS inertial device, the ASIC wafer, and the TEC.

9. The method for preparing a MEMS inertial chip according to claim 8, characterized in that: The preparation method of the TEC is: Making a P-type doping layer and making a plurality of N-type doping points on the P-type doping layer, wherein the N-type doping points are arranged at intervals, and the P-type doping layer and the N-type doping points form a PN junction layer; making an insulating layer above the PN junction layer; Repeat the above steps X times on the insulating layer, where X≥1, to conduct at least one PN junction layer and electrically connect it to the signal lead-out line.

10. The method for preparing a MEMS inertial chip according to claim 8, characterized in that: The preparation method of the TEC is: Making a plurality of P-type doping points, wherein the P-type doping points are arranged at intervals, and making an N-type doping point next to each of the P-type doping points, wherein adjacent P-type doping points and N-type doping points form a PN junction; Each of the PN junctions is turned on, and at least one of the PN junctions is electrically connected to the signal lead line.

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