Timing synchronization method based on parameterized interaction
By adopting a timing synchronization method based on parameterized interaction in the radar timing synchronization system, the existing system has been solved, and dynamic adjustment and real-time synchronization of timer timing are realized, and the system portability and versatility are improved.
Patent Information
- Application Number
- CN202411797030.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-09
- Publication Date
- 2025-03-18
AI Technical Summary
The existing radar timing synchronization system has been developed for a long time, low program portability, poor versatility, and high versatility requirements.
Using a timing synchronization method based on parameterized interaction, dynamic adjustment and real-time synchronization of timer timing are realized through the collaborative work of the first processor and the second processor. The specific steps include the first processor receiving the timing interrupt signal and sending the timing parameter table to the second processor, the second processor parsing and updating the parameter table, and generating corresponding pulse signals and interrupt signals for radar state control.
It improves the portability and versatility of the radar timing synchronization system, realizes real-time dynamics of multiple timing parameters, and reduces R&D costs.
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Figure CN119644700A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of radar timing technology, and in particular to a timing synchronization method based on parameterized interaction. Background Art
[0002] Radar is a complex system composed of many discrete modules with different functions. Different modules must work in coordination according to a certain timing. The timer is an important part of the radar system, providing the radar with various control timing signals and control commands. At present, the working mode of radar is becoming more and more diverse, and the timing relationship is becoming more and more complex. More and more radar systems use independent timers to realize the synchronous timing control of the subsystems of the entire radar.
[0003] As an important component of radar signal processor, the basic principle of timer is relatively mature. In recent years, the research has mainly focused on its specific implementation.
[0004] Regarding the above technical solution, the inventors found that there are at least the following technical problems:
[0005] The existing radar timing synchronization system has problems such as long development time, low program portability, poor versatility and high multi-functionality requirements.
[0006] Therefore, it is necessary to improve one or more problems existing in the above-mentioned related technical solutions.
[0007] It should be noted that this section is intended to provide background or context for the technical solutions of the present invention stated in the claims. The description herein is not admitted to be prior art by inclusion in this section. Summary of the invention
[0008] The object of the present invention is to provide a timing synchronization method based on parameterized interaction, thereby solving one or more problems caused by the limitations and defects of the above-mentioned related technologies at least to a certain extent.
[0009] The present invention provides a timing synchronization method based on parameterized interaction, comprising:
[0010] The first processor sends a second timing parameter table including a second timing control signal and a second timing parameter signal to the second processor upon receiving the first timing interrupt signal;
[0011] The first processor updates the second timing parameter table to a third timing parameter table according to the real-time status of the radar; wherein the third timing parameter table includes a third timing control signal and a third timing parameter signal;
[0012] The second processor receives and parses the second timing parameter table, and determines the correctness of the second timing parameter table;
[0013] The second processor updates the first timing parameter information at the latch to the second timing parameter signal when determining that the second timing parameter table is correct;
[0014] The second processor generates a second timing pulse signal and a second timing interrupt signal according to the second timing parameter information; and sends the second timing pulse signal to each subsystem of the radar to control the radar state; and sends the second timing interrupt signal to the first processor;
[0015] The first processor sends the third timing parameter table to the second processor when receiving the second timing interrupt signal.
[0016] Optionally, an initialization step is also included:
[0017] The first processor generates an initial timing parameter table including an initial timing control signal and an initial timing parameter signal according to the initial setting, and sends the initial timing parameter table to the second processor;
[0018] The second processor receives and parses the initial timing parameter table, latches the initial timing parameter signal, and generates an initial timing pulse signal and a first timing interrupt signal according to the initial timing parameter signal; sends the initial timing pulse signal to each subsystem of the radar to initialize the radar; and sends the first timing interrupt signal to the first processor.
[0019] Optionally, the step of the second processor receiving and parsing the second timing parameter table, and determining the correctness of the second timing parameter table includes:
[0020] When the second processor determines that the second timing parameter table is incorrect, the second processor does not update the first timing parameter information at the latch; and generates the second timing pulse signal and the second timing interrupt signal according to the first timing parameter information.
[0021] Optionally, when the second processor determines that the second timing parameter table is incorrect, the step of not updating the first timing parameter information at the latch includes:
[0022] When the second processor determines that the second timing parameter table is incorrect, the second timing parameter table is marked as an error state and sent back to the first processor.
[0023] Optionally, the second timing parameter table and the third timing parameter table both include synchronization delay, repetition period, pulse width and number of pulses of timing 1 to timing n.
[0024] Optionally, the step of the second processor receiving and parsing the second timing parameter table, and determining the correctness of the second timing parameter table includes:
[0025] Taking the repetition period of timing 1 as a reference, the repetition period and the number of pulses of timing 2 to timing n are calculated to determine whether the value of the product of the repetition period and the number of pulses of timing i is less than the value of the product of the repetition period and the number of pulses of timing 1; if so, the second timing parameter table is determined to be correct, otherwise, the second timing parameter table is determined to be incorrect.
[0026] Optionally, the step of the first processor updating the second timing parameter table to a third timing parameter table according to the real-time state of the radar includes:
[0027] The real-time status includes the results and control status of radar resource scheduling management.
[0028] Optionally, the step of the first processor updating the second timing parameter table to a third timing parameter table according to the real-time state of the radar includes:
[0029] 500 μs before each subsystem of the radar completes radar state control according to the first timing pulse signal, the first processor completes updating the second timing parameter table to the third timing parameter table according to the real-time state of the radar.
[0030] Optionally, the first processor is a CPU, and the second processor is a FPGA.
[0031] The technical solution provided by the present invention may include the following beneficial effects:
[0032] In the present invention, the radar timer is parameterized to more conveniently adjust the timer timing, which has good portability, and the parameterized timing information is interacted to improve the versatility of the hardware program, thereby realizing the real-time dynamicization of multiple timing parameters in the radar timing synchronization system. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification are used to explain the principles of the present invention. Obviously, the accompanying drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other accompanying drawings can be obtained based on these accompanying drawings without creative work.
[0034] Figure 1 A schematic flow chart showing a timing synchronization method based on parameterized interaction in an exemplary embodiment of the present invention;
[0035] Figure 2A schematic diagram showing a logic decision process of a timing synchronization method based on parameterized interaction in an exemplary embodiment of the present invention;
[0036] Figure 3 A schematic diagram showing the structure of a CPU and an FPGA in an exemplary embodiment of the present invention is shown;
[0037] Figure 4 A basic timing 2 pulse generation diagram in a specific embodiment is shown;
[0038] Figure 5 A timing 2 pulse generation diagram showing pulse width parameters in a specific embodiment is shown;
[0039] Figure 6 A timing 2 pulse generation diagram showing repetition period parameters in a specific embodiment is shown;
[0040] Figure 7 A timing 2 pulse generation diagram showing the pulse number parameter in a specific embodiment is shown. DETAILED DESCRIPTION
[0041] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present invention will be more comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
[0042] In addition, the accompanying drawings are only schematic illustrations of embodiments of the present invention and are not necessarily drawn to scale. The same reference numerals in the drawings represent the same or similar parts, and their repeated descriptions will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities.
[0043] The present invention provides a timing synchronization method based on parameterized interaction, referring to Figure 1 As shown in, including:
[0044] Step S100: upon receiving the first timing interrupt signal, the first processor sends a second timing parameter table including a second timing control signal and a second timing parameter signal to the second processor.
[0045] Step S200: The first processor updates the second timing parameter table to a third timing parameter table according to the real-time status of the radar, wherein the third timing parameter table includes a third timing control signal and a third timing parameter signal.
[0046] Step S300: The second processor receives and parses the second timing parameter table, and determines the correctness of the second timing parameter table.
[0047] Step S400: When the second processor determines that the second timing parameter table is correct, the second processor updates the first timing parameter information at the latch to the second timing parameter signal.
[0048] Step S500: The second processor generates a second timing pulse signal and a second timing interrupt signal according to the second timing parameter information; and sends the second timing pulse signal to each subsystem of the radar to control the radar status; and sends the second timing interrupt signal to the first processor.
[0049] Step S600: the first processor sends the third timing parameter table to the second processor when receiving the second timing interrupt signal.
[0050] It should be understood that the timing parameters of the timing synchronization system are generated in the data processing software and are designed and implemented based on the C language, so that the timing parameters of the timing synchronization system can be quickly adjusted according to the real-time status of the radar. The radar data processing software sends the control status of the subsystem, and the subsystem reads and completes the analysis. When the next timing pulse arrives, the corresponding action is executed to realize the control of the device status and function.
[0051] It is also necessary to understand that the traditional single or fixed timing timer is changed to a dynamic timing parameterized timer. The timing parameter table in the timer is generated in real time by the data processing software in the CPU according to the results and control status of the radar resource scheduling management. When the timing interrupt signal sent by the timer is received, the dynamic timing parameter table is sent to the FPGA. After receiving the timing parameter table, the FPGA unpacks it according to the protocol. The verification logic control module will judge the correctness of the unpacked timing parameters, latch the timing parameter data when correct, use the previous package parameter data when it does not meet the requirements, and record the error parameter count in the timing parameter table check bit. The timing control module generates corresponding timing signals and interrupt signals based on the latched timing parameters, and the FPGA returns the modified timing parameter table to the data processing software.
[0052] It is also necessary to understand that the specific steps include: Step 1: System initialization. Step 2: FPGA initial timing parameter processing and initial timing generation. Step 3: Generate dynamic timing parameter table. Step 4: FPGA dynamic timing parameter processing and generate dynamic timing signal. Step 5: Interrupt real-time update of dynamic timing parameter table. Step 6: Repeat steps 3 to 5 when the radar is working.
[0053] It is also necessary to understand that after the FPGA receives the timing parameter table sent by the data processing software, it unpacks the timing parameter table according to the corresponding data protocol and judges the correctness of the unpacked data. If it does not meet the requirements, the timing parameters are used when the FPGA is initialized, and the error status is recorded. If it meets the requirements, the unpacked timing parameters are latched.
[0054] It should also be understood that the timing generation module outputs a timing interrupt signal while outputting a timing pulse. After receiving the timing interrupt signal, the data processing software generates a timing control signal and a timing parameter signal according to the requirements of the radar system and updates the dynamic timing parameter table.
[0055] It is also necessary to understand that on the basis of the traditional timing synchronization system, a dynamic timing synchronization method based on parameterized interaction has been added. This effectively solves the problem that the timing generation module inside the FPGA of the traditional radar timing synchronization system is difficult to meet the requirements of the radar system in a complex timing environment. The dynamic parameterized design has good portability and can effectively reduce R&D costs. A fixed timing generation module is used inside the FPGA, and the timing generation module can be instantiated multiple times according to the actual needs of the radar to generate multiple timing pulses. The FPGA transmits the error status back to the data processing software through the dynamic timing parameter table, which can assist software designers in real-time grasping the status of the internal timing generation of the FPGA.
[0056] The above-mentioned timing synchronization method based on parameterized interaction is adopted. By parameterizing the radar timer, the timer timing can be adjusted more conveniently, which has good portability. The parameterized timing information is interacted to improve the versatility of the hardware program, and the real-time dynamicization of multiple timing parameters in the radar timing synchronization system is realized.
[0057] Next, we will refer to Figures 1 to 7 Each step of the above-mentioned timing synchronization method based on parameterized interaction in this exemplary embodiment is described in more detail.
[0058] In some embodiments, reference Figure 3 As shown in , the first processor is a CPU and the second processor is an FPGA.
[0059] What needs to be understood is that, taking the timing synchronization design of a radar computer system as an example: the system hardware part consists of a data processing board and a data acquisition board. The data acquisition board consists of a Feiteng processor, SATA solid-state storage, FPGA chip, gigabit network switching, interface chip and level conversion chip. The data processing board consists of 1 FPGA, 1 network switch chip, 1 SRIO switch chip, differential chip, LVDS conversion chip and level conversion chip. The Feiteng processor and FPGA in the board are interconnected through RS422 serial port and network port. On the basis of the traditional radar timer, the timing synchronization system is divided into two parts to achieve. They are the real-time dynamic timing parameter table implemented by the CPU and the FPGA timing generation module. The dynamic timing parameter table is sent by the radar data processing software. The FPGA receives the dynamic timing parameter table sent down and generates the corresponding timing pulse signal in the general timing generation module.
[0060] In some embodiments, reference Figure 2 As shown in , it also includes the initialization step:
[0061] The first processor generates an initial timing parameter table including an initial timing control signal and an initial timing parameter signal according to the initial setting, and sends the initial timing parameter table to the second processor;
[0062] The second processor receives and parses the initial timing parameter table, latches the initial timing parameter signal, and generates an initial timing pulse signal and a first timing interrupt signal according to the initial timing parameter signal; sends the initial timing pulse signal to each subsystem of the radar to initialize the radar; and sends the first timing interrupt signal to the first processor.
[0063] It should be understood that in the initial state, the data processing software generates an initial timing parameter table according to a fixed template and outputs it to the FPGA. The FPGA timing control module generates timing and control information to complete the initialization of the radar system state. The FPGA generates an initial timing signal and an interrupt signal based on the timing parameters.
[0064] In some embodiments, step S300 includes:
[0065] Step S310: When the second processor determines that the second timing parameter table is incorrect, the second processor does not update the first timing parameter information at the latch; and generates the second timing pulse signal and the second timing interrupt signal according to the first timing parameter information.
[0066] It is important to understand that reference Figure 2As shown in , the data processing software transmits the dynamic timing parameter table to the data receiving module of the FPGA through the data bus. The FPGA unpacks the dynamic timing parameters and stores them in the DPRAM according to the address. The FPGA judges the correctness of the received dynamic timing parameters. The timing control module reads and latches the correct dynamic timing parameter information when the timing 1 synchronization pulse arrives. The wrong timing parameters are not updated. The FPGA timing generation module generates the corresponding timing and interrupt signals based on the latched timing parameter information and sends them to each radar subsystem for radar status control.
[0067] In some embodiments, reference Figure 2 As shown in , step S310 includes:
[0068] When the second processor determines that the second timing parameter table is incorrect, the second timing parameter table is marked as an error state and sent back to the first processor.
[0069] It should be understood that a fixed timing generation module is used inside the FPGA, and the timing generation module can be instantiated multiple times according to the actual needs of the radar to generate multiple timing pulses. The timing generation module will output a timing interrupt signal while generating the timing pulse. After the data processing software receives the timing interrupt signal, it generates a timing control signal and a timing parameter signal according to the needs of the radar system and updates them to the dynamic timing parameter table. The FPGA transmits the error status back to the data processing software through the dynamic timing parameter table.
[0070] In some embodiments, the second timing parameter table and the third timing parameter table both include synchronization delay, repetition period, pulse width and number of pulses of timing 1 to timing n.
[0071] It should be understood that reference is made to Table 1.
[0072] Table 1 Timing parameter table template
[0073]
[0074] In some embodiments, step S300 includes:
[0075] Taking the repetition period of sequence 1 as a reference, the repetition period and the number of pulses of sequence 2 to sequence n are calculated to determine whether the value of the multiplication of the repetition period and the number of pulses of sequence i is less than the value of the multiplication of the repetition period and the number of pulses of sequence 1; if so, the second timing parameter table is determined to be correct, otherwise, the second timing parameter table is determined to be incorrect. n is an integer greater than or equal to 3. i is any integer between 2 and n.
[0076] It should be understood that four of the timing sequences are taken as examples, as shown in Table 2, a dynamic timing parameter table.
[0077] Table 2 Dynamic timing parameters
[0078]
[0079]
[0080] After receiving the timing parameter table sent by the data processing software, the FPGA unpacks the timing parameter table according to the corresponding data protocol and judges the correctness of the unpacked data. The judgment criteria are: taking the period of timing 1 as the benchmark, calculate the remaining pulse periods and numbers to see if the period and the number of pulses multiplied by the period is less than the maximum period of the timing 1 pulse. When the judgment criteria are not met, the FPGA is used to initialize the timing parameters, and the error status is recorded. The error counter counts and writes the verification status word. When the judgment criteria are met, the unpacked timing parameters are latched. The FPGA generates initial timing signals and interrupt signals based on the timing parameters.
[0081] After the radar completes the initialization, it enters the dynamic workflow. The radar data processing software analyzes and processes the real-time status of the radar collected, and generates timing control signals and timing parameter signals in real time according to the needs of the radar system. Timing 1 is the reference pulse, and the period is a fixed value. Timing 2, timing 3, and timing 4 are based on timing 1, and timing synchronization pulses are generated according to the dynamic timing parameter table. The data processing software completes the organization of the next dynamic timing parameter table 500μs before the timing 1 synchronization pulse, and implements the issuance of the next dynamic timing parameter table after the arrival of each timing 1 synchronization pulse.
[0082] In some embodiments, step S200 includes:
[0083] The real-time status includes the results and control status of radar resource scheduling management.
[0084] It is important to understand that after entering the workflow, a dynamic timing parameter table is generated in real time according to the results and control status of radar resource scheduling management. After the data processing software receives the timing interrupt signal, it is sent to the FPGA via the data bus.
[0085] In some embodiments, step S200 includes:
[0086] 500 μs before each subsystem of the radar completes radar state control according to the first timing pulse signal, the first processor completes updating the second timing parameter table to the third timing parameter table according to the real-time state of the radar.
[0087] It should be understood that after the radar is initialized, it enters the dynamic workflow. The radar data processing software analyzes and processes the real-time status of the radar collected, and generates timing control signals and timing parameter signals in real time according to the needs of the radar system. The data processing software completes the organization of the next dynamic timing parameter table 500μs before the timing 1 synchronization pulse, and implements the issuance of the next dynamic timing parameter table after each timing 1 synchronization pulse interrupt arrives.
[0088] Taking timing 1 and timing 2 in Table 2 as examples, the following describes the specific process of the FPGA timing generation module generating corresponding timing and interrupt signals according to the timing delay amount, timing pulse number, timing repetition period and timing pulse width parameters of the latched timing parameter information.
[0089] a) Each timing parameter is stored inside the FPGA, the counter count is controlled by counting the clock, and the counter value is compared with the corresponding timing parameter value to generate a timing synchronization pulse.
[0090] b) When the value of the reference counter is greater than the delay amount, pulses are generated and the timing 2 pulse counter starts to accumulate. At this time, the pulse signal is pulled high. When the value of the reference counter is greater than the value of the pulse delay amount plus the pulse width, the pulse signal is pulled low. When the value of the timing 2 pulse counter is equal to the timing cycle number minus 1, the timing 2 pulse counter is cleared and starts counting again.
[0091] if(base counter < timing delay)
[0092] Timing pulse = 0;
[0093] Timing 2 pulse counter = 0;
[0094] else if (timing delay amount <= reference counter < timing pulse width)
[0095] Timing pulse = 1;
[0096] timing2pulsecounter++;
[0097] else if (Sequence 2 pulse counter = Sequence 2 sequence repetition period - 1)
[0098] Base counter = 0;
[0099] else
[0100] timing2pulsecounter++;
[0101] like Figure 4As shown, clk is a 20M clock, cpi_pulse is a timing 1 pulse, jltb_pulse is a timing 2 pulse, cpi_cnt is a reference counter, cnt is a timing 2 counter, can_num is a timing 2 pulse number counter, and pluse_delay is the delay of timing 2 relative to timing 1.
[0102] like Figure 5 As shown, pluse_width is the timing 2 pulse width parameter.
[0103] like Figure 6 As shown, pluse_cycle is the repetition cycle of timing 2.
[0104] c) When the value of the timing 2 pulse counter is equal to the timing cycle number minus 2, the pulse number counter is incremented by 1. When the value of the pulse number counter is the same as the pulse number, the pulse number counter is maintained and the timing 2 pulse counter is cleared.
[0105] if (timing 2 pulse counter = timing repetition period - 2)
[0106] Pulse number counter +1;
[0107] else if (pulse number counter = number of timing pulses)
[0108] Pulse number counter = number of timing pulses;
[0109] else
[0110] Pulse number counter = pulse number counter;
[0111] like Figure 7 As shown, pluse_time is the number of pulses in timing 2.
[0112] The generated timing synchronization pulses and interrupt signals are sent to each radar subsystem for radar status control.
[0113] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in this specification.
[0114] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art that are not disclosed by the present invention. The specification and examples are to be considered exemplary only, and the true scope and spirit of the present invention are indicated by the appended claims.
Claims
1. A timing synchronization method based on parameterized interaction, characterized in that: include: The first processor sends a second timing parameter table including a second timing control signal and a second timing parameter signal to the second processor upon receiving the first timing interrupt signal; The first processor updates the second timing parameter table to a third timing parameter table according to the real-time status of the radar; wherein the third timing parameter table includes a third timing control signal and a third timing parameter signal; The second processor receives and parses the second timing parameter table, and determines the correctness of the second timing parameter table; The second processor updates the first timing parameter information at the latch to the second timing parameter signal when determining that the second timing parameter table is correct; The second processor generates a second timing pulse signal and a second timing interrupt signal according to the second timing parameter information; and sends the second timing pulse signal to each subsystem of the radar to control the radar state; and sends the second timing interrupt signal to the first processor; The first processor sends the third timing parameter table to the second processor when receiving the second timing interrupt signal.
2. The timing synchronization method based on parameterized interaction according to claim 1, characterized in that: It also includes the initialization steps: The first processor generates an initial timing parameter table including an initial timing control signal and an initial timing parameter signal according to the initial setting, and sends the initial timing parameter table to the second processor; The second processor receives and parses the initial timing parameter table, latches the initial timing parameter signal, and generates an initial timing pulse signal and a first timing interrupt signal according to the initial timing parameter signal; sends the initial timing pulse signal to each subsystem of the radar to initialize the radar; and sends the first timing interrupt signal to the first processor.
3. The timing synchronization method based on parameterized interaction according to claim 1, characterized in that: The steps of receiving and parsing the second timing parameter table by the second processor, and determining the correctness of the second timing parameter table include: When the second processor determines that the second timing parameter table is incorrect, the second processor does not update the first timing parameter information at the latch; and generates the second timing pulse signal and the second timing interrupt signal according to the first timing parameter information.
4. The timing synchronization method based on parameterized interaction according to claim 3, characterized in that: The step of the second processor not updating the first timing parameter information at the latch when determining that the second timing parameter table is incorrect includes: When the second processor determines that the second timing parameter table is incorrect, the second timing parameter table is marked as an error state and sent back to the first processor.
5. The timing synchronization method based on parameterized interaction according to claim 3, characterized in that: The second timing parameter table and the third timing parameter table both contain synchronization delays, repetition cycles, pulse widths, and pulse numbers of timings 1 to n.
6. The timing synchronization method based on parameterized interaction according to claim 5, characterized in that: The steps of receiving and parsing the second timing parameter table by the second processor, and determining the correctness of the second timing parameter table include: Taking the repetition period of timing 1 as a reference, the repetition period and the number of pulses of timing 2 to timing n are calculated to determine whether the value of the product of the repetition period and the number of pulses of timing i is less than the value of the product of the repetition period and the number of pulses of timing 1; if so, the second timing parameter table is determined to be correct, otherwise, the second timing parameter table is determined to be incorrect.
7. The timing synchronization method based on parameterized interaction according to claim 6, characterized in that: The step of the first processor updating the second timing parameter table to the third timing parameter table according to the real-time status of the radar includes: The real-time status includes the results and control status of radar resource scheduling management.
8. The timing synchronization method based on parameterized interaction according to claim 1, characterized in that: The step of the first processor updating the second timing parameter table to the third timing parameter table according to the real-time status of the radar includes: 500 μs before each subsystem of the radar completes radar status control according to the first timing pulse signal, the first processor completes updating the second timing parameter table to the third timing parameter table according to the real-time status of the radar.
9. The timing synchronization method based on parameterized interaction according to any one of claims 1 to 7, characterized in that: The first processor is a CPU, and the second processor is an FPGA.