In-memory multiply-accumulate calculation device and method based on SRAM

Abstract

The invention discloses an SRAM (Static Random Access Memory)-based in-memory multiply-accumulate calculation device and method. The device comprises a first SRAM bit cell, a second SRAM bit cell, a first transmission gate circuit and a second transmission gate circuit, wherein the first transmission gate circuit comprises a first NMOS (N-channel Metal Oxide Semiconductor) tube, a first PMOS (P-channel Metal Oxide Semiconductor) tube and a first input port; the second transmission gate circuit comprises a second NMOS tube, a second PMOS tube and a second input port; a third MOS tube and a fourth MOS tube are arranged between the BLL bit line and the first and second transmission gate circuits; a fifth MOS tube and a sixth MOS tube are arranged between the BLR bit line and the first and second transmission gate circuits; a NOT gate is arranged between the BLR bit line and the carry output port, and the input end of the NOR gate is connected with the output end of the NOT gate and the BLL bit line. By adopting the technical scheme, multiply-accumulate results of two groups of inputs and weights can be directly output, a multiplication unit and a first-stage half adder circuit in an adder tree are not needed, the use of transistors is saved, the area and power consumption overhead of the adder tree are reduced, and the energy efficiency of the whole CIM macro is improved.

Description

Technical Field

[0001] The present invention relates to the field of digital storage and calculation technology, and in particular to an in-memory multiplication and accumulation calculation device and method based on SRAM. Background Art

[0002] Traditional computer architecture is based on the von Neumann architecture, which is a design that separates computing from storage. However, with the rapid development of artificial intelligence technology, neural networks have been widely used in many fields. Neural networks require huge amounts of computation. The traditional von Neumann architecture needs to frequently transfer data between the memory and the processor during calculation, resulting in most of the energy being consumed in the data transfer process. The energy actually used for computing accounts for a very small proportion, which seriously affects the overall energy efficiency. In addition, there is a significant gap in the development speed of processors and memory, forming a "storage wall" and "power consumption wall" effect, namely the von Neumann bottleneck.

[0003] In this context, the integrated storage and computing architecture came into being. This architecture integrates storage units and computing units, effectively reducing data transmission, significantly improving energy efficiency and data throughput, and thus breaking through the von Neumann bottleneck. The integrated storage and computing architecture can be further divided into analog storage and computing and digital storage and computing. In the analog storage and computing architecture, information is stored in the form of continuous voltage or current and is directly used to perform computing tasks. This architecture is susceptible to factors such as PVT (process, temperature, voltage), and accuracy is relatively difficult to guarantee. The digital storage and computing architecture is based on traditional digital logic circuit design and uses digital signals (i.e., discrete states of 0 and 1) for calculations. It is not easily affected by external interference and has higher accuracy.

[0004] However, the existing digital storage and computing architecture also has its own problems. The existing digital storage and computing architecture requires an adder tree to complete the accumulation operation. The power consumption of the adder tree is the main part of the power consumption of the CIM (Computing In Memory) macro. A large number of accumulation operations often bring high area and power consumption overhead, which in turn causes the energy efficiency of the CIM macro to decrease. In the adder tree circuit, the area and power consumption overhead of the first-level adder usually occupy most of the entire adder tree circuit. This is because the number of first-level adders is the largest, and they process the initial parallel accumulation of all input data. The area and overhead of the first-level adder occupy about 50% or more of the entire adder tree circuit, or even higher. The first level processes the largest number of inputs, resulting in the number of adder units reaching a peak at this level. As the number of layers increases, the number of adders required decreases layer by layer. In terms of power consumption, the first-level adder also usually accounts for 50-60% of the power consumption of the entire adder tree. This is because the parallel addition operation in the initial stage of the circuit requires a large number of adder units to be activated at the same time, resulting in high power consumption. Although the power consumption decreases gradually with the increase of the number of layers and the number of adders required decreases, the energy efficiency of the CIM macro is difficult to effectively reduce due to the problems existing in the first-layer adders.

[0005] In addition, traditional SRAM in-memory computing units generally perform AND operations or XOR operations on external inputs and weights stored in SRAM units to achieve the purpose of multiplication, and the multiplication result is single-bit data. Most neural networks use matrix operations during training and inference, which will generate a large number of multiplication and accumulation calculations. After multiplying multiple sets of inputs and multiple sets of weights, multiple single-bit multiplication results will be generated. Multiple multiplication results with the same weight need to be accumulated, and such accumulation calculations are generally directly performed using addition tree circuits. Summary of the invention

[0006] Purpose of the invention: The present invention provides an in-memory multiplication-accumulation computing device and method based on SRAM, aiming to solve the technical problems in the prior art that the area and power consumption of the adder tree in the digital storage and computing architecture are too high, and an independent multiplication unit is required to perform multiplication calculations.

[0007] Technical solution: The present invention provides an in-memory multiplication and accumulation computing device based on SRAM, comprising: a BLL bit line, a BLR bit line, a first SRAM bit unit, a second SRAM bit unit, a first transmission gate circuit, a second transmission gate circuit, a carry output port and a sum output port, wherein: the first transmission gate circuit comprises a first NMOS tube, a first PMOS tube and a first input port, the source of the first NMOS tube is connected to the source of the first PMOS tube, the connection point of the two sources serves as the first input port, the drain of the first NMOS tube is connected to the drain of the first PMOS tube, The gate of the first NMOS tube is connected to the Q node of the first SRAM bit unit, and the gate of the first PMOS tube is connected to the QB node of the first SRAM bit unit; the second transmission gate circuit includes a second NMOS tube, a second PMOS tube and a second input port, the source of the second NMOS tube is connected to the source of the second PMOS tube, and the connection point of the two sources serves as the second input port, the drain of the second NMOS tube is connected to the drain of the second PMOS tube, the gate of the second NMOS tube is connected to the Q node of the second SRAM bit unit, and the gate of the second PMOS tube is connected to the Q node of the second SRAM bit unit. A third MOS tube is arranged between the BLL bit line and the first transmission gate circuit, the gate of the third MOS tube is connected to the drain of the first NMOS tube, and the other two electrodes of the third MOS tube are respectively connected to the BLL bit line and the ground; a fourth MOS tube is arranged between the BLL bit line and the second transmission gate circuit, the gate of the fourth MOS tube is connected to the drain of the second NMOS tube, and the other two electrodes of the fourth MOS tube are respectively connected to the BLL bit line and the ground; a fifth MOS tube is arranged between the BLR bit line and the first transmission gate circuit, and the BLR bit line is connected to the second transmission gate circuit A sixth MOS tube is arranged between the two paths; the gate of the fifth MOS tube is connected to the drain of the first PMOS tube, and the other two electrodes of the fifth MOS tube are respectively connected to the BLR bit line and the sixth MOS tube; the gate of the sixth MOS tube is connected to the drain of the second PMOS tube, and the other two electrodes of the sixth MOS tube are respectively connected to the fifth MOS tube and the ground; a NOT gate is arranged between the BLR bit line and the carry output port, and the output end of the NOT gate is connected to the carry output port; a NOR gate is arranged between the output end of the NOT gate and the summation output port, and the input end of the NOR gate is respectively connected to the output end of the NOT gate and the BLL bit line.

[0008] Specifically, the first SRAM bit cell and the second SRAM bit cell are both 6T SRAM bit cells.

[0009] Specifically, the 6T SRAM bit cell includes a first inverter and a second inverter, wherein the Q node is the output of the first inverter, and the QB node is the output of the second inverter; the levels of the Q node and the QB node are opposite.

[0010] Specifically, it also includes a precharge circuit, which includes a MOS tube arranged between the BLL bit line and the BLR bit line, the gate of the MOS tube is used to receive a precharge signal, and the other two electrodes of the MOS tube are respectively connected to the BLL bit line and the BLR bit line.

[0011] Specifically, it also includes a pre-charging circuit, which includes a first pre-charging MOS tube corresponding to the BLL bit line, and a second pre-charging MOS tube corresponding to the BLR bit line, wherein the gate of the first pre-charging MOS tube is used to receive a pre-charging signal, and the other two electrodes of the first pre-charging MOS tube are respectively connected to the BLL bit line and the power supply; the gate of the second pre-charging MOS tube is used to receive a pre-charging signal, and the other two electrodes of the second pre-charging MOS tube are respectively connected to the BLR bit line and the power supply.

[0012] Specifically, the third MOS tube, the fourth MOS tube, the fifth MOS tube and the sixth MOS tube are all NMOS tubes, the source of the third MOS tube is grounded, and the drain of the third MOS tube is connected to the BLL bit line; the source of the fourth MOS tube is grounded, and the drain of the fourth MOS tube is connected to the BLL bit line; the drain of the fifth MOS tube is connected to the BLR bit line; the source of the sixth MOS tube is grounded, and the drain of the sixth MOS tube is connected to the source of the fifth MOS tube.

[0013] The present invention also provides an in-memory multiplication-accumulation calculation method based on SRAM, and the in-memory multiplication-accumulation calculation device based on SRAM provided by the present invention is applied, including: charging the BLL bit line and the BLR bit line to a high level; inputting a signal combination including a first input signal and a second input signal, wherein the first input port of the first transmission gate circuit receives the first input signal, and the second input port of the second transmission gate circuit receives the second input signal; determining the weight corresponding to the signal combination according to the written weight data, the first SRAM bit unit controls the level of the Q node based on the weight, and the second SRAM bit unit controls the level of the Q node based on the weight; obtaining the carry signal output by the carry output port and the sum signal output by the sum output port.

[0014] Specifically, the weight corresponding to the signal combination is determined according to the written weight data, which includes: performing a write operation on the SRAM array in the storage mode, and writing the weight data into the corresponding SRAM array.

[0015] Specifically, when the Q node of the first SRAM bit unit is at a high level and the first input signal is at a high level, the third MOS tube is turned on, and the BLL bit line is discharged to a low level to the ground through the third MOS tube; when the Q node of the second SRAM bit unit is at a high level and the second input signal is at a high level, the fourth MOS tube is turned on, and the BLL bit line is discharged to a low level to the ground through the fourth MOS tube.

[0016] Specifically, when the Q node of the first SRAM bit cell is at a high level, the Q node of the second SRAM bit cell is at a high level, and the first input signal and the second input signal are both at high levels, the BLL bit line discharges to the ground to a low level, and the BLR bit line discharges to the ground to a low level through the fifth MOS tube and the sixth MOS tube.

[0017] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages: it can directly output the multiplication and accumulation results of two sets of inputs and weights, without the need for a multiplication unit and a first-stage half-adder circuit in the addition tree, which greatly saves the use of transistors, helps to reduce the area and power consumption of the addition tree, and improves the energy efficiency of the overall CIM macro. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The present invention provides a schematic diagram of the structure of an in-memory multiplication and accumulation computing device based on SRAM. DETAILED DESCRIPTION

[0019] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0020] See also Figure 1 , which is a schematic diagram of the structure of the SRAM-based in-memory multiplication and accumulation computing device provided by the present invention.

[0021] The present invention provides an in-memory multiplication and accumulation computing device based on SRAM, comprising: a BLL bit line, a BLR bit line, a first SRAM bit unit, a second SRAM bit unit, a first transmission gate circuit, a second transmission gate circuit, a carry output port (Cout) and a sum output port (Sum), wherein: the first transmission gate circuit comprises a first NMOS tube (N1), a first PMOS tube (P1) and a first input port (IN1), the source of the first NMOS tube is connected to the source of the first PMOS tube, the connection point of the two sources serves as the first input port, the drain of the first NMOS tube is connected to the drain of the first PMOS tube (serving as a carry output port), and the drain of the first NMOS tube is connected to the drain of the first PMOS tube (serving as a carry output port). The first transmission gate circuit includes a second NMOS tube (N2), a second PMOS tube (P2) and a second input port (IN2), a source of the second NMOS tube connected to the source of the second PMOS tube, a connection point of the two sources serving as a second input port, a drain of the second NMOS tube connected to the drain of the second PMOS tube (serving as a transmission gate), and a gate of the second NMOS tube connected to the Q node (Q1) of the second SRAM bit unit. 2), the gate of the second PMOS tube is connected to the QB node (Q2B) of the second SRAM bit unit; a third MOS tube (N3) is arranged between the BLL bit line and the first transmission gate circuit, the gate of the third MOS tube is connected to the drain of the first NMOS tube, and the other two electrodes of the third MOS tube are respectively connected to the BLL bit line and the ground; a fourth MOS tube (N4) is arranged between the BLL bit line and the second transmission gate circuit, the gate of the fourth MOS tube is connected to the drain of the second NMOS tube, and the other two electrodes of the fourth MOS tube are respectively connected to the BLL bit line and the ground; a fifth MOS tube ( N5), a sixth MOS tube (N6) is arranged between the BLR bit line and the second transmission gate circuit; the gate of the fifth MOS tube is connected to the drain of the first PMOS tube, and the other two electrodes of the fifth MOS tube are respectively connected to the BLR bit line and the sixth MOS tube; the gate of the sixth MOS tube is connected to the drain of the second PMOS tube, and the other two electrodes of the sixth MOS tube are respectively connected to the fifth MOS tube and the ground; a NOT gate is arranged between the BLR bit line and the carry output port, and the output end of the NOT gate is connected to the carry output port; a NOR gate is arranged between the output end of the NOT gate and the sum output port, and the input end of the NOR gate is respectively connected to the output end of the NOT gate and the BLL bit line.

[0022] In the embodiment of the present invention, both the first SRAM bit cell and the second SRAM bit cell are 6T SRAM bit cells.

[0023] In an embodiment of the present invention, the 6T SRAM bit cell includes a first inverter, a second inverter and two transmission transistors (MOS tubes), wherein the Q node is the output of the first inverter, and is connected to the input of the second inverter (the gate connection point of the two MOS tubes) and the transmission transistor (the MOS tube close to the BL bit line), the QB node is the output of the second inverter, and is connected to the input of the first inverter (the gate connection point of the two MOS tubes) and the transmission transistor (the MOS tube close to the BLB bit line); the levels of the Q node and the QB node are opposite.

[0024] In specific implementation, 6T SRAM (Static Random Access Memory) is a commonly used static random access memory, which consists of six transistors to form a storage unit. 6T SRAM is widely used in cache, register file and other scenarios that require fast access to data due to its high speed, low power consumption and high reliability. A 6T SRAM storage unit is composed of two inverters cross-coupled to form a bistable trigger. Each inverter is composed of two transistors (MOS tubes), plus two transfer transistors (MOS tubes), so the entire 6TSRAM storage unit is composed of six transistors.

[0025] In a specific implementation, the gates of two MOS transistors serving as transfer transistors in a 6T SRAM are connected to the same word line (Word Line, WL). When the word line is activated, the transfer transistor is turned on, and data signals can be read or written from the bit line (Bit Line, BL) and the bit line bar (Bit Line Bar, BLB).

[0026] like Figure 1 The specific structure diagram of 6T SRAM shown in FIG. 1 shows that in 6T SRAM, Q point and QB point are two important nodes, which represent two complementary logic states stored in the memory cell. The states of these two points determine whether the data stored in the memory cell is "0" (low level) or "1" (high level).

[0027] In an embodiment of the present invention, a pre-charging circuit is also included, and the pre-charging circuit includes a first pre-charging MOS tube corresponding to the BLL bit line, and a second pre-charging MOS tube corresponding to the BLR bit line, wherein the gate of the first pre-charging MOS tube is used to receive a pre-charging signal (Pre-Charge), and the other two electrodes of the first pre-charging MOS tube are respectively connected to the BLL bit line and the power supply (VDD); the gate of the second pre-charging MOS tube is used to receive a pre-charging signal (Pre-Charge), and the other two electrodes of the second pre-charging MOS tube are respectively connected to the BLR bit line and the power supply (VDD).

[0028] In a specific implementation, the four MOS tubes N3 to N6 can be NMOS tubes or PMOS tubes, and the connection method meets the requirements of the application scenario of the present invention, that is, the BLL bit line and the BLR bit line are connected to the ground and discharge toward the ground. In an embodiment of the present invention, a specific implementation method provided is that the four MOS tubes N3 to N6 are NMOS tubes.

[0029] In the embodiment of the present invention, the third MOS tube, the fourth MOS tube, the fifth MOS tube and the sixth MOS tube are all NMOS tubes, the source of the third MOS tube is grounded, and the drain of the third MOS tube is connected to the BLL bit line; the source of the fourth MOS tube is grounded, and the drain of the fourth MOS tube is connected to the BLL bit line; the drain of the fifth MOS tube is connected to the BLR bit line; the source of the sixth MOS tube is grounded, and the drain of the sixth MOS tube is connected to the source of the fifth MOS tube.

[0030] In the embodiment of the present invention, the pre-charging circuit further includes a MOS tube arranged between the BLL bit line and the BLR bit line, the gate of the MOS tube is used to receive a pre-charging signal (Pre-Charge), and the other two electrodes of the MOS tube are respectively connected to the BLL bit line and the BLR bit line.

[0031] In a specific implementation, a MOS tube is arranged between the BLL bit line and the BLR bit line, and its function is to balance the voltage and ensure that the initial voltages on the two bit lines are consistent.

[0032] In an embodiment of the present invention, a method for performing in-memory multiplication and accumulation calculation based on SRAM is provided, and an in-memory multiplication and accumulation calculation device based on SRAM provided by the present invention is applied.

[0033] In the SRAM-based in-memory multiplication-accumulation calculation method provided by the present invention, a write operation can be first performed on the SRAM array (the first SRAM bit unit and the second SRAM bit unit) in the storage mode to write the weight data into the corresponding SRAM array.

[0034] In the embodiment of the present invention, the Pre-Charge signal of the pre-charging circuit controls the corresponding first pre-charging MOS transistor and the second pre-charging MOS transistor, so that the bit lines BLL and BLR are pre-charged to the high level VDD.

[0035] In the embodiment of the present invention, the input includes a signal combination of a first input signal and a second input signal, wherein the first input port (IN1) of the first transmission gate circuit receives the first input signal, and the second input port (IN2) of the second transmission gate circuit receives the second input signal. In the description and explanation, IN1 is used to refer to the first input signal, and IN2 is used to refer to the second input signal.

[0036] In an embodiment of the present invention, the weight corresponding to the signal combination is determined according to the written weight data, the first SRAM bit unit controls the level of the Q node (Q1) based on the weight, and the second SRAM bit unit controls the level of the Q node (Q2) based on the weight.

[0037] In a specific implementation, the written weight data can realize the mathematical logic operation of IN1×Q1 and IN2×Q2. That is, according to the weight data, in the signal combination, the level signal multiplication signal corresponding to the first input signal (represented by the Q1 node of the first SRAM bit unit as a high level or a low level), the level signal multiplication signal corresponding to the second input signal (represented by the Q2 node of the second SRAM bit unit as a high level or a low level), the level of the QB node is opposite to the level of the Q node.

[0038] In a specific implementation, when Q1 and Q2 are both at low levels, the first transmission gate circuit and the second transmission gate circuit are not conducting (N1, N2, P1 and P2 are not conducting), and since no voltage is applied to the gates of N3, N4, N5 and N6, the voltage of the bit lines BLL and BLR always remains at VDD regardless of the input value.

[0039] In the embodiment of the present invention, when the Q1 node of the first SRAM bit unit is at a high level (the Q2 node of the second SRAM bit unit is at a low level), the first transmission gate circuit is turned on, and when the first input signal is at a high level, the third MOS transistor (N3) and the fifth MOS transistor (N5) are turned on, and the BLL bit line is discharged to the ground to a low level through the third MOS transistor. Since the fourth MOS transistor (N4) and the sixth MOS transistor (N6) are not turned on, and the fifth MOS transistor and the sixth MOS transistor are connected in series, the bit line BLR cannot form a path to the ground and still remains at VDD.

[0040] Similarly, when the Q2 node of the second SRAM bit unit is at a high level (the Q1 node of the first SRAM bit unit is at a low level), the second transmission gate circuit is turned on, and the second input signal is at a high level, the fourth MOS transistor (N4) and the sixth MOS transistor (N6) are turned on, and the BLL bit line is discharged to the ground to a low level through the fourth MOS transistor, the third MOS transistor (N3) and the fifth MOS transistor (N5) are not turned on, and the bit line BLR cannot form a path to the ground and still remains at VDD.

[0041] In the embodiment of the present invention, the Q1 node of the first SRAM bit cell is at a high level, the Q2 node of the second SRAM bit cell is at a high level, the first transmission gate circuit and the second transmission gate circuit are turned on, and at the same time, the first input signal IN1 and the second input signal IN2 are both at a high level, N3 to N6 are all turned on, the BLL bit line is discharged to the ground to a low level through N3 and N4, and the BLR bit line is discharged to the ground to a low level through N5 and N6.

[0042] In the embodiment of the present invention, a carry signal (of a signal combination) outputted by a carry output port and a sum signal (of a signal combination) outputted by a sum output port are obtained.

[0043] In a specific implementation, according to the above, the Boolean logic expressions of the BLL bit line and the BLR bit line can be obtained respectively:

[0044]

[0045] In a specific implementation, a single horizontal bar on a letter symbol or a formula indicates that the letter symbol or the formula is negated.

[0046] In a specific implementation, since the bit line BLR outputs the carry output signal Cout through the NOT gate, and the bit line BLL and the carry output signal Cout output the sum output signal through the NOR gate, the Boolean logic expression of the sum output signal Sum and the carry output signal Cout can be obtained (for convenience of explanation, A is used to represent IN1×Q1, and B is used to represent IN2×Q2):

[0047]

[0048] The truth table of the half adder is shown in Table 1. The logical expression of the half adder is:

[0049] Cout = AB.

[0050] Table 1:

[0051]

[0052] The in-memory multiplication-accumulation computing device and the corresponding computing method provided by the present invention use a computing device to connect in a specific connection mode to realize the accumulation of the result after the first input signal is multiplied by the corresponding weight and the result after the second input signal is multiplied by the corresponding weight, and obtain a sum output signal and a carry output signal. The multiplication-accumulation result of the two sets of inputs and the weights can be directly output through calculation, so there is no need for a multiplication unit and a first-level half adder circuit in the addition tree. Compared with the previous design, the multiplication-accumulation operation of the two sets of inputs and the weights requires 2 AND gates and 1 half adder, which requires a total of 26 transistors, while the in-memory multiplication-accumulation computing device proposed by the present invention only needs 14 transistors to achieve the same function, which greatly saves the use of transistors, helps to reduce the area and power consumption of the addition tree, and improves the energy efficiency of the overall CIM macro.

Claims

1. A SRAM-based in-memory multiplication and accumulation computing device, characterized in that: include: BLL bit line, BLR bit line, first SRAM bit cell, second SRAM bit cell, first transmission gate circuit, second transmission gate circuit, carry output port and sum output port, wherein: The first transmission gate circuit includes a first NMOS tube, a first PMOS tube and a first input port, the source of the first NMOS tube is connected to the source of the first PMOS tube, the connection point of the two sources serves as the first input port, the drain of the first NMOS tube is connected to the drain of the first PMOS tube, the gate of the first NMOS tube is connected to the Q node of the first SRAM bit unit, and the gate of the first PMOS tube is connected to the QB node of the first SRAM bit unit; The second transmission gate circuit includes a second NMOS tube, a second PMOS tube and a second input port, the source of the second NMOS tube is connected to the source of the second PMOS tube, the connection point of the two sources serves as the second input port, the drain of the second NMOS tube is connected to the drain of the second PMOS tube, the gate of the second NMOS tube is connected to the Q node of the second SRAM bit unit, and the gate of the second PMOS tube is connected to the QB node of the second SRAM bit unit; A third MOS tube is arranged between the BLL bit line and the first transmission gate circuit, the gate of the third MOS tube is connected to the drain of the first NMOS tube, and the other two electrodes of the third MOS tube are connected to the BLL bit line and the ground respectively; a fourth MOS tube is arranged between the BLL bit line and the second transmission gate circuit, the gate of the fourth MOS tube is connected to the drain of the second NMOS tube, and the other two electrodes of the fourth MOS tube are connected to the BLL bit line and the ground respectively; A fifth MOS tube is provided between the BLR bit line and the first transmission gate circuit, and a sixth MOS tube is provided between the BLR bit line and the second transmission gate circuit; the gate of the fifth MOS tube is connected to the drain of the first PMOS tube, and the other two electrodes of the fifth MOS tube are respectively connected to the BLR bit line and the sixth MOS tube; the gate of the sixth MOS tube is connected to the drain of the second PMOS tube, and the other two electrodes of the sixth MOS tube are respectively connected to the fifth MOS tube and the ground; A NOT gate is arranged between the BLR bit line and the carry output port, and the NOT gate output end is connected to the carry output port; a NOR gate is arranged between the output end of the NOT gate and the sum output port, and the NOR gate input end is respectively connected to the NOT gate output end and the BLL bit line.

2. The SRAM-based in-memory multiplication and accumulation computing device according to claim 1, characterized in that: The first SRAM bit cell and the second SRAM bit cell are both 6T SRAM bit cells.

3. The SRAM-based in-memory multiplication and accumulation computing device according to claim 2, characterized in that: The 6T SRAM bit cell includes a first inverter and a second inverter, wherein the Q node is the output of the first inverter, and the QB node is the output of the second inverter; the levels of the Q node and the QB node are opposite.

4. The SRAM-based in-memory multiplication and accumulation computing device according to claim 1, characterized in that: It also includes a precharge circuit, which includes a MOS tube arranged between the BLL bit line and the BLR bit line, the gate of the MOS tube is used to receive a precharge signal, and the other two electrodes of the MOS tube are respectively connected to the BLL bit line and the BLR bit line.

5. The SRAM-based in-memory multiplication and accumulation computing device according to claim 1, characterized in that: It also includes a pre-charging circuit, which includes a first pre-charging MOS tube corresponding to the BLL bit line, and a second pre-charging MOS tube corresponding to the BLR bit line, wherein the gate of the first pre-charging MOS tube is used to receive a pre-charging signal, and the other two electrodes of the first pre-charging MOS tube are respectively connected to the BLL bit line and the power supply; the gate of the second pre-charging MOS tube is used to receive a pre-charging signal, and the other two electrodes of the second pre-charging MOS tube are respectively connected to the BLR bit line and the power supply.

6. The SRAM-based in-memory multiplication and accumulation computing device according to claim 1, characterized in that: The third MOS tube, the fourth MOS tube, the fifth MOS tube and the sixth MOS tube are all NMOS tubes, the source of the third MOS tube is grounded, and the drain of the third MOS tube is connected to the BLL bit line; the source of the fourth MOS tube is grounded, and the drain of the fourth MOS tube is connected to the BLL bit line; the drain of the fifth MOS tube is connected to the BLR bit line; the source of the sixth MOS tube is grounded, and the drain of the sixth MOS tube is connected to the source of the fifth MOS tube.

7. A method for calculating multiplication and accumulation in memory based on SRAM, characterized in that: The SRAM-based in-memory multiplication and accumulation computing device according to any one of claims 1 to 6 is applied, comprising: Charge the BLL bit line and the BLR bit line to a high level; The input includes a signal combination of a first input signal and a second input signal, wherein a first input port of the first transmission gate circuit receives the first input signal, and a second input port of the second transmission gate circuit receives the second input signal; Determine the weight corresponding to the signal combination according to the written weight data, the first SRAM bit unit controls the level of the Q node based on the weight, and the second SRAM bit unit controls the level of the Q node based on the weight; Obtain the carry signal output by the carry output port and the sum signal output by the sum output port.

8. The SRAM-based in-memory multiplication and accumulation calculation method according to claim 7, characterized in that: The step of determining the weight corresponding to the signal combination according to the written weight data comprises: In storage mode, a write operation is performed on the SRAM array to write the weight data into the corresponding SRAM array.

9. The SRAM-based in-memory multiplication and accumulation calculation method according to claim 7, characterized in that: The first SRAM bit unit controls the level of the Q node based on the weight, and the second SRAM bit unit controls the level of the Q node based on the weight, including: When the Q node of the first SRAM bit unit is at a high level and the first input signal is at a high level, the third MOS tube is turned on, and the BLL bit line is discharged to a low level to the ground through the third MOS tube; when the Q node of the second SRAM bit unit is at a high level and the second input signal is at a high level, the fourth MOS tube is turned on, and the BLL bit line is discharged to a low level to the ground through the fourth MOS tube.

10. The SRAM-based in-memory multiplication and accumulation calculation method according to claim 7, characterized in that: The first SRAM bit unit controls the level of the Q node based on the weight, and the second SRAM bit unit controls the level of the Q node based on the weight, including: When the Q node of the first SRAM bit cell is at a high level, the Q node of the second SRAM bit cell is at a high level, and the first input signal and the second input signal are both at high levels, the BLL bit line discharges to the ground to a low level, and the BLR bit line discharges to the ground to a low level through the fifth MOS tube and the sixth MOS tube.

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