Data transmission system, method and device and computer program product

Abstract

The invention discloses a data transmission system, method and device and a computer program product, and relates to the technical field of integrated circuits, and the system comprises an APB interface which is used for obtaining a transmission signal of APB equipment; the AHB interface is used for acquiring a transmission signal of AHB equipment; and the data conversion module jumps to a signal configuration state based on the high-level chip selection signal and the transmission response signal as well as the low-level enable signal. According to the technical scheme, data transmission management between the APB device and the AHB device is achieved, the redundant transmission time is shortened, the data transmission efficiency is improved, meanwhile, the configured working state only needs to occupy few register resources, and the area overhead of a bus matrix is reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a data transmission system, method, device and computer program product. Background Art

[0002] The Advanced High-performance Bus (AHB) and the Advanced Peripheral Bus (APB) are the two most commonly used buses in System-on-a-chip (SOC). The data transmission between the two has become the focus of attention in the chip field.

[0003] In the prior art, a direct memory access (DMA) function is usually mounted to an AHB bus device, and data transmission and register configuration with other bus devices (eg, APB devices) are completed through the DMA function.

[0004] However, this data transmission method has a large bus matrix area overhead and occupies a large amount of data transmission resources. Summary of the invention

[0005] The present invention provides a data transmission system, method, device, storage medium and computer program product to solve the problem of large data transmission resource occupation between APB equipment and AHB equipment.

[0006] According to one aspect of the present invention, there is provided a data transmission system, comprising: an advanced peripheral bus interface, a data conversion module and an advanced high-performance bus interface;

[0007] The advanced peripheral bus interface is connected to the advanced peripheral bus device and the data conversion module, and is used to obtain the transmission signal of the advanced peripheral bus device;

[0008] The advanced high-performance bus interface is connected to the advanced high-performance bus device and the data conversion module, and is used to obtain the transmission signal of the advanced high-performance bus device;

[0009] The data conversion module is used to jump from an idle state to a signal configuration state in response to detecting a high-level chip selection signal and a transmission response signal, and a low-level enable signal;

[0010] The data conversion module is also used to jump from the signal configuration state to the write operation state in response to detecting a high-level chip select signal, a transmission response signal, an enable signal and a write enable signal; and to jump from the signal configuration state to the read operation state in response to detecting a high-level chip select signal, a transmission response signal and an enable signal, and a low-level write enable signal.

[0011] The data conversion module is also used to, after jumping to the signal configuration state, send a second address signal, a transmission bit width signal and a transmission type signal to the advanced high-performance bus device according to the first address signal sent by the advanced peripheral bus device, and send a low-level transmission ready signal to the advanced peripheral bus device.

[0012] The data conversion module is also used to, after jumping to the write operation state, send a second write data signal to the advanced high-performance bus device according to the first write data signal sent by the advanced peripheral bus device, and send a transmission ready signal to the advanced high-performance bus device according to the transmission response signal sent by the advanced peripheral bus device.

[0013] The data conversion module is also used to send a high-level transmission direction signal to the advanced high-performance bus device when a high-level chip select signal, a transmission response signal and a write enable signal, as well as a low-level enable signal, are detected, and after sending a high-level transmission direction signal to the advanced high-performance bus device, send a low-level transmission direction signal to the advanced high-performance bus device.

[0014] The data conversion module is also used to, after jumping to the read operation state, send a first read data signal to the advanced peripheral bus device according to a second read data signal sent by the advanced high-performance bus device, and send a transmission ready signal to the advanced peripheral bus device according to a transmission response signal sent by the advanced high-performance bus device.

[0015] The data conversion module is also used to send a low-level transmission direction signal to the advanced high-performance bus device when a high-level chip select signal and a transmission response signal, and a low-level write enable signal and an enable signal are detected, and to send a high-level transmission direction signal to the advanced high-performance bus device after sending a low-level transmission direction signal to the advanced high-performance bus device.

[0016] According to another aspect of the present invention, there is provided a data transmission method, comprising:

[0017] Acquire transmission signals of advanced peripheral bus devices and transmission signals of advanced high-performance bus devices;

[0018] In response to detecting a high-level chip select signal and a transmission response signal, as well as a low-level enable signal, the idle state jumps to the signal configuration state.

[0019] According to another aspect of the present invention, there is provided a data transmission device, comprising:

[0020] A transmission signal acquisition module, used to acquire transmission signals of advanced peripheral bus devices and transmission signals of advanced high-performance bus devices;

[0021] The address jump execution module is used to jump from the idle state to the signal configuration state in response to detecting a high-level chip selection signal and a transmission response signal, as well as a low-level enable signal.

[0022] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the data transmission method described in any embodiment of the present invention when executed.

[0023] According to another aspect of the present invention, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the data transmission method according to any embodiment of the present invention is implemented.

[0024] According to the technical solution of the embodiment of the present invention, the data transmission system obtains the transmission signals sent by the APB device and the AHB device respectively through the APB interface and the AHB interface, and then jumps to one of the working states of the idle state, the signal configuration state, the write operation state and the read operation state according to the different level states of the different types of transmission signals, and executes the matching transmission tasks in different working states, thereby realizing the data transmission management between the APB device and the AHB device, reducing the redundant transmission time, and improving the data transmission efficiency. At the same time, the four configured working states only need to occupy a small number of register resources to realize the state machine management, reducing the area overhead of the bus matrix and saving the chip resources occupied by the data transmission management.

[0025] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 is a structural diagram of a data transmission system provided according to Embodiment 1 of the present invention;

[0028] Figure 2 is a schematic diagram of a transmission signal flow provided according to Embodiment 1 of the present invention;

[0029] Figure 3 is a schematic diagram of the jump of the working state of the data transmission system provided according to the first embodiment of the present invention;

[0030] Figure 4 is a signal timing diagram of a data transmission system according to Embodiment 2 of the present invention when transmitting data;

[0031] Figure 5 is a flowchart of a data transmission method provided according to Embodiment 3 of the present invention;

[0032] Figure 6 It is a structural diagram of a data transmission device provided according to Embodiment 4 of the present invention. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0035] Embodiment 1

[0036] Figure 1 A structural diagram of a data transmission system provided in Embodiment 1 of the present invention is shown in FIG. Figure 1As shown, the data transmission system includes an advanced peripheral bus interface 100, a data conversion module 200 and an advanced high-performance bus interface 300; the advanced peripheral bus interface 100 is connected to an advanced peripheral bus device 400 and the data conversion module 200, and is used to obtain the transmission signal of the advanced peripheral bus device 400; the advanced high-performance bus interface 300 is connected to an advanced high-performance bus device 500 and the data conversion module 200, and is used to obtain the transmission signal of the advanced high-performance bus device 500.

[0037] Specifically, the APB device 400 refers to an on-chip component on the chip that performs data transmission through the APB bus, and the AHB device 500 refers to an on-chip component on the chip that performs data transmission through the AHB bus; the APB interface 100 is connected to the APB device 400 through the APB bus, and the AHB interface 300 is connected to the AHB device 500 through the AHB bus; since the data transmission characteristics of the APB bus suitable for low speed and low power are different from those of the AHB bus suitable for high speed and high bandwidth, the data conversion module 200 is used to complete the data conversion between the two, that is, the transmission data sent by the APB device 400 is written into the AHB device 500 based on the transmission characteristics of the AHB bus; the transmission data of the AHB device 500 read is returned to the APB device 400 based on the transmission characteristics of the APB bus.

[0038] The transmission signal type and transmission signal direction between the APB device 400 and the data transmission system, and the transmission signal type and transmission signal direction between the data transmission system and the AHB device 500, such as Figure 2 As shown; wherein, the chip select (Peripheral Select) signal, i.e., the psel signal, is used by the APB device 400 to select a specific opposite device for communication. If the psel signal is high, it indicates that the opposite device is selected. If the psel signal is low, it indicates that the opposite device is not selected. When the data conversion module 200 detects a high-level psel signal, it indicates that the APB device 400 has selected the AHB device 500 as the communication object.

[0039] The enable (Peripheral Enable) signal, i.e., the penable signal, is used by the APB device 400 to configure the enable state of the selected peer device. At the same time, the penable signal is also the start mark of data transmission. After the APB device 400 sends a high-level psel signal to the peer device that needs to communicate, it will continue to send a high-level penable signal in the next clock cycle to notify the peer device to start executing the data communication task. The first address signal, i.e., the paddr signal, is used to indicate the data write address that the APB device 400 writes to the AHB device 500, or the data read address that the APB device 400 reads data from the AHB device 500.

[0040] A write enable signal, i.e., a pwrite signal, is used to indicate the data operation type of the APB device 400; wherein, a high-level pwrite signal indicates a write operation; a low-level pwrite signal indicates a read operation; a first write data signal, i.e., a pwdata signal, is used to indicate the data written by the APB device 400 to the AHB device 500; a first read data signal, i.e., a prdata signal, is used to indicate the data read by the APB device 400 from the AHB device 500; a transfer ready signal, i.e., a pready signal, is used to indicate whether the data transfer has ended; wherein, a high-level pready signal indicates that the data transfer has ended, and a low-level pready signal indicates that the data transfer has not ended.

[0041] The transmission type signal, i.e., the htrans signal, indicates the transmission type of data transmitted in the AHB bus, which may specifically include four types, i.e., no transmission data (i.e., Idle type), bursty no data transmission (Busy type), single data transmission (i.e., NOSEQ type, also i.e., NQ type) and continuous transmission (i.e., SEQ type); the second address signal, i.e., the haddr signal, is used to indicate the address information of data written into the AHB device 500, or the address information of data read from the AHB device 500; the transmission bit width signal, i.e., the hsize signal, is used to indicate the bit width information of data written into the AHB device 500, or the bit width information of data read from the AHB device 500.

[0042] The transmission direction signal, i.e., the hwrite signal, is used to indicate the data transmission direction; when the hwrite signal is at a high level, it indicates that the data transmission direction is to write data into the AHB device 500; when the hwrite signal is at a low level, it indicates that the data transmission direction is to read data from the AHB device 500; the second write data signal, i.e., the hwdata signal, is used to indicate the data written into the AHB device 500; the second read data signal, i.e., the hrdata signal, is used to indicate the data read from the AHB device 500.

[0043] The transmission response signal, i.e., the hready signal, is used to indicate whether the data transmission of the AHB device 500 has been completed; when the hready signal is at a high level, it indicates that the AHB device 500 has completed the data transmission; when the hready signal is at a low level, it indicates that the AHB device 500 has not completed the data transmission and is still waiting for the data transmission to be completed, that is, there is data that has not been completed at this time. The transmission status signal, i.e., the hresp signal, indicates the bus transmission status returned by the AHB device 500 to the APB device 400; when the hresp signal is at a low level, it indicates that the data transmission is successful (Okay); when the hresp signal is at a high level, it indicates that the data transmission is wrong (Error).

[0044] like Figure 3 As shown, the data conversion module 200 is used to jump from the idle state to the signal configuration state in response to the detection of a high-level chip select signal and a transmission response signal, as well as a low-level enable signal. When the data conversion module 200 detects a low-level psel signal, it indicates that the APB device 400 has not selected the AHB device 500 as the data transmission object. The APB device 400 may be in an idle state or in the process of data transmission with other devices. At this time, the data conversion module 200 remains in an idle state; in addition, when the data conversion module 200 detects a low-level hready signal, it indicates that the AHB device 500 is not ready for data transmission. The AHB device 500 may be in an idle state or in the process of data transmission with other devices. At this time, the data conversion module 200 also remains in an idle state.

[0045] When the data conversion module 200 detects high-level psel signals and hready signals, it indicates that the AHB device 500 has been selected by the APB device 400, and there is no data being transmitted in the AHB device 500, that is, it is ready for data transmission, and the low-level penable signal indicates that data transmission has not yet started; at this time, the data conversion module 200 enters the signal configuration state from the idle state; wherein the signal configuration state indicates that in this state, the data conversion module 200 performs the transmission operation of the read and write address and the transmission operation of the transmission bit width, so that the AHB device 500 knows the data address to be read or written by the APB device 400, and the data bit width to be read or written.

[0046] Optionally, in an embodiment of the present invention, the data conversion module 200 is also used to send a second address signal, a transmission bit width signal and a transmission type signal to the advanced high-performance bus device 500 according to the first address signal sent by the advanced peripheral bus device 400 after jumping to the signal configuration state, and send a low-level transmission ready signal to the advanced peripheral bus device 400.

[0047] Specifically, after entering the signal configuration state from the idle state, the data conversion module 200 regards the paddr signal on the APB bus as a valid signal, and sends a haddr signal to the AHB device 500 according to the paddr signal, so that the AHB device 500 can promptly know the transmission address of the data to be transmitted. At the same time, it sends an hsize signal to the AHB device 500 so that the AHB device 500 can know the transmission bit width of the data to be transmitted; wherein, the data conversion module 200 can customize the data transmission bit width between itself and the AHB device 500, and can also configure the corresponding data transmission bit width according to the agreed rules between itself and the AHB device 500.

[0048] In addition, since this transmission is carried out in the form of a single data transmission, the htrans signal sent to the AHB device 500 can be configured as the NOSEQ type, so that the transmission of the haddr signal, the hsize signal and the htrans signal can be completed in advance before the data transmission is executed, thereby ensuring the integrity of the parameters required for data transmission; in particular, since the data conversion module 200 only sends out the haddr signal and the hsize signal at the current stage, the transmission data body is not actually transmitted, so the data conversion module 200 also needs to send a low-level pready signal to the APB device 400, so that the APB device 400 is informed in time that the data transmission operation has not been completed, so as to avoid the data transmission interruption phenomenon of the APB device 400, and ensure the timing of data transmission between the APB device 400 and the AHB device 500.

[0049] The data conversion module 200 is also used to jump from the signal configuration state to the write operation state in response to the detection of a high-level chip select signal, a transmission response signal, an enable signal and a write enable signal. After the data conversion module 200 detects a high-level penable signal, since the psel signal, the penable signal and the hready signal are all high-level at this time, it indicates that the AHB device 500 has been selected as a communication object by the APB device 400, and the AHB device 500 is also ready for data transmission, and the data transmission has started. If a high-level pwrite signal sent by the APB device 400 is also detected at this time, it indicates that the data operation of the APB device 400 is a write operation, and the data conversion module 200 enters the write operation state; wherein, the write operation state is the process of writing the data sent by the APB device 400 to the AHB device 500.

[0050] Optionally, in an embodiment of the present invention, the data conversion module 200 is also used to, after jumping to the write operation state, send a second write data signal to the advanced high-performance bus device 500 according to the first write data signal sent by the advanced peripheral bus device 400, and send a transmission ready signal to the advanced peripheral bus device 400 according to the transmission response signal sent by the advanced high-performance bus device 400.

[0051] Specifically, after entering the write operation state, the data conversion module 200 sends an hwdata signal to the AHB device 500 according to the pwdata signal sent by the APB device 400 to achieve effective transmission of the data to be transmitted. At the same time, according to the hready signal fed back by the AHB device 500, a pready signal with the same level state is sent to the APB device 400, that is, if the hready signal is high at this time, the pready signal is also high at this time, and if the hready signal is low at this time, the pready signal is also low at this time, thereby ensuring the timely reporting of the write status of the AHB device 500; and when the hready signal is high, that is, when the pready signal fed back to the APB device 400 is high, it indicates that the write operation process has ended; if the low-level hresp signal is also obtained at this time, it indicates that the write operation state is ended, and the write operation state jumps to the idle state.

[0052] Optionally, in an embodiment of the present invention, the data conversion module 200 is also used to send a high-level transmission direction signal to the advanced high-performance bus device 500 when a high-level chip select signal, a transmission response signal and a write enable signal, and a low-level enable signal are detected, and after sending a high-level transmission direction signal to the advanced high-performance bus device 500, send a low-level transmission direction signal to the advanced high-performance bus device 500.

[0053] Specifically, as described in the above technical solution, when high-level psel signals, hready signals and pwrite signals, as well as low-level penable signals are detected, a high-level hwrite signal needs to be sent to the AHB device 500 to enable the AHB device 500 to know the direction of this data transmission, and the APB device 400 writes the data into the AHB device 500; since the hwrite signal only needs to maintain a high level for one clock cycle, the AHB device 500 can know the direction of this data transmission, so after sending a high-level hwrite signal to the AHB device 500, the hwrite signal can be pulled low in the next clock cycle, that is, a low-level hwrite signal is sent to the AHB device 500, so as to avoid the AHB device 500 from obtaining other write data again after the data transmission status is reported, thereby avoiding the resulting data write abnormality and improving the accuracy of data transmission.

[0054] The data conversion module 200 is also used to jump from the signal configuration state to the read operation state in response to the detection of a high-level chip select signal, a transmission response signal and an enable signal, as well as a low-level write enable signal. After the data conversion module 200 detects a high-level penable signal, since the psel signal, the penable signal and the hready signal are all high at this time, it indicates that the AHB device 500 has been selected by the APB device 400, and the AHB device 500 is also ready for data transmission, and the data transmission has started. If a low-level pwrite signal sent by the APB device 400 is also detected at this time, it indicates that the data operation of the APB device 400 is a read operation, and the data conversion module 200 enters the read operation state at this time; wherein, the read operation state is the process in which the APB device 400 reads the data stored in the AHB device 500.

[0055] Optionally, in an embodiment of the present invention, the data conversion module 200 is also used to, after jumping to the read operation state, send a first read data signal to the advanced peripheral bus device 400 according to a second read data signal sent by the advanced high-performance bus device 500, and send a transmission ready signal to the advanced peripheral bus device 400 according to a transmission response signal sent by the advanced high-performance bus device 500.

[0056] Specifically, after entering the read operation state, the data conversion module 200 sends a pwdata signal to the APB device 400 according to the hwdata signal sent by the AHB device 500 to achieve effective transmission of the data to be transmitted. At the same time, according to the hready signal sent by the AHB device 500, a pready signal with the same level state is sent to the APB device 400, that is, if the hready signal is high at this time, the pready signal is also high at a high level, and if the hready signal is low at a low level, the pready signal is also low at a low level, thereby ensuring the timely reporting of the read status of the AHB device 500; and when the hready signal is high, that is, when the pready signal sent to the APB device 400 is high, it indicates that the read operation process has ended; if the low-level hresp signal is also obtained at this time, it indicates that the read operation state is ended, and the read operation state jumps to the idle state.

[0057] Optionally, in an embodiment of the present invention, the data conversion module 200 is also used to send a low-level transmission direction signal to the advanced high-performance bus device 500 when a high-level chip select signal and a transmission response signal, and a low-level write enable signal and an enable signal are detected, and to send a high-level transmission direction signal to the advanced high-performance bus device 500 after sending a low-level transmission direction signal to the advanced high-performance bus device 500.

[0058] Specifically, as described in the above technical solution, when high-level psel signals and hready signals, as well as low-level pwrite and penable signals are detected, a low-level hwrite signal needs to be sent to the AHB device 500, so that the AHB device 500 knows that the direction of this data transmission is that the APB device 400 reads the data of the AHB device 500; since the hwrite signal only needs to maintain a low level for one clock cycle, the AHB device 500 can know the direction of this data transmission, so after sending a low-level hwrite signal to the AHB device 500, the hwrite signal can be pulled high in the next clock cycle, that is, a high-level hwrite signal is sent to the AHB device 500, so as to avoid the AHB device 500 from providing read data to the outside again after the data transmission status is reported, thereby causing data reading abnormalities, thereby improving the accuracy and security of data transmission.

[0059] The data conversion module 200 configures its own working state into four states, namely, an idle state, a signal configuration state, a write operation state and a read operation state, so that only 2 bits of storage resources (for example, register resources) are needed to complete the state management of the state machine, that is, "00", "01", "10" and "11" can respectively represent different working states, thereby reducing the occupation of register resources, reducing the area overhead of the bus matrix, and saving the occupation of system resources in the data transmission process; at the same time, the data conversion module 200 manages the data transmission between the APB device 400 and the AHB device 500 respectively through different working stages, and the close switching between the above-mentioned different working states avoids the existence of intermediate idle time, reduces the redundant transmission time between the APB device 400 and the AHB device 500, and improves the data transmission efficiency.

[0060] According to the technical solution of the embodiment of the present invention, the data transmission system obtains the transmission signals sent by the APB device and the AHB device respectively through the APB interface and the AHB interface, and then jumps to one of the working states of the idle state, the signal configuration state, the write operation state and the read operation state according to the different level states of the different types of transmission signals, and executes the matching transmission tasks in different working states, thereby realizing the data transmission management between the APB device and the AHB device, reducing the redundant transmission time, and improving the data transmission efficiency. At the same time, the four configured working states only need to occupy a small number of register resources to realize the state machine management, reducing the area overhead of the bus matrix and saving the chip resources occupied by the data transmission process.

[0061] Embodiment 2

[0062] Figure 4 This is a timing diagram of the data transmission system provided in the second embodiment of the present invention when transmitting data, such as Figure 4 As shown, taking the system clock (clk) as the unit time, for the data conversion module 200, it is necessary to determine the state change result of the state machine according to the signal sampled in the previous clock cycle, and thereby enter the matching working state in the current clock cycle. Therefore, the working state change of the data conversion module 200 is delayed by one clock cycle compared with the actual signal detection result. For example, although the various signals triggered at time T(N) meet the signal conditions for entering the signal configuration state, the data conversion module 200 needs to evaluate the sampling result at time T(N) at time T(N+1), that is, the data conversion module 200 will actually enter the address configuration stage at time T(N+1); wherein N is an integer greater than or equal to 1.

[0063] like Figure 4As shown, the process of the data conversion module 200 performing the write operation task is as follows: at time T1, the psel signal is at a low level, so at time T2, the data conversion module 200 confirms that the current time is an idle state (i.e., IDLE state) according to the signal sampling result at time T1; at the same time, since at time T1, there is no sampling result of the previous sampling time, the data conversion module 200 obviously also maintains an idle state at T1.

[0064] At T2 and T10, the psel signal is high, the penable signal is low, and the hready signal is high. Therefore, at T3 and T11, the data conversion module 200 confirms that it has entered the signal configuration state (i.e., the CON state) based on the detection results; in the signal configuration state, the data conversion module 200 regards the paddr signal as valid, and sends the haddr signal, hsize signal, and htrans signal to the AHB device 500 based on the paddr signal, and at the same time, sends a low-level pready signal to the APB device 400.

[0065] At the same time, at T3 and T11, the psel signal, penable signal, hready signal and pwrite signal are all high levels, so at T4 and T12, the data conversion module 200 confirms that it has entered the write operation state (i.e., WR state) based on the detection results; in the write operation state, the data conversion module 200 sends out an hwdata signal based on the pwdata signal, and sends out a pready signal based on the hready signal; wherein, at T4, the hready signal is high, and at this time, pulling the pready signal high represents the completion of the write operation; at T12, the hready signal is low, representing that the write operation is not completed; at T13, the hready signal is pulled high, representing that the write operation is completed.

[0066] After the write operation is completed, if the hresp signal is at a low level, the data conversion module 200 will enter an idle state; in addition, the pwrite signal is pulled high at T2 and T10, and the data conversion module 200 confirms that the pwrite signal has been pulled high at T3 and T11, and then pulls the hwrite signal high at T3 and T11, and then pulls the hwrite signal low at T4 and T12.

[0067] As described in the above technical solution, when the hready signal is not pulled low, the data conversion module 200 only needs three clock cycles (i.e., T2, T3, and T4) to complete the write operation; and when the hready signal is pulled low by one clock cycle, only four clock cycles (i.e., T10, T11, T12, and T13) are needed to complete the write operation; that is, in fact, the data writing time of the present application is only 3+X clock cycles; wherein X is the number of clock cycles in which the hready signal is pulled low; thereby greatly reducing the data writing time and improving the data transmission efficiency.

[0068] like Figure 4 As shown, the process of the data conversion module 200 performing the read operation task is as follows: at T6 and T15, the psel signal is high and the penable signal is low, so at T7 and T16, the data conversion module 200 enters the signal configuration state; in the signal configuration state, the data conversion module 200 regards the paddr signal as valid, and sends a haddr signal, an hsize signal and an htrans signal to the AHB device 500 according to the paddr signal, and at the same time, sends a low-level pready signal to the APB device 400.

[0069] At the same time, at T7 and T16, the psel signal, the penable signal and the hready signal are all high, and the pwrite signal is low, so at T8 and T17, the data conversion module 200 enters the read operation state (i.e., the RD state); wherein, at T8, the hready signal is pulled high, indicating that the read operation is completed and the hrdata signal is valid, at this time, the prdata signal is issued according to the hrdata signal, and the pready signal is issued according to the hready signal; at T17, the hready signal is low, indicating that the read operation is not completed; at T18, the hready signal is pulled high, indicating that the read operation is completed and the hrdata signal is valid, at this time, the prdata signal is issued according to the hrdata signal, and the pready signal is issued according to the hready signal.

[0070] After the read operation is completed, if the hresp signal is at a low level, the data conversion module 200 will enter an idle state; in addition, the hwrite signal is pulled high at T8 and T17, and then pulled low at T9 and T19, so that the AHB device 500 can know the data transmission direction in time; and at T21, the hready signal is at a low level, the data conversion module 200 will continue to maintain an idle state and will not transmit the transmission data sent by the APB device 400 to the AHB device 500.

[0071] As described in the above technical solution, when the hready signal is not pulled low, only three clock cycles (i.e., T6, T7, and T8) are required to complete the read operation; and when the hready signal is pulled low by one clock cycle, only four clock cycles (i.e., T15, T16, T17, and T18) are required to complete the read operation; that is, in fact, the data reading time of the present application is also 3+X clock cycles; wherein X is the number of clock cycles during which the hready signal is pulled low; thereby greatly reducing the data reading time and improving the data transmission efficiency.

[0072] The technical solution of the embodiment of the present invention, through the working status management of the data conversion module, the data transmission system continuously switches between the idle state, the write operation state, the read operation state and the signal configuration state. Whether executing a write operation task or a read operation task, only a small number of clock cycles are needed to complete it, which greatly reduces the data transmission time and improves the data transmission efficiency.

[0073] Embodiment 3

[0074] Figure 5 This is a flowchart of a data transmission method provided in the third embodiment of the present invention. The method can be executed by a data transmission device. The data transmission device can be implemented in the form of hardware and / or software. The data transmission device can be configured in the data transmission system in any embodiment of the present invention. The data transmission system is configured in a chip. Figure 5 As shown, the method includes:

[0075] S501, acquiring a transmission signal of an advanced peripheral bus device and a transmission signal of an advanced high-performance bus device.

[0076] S502 , in response to detecting a high-level chip select signal and a transmission response signal, and a low-level enable signal, jumping from an idle state to a signal configuration state.

[0077] Optionally, in an embodiment of the present invention, the data transmission method further includes: in response to detecting a high-level chip select signal, a transmission response signal, an enable signal and a write enable signal, jumping from a signal configuration state to a write operation state; or in response to detecting a high-level chip select signal, a transmission response signal and an enable signal, and a low-level write enable signal, jumping from a signal configuration state to a read operation state.

[0078] According to the technical solution of the embodiment of the present invention, the data transmission system obtains the transmission signals sent by the APB device and the AHB device respectively through the APB interface and the AHB interface, and then jumps to one of the working states of the idle state, the signal configuration state, the write operation state and the read operation state according to the different level states of the different types of transmission signals, and executes the matching transmission tasks in different working states, thereby realizing the data transmission management between the APB device and the AHB device, reducing the redundant transmission time, and improving the data transmission efficiency. At the same time, the four configured working states only need to occupy a small number of register resources to realize the state machine management, reducing the area overhead of the bus matrix and saving the chip resources occupied by the data transmission process.

[0079] Embodiment 4

[0080] Figure 6 : is a structural block diagram of a data transmission device provided by Embodiment 4 of the present invention, and the device specifically includes:

[0081] The transmission signal acquisition module 601 is used to acquire the transmission signal of the advanced peripheral bus device and the transmission signal of the advanced high-performance bus device;

[0082] The address jump execution module 602 is used to jump from the idle state to the signal configuration state in response to detecting a high-level chip selection signal and a transmission response signal, and a low-level enable signal.

[0083] According to the technical solution of the embodiment of the present invention, the data transmission system obtains the transmission signals sent by the APB device and the AHB device respectively through the APB interface and the AHB interface, and then jumps to one of the working states of the idle state, the signal configuration state, the write operation state and the read operation state according to the different level states of the different types of transmission signals, and executes the matching transmission tasks in different working states, thereby realizing the data transmission management between the APB device and the AHB device, reducing the redundant transmission time, and improving the data transmission efficiency. At the same time, the four configured working states only need to occupy a small number of register resources to realize the state machine management, reducing the area overhead of the bus matrix and saving the chip resources occupied by the data transmission process.

[0084] Optionally, the address jump execution module 602 is also used to jump from the signal configuration state to the write operation state in response to detecting a high-level chip select signal, a transmission response signal, an enable signal and a write enable signal; or to jump from the signal configuration state to the read operation state in response to detecting a high-level chip select signal, a transmission response signal and an enable signal, and a low-level write enable signal.

[0085] The above device can execute the data transmission method provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method. For technical details not described in detail in this embodiment, please refer to the data transmission method provided by any embodiment of the present invention.

[0086] Embodiment 5

[0087] In some embodiments, the data transmission method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit. In some embodiments, part or all of the computer program may be loaded and / or installed on a heterogeneous hardware accelerator via a ROM and / or a communication unit. When the computer program is loaded into RAM and executed by a processor, one or more steps of the data transmission method described above may be performed. Alternatively, in other embodiments, the processor may be configured to perform the data transmission method in any other appropriate manner (e.g., by means of firmware).

[0088] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0089] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0090] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0091] To provide interaction with a user, the systems and techniques described herein may be implemented on a heterogeneous hardware accelerator having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) through which a user can provide input to the heterogeneous hardware accelerator. Other types of devices may also be used to provide interaction with a user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0092] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0093] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0094] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0095] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A data transmission system, characterized in that: include: Advanced peripheral bus interface, data conversion module and advanced high-performance bus interface; The advanced peripheral bus interface is connected to the advanced peripheral bus device and the data conversion module, and is used to obtain the transmission signal of the advanced peripheral bus device; The advanced high-performance bus interface is connected to the advanced high-performance bus device and the data conversion module, and is used to obtain the transmission signal of the advanced high-performance bus device; The data conversion module is used to jump from an idle state to a signal configuration state in response to detecting a high-level chip selection signal and a transmission response signal, and a low-level enable signal.

2. The data transmission system according to claim 1, characterized in that: The data conversion module is also used to jump from the signal configuration state to the write operation state in response to detecting a high-level chip select signal, a transmission response signal, an enable signal and a write enable signal; or to jump from the signal configuration state to the read operation state in response to detecting a high-level chip select signal, a transmission response signal and an enable signal, and a low-level write enable signal.

3. The data transmission system according to claim 1, characterized in that: The data conversion module is also used to, after jumping to the signal configuration state, send a second address signal, a transmission bit width signal and a transmission type signal to the advanced high-performance bus device according to the first address signal sent by the advanced peripheral bus device, and send a low-level transmission ready signal to the advanced peripheral bus device.

4. The data transmission system according to claim 2, characterized in that: The data conversion module is also used to, after jumping to the write operation state, send a second write data signal to the advanced high-performance bus device according to the first write data signal sent by the advanced peripheral bus device, and send a transmission ready signal to the advanced peripheral bus device according to the transmission response signal sent by the advanced high-performance bus device.

5. The data transmission system according to claim 4, characterized in that: The data conversion module is also used to send a high-level transmission direction signal to the advanced high-performance bus device when a high-level chip select signal, a transmission response signal write enable signal, and a low-level enable signal are detected, and after sending a high-level transmission direction signal to the advanced high-performance bus device, send a low-level transmission direction signal to the advanced high-performance bus device.

6. The data transmission system according to claim 2, characterized in that: The data conversion module is also used to, after jumping to the read operation state, send a first read data signal to the advanced peripheral bus device according to a second read data signal sent by the advanced high-performance bus device, and send a transmission ready signal to the advanced peripheral bus device according to a transmission response signal sent by the advanced high-performance bus device.

7. The data transmission system according to claim 6, characterized in that: The data conversion module is also used to send a low-level transmission direction signal to the advanced high-performance bus device when a high-level chip select signal and a transmission response signal, and a low-level write enable signal and an enable signal are detected, and to send a high-level transmission direction signal to the advanced high-performance bus device after sending a low-level transmission direction signal to the advanced high-performance bus device.

8. A data transmission method, characterized in that: include: Acquire transmission signals of advanced peripheral bus devices and transmission signals of advanced high-performance bus devices; In response to detecting a high-level chip select signal and a transmission response signal, as well as a low-level enable signal, the idle state jumps to the signal configuration state.

9. The data transmission method according to claim 8, characterized in that: The data transmission method further includes: In response to detecting a high-level chip select signal, a transmission response signal, an enable signal, and a write enable signal, the signal configuration state jumps to a write operation state; Or in response to detecting a high-level chip select signal, a transmission response signal and an enable signal, and a low-level write enable signal, the signal configuration state jumps to the read operation state.

10. A data transmission device, characterized in that: include: A transmission signal acquisition module, used to acquire transmission signals of advanced peripheral bus devices and transmission signals of advanced high-performance bus devices; The address jump execution module is used to jump from the idle state to the signal configuration state in response to detecting a high-level chip selection signal and a transmission response signal, as well as a low-level enable signal.

11. A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements the data transmission method according to claim 8.

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