A state decomposition based triple exposure two-terminal line mesh routing method and system

Abstract

The application provides a kind of based on state decomposition triple exposure two end line net wiring method and system, it is related to circuit wiring technical field, method includes: obtaining wiring data;According to wiring data, construct wiring graph structure;State decomposition is carried out to wiring graph structure, obtain multiple independent connection edges;The weight of each connection edge is calculated;Based on the weight of each connection edge, wiring search is carried out to two end line net, and the final wiring scheme is determined.The application can effectively reduce the wiring complexity, improve the accuracy and routing rate of wiring by combining the wiring and mask state, using decomposition connection edge, calculating weight and dynamic search strategy, fully consider the distribution of multi-layer mask in the wiring process, reduce conflict and process violation, suitable for high-density, complex circuit wiring demand, significantly improve the efficiency of wiring.

Description

Technical Field

[0001] This invention relates to the field of circuit routing technology, and in particular to a triple-exposure two-end net routing method and system based on state decomposition. Background Technology

[0002] As the feature size of integrated circuits continues to shrink and the density of layout patterns continues to increase, multiple exposure lithography has become a key technology to further improve the success rate of chip manufacturing. Multiple exposure lithography decomposes the layout pattern onto multiple different masks, and through multiple exposure and etching iterations, a complete silicon wafer pattern is finally formed. The minimum distance between layout patterns on different masks can be smaller than the minimum distance between layout patterns on the same mask, thus posing higher and more complex requirements for integrated circuit design.

[0003] In the design of very large-scale integrated circuit chips, wiring is the most time-consuming and important step, which has an extremely important impact on the chip's performance, power consumption and yield. In order to meet the requirements of multiple exposure lithography process, wiring needs to be distributed on different masks and the minimum spacing requirement between the layout patterns on different masks or on the same mask must be met.

[0004] However, as design scale and complexity increase, triple exposure technology is gradually becoming a new design trend. However, existing design methods mainly focus on double exposure technology, which usually does not consider mask allocation during routing. Instead, the layout is decomposed after routing to determine the routing mask, which can easily lead to a low routing success rate. Summary of the Invention

[0005] To address the issue that triple exposure technology is gradually becoming a new design trend as design scale and complexity increase, existing design methods mainly focus on double exposure technology. Typically, mask allocation is not considered during routing, but layout decomposition is performed after routing to determine the routing mask, which easily leads to a low routing success rate. This invention provides a triple exposure two-end net routing method and system based on state decomposition.

[0006] The technical solutions provided by the embodiments of the present invention are as follows:

[0007] First aspect

[0008] This invention provides a triple exposure two-end net routing method based on state decomposition, comprising:

[0009] S1: Obtain wiring data;

[0010] S2: Construct the wiring diagram structure based on the wiring data;

[0011] S3: Decompose the wiring diagram structure into states to obtain multiple independent connection edges;

[0012] S4: Calculate the weight of each connecting edge;

[0013] S5: Based on the weight of each connecting edge, perform a routing search on the nets at both ends to determine the final routing scheme.

[0014] Second aspect

[0015] This invention provides a triple-exposure two-end net routing system based on state decomposition, comprising:

[0016] processor;

[0017] The memory stores computer-readable instructions, which, when executed by a processor, implement the state-decomposition-based triple exposure two-end net routing method as described in the first aspect.

[0018] Third aspect

[0019] The present invention provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the triple exposure two-end net routing method based on state decomposition as described in the first aspect.

[0020] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0021] In this invention, state decomposition is performed based on different mask conditions, avoiding conflicts between different mask layers, significantly improving routing success rate, and effectively reducing the probability of routing failures and retries. By introducing triple exposure technology, the routing structure can be decomposed onto different mask layers, significantly improving the accuracy and resolution of routing. By constructing a routing graph structure, path optimization can be flexibly performed in multi-layer routing, making the routing more comprehensive and accurate. By calculating the weight of the connection edges, the potential variation risk of the routing path during the manufacturing process can be assessed in advance, and high-risk paths can be avoided during the routing search process, effectively improving the manufacturing yield of the routing design, thereby making decisions that are more in line with design and process requirements during optimization. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1A schematic flowchart of a triple exposure two-end net routing method based on state decomposition provided in an embodiment of the present invention;

[0024] Figure 2 This is a schematic diagram of the initial wiring diagram structure provided in an embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram showing the decomposition of the wiring connection edge state provided in an embodiment of the present invention;

[0026] Figure 4 This is a schematic diagram of the wiring diagram structure after state decomposition provided in an embodiment of the present invention;

[0027] Figure 5 This is a schematic diagram of the wiring result of the wiring diagram structure after state decomposition provided in an embodiment of the present invention;

[0028] Figure 6 This is a schematic diagram of a simple wire mesh wiring result provided in an embodiment of the present invention;

[0029] Figure 7 This is a schematic diagram of a triple exposure two-end net routing system based on state decomposition, provided as an embodiment of the present invention. Detailed Implementation

[0030] The technical solution of the present invention will now be described with reference to the accompanying drawings.

[0031] In embodiments of the present invention, words such as "exemplarily," "for example," etc., are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" in the present invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the word "exemplary" is intended to present the concept in a concrete manner. Furthermore, in embodiments of the present invention, the meaning expressed by "and / or" can be both, or either one.

[0032] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0033] Reference manual attached Figure 1 The diagram shows a schematic flowchart of a triple exposure two-end net routing method based on state decomposition provided by an embodiment of the present invention.

[0034] This invention provides a triple exposure two-end net routing method based on state decomposition, including:

[0035] S1: Obtain wiring data.

[0036] In one possible implementation, the wiring data includes chip size information, chip layer number information, chip track distribution information, component location information, wiring net information, and process constraint information.

[0037] It should be noted that by obtaining detailed routing data, comprehensive and accurate basic information can be provided for the subsequent routing process. This comprehensive data collection can not only accurately reflect the physical layout of the chip design, but also provide the key constraints required in the routing process, ensuring that process limitations and design requirements are fully considered during routing, thereby optimizing the routing path and improving the success rate and design efficiency of routing.

[0038] Reference manual attached Figure 2 The diagram shows a schematic of the initial wiring diagram structure provided in an embodiment of the present invention.

[0039] like Figure 2 Within the chip area, wiring diagram nodes (black circular patterns) are added according to the intersections of the chip track distribution. There are wiring connection edges between adjacent wiring diagram nodes in the vertical or horizontal direction, and there are wiring connection edges between nodes at the same position in adjacent layers. White rectangular patterns represent components.

[0040] S2: Construct the wiring diagram structure based on the wiring data.

[0041] In this context, the wiring graph structure refers to abstracting the wiring problem into a graph. The nodes of the graph represent key locations in the circuit (such as the start point, end point, intersection, etc.), while the connecting edges represent possible wiring paths. The weight of the edge usually represents the cost or constraint of the wiring.

[0042] In one possible implementation, S2 specifically includes:

[0043] S201: Based on chip size information, chip layer information, and chip track distribution information, establish wiring diagram nodes and wiring connection edges.

[0044] Chip size information refers to the physical dimensions of the chip, including its length, width, and boundary positions, used to determine the overall layout range of the chip. Chip layer information refers to the number of metal layers used for routing within the chip, typically identified as M1, M2, etc. Different metal layers can be used for different routing paths. Chip track distribution information refers to the pre-defined distribution of available routing tracks in each routing layer, used to guide the specific path selection for routing. Routing graph nodes are points representing specific locations in the routing graph, such as the start point, end point, and intersection of a signal. Routing connection edges represent paths connecting two nodes in the routing graph; the weight of the edge usually reflects the cost or constraint of the routing.

[0045] It should be noted that by using chip size, number of layers, and track distribution information to establish routing graph nodes and connection edges, the starting point and potential path of each routing can be accurately located, effectively delineating the feasible area of ​​routing and avoiding invalid searches.

[0046] S202: Determine the correspondence between components and wiring diagram nodes based on component location information.

[0047] Among them, component location information refers to the specific physical coordinates of each component (such as transistors, resistors, capacitors, etc.) in the chip design.

[0048] It should be noted that determining the correspondence between components and wiring diagram nodes based on component location information helps to accurately define the start and end points of signals, ensuring that the nodes in the wiring diagram can accurately reflect the actual layout of the chip, reducing positional errors in path planning, and thus improving the accuracy of wiring and the consistency of the design.

[0049] S203: Construct the wiring diagram structure by combining the wiring diagram nodes, wiring connection edges, and the correspondence between components and wiring diagram nodes.

[0050] In one possible implementation, the wiring diagram nodes have location attributes and distance attributes.

[0051] The location attribute indicates the position of the current wiring diagram node in the actual physical space, including the horizontal and vertical coordinates and the chip layer it belongs to. The distance attribute indicates the shortest distance from the starting point of the wiring diagram node, which is initially positive infinity.

[0052] It should be noted that constructing a wiring graph structure using wiring data can intuitively represent complex wiring problems in the form of a graph, clearly define the possible paths between each node and their associated constraints, and transform the wiring problem into a graph search and optimization problem. This helps improve the global planning capability of wiring and provides a standardized basis for subsequent path search and weight calculation, thereby optimizing the overall wiring efficiency.

[0053] Reference manual attached Figure 3 The diagram illustrates a decomposition of the wiring connection edge state provided in an embodiment of the present invention.

[0054] Figure 3 In the original wiring diagram structure, one wiring connection edge is decomposed into three wiring connection edges, which respectively represent the wiring state when allocated to the first layer mask (dashed line), the second layer mask (solid line), and the third layer mask (dotted line).

[0055] S3: Decompose the wiring diagram structure into states to obtain multiple independent connection edges.

[0056] In one possible implementation, S3 specifically refers to:

[0057] Based on the mask state, the wiring connection edges in the wiring diagram structure are decomposed into multiple connection edges with the same physical space, representing connection edges under different mask states.

[0058] In this context, mask state refers to the state of different photolithographic mask layers used to achieve high-resolution wiring in a multi-exposure process. Each mask state corresponds to an independent exposure operation.

[0059] Specifically, by decomposing the wiring connection edge into multiple connection edges with the same physical space according to the mask state, the multi-exposure process can be better simulated, mask conflicts can be avoided, and the mutual influence between different masks can be fully considered in the design stage during the wiring process, thereby optimizing the wiring results and improving the wiring success rate and the adaptability to the manufacturing process.

[0060] In one possible implementation, the number of connection edges with the same physical space is equal to the number of masks in the wiring diagram structure.

[0061] In practice, the number of masks in the wiring diagram structure under triple exposure process is 3.

[0062] It should be noted that state decomposition of the routing diagram structure can break down the complex global routing problem into multiple independent connection edges, effectively reducing the complexity of routing optimization. This allows each connection edge to be processed under different mask states, thereby reducing conflicts, improving routing flexibility and routing success rate, and being more efficient under multi-exposure technology.

[0063] Reference manual attached Figure 4 The diagram shows a schematic of the wiring diagram structure after state decomposition provided in an embodiment of the present invention.

[0064] like Figure 4 The black rectangle represents the routing on the first layer mask, and the diagonal rectangle represents the routing on the second layer mask. The weight of the edge connecting to the same mask near the existing routing will be increased by a preset penalty value P. The routing method will search for routing starting from the component on the routing diagram structure after state decomposition.

[0065] S4: Calculate the weight of each connecting edge.

[0066] In the wiring diagram, the weight of a connection edge refers to the cost or effort required to traverse that edge.

[0067] In one possible implementation, the weight of the connecting edge is calculated based on the physical length of the connecting edge, the cost of changing the routing layer, and the cost of violating process constraints.

[0068] Physical length refers to the actual geometric distance of the connection edge in the wiring diagram, which is usually positively correlated with signal delay and wiring resource consumption. Layer switching cost refers to the cost or expense required to switch from one layer to another in multi-layer wiring, which usually involves the use of cross-layer vias. Process constraint violation cost refers to the penalty cost caused by violating process rules (such as minimum line width, spacing, etc.) during the wiring process, indicating the degree of deviation between design and process specifications.

[0069] Define E ijk Let E be the weight of the wiring connection edge between the i-th and j-th wiring graph nodes when using the k-th mask; if the i-th and j-th wiring graph nodes are on the same layer, E ijk The initial value is set to the actual length of the wiring connection edge; if the i-th wiring diagram node and the j-th wiring diagram node are located on the same layer, E ijk The initial setting is a preset layer replacement cost T; based on existing net and component location information, if the distance between the routing connection edge and the net or component is less than the process constraint, the weight E of the routing connection edge is adjusted. ijk Add a preset penalty value P.

[0070] Specifically, by defining the weight of the connecting edge as physical length, layer change routing cost, and process constraint violation cost, the true cost of each path can be fully reflected. This helps the routing algorithm to weigh multiple factors when selecting a path, optimize the routing path, reduce process conflicts and excessive layer changes, thereby improving the overall quality of routing and the success rate of manufacturing.

[0071] It should be noted that calculating the weight of each connection edge can quantify the overall cost of each path, enabling the routing algorithm to make optimization choices based on these weights. This helps to accurately evaluate the merits of each path, thereby finding a routing path that better meets design rules, delay requirements, and process constraints, and improving the overall efficiency and effectiveness of routing.

[0072] Reference manual attached Figure 5 This diagram illustrates the wiring result of the state decomposition wiring diagram structure provided in an embodiment of the present invention.

[0073] like Figure 5 The net paths at both ends utilize the third mask for routing without involving routing through other mask layers. This indicates that by selecting a suitable mask layer during the design process, the additional costs and complexities caused by mask switching can be effectively avoided. The nets at both ends searched in the figure use the third mask for routing (dotted lines) without mask switching, and the corresponding paths are represented by dark gray patterns.

[0074] Reference manual attached Figure 6 The diagram shows a simplified wire mesh wiring result provided by an embodiment of the present invention.

[0075] like Figure 6 The black rectangle represents the routing on the first layer mask. During routing, it's crucial to ensure it doesn't conflict with routing on other layers and to maximize the utilization of this layer's routing resources. The diagonal rectangle represents the routing on the second layer mask, an independent routing path from the first layer. In practical design, since different masks can be exposed independently, it's essential to ensure that each layer's routing doesn't conflict with the process. The white rectangle represents the routing on the third layer mask, which needs to be separated from the first two layers to avoid occlusion or overlap within the same physical space. Through multi-mask design, the routing on each layer becomes relatively independent, effectively improving routing throughput and density. The advantage of triple exposure lies in providing more space options for high-density routing, reducing routing conflicts, increasing routing flexibility, and improving design success rate in complex routing scenarios.

[0076] S5: Based on the weight of each connecting edge, perform a routing search on the nets at both ends to determine the final routing scheme.

[0077] Among them, the two-end network is one or more wiring paths with a clear start and end point, used to connect specific signal points or power points.

[0078] In one possible implementation, S5 specifically includes:

[0079] S501: Initialize the starting node of the wiring diagram structure and add the starting node to the search list.

[0080] In the wiring diagram, the starting node is a specific location (or point) that indicates the start of the wiring, usually corresponding to the starting point of a signal or power supply. The search list is a dynamic storage structure used to store nodes that need to be further expanded and processed during the wiring search process.

[0081] Specifically, by initializing the starting node and adding it to the search list, the starting point of the routing search is clarified, giving the search process a clear direction. This helps to accurately define the starting point of the path in the early stages of the routing search and ensures that the search can be systematically expanded from that point, thereby improving the effectiveness of the path search and the accuracy of the overall routing.

[0082] S502: Select the wiring diagram node with the smallest distance attribute from the search list for expansion.

[0083] It should be noted that selecting the node with the smallest distance attribute in the search list for expansion can prioritize the node with the lowest cost, ensuring that each step moves towards the optimal path. This reduces redundancy and invalid attempts in the search, thereby accelerating the convergence speed of routing, improving the efficiency of path selection, and ultimately optimizing the routing results.

[0084] S503: Update the distance attribute of the selected wiring diagram node to the adjacent wiring diagram nodes, and add the updated wiring diagram node to the search list.

[0085] It should be noted that updating the distance attributes of adjacent nodes of the selected wiring diagram node and adding the updated node to the search list helps to dynamically adjust and optimize each possible path. This ensures that the distance information of each node is up-to-date during the wiring process, thereby improving the accuracy of path selection, avoiding incorrect or inefficient path selection, and ultimately finding the globally optimal wiring path.

[0086] S504: Repeat steps S502 to S503 until the selected wiring diagram node is the target endpoint.

[0087] Specifically, by iteratively expanding and optimizing the path and continuously updating the distance attribute, we can ensure that an optimal path from the starting node to the target endpoint is found. This allows us to gradually approach the target in a complex wiring diagram, avoiding omissions or the selection of suboptimal paths, thereby improving the overall accuracy and success rate of wiring.

[0088] S505: Backtrack the path extended to the target endpoint, determine the final routing scheme, and update the process constraint violation cost of the connection edge.

[0089] It should be noted that routing search based on the weight of each connection edge can effectively balance the length of the routing path, the cost of layer switching, and process constraints, and find the globally optimal routing path. Under multiple constraints, it can automatically select the routing scheme with the lowest cost, improve the overall efficiency and design quality of routing, and reduce the risk of conflicts and process violations.

[0090] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0091] In this invention, state decomposition is performed based on different mask conditions, avoiding conflicts between different mask layers, significantly improving routing success rate, and effectively reducing the probability of routing failures and retries. By introducing triple exposure technology, the routing structure can be decomposed onto different mask layers, significantly improving the accuracy and resolution of routing. By constructing a routing graph structure, path optimization can be flexibly performed in multi-layer routing, making the routing more comprehensive and accurate. By calculating the weight of the connection edges, the potential variation risk of the routing path during the manufacturing process can be assessed in advance, and high-risk paths can be avoided during the routing search process, effectively improving the manufacturing yield of the routing design, thereby making decisions that are more in line with design and process requirements during optimization.

[0092] Reference manual attached Figure 7 The diagram shows a schematic of the structure of a triple exposure two-end net routing system based on state decomposition provided by the present invention.

[0093] The present invention also provides a triple exposure two-end net routing system 20 based on state decomposition, applied to the above-mentioned triple exposure two-end net routing method based on state decomposition, comprising:

[0094] Processor 201.

[0095] The memory 202 stores computer-readable instructions. When the computer-readable instructions are executed by the processor 201, they implement the triple exposure two-end net routing method based on state decomposition as described in the method embodiment.

[0096] The triple exposure two-end net routing system 20 based on state decomposition provided by the present invention can perform the above-described triple exposure two-end net routing method based on state decomposition and achieve the same or similar technical effects. To avoid repetition, the present invention will not elaborate further.

[0097] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0098] In this invention, state decomposition is performed based on different mask conditions, avoiding conflicts between different mask layers, significantly improving routing success rate, and effectively reducing the probability of routing failures and retries. By introducing triple exposure technology, the routing structure can be decomposed onto different mask layers, significantly improving the accuracy and resolution of routing. By constructing a routing graph structure, path optimization can be flexibly performed in multi-layer routing, making the routing more comprehensive and accurate. By calculating the weight of the connection edges, the potential variation risk of the routing path during the manufacturing process can be assessed in advance, and high-risk paths can be avoided during the routing search process, effectively improving the manufacturing yield of the routing design, thereby making decisions that are more in line with design and process requirements during optimization.

[0099] It should be understood that the processor in the embodiments of the present invention can be a central processing unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0100] It should also be understood that the memory in the embodiments of the present invention can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0101] The above embodiments can be implemented, in whole or in part, by software, hardware (such as circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the flow or function according to the embodiments of the present invention is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. A computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. Available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media. Semiconductor media can be solid-state drives.

[0102] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.

[0103] In this invention, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be a single item or multiple items.

[0104] It should be understood that, in various embodiments of the present invention, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0105] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0106] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the devices, apparatuses, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0107] In the embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0108] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0109] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0110] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0111] This invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the triple exposure two-end net routing method based on state decomposition as described in the method embodiment.

[0112] The computer-readable storage medium provided by this invention can implement the steps and effects of the triple exposure two-end net routing method based on state decomposition in the above-described method embodiments. To avoid repetition, this invention will not repeat the details.

[0113] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0114] In this invention, state decomposition is performed based on different mask conditions, avoiding conflicts between different mask layers, significantly improving routing success rate, and effectively reducing the probability of routing failures and retries. By introducing triple exposure technology, the routing structure can be decomposed onto different mask layers, significantly improving the accuracy and resolution of routing. By constructing a routing graph structure, path optimization can be flexibly performed in multi-layer routing, making the routing more comprehensive and accurate. By calculating the weight of the connection edges, the potential variation risk of the routing path during the manufacturing process can be assessed in advance, and high-risk paths can be avoided during the routing search process, effectively improving the manufacturing yield of the routing design, thereby making decisions that are more in line with design and process requirements during optimization.

[0115] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0116] The following points need to be explained:

[0117] (1) The accompanying drawings of the embodiments of the present invention only involve the structures involved in the embodiments of the present invention. Other structures can refer to the general design.

[0118] (2) For clarity, the thickness of layers or regions is enlarged or reduced in the drawings used to describe embodiments of the invention, i.e., these drawings are not drawn to scale. It is understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element or there may be intermediate elements.

[0119] (3) Where there is no conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other to obtain new embodiments.

[0120] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. The scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A state-decomposition based triple-exposure two-terminal net routing method, characterized by, The method comprises the following steps: S1: obtaining routing data; wherein the routing data comprises chip size information, chip layer number information, chip track distribution information, element position information, routing net information and process constraint information; S2: constructing a routing graph structure according to the routing data; S3: performing state decomposition on the routing graph structure to obtain a plurality of independent connection edges; wherein the S3 is specifically as follows: decomposing the routing connection edges in the routing graph structure into a plurality of connection edges with the same physical space according to mask states, and respectively representing the connection edges under different mask states; S4: calculating the weight of each connection edge; wherein the weight of the connection edge is calculated based on the physical length of the connection edge, the layer change wiring cost and the process constraint violation cost; S5: performing routing search on the two-end net based on the weight of each connection edge to determine a final routing scheme.

2. The state-decomposition based triple exposure two-terminal net routing method according to claim 1, wherein, The S2 specifically comprises: S201: establishing routing graph nodes and routing connection edges according to the chip size information, the chip layer number information and the chip track distribution information; S202: determining the correspondence between elements and the routing graph nodes according to the element position information; S203: constructing a routing graph structure in combination with the routing graph nodes, the routing connection edges and the correspondence between elements and the routing graph nodes.

3. The state-decomposition based triple-exposure two-terminal line mesh routing method according to claim 2, wherein, The routing graph node has a position attribute and a distance attribute.

4. The triple exposure two-end netting method based on state decomposition according to claim 1, characterized in that, The number of connection edges with the same physical space is the number of masks in the routing graph structure.

5. The state-decomposition based triple-exposure two-terminal net routing method of claim 1, wherein, The weight of the connection edge is specifically as follows: Cost = Cost(length) + Cost(via) + Cost(drc) wherein Cost represents the weight of the connection edge, Cost(length) represents the weight related to the physical length of the connection edge, Cost(via) represents the weight related to the layer change wiring cost, and Cost(drc) represents the weight related to the connection edge violation process constraint cost.

6. The state-decomposition based triple-exposure two-terminal net routing method of claim 3, wherein, The S5 specifically comprises: S501: initializing a starting node of the routing graph structure, and adding the starting node to a to-be-searched list; S502: selecting a routing graph node with the smallest distance attribute in the to-be-searched list for expansion; S503: updating the distance attribute of the adjacent routing graph nodes of the selected routing graph node, and adding the updated routing graph node to the to-be-searched list; S504: repeating steps S502 to S503 until the selected routing graph node is a target terminal point; S505: backtracking the path expanded to the target terminal point to determine a final routing scheme and update the process constraint violation cost of the connection edge.

7. A state decomposition based triple exposure two-terminal net routing system, characterized by, The method comprises the following steps: a processor; a memory having computer readable instructions stored thereon, wherein the computer readable instructions, when executed by the processor, implement the state decomposition-based triple exposure two-end net routing method of any one of claims 1 to 6.

8. A computer-readable storage medium having stored thereon a computer program, characterized in that, The program, when executed by the processor, implements the state decomposition-based triple exposure two-end net routing method of any one of claims 1 to 6.

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