Storage system and data center including the same

Abstract

A storage system and a data center including the same are provided. The memory system includes a plurality of DRAM-less memory devices, a CXL memory extender, and a PLP capacitor. The DRAM-less storage device includes a non-volatile memory as a storage medium, and the DRAM is omitted in the DRAM-less storage device. The CXL memory extender is electrically connected to the DRAM-less storage device, communicates through the CXL interface, and operates as a buffer memory of the DRAM-less storage device. The PLP capacitor is electrically connected to the DRAM-less storage device and the CXL memory extender, is disposed outside the DRAM-less storage device, and supplies the auxiliary power supply voltage to the DRAM-less storage device and the CXL memory extender under an SPO condition in which the external power supply voltage is suddenly disconnected.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2023-0123706 filed on September 18, 2023 in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety.

[0002] TECHNICAL FIELD The present disclosure relates to semiconductor integrated circuits, and more particularly, to a storage system and a data center including the storage system. Background Art

[0003] One or more semiconductor memory devices may be used in a data storage device. Examples of such data storage devices include solid-state drives (SSDs). SSDs typically use flash memory and are used as secondary storage devices. SSDs may have various design and / or performance advantages over hard disk drives (HDDs). Examples of these advantages include: the absence of moving mechanical components, higher data access speeds, stability, durability, and / or low power consumption. Various systems (e.g., one or more of laptop computers, cars, airplanes, drones, etc.) have adopted SSDs for data storage.

[0004] When a storage system including a storage device is to be applied to a storage server, the performance and cost of the storage server may have a trade-off relationship. For example, a storage server with high performance may require a memory device with high performance, which is an expensive product. In another example, in a storage server implemented to store a large amount of data, a memory device with a large storage capacity rather than high performance may be required, and these memory devices may be low-cost products. Summary of the invention

[0005] The present disclosure relates generally to semiconductor integrated circuits, and more particularly to storage systems and data centers including storage systems. In some embodiments, such storage systems can have improved performance at high capacity and low cost.

[0006] In general, aspects of the subject matter described in this specification may include a memory system including: a plurality of DRAM-less memory devices, at least one compute express link (CXL) memory expander, and a power-off protection (PLP) capacitor. Each of the plurality of DRAM-less memory devices includes a plurality of non-volatile memories as a storage medium, and a dynamic random access memory (DRAM) as a buffer memory is omitted in each of the plurality of DRAM-less memory devices. The at least one CXL memory expander is electrically connected to the plurality of DRAM-less memory devices, communicates through a CXL interface, and operates as a buffer memory for the plurality of DRAM-less memory devices. The PLP capacitor is electrically connected to the plurality of DRAM-less memory devices and the at least one CXL memory expander, is disposed outside the plurality of DRAM-less memory devices, and supplies an auxiliary power supply voltage to the plurality of DRAM-less memory devices and the at least one CXL memory expander under a sudden power off (SPO) condition in which an external power supply voltage is suddenly disconnected. The at least one CXL memory expander includes a first memory area allocated as a dedicated area for the plurality of DRAM-less memory devices. The first memory area stores mapping data including mapping information corresponding to a plurality of user data stored in the plurality of nonvolatile memories included in the plurality of DRAM-less memory devices.

[0007] Another general aspect may include a data center, the data center including: a plurality of application servers and a plurality of storage servers. The plurality of application servers receive data write requests or data read requests. The plurality of storage servers store write data corresponding to the data write requests or output read data corresponding to the data read requests. A first storage server among the plurality of storage servers includes: a plurality of first DRAM-less storage devices, at least one first compute express link (CXL) memory expander, and a first power-off protection (PLP) capacitor. Each of the plurality of first DRAM-less storage devices includes a plurality of non-volatile memories as storage media, and a dynamic random access memory (DRAM) as a buffer memory is omitted in each of the plurality of first DRAM-less storage devices. The at least one first CXL memory expander is electrically connected to the plurality of first DRAM-less storage devices, communicates via a CXL interface, and operates as a buffer memory for the plurality of first DRAM-less storage devices. The first PLP capacitor is electrically connected to the plurality of first DRAM-less memory devices and the at least one first CXL memory expander, is disposed outside the plurality of first DRAM-less memory devices, and supplies an auxiliary power supply voltage to the plurality of first DRAM-less memory devices and the at least one first CXL memory expander under a sudden power off (SPO) condition in which an external power supply voltage is suddenly disconnected. The at least one first CXL memory expander includes a first memory area allocated as a dedicated area for the plurality of first DRAM-less memory devices. The first memory area stores mapping data including mapping information corresponding to a plurality of user data stored in the plurality of nonvolatile memories included in the plurality of first DRAM-less memory devices.

[0008] Another general aspect may include a storage system, the storage system including: a host device, a plurality of quad-level cell (QLC) DRAM-less storage devices controlled by the host device, at least one compute fast link (CXL) memory expander controlled by the host device, at least one accelerator formed separately from the host device, and a power-loss protection (PLP) capacitor. Each of the plurality of QLC DRAM-less storage devices includes a plurality of QLC non-volatile memories as storage media, the plurality of QLC non-volatile memories include a plurality of QLCs configured to store 4-bit data, and a dynamic random access memory (DRAM) as a buffer memory is omitted in each of the plurality of QLC DRAM-less storage devices. The at least one CXL memory expander is electrically connected to the plurality of QLC DRAM-less storage devices, communicates through a CXL interface, and operates as a buffer memory for the plurality of QLC DRAM-less storage devices. The at least one accelerator is electrically connected to the plurality of QLC DRAM-less storage devices and the at least one CXL memory expander, performs a data processing function, and performs at least one of an erasure coding function and an end-to-end data protection function on the plurality of QLC DRAM-less storage devices. The PLP capacitor is electrically connected to the plurality of QLC DRAM-less memory devices and the at least one CXL memory expander, is disposed outside the plurality of QLC DRAM-less memory devices, and supplies an auxiliary power supply voltage to the plurality of QLC DRAM-less memory devices and the at least one CXL memory expander under a sudden power off (SPO) condition in which an external power supply voltage is suddenly disconnected. The at least one CXL memory expander includes: a first memory area allocated as a dedicated area for the plurality of QLC DRAM-less memory devices; and a second memory area configured to be accessed and managed by a host device. The first memory area stores mapping data, the mapping data including mapping information corresponding to a plurality of user data stored in the plurality of QLC non-volatile memories included in the plurality of QLC DRAM-less memory devices. The at least one accelerator includes at least one non-volatile memory. Under the SPO condition, the data stored in the at least one CXL memory expander is flushed to the at least one non-volatile memory included in the at least one accelerator.

[0009] In a storage system and a data center, a CXL memory expander operating as a buffer memory of a DRAM-less storage device may be included, and a PLP capacitor disposed outside the DRAM-less storage device may be included. Mapping data, write operations, etc. may be managed normally and / or stably by the CXL memory expander. Even under SPO conditions, an auxiliary power supply voltage supplied from the PLP capacitor may be used to prevent data loss. In addition, the erasure code function and the end-to-end data protection function may be performed by a separately formed accelerator and / or a computational storage device, or the DRAM-less storage device may perform an enhanced error correction code function by itself, and therefore, data integrity may be maintained. Therefore, the storage system may have improved or enhanced performance with a relatively large storage capacity and a low manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram illustrating an example of a storage system.

[0011] Figure 2 , Figure 3A , Figure 3B , Figure 4 , Figure 5A and Figure 5B is a diagram for describing an example of the operation of a storage system.

[0012] Figure 6 is a block diagram illustrating an example of a storage system.

[0013] Fig. 7A and Figure 7B It is used to describe the Figure 6 Schematic diagram of an example of a DRAM-less memory device and a CXL memory expander in a memory system of FIG.

[0014] Figure 8 , Fig. 9 , Fig.10 and Fig.11 is a diagram illustrating an example of a DRAM-less memory device and a nonvolatile memory included in a memory system.

[0015] Fig.12 and Fig.13 is a diagram illustrating an example of a CXL memory expander and a volatile memory included in a storage system.

[0016] Fig.14 is a block diagram illustrating an example of a storage system.

[0017] Fig.15 Is used to describe Fig.14 A diagram of an example of the operation of a storage system.

[0018] Fig.16 is a block diagram illustrating an example of a storage system.

[0019] Fig.17 is a diagram illustrating an example of a computing storage device included in a storage system.

[0020] Fig.18 Is used to describe Fig.16 A diagram of an example of the operation of a storage system.

[0021] Fig.19 is a block diagram illustrating an example of a storage system.

[0022] Fig. 20 and Fig.21 It is shown that the Fig.19 Schematic diagram of an example of a DRAM-less storage device in a storage system.

[0023] Fig. 22 Is used to describe Fig.19 An illustration of the operation of a storage system.

[0024] Fig.23 and Fig.24 is a block diagram illustrating an example of a data center including a storage system.

[0025] Like reference numerals refer to like elements throughout the application. DETAILED DESCRIPTION

[0026] Figure 1 is a block diagram illustrating an example of a storage system.

[0027] Reference Figure 1 , the memory system 100 includes a plurality of DRAM-less memory devices 130_1, 130_2, ..., 130_K, at least one compute fast link (CXL) memory expander 140, and a power loss protection (PLP) capacitor 150, wherein K is a positive integer greater than or equal to two. The memory system 100 may also include a host device 110, a bus 115, and a host memory 120.

[0028] In some embodiments, the storage system 100 may be one of various computing devices, such as a personal computer (PC), a server computer, a data center, a workstation, a digital television (TV), a set-top box, etc. In some embodiments, the storage system 100 may be one of various mobile devices, such as a mobile phone, a smart phone, a tablet computer, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a portable game console, a music player, a video camera, a video player, a navigation device, a wearable device, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, an e-book reader, a virtual reality (VR) device, an augmented reality (AR) device, a robotic device, a drone, a car, etc.

[0029] The host device 110 may control the overall operation of the storage system 100. For example, the host device 110 may include at least one of various processing units (e.g., a central processing unit (CPU), etc.). For example, the host device 110 may execute an operating system (OS). The OS may include, for example, a file system for file management and a device driver for controlling peripheral devices at the OS level.

[0030] The host memory 120 may be used as a main memory or system memory of the memory system 100. The host memory 120 may store instructions and / or data executed and / or processed by the host device 110. The host memory 120 may have a first form factor. For example, the host memory 120 may be or may include a dynamic random access memory (DRAM) and may have a form factor of a dual in-line memory module (DIMM).

[0031] Each of the plurality of DRAM-less memory devices 130_1 to 130_K includes a plurality of nonvolatile memories QLCNVM as storage media, and a DRAM as a buffer memory is omitted in each of the plurality of DRAM-less memory devices 130_1 to 130_K. Each of the plurality of DRAM-less memory devices 130_1 to 130_K may also include a memory controller STGCONT that controls the operation of a corresponding DRAM-less memory device in the plurality of DRAM-less memory devices 130_1 to 130_K. For example, the plurality of DRAM-less memory devices 130_1 to 130_K may include a first DRAM-less memory device 130_1 to a Kth DRAM-less memory device 130_K. Reference will be made to Figures 8 to 11 The configuration of each of the plurality of DRAM-less memory devices 130_1 to 130_K is described.

[0032] In some embodiments, the plurality of nonvolatile memories QLC NVM may be QLC nonvolatile memories including a plurality of quad-level cells (QLCs), each QLC storing 4 bits of data, and the plurality of DRAM-less memory devices 130_1 to 130_K may be QLC DRAM-less memory devices. Hereinafter, examples will be described based on QLC nonvolatile memories and QLC DRAM-less memory devices, but other examples are also feasible. For example, the plurality of nonvolatile memories included in the plurality of DRAM-less memory devices 130_1 to 130_K may include a plurality of memory cells, each memory cell storing data having two or more bits. For example, each of the plurality of memory cells may be a memory cell storing k bits of data and programmed to have 2 k Any number of bit cells that can be in one of a number of states, where k is a positive integer greater than or equal to two.

[0033] At least one CXL memory expander 140 is electrically connected to the plurality of DRAM-less memory devices 130_1 to 130_K, communicates via a CXL interface, and operates as a buffer memory for the plurality of DRAM-less memory devices 130_1 to 130_K. For ease of explanation, Figure 1 Only one CXL memory expander 140 is shown in the figure, however, the storage system 100 may include two or more CXL memory expanders. The CXL memory expander 140 may include a CXL controller CXL CONT that controls the operation of the CXL memory expander 140 and a plurality of volatile memories VM that store data. Figure 3A , Figure 3B and Figure 4 The operation of using the CXL memory expander 140 as a buffer memory for the plurality of DRAM-less memory devices 130_1 to 130_K will be described. Fig.12 and Fig.13 The configuration of CXL memory expander 140 is described.

[0034] The CXL memory expander 140 may operate under the control of the host device 110 and may store data. The CXL memory expander 140 may communicate with the host device 110 through an interface (e.g., an interface based on a CXL protocol or a CXL interface) different from an interface of the host memory 120 (e.g., DRAM), and may be electrically connected to the host device 110 without adding a memory channel to the host device 110. Therefore, regardless of existing or conventional memory technology, the CXL memory expander 140 may be additionally installed in the memory system 100, and the memory capacity and memory bandwidth of the memory system 100 may be effectively increased.

[0035] The CXL protocol is an open standard for high-speed CPU-to-device and CPU-to-memory connections designed for, for example, high-performance data center computers. The CXL protocol can be built on, for example, Peripheral Component Interconnect Express (PCIe) to form physical and electrical interfaces in some areas such as input / output (I / O), memory, and cache. The CXL protocol can maintain memory consistency between CPU memory (e.g., host memory 120) directly attached to the CPU and memory on the CXL device (e.g., CXL memory expander 140). For example, the CPU and the CXL device can seamlessly access (e.g., read, write, and / or transfer) the same data. For example, when the CXL protocol is applied or adopted, the CPU can use both the CPU memory and the CXL device as buffer memory. In other words, the CXL protocol and / or interface can represent a low-latency and high-bandwidth link that supports dynamic protocol multiplexing and enables various connections between various devices.

[0036] Although the examples are described according to the CXL memory expander 140 implemented based on the CXL protocol, other examples are also possible. For example, the CXL memory expander 140 may be implemented based on at least one of various protocols (such as the Gen-Z protocol, the NVLink protocol, the Cache Coherent Interconnect for Accelerators (CCIX) protocol, the open Coherent Accelerator Processor Interface (CAPI) protocol, etc.).

[0037] In some embodiments, the plurality of DRAM-less memory devices 130_1 to 130_K and the CXL memory expander 140 may have the same form factor. For example, the plurality of DRAM-less memory devices 130_1 to 130_K and the CXL memory expander 140 may have a second form factor different from the first form factor. Figure 6 , Fig. 7A and Figure 7B The form factors of the plurality of DRAM-less memory devices 130_1 to 130_K and the CXL memory expander 140 are described.

[0038] The host device 110, the plurality of DRAM-less storage devices 130_1 to 130_K, and the CXL memory expander 140 may be connected to each other and may communicate with each other through the bus 115. For example, the host device 110 and the plurality of DRAM-less storage devices 130_1 to 130_K may communicate through an interface such as Peripheral Component Interconnect Express (PCIe), Non-Volatile Memory Express (NVMe), etc., the host device 110 and the CXL memory expander 140 may communicate through an interface such as CXL, and the bus 115 may be implemented to support different interfaces (e.g., heterogeneous interfaces). However, the present disclosure is not limited thereto. For another example, the host device 110, the plurality of DRAM-less storage devices 130_1 to 130_K, and the CXL memory expander 140 may communicate through the same or similar interfaces, and the bus 115 may be implemented to support the same or similar interfaces (e.g., homogeneous interfaces).

[0039] The PLP capacitor 150 is electrically connected to the plurality of DRAM-less memory devices 130_1 to 130_K and the CXL memory expander 140, is disposed outside the plurality of DRAM-less memory devices 130_1 to 130_K, and supplies an auxiliary power supply voltage to the plurality of DRAM-less memory devices 130_1 to 130_K and the CXL memory expander 140 in a sudden power off (SPO) condition (or situation) in which an external power supply voltage is suddenly (e.g., accidentally) disconnected. The PLP capacitor 150 may be referred to as an auxiliary (or secondary) power supply device, a PLP integrated circuit (IC), etc. Reference will be made to Figure 5A and Figure 5B The operation using the PLP capacitor 150 is described.

[0040] A storage system and / or server system including a plurality of DRAM-less storage devices has been studied for high capacity and low cost. Since the DRAM-less storage device does not include a DRAM as a buffer memory and a PLP capacitor for supplying an auxiliary power supply voltage under an SPO condition to reduce manufacturing costs, there are problems in that performance may be degraded due to the absence of the buffer memory and data may be lost under an SPO condition due to the absence of the PLP capacitor. In addition, since the DRAM-less storage device includes a nonvolatile memory having a multi-bit memory cell as a storage medium to reduce manufacturing costs, there is a problem in that the possibility of data integrity being damaged is relatively high.

[0041] The memory system 100 may include at least one CXL memory expander 140 that "operates as a buffer memory of a plurality of DRAM-less memory devices 130_1 to 130_K", and may include a PLP capacitor 150 disposed outside the plurality of DRAM-less memory devices 130_1 to 130_K. Even if the storage capacity of the plurality of DRAM-less memory devices 130_1 to 130_K increases, mapping data, write operations, etc. may be managed normally and / or stably by the CXL memory expander 140. Even under SPO conditions, data loss may be prevented using an auxiliary power supply voltage supplied from the PLP capacitor 150. In addition, as will be referred to Fig.14 , Fig.16 and Fig.19 As described, the erasure coding function and the end-to-end data protection function may be performed by a separately formed accelerator and / or a computing storage device, or the plurality of DRAM-less storage devices 130_1 to 130_K may perform an enhanced error correction code (ECC) function by themselves, so that data integrity may be maintained. Therefore, the storage system 100 may have improved or enhanced performance with a relatively large storage capacity and a low manufacturing cost.

[0042] Figure 2 , Figure 3A , Figure 3B , Figure 4 , Figure 5A and Figure 5B is a diagram for describing an example of the operation of a storage system.

[0043] Reference Figure 2 , showing that included in Figure 1 For convenience of explanation, only one volatile memory 141 included in the CXL memory expander 140, one first nonvolatile memory 131_1 included in the first DRAM-less memory device 130_1, one second nonvolatile memory 131_2 included in the second DRAM-less memory device 130_2, and one K-th nonvolatile memory 131_K included in the K-th DRAM-less memory device (130_K) are shown.

[0044] The first DRAM-less storage device 130_1 may store the first user data UD1 and the first mapping data MD1 corresponding to the first user data UD1 in the first nonvolatile memory 131_1. The second DRAM-less storage device 130_2 may store the second user data UD2 and the second mapping data MD2 corresponding to the second user data UD2 in the second nonvolatile memory 131_2. The Kth DRAM-less storage device 130_K may store the Kth user data UDK and the Kth mapping data MDK corresponding to the Kth user data UDK in the Kth nonvolatile memory 131_K. The mapping data may include information associated with or related to “a mapping relationship (or a corresponding relationship) between a logical address managed by the host device 110 and a physical address of a nonvolatile memory”, and the data stored in the nonvolatile memory may be managed using the mapping data. For example, the first mapping data MD1 may include a relationship between a logical address and a physical address of the first user data UD1.

[0045] The CXL memory expander 140 may include a first memory region MR1 and a second memory region MR2 that are different from each other in the volatile memory 141. For example, the first memory region MR1 and the second memory region MR2 may be set by the host device 110, and may be set at an initial operation time of the memory system 100 or at the start of the operation (e.g., after a power supply voltage is supplied to the memory system 100).

[0046] The first memory region MR1 may be allocated as a dedicated area for the plurality of DRAM-less memory devices 130_1 to 130_K (e.g., for the plurality of nonvolatile memories 131_1 to 131_K). For example, the first memory region MR1 may be accessed by the plurality of DRAM-less memory devices 130_1 to 130_K and may store a plurality of mapping data MD1 to MDK of the plurality of DRAM-less memory devices 130_1 to 130_K.

[0047] As described above, since each of the plurality of DRAM-less memory devices 130_1 to 130_K does not include a DRAM as a buffer memory, a buffer area may be required to store mapping data MD1 to MDK, and the first memory region MR1 may be used as a buffer memory for the plurality of DRAM-less memory devices 130_1 to 130_K.

[0048] Among the areas of the volatile memory 141, the remaining area (e.g., the second memory area MR2) that is not allocated as a dedicated area for the plurality of DRAM-less memory devices 130_1 to 130_K may be an area accessible by the host device 110 and / or an area managed by the host device 110. For example, the second memory area MR2 may be used for a role similar to that of the host memory 120 (e.g., as an extended main memory or an extended system memory of the memory system 100).

[0049] Reference Figure 3A and Figure 3B , showing that Figure 2 1. For convenience of explanation, components irrelevant to the operation of storing the mapping data MD1 to MDK are omitted.

[0050] In some embodiments, Figure 3A As shown in , a plurality of DRAM-less memory devices 130_1 to 130_K and a CXL memory expander 140 may exchange mapping data MD1 to MDK based on a peer-to-peer (P2P) scheme. For example, a storage controller STG CONT included in each of the plurality of DRAM-less memory devices 130_1 to 130_K may include a direct memory access (DMA) engine SDMA. The DMA engine SDMA included in the storage controller STG CONT may send the mapping data MD1 to MDK stored in the non-volatile memory QLC NVM to the CXL memory expander 140 without intervention and / or control of the host device 110. In other words, the mapping data MD1 to MDK may be sent from the plurality of DRAM-less memory devices 130_1 to 130_K to the CXL memory expander 140 based on the P2P scheme, and may be stored in the volatile memory VM (e.g., in the first memory region MR1).

[0051] In some embodiments, Figure 3B As shown in FIG. 1 , a plurality of DRAM-less memory devices 130_1 to 130_K and a CXL memory expander 140 may exchange mapping data MD1 to MDK based on a DMA scheme under the control of a host device 110. For example, the host device 110 may include a DMA engine HDMA. The DMA engine HDMA of the host device 110 may read the mapping data MD1 to MDK from the plurality of DRAM-less memory devices 130_1 to 130_K, and may transmit the read mapping data MD1 to MDK to the CXL memory expander 140.

[0052] In some embodiments, the above-described mapping data transfer operation from the plurality of DRAM-less memory devices 130_1 to 130_K to the CXL memory expander 140 may be performed at an initial operation time or start of operation of the memory system 100 .

[0053] In some embodiments, a mapping data transfer operation (e.g., a mapping data backup or flush operation) from CXL memory expander 140 to multiple DRAM-less memory devices 130_1 to 130_K may also be implemented in a similar manner as described above. For example, a mapping data transfer operation from CXL memory expander 140 to multiple DRAM-less memory devices 130_1 to 130_K may be performed periodically and / or based on a request while the memory system 100 is operating or driving.

[0054] In the memory system 100, each of the plurality of DRAM-less memory devices 130_1 to 130_K may not include a DRAM as a buffer memory to reduce manufacturing costs, and a portion (e.g., the first memory region MR1) in the CXL memory expander 140 located outside the plurality of DRAM-less memory devices 130_1 to 130_K may be used as a buffer memory. The CXL memory expander 140 may be formed separately from the DRAM-less memory devices 130_1 to 130_K, and thus may be implemented with a relatively large capacity. Therefore, even if the size of the mapping data MD1 to MDK increases as the storage capacity of the DRAM-less memory devices 130_1 to 130_K increases, the mapping data MD1 to MDK may be managed normally and / or efficiently by the CXL memory expander 140.

[0055] Reference Figure 4 , showing the Figure 1 FIG. 1 is an example of a write operation of a plurality of DRAM-less memory devices 130_1 to 130_K in FIG. 1 . For ease of explanation, components not related to the write operation are omitted.

[0056] When write data WD is to be stored or programmed in the first DRAM-less memory device 130_1 among the plurality of DRAM-less memory devices 130_1 to 130_K, the host device 110 may transmit the write data WD to the CXL memory expander 140, and the write data WD may be temporarily stored in the volatile memory VM (e.g., in the first memory region MR1) of the CXL memory expander 140. Thereafter, the write data WD may be stored in the nonvolatile memory QLC NVM included in the first DRAM-less memory device 130_1 using the write data WD temporarily stored in the CXL memory expander 140, and thus the write operation may be completed.

[0057] As described above, since each of the plurality of DRAM-less memory devices 130_1 to 130_K does not include a DRAM as a buffer memory, a buffer area may be required to temporarily store write data WD, and the volatile memory VM (e.g., the first memory area MR1) of the CXL memory expander 140 may be used as a buffer memory for the plurality of DRAM-less memory devices 130_1 to 130_K. For example, a write operation for storing the write data WD may be performed similarly to an on-chip buffered programming (OBP) scheme.

[0058] DRAM-less storage devices do not include DRAM as a buffer memory to reduce manufacturing costs. In conventional DRAM-less storage devices, a host memory buffer (HMB) scheme using a host memory as a buffer memory is used to perform write operations. As a result, there is a problem that the performance of the host device is reduced due to excessive use of the host memory.

[0059] In the memory system 100, a portion of the CXL memory expander 140 located outside the plurality of DRAM-less memory devices 130_1 to 130_K and formed separately from the host memory 120 may be used as a buffer memory. Therefore, a write operation may be efficiently performed without performance reduction (or degradation) of the host device 110.

[0060] Reference Figure 3A , Figure 3B and Figure 4 The described data transfer operations are merely exemplary, and the present disclosure is not limited thereto.

[0061] Reference Figure 5A and Figure 5B , showing the use of Figure 1 FIG. 1 is an example of an operation in which the PLP capacitor 150 in FIG. 1 supplies the auxiliary power voltage PWR_AUX. For convenience of explanation, components irrelevant to the supply of the auxiliary power voltage PWR_AUX are omitted.

[0062] like Figure 5A As shown in , when the external power supply voltage PWR_EXT is normally supplied, the plurality of DRAM-less memory devices 130_1 to 130_K and the CXL memory expander 140 may operate based on the external power supply voltage PWR_EXT, and the PLP capacitor 150 may be charged based on the external power supply voltage PWR_EXT. For example, the operating voltage generated based on the external power supply voltage PWR_EXT may be supplied to the memory controller STG CONT, the nonvolatile memory QLC NVM, the CXL controller CXL CONT, and the volatile memory VM.

[0063] like Figure 5B As shown in , when the supply of the external power supply voltage PWR_EXT is blocked, cut off, or stopped (for example, when an SPO situation occurs), the PLP capacitor 150 may generate an auxiliary power supply voltage PWR_AUX, and the plurality of DRAM-less memory devices 130_1 to 130_K and the CXL memory expander 140 may operate based on the auxiliary power supply voltage PWR_AUX. For example, the operating voltage generated based on the auxiliary power supply voltage PWR_AUX may be supplied to the memory controller STG CONT, the nonvolatile memory QLC NVM, the CXL controller CXL CONT, and the volatile memory VM.

[0064] In some embodiments, even if the supply of the external power supply voltage PWR_EXT is blocked, a PLP operation or a PLP dump operation that usually terminates the operation of the memory system 100 may be performed within a predetermined time interval based on the auxiliary power supply voltage PWR_AUX. For example, the auxiliary power supply voltage PWR_AUX may be generated by the charge in the PLP capacitor 150 stored based on the external power supply voltage PWR_EXT, and when a certain period of time has passed after the supply of the external power supply voltage PWR_EXT is blocked, the supply of the auxiliary power supply voltage PWR_AUX may also be blocked, and thus a reset operation and / or a flush operation may be performed based on the auxiliary power supply voltage PWR_AUX before the supply of the auxiliary power supply voltage PWR_AUX is blocked. For example, as will be referred to Fig.15 , Fig.18 and Fig. 22 As described, data stored in CXL memory expander 140 may be moved to another storage space.

[0065] The DRAM-less memory device does not include a PLP capacitor for supplying an auxiliary power supply voltage under an SPO condition to reduce manufacturing costs. In this case, there is a problem that data loss occurs under an SPO condition.

[0066] In the memory system 100, the PLP capacitor 150 may be formed outside the plurality of DRAM-less memory devices 130_1 to 130_K. Therefore, data loss may be prevented using the auxiliary power supply voltage PWR_AUX supplied from the PLP capacitor 150 under the SPO condition.

[0067] Figure 6 is a block diagram showing an example of a storage system. Figure 1 The repeated description will be omitted.

[0068] Reference Figure 6 , the memory system 101 includes a host device 110, a host memory 120, a plurality of DRAM-less memory devices 130_1 to 130_K, at least one CXL memory expander 140, and a PLP capacitor 150. The memory system 101 may also include a first substrate 103_1, a second substrate 103_2, and a third substrate 103_3. For ease of description, Figure 1 Components corresponding to the bus 115 in FIG. 1 are omitted, and detailed configurations of the DRAM-less memory devices 130_1 to 130_K and the CXL memory expander 140 are omitted.

[0069] The DRAM-less memory devices 130_1 to 130_K and the CXL memory expander 140 may be mounted on the first substrate 103_1. The PLP capacitor 150 may be mounted on the second substrate 103_2 formed separately from the first substrate 103_1. The host device 110 and the host memory 120 may be mounted on the third substrate 103_3 formed separately from the first substrate 103_1 and the second substrate 103_2. For example, each of the first substrate 103_1 to the third substrate 103_3 may be a printed circuit board (PCB). The first substrate 103_1 may be referred to as a storage substrate or a memory substrate, the second substrate 103_2 may be referred to as a backplane, and the third substrate 103_3 may be referred to as a motherboard.

[0070] A backplane or backplane system is a set of electrical connectors arranged in parallel with each other so that each pin of each connector links to the same associated pin of all other connectors to form a computer bus. Backplanes are used to connect a number of printed circuit boards together to form a complete computer system. Backplanes are usually distinguished from motherboards by the lack of on-board processing and memory elements.

[0071] In the memory system 101, the PLP capacitor 150 may be mounted on a second substrate 103_2 (e.g., a base plate) that is different from the first substrate 103_1 on which the DRAM-less memory devices 130_1 to 130_K and the CXL memory expander 140 are mounted. Therefore, the PLP capacitor 150 may be mounted without reducing a space in which the DRAM-less memory devices 130_1 to 130_K and the CXL memory expander 140 are mounted.

[0072] Fig. 7A and Figure 7B It is used to describe the Figure 6 Schematic diagram of an example of a DRAM-less memory device and a CXL memory expander in a memory system.

[0073] Reference Fig. 7A , a plurality of slots 105 a , 105 b , . . . , 105 c (or any other suitable structure (such as a socket)) are formed on the first substrate 103_1 .

[0074] The DRAM-less memory devices 130_1 to 130_K and the CXL memory expander 140 may be electrically attached to and detached from the first substrate 103_1 using a plurality of slots 105a to 105c, into which the DRAM-less memory devices 130_1 to 130_K and the CXL memory expander 140 are connected (e.g., inserted). For example, the CXL memory expander 140 may be inserted into the slot 105a and electrically attached to the first substrate 103_1 and the memory system 101, and may be removed from the slot 105a and electrically detached from the first substrate 103_1 and the memory system 101. Similarly, the DRAM-less memory device 130_1 may be inserted into and removed from the slot 105b, and the DRAM-less memory device 130_K may be inserted into and removed from the slot 105c.

[0075] Reference Figure 7B , the plurality of DRAM-less memory devices 130_1 to 130_K and the CXL memory expander 140 may have the same form factor. For example, the plurality of DRAM-less memory devices 130_1 to 130_K and the CXL memory expander 140 may have the same form factor for mounting on the first substrate 103_1.

[0076] For example, the structure or configuration (eg, number, arrangement, shape, etc.) of the plurality of connectors and / or pins 135_1 of the first DRAM-less memory device 130_1 may be substantially the same as the structure or configuration of the plurality of connectors and / or pins 145 of the CXL memory expander 140. Figure 7B , but each of the remaining DRAM-less memory devices 130_2 to 130_K may also have the same form factor.

[0077] In some embodiments, the plurality of DRAM-less storage devices 130_1 to 130_K and the CXL memory expander 140 may be implemented based on an enterprise and data center standard form factor (EDSFF). For example, the plurality of DRAM-less storage devices 130_1 to 130_K and the CXL memory expander 140 may be implemented based on one of the E1.S, E1.L, E3.S, and E3.L form factors. As another example, the plurality of DRAM-less storage devices 130_1 to 130_K and the CXL memory expander 140 may be implemented based on one of the M.2 form factor, the U.2 form factor, various other PCIe-based form factors, and / or various other small form factors. Optionally, the plurality of DRAM-less storage devices 130_1 to 130_K and the CXL memory expander 140 may be implemented based on one of the other various form factors and may support a hot-swap function that may be installed on or removed from a physical port (e.g., slots 105a to 105c).

[0078] In the memory system 101, the DRAM-less memory devices 130_1 to 130_K and the CXL memory expander 140 may have the same form factor, so the number of DRAM-less memory devices 130_1 to 130_K and the number of CXL memory expanders 140 may be freely and differently determined in the memory system 101. Figure 6 and Fig. 7A In the memory system 101 including one CXL memory expander 140 and K DRAM-less memory devices 130_1 to 130_K shown in FIG, when the DRAM-less memory device 130_1 is removed from the slot 105b and another CXL memory expander is inserted into the slot 105b, a memory system including two CXL memory expanders and (K-1) DRAM-less memory devices can be easily implemented.

[0079] Figure 8 , Fig. 9 , Fig.10 and Fig.11is a diagram illustrating an example of a DRAM-less memory device and a nonvolatile memory included in a memory system.

[0080] Reference Figure 8 , DRAM-less storage devices (e.g., Figure 1 The DRAM-less memory device 130_1 in the embodiment may include a memory controller 300 and a plurality of non-volatile memories 360. The memory controller 300 may include a processor 310, a flash translation layer (FTL) 320, an ECC engine 330, a host interface (I / F) 340, and a non-volatile memory interface 350. Figure 8 , but the storage controller 300 may also include an Advanced Encryption Standard (AES) engine that performs encryption / decryption operations.

[0081] The processor 310 may respond to a request from a host device (eg, Figure 1 The processor 310 controls the operation of the memory controller 300 by receiving a request or command from the host device 110 in the memory controller 300. For example, the processor 310 may control the operation of the DRAM-less memory device, and may control corresponding components by adopting firmware (FW) for operating the DRAM-less memory device.

[0082] The FTL 320 may perform various functions (such as, for example, an address mapping operation, a wear-leveling operation, a garbage collection operation, etc.). The address mapping operation may be an operation of converting a logical address received from a host device into a physical address for storing data in the non-volatile memory 360. The wear-leveling operation may be a technique for preventing excessive degradation of a specific block by allowing the blocks of the non-volatile memory 360 to be used evenly. As an example, the wear-leveling operation may be implemented using a FW technique of balancing the erase counts of physical blocks. The garbage collection operation may be a technique for ensuring available capacity in the non-volatile memory 360 by erasing an existing block after copying valid data of the existing block to a new block.

[0083] The ECC engine 330 for error correction may perform coding modulation using, for example, Bose-Chaudhuri-Hocquenghem (BCH) codes, low-density parity-check (LDPC) codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), trellis coded modulation (TCM), block coded modulation (BCM), etc., or may perform ECC encoding and ECC decoding using the above codes or other error correction codes.

[0084] The host interface 340 may provide a physical connection between the host device and the DRAM-less memory device. The host interface 340 may provide an interface corresponding to a bus format of the host device for communication between the host device and the DRAM-less memory device.

[0085] The nonvolatile memory interface 350 may exchange data with the nonvolatile memory 360. The nonvolatile memory interface 350 may transmit data to the nonvolatile memory 360 or may receive data read from the nonvolatile memory 360. For example, the nonvolatile memory interface 350 may be configured to comply with a standard protocol such as Toggle or Open NAND Flash Interface (ONFI) as an example.

[0086] Reference Fig. 9 , showing that a host device (e.g., Figure 1 The host OS 410 executed by the host device 110 in FIG. 1 and the DRAM-less storage device (eg, Figure 1 An example of a software hierarchical structure of the storage FW 430 executed by the DRAM-less storage device 130_1 in FIG.

[0087] The host OS 410 includes an application 421 , a file system 422 , a block layer 423 , and a device driver 424 . The storage FW 430 includes a host interface layer (HIL) 441 , an FTL 442 , a device manager 443 (or a non-volatile memory manager), and a low-level driver 444 .

[0088] Application 421 may be an application software program executed on host OS 410. For example, application 421 may have been programmed to help create, copy, and delete files.

[0089] The file system 422 may manage files used by the host OS 410. For example, the file system 422 may manage file names, extensions, file attributes, file sizes, cluster information, etc. of files accessed by requests from the host OS 410 or by applications executed by the host OS 410. The file system 422 may generate, delete, and manage data based on files.

[0090] The block layer 423 may be referred to as a block input / output (I / O) layer, and may perform data read / write operations in units of memory blocks.

[0091] The device driver 424 may control the DRAM-less storage device at the OS level. The device driver 424 may be, for example, a software module of a kernel for controlling the DRAM-less storage device. The host OS 410 or an application executed by the host OS 410 may request a data read / write operation via the device driver 424.

[0092] The HIL 441 may process or handle I / O requests from the host OS 410. For example, the HIL 441 may include an I / O flow manager.

[0093] FTL 442 can be used with Figure 8 The FTL 320 in is substantially the same and may perform some operations and / or functions such as a data placement operation DP (eg, address mapping), a garbage collection operation GC, and a wear leveling operation WEL.

[0094] The device manager 443 may perform some operations and / or functions such as a metadata management operation MM, a bad block management operation BBM, and a page access scheduling operation PAS.

[0095] The low-level driver 444 may utilize non-volatile memory (e.g., Figure 8 The non-volatile memory 360 in the processor performs I / O operations.

[0096] Reference Fig.10 , the nonvolatile memory 500 includes a memory cell array 510 , an address decoder 520 , a page buffer circuit 530 , a data input / output (I / O) circuit 540 , a voltage generator 550 , and a control circuit 560 .

[0097] The memory cell array 510 may be connected to the address decoder 520 via a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL. The memory cell array 510 may also be connected to the page buffer circuit 530 via a plurality of bit lines BL. The memory cell array 510 may include a plurality of memory cells (e.g., a plurality of nonvolatile memory cells) connected to a plurality of word lines WL and a plurality of bit lines BL. The memory cell array 510 may be divided into a plurality of memory blocks BLK1, BLK2, ..., BLKz, each of which includes a memory cell, wherein z is a positive integer. In addition, each of the plurality of memory blocks BLK1 to BLKz may be divided into a plurality of pages.

[0098] In some embodiments, the plurality of memory cells included in the memory cell array 510 may be arranged in a two-dimensional (2D) array structure or a three-dimensional (3D) vertical array structure. The 3D vertical array structure may include a vertical cell string oriented vertically so that at least one memory cell is located above another memory cell. At least one memory cell may include a charge trapping layer. The following describes a suitable construction of a memory cell array including a 3D vertical array structure by reference to the patent documents fully included herein, wherein the three-dimensional memory array is constructed into multiple levels and word lines and / or bit lines are shared between levels: U.S. Patent No. 7,679,133, U.S. Patent No. 8,553,466, U.S. Patent No. 8,654,587, U.S. Patent No. 8,559,235; and U.S. Patent Publication No. 2011 / 0233648.

[0099] The control circuit 560 may be external to the nonvolatile memory 500 (e.g., from Figure 8 The memory controller 300 in the nonvolatile memory 500 receives the command CMD and the address ADDR, and can control the erase, program and read operations of the nonvolatile memory 500 based on the command CMD and the address ADDR. The erase operation may include executing an erase cycle sequence, and the program operation may include executing a program cycle sequence. Each program cycle may include a program operation and a program verification operation. Each erase cycle may include an erase operation and an erase verification operation. The read operation may include a normal read operation and a data recovery read operation.

[0100] For example, based on the command CMD, the control circuit 560 may generate a control signal CON for controlling the voltage generator 550, may generate a control signal PBC for controlling the page buffer circuit 530, and may generate a row address R_ADDR and a column address C_ADDR based on the address ADDR. The control circuit 560 may provide the row address R_ADDR to the address decoder 520, and may provide the column address C_ADDR to the data I / O circuit 540.

[0101] The address decoder 520 may be connected to the memory cell array 510 via a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL. For example, in a data erase / write / read operation, based on a row address R_ADDR, the address decoder 520 may determine at least one of the plurality of word lines WL as a selected word line, may determine at least one of the plurality of string selection lines SSL as a selected string selection line, and may determine at least one of the plurality of ground selection lines GSL as a selected ground selection line.

[0102] The voltage generator 550 may generate a voltage VS for operation of the nonvolatile memory 500 based on the power supply voltage PWR and the control signal CON. The voltage VS may be applied to a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL via the address decoder 520. In addition, the voltage generator 550 may generate an erase voltage VERS for a data erase operation based on the power supply voltage PWR and the control signal CON.

[0103] The page buffer circuit 530 may be connected to the memory cell array 510 via a plurality of bit lines BL. The page buffer circuit 530 may include a plurality of page buffers. The page buffer circuit 530 may store data DAT to be programmed into the memory cell array 510, or may read data DAT sensed from the memory cell array 510. For example, the page buffer circuit 530 may operate as a write driver or a sense amplifier according to an operation mode of the nonvolatile memory 500.

[0104] The data I / O circuit 540 may be connected to the page buffer circuit 530 via the data line DL. Based on the column address C_ADDR, the data I / O circuit 540 may provide data DAT from the outside of the nonvolatile memory 500 to the memory cell array 510 via the page buffer circuit 530, or may provide data DAT from the memory cell array 510 to the outside of the nonvolatile memory 500.

[0105] Reference Fig.11 , showing an example of a threshold voltage distribution in which 4-bit data is stored in a memory cell (eg, where each memory cell is a QLC storing data having four bits). For example, the horizontal axis may represent a threshold voltage VTH.

[0106] Each QLC may be programmed to have one of a plurality of states E, P1q, P2q, P3q, P4q, P5q, P6q, P7q, P8q, P9q, P10q, P11q, P12q, P13q, P14q, and P15q, and the threshold voltage distribution of the QLC may include a plurality of states E and P1q to P15q. For example, state E may represent an erase state, and states P1q to P15q may represent a plurality of programmed states. A plurality of threshold voltage levels VL1q, VL2q, VL3q, VL4q, VL5q, VL6q, VL7q, VL8q, VL9q, VL10q, VL11q, VL12q, VL13q, VL14q, and VL15q may be used to distinguish a plurality of states E and P1q to P15q. For example, the threshold voltage level VL1q may be used to distinguish whether a memory cell is in the erase state E or the program state P1q.

[0107] However, the present disclosure is not limited to QLC, and each memory cell included in the nonvolatile memory may be a memory cell storing k-bit data and programmed to have 2 k Any multi-bit cell that is in one of two states.

[0108] Although the nonvolatile memory is described based on NAND flash memory, the nonvolatile memory may be any nonvolatile memory (e.g., phase random access memory (PRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), etc.). Although the memory cell is described based on QLC, the memory cell included in the nonvolatile memory may be a memory cell that stores X-bit data and is programmed to have 2 X Any multi-bit cell that can be in one of two states, where X is a positive integer greater than or equal to four. In some embodiments, the memory cell included in the nonvolatile memory can be a multi-level cell (MLC) storing two bits of data or a triple-level cell (TLC) storing three bits of data.

[0109] Fig.12 and Fig.13 is a diagram illustrating an example of a CXL memory expander and a volatile memory included in a storage system.

[0110] Reference Fig.12 , CXL memory expanders (e.g., Figure 1 The CXL memory expander 140 in FIG. 1 includes a CXL controller 600 and a plurality of volatile memories 650. The CXL controller 600 includes a processor 610, a memory manager 620, a CXL interface 630, and a volatile memory interface 640. Fig.12 Although not shown, CXL controller 600 may further include an ECC engine, an AES engine, and the like.

[0111] Processor 610 may respond to a request from a host device (eg, Figure 1 The operation of CXL controller 600 is controlled based on requests or commands received from host device 110 in the CXL controller 600.

[0112] The memory manager 620 may convert a memory address (eg, a logical address or a virtual address) accessed from the host device into a physical address of the volatile memory 650 .

[0113] The CXL interface 630 may provide a physical connection between a host device and a CXL memory expander. For example, the host device and the CXL memory expander may communicate with each other using CXL.io as an I / O protocol. For example, the host device and the CXL memory expander may communicate with each other using CXL.mem as a memory access protocol. For example, CXL.io may be an inconsistent I / O protocol based on PCIe, and CXL.mem may be a protocol that supports access to memory. The above access types (e.g., CXL.io and CXL.mem) are merely exemplary, and the present disclosure is not limited thereto.

[0114] The volatile memory interface 640 may exchange data with the volatile memory 650. The volatile memory interface 640 may transmit data to the volatile memory 650 or may receive data read from the volatile memory 650.

[0115] Reference Fig.13 , the volatile memory 200 may include a control logic 210, a refresh control circuit 215, an address register 220, a memory body control logic 230, a row address multiplexer (RA MUX) 240, a column address (CA) latch 250, a row decoder, a column decoder, a memory cell array, a sense amplifier unit, an I / O gating circuit 290, a data I / O buffer 295, and a data I / O pad 299.

[0116] The memory cell array may include a plurality of memory cells. The memory cell array may include a plurality of memory bank arrays (e.g., first to fourth memory bank arrays 280a, 280b, 280c, and 280d). The row decoder may include a plurality of memory bank row decoders (e.g., first to fourth memory bank arrays 280a, 280b, 280c, and 280d, respectively connected to the first to fourth memory bank arrays 280a, 280b, 280c, and 280d, respectively). The column decoder may include a plurality of memory bank column decoders (e.g., first to fourth memory bank column decoders 270a, 270b, 270c, and 270d, respectively connected to the first to fourth memory bank arrays 280a, 280b, 280c, and 280d, respectively). The sense amplifier unit may include a plurality of bank sense amplifiers (eg, first to fourth bank sense amplifiers 285a, 285b, 285c, and 285d connected to first to fourth bank arrays 280a, 280b, 280c, and 280d, respectively).

[0117] The address register 220 may be received from outside the volatile memory 200 (e.g., from Fig.12The CXL controller 600 in FIG. 6 receives an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR.

[0118] The bank control logic 230 may generate a bank control signal in response to receiving the bank address BANK_ADDR. One bank row decoder and one bank column decoder corresponding to the received bank address BANK_ADDR may be activated in response to the bank control signal.

[0119] The refresh control circuit 215 may generate a refresh address REF_ADDR in response to receiving a refresh command or entering any self-refresh mode.

[0120] The row address multiplexer 240 may receive the row address ROW_ADDR from the address register 220 , may receive the refresh address REF_ADDR from the refresh control circuit 215 , and may selectively output the row address ROW_ADDR or the refresh address REF_ADDR.

[0121] The activated bank row decoder may decode the row address output from the row address multiplexer 240 and may activate a word line corresponding to the row address.

[0122] The column address latch 250 may receive the column address COL_ADDR from the address register 220 and may temporarily store the received column address COL_ADDR.

[0123] The activated bank column decoder may decode the column address COL_ADDR output from the column address latch 250 and may control the I / O gating circuit 290 to output data corresponding to the column address COL_ADDR.

[0124] The I / O gating circuit 290 may include a circuit for gating I / O data. For example, although not shown, the I / O gating circuit 290 may include an input data mask logic, a read data latch for storing data output from the first memory bank array 280a to the fourth memory bank array 280d, and a write driver for writing data to the first memory bank array 280a to the fourth memory bank array 280d.

[0125] The data DQ to be read from one of the first to fourth memory bank arrays 280a to 280d may be sensed by a sense amplifier connected to the one memory bank array and may be stored in a read data latch. The data DQ stored in the read data latch may be provided to a memory controller via a data I / O buffer 295 and a data I / O pad 299. The data DQ to be written to one of the first to fourth memory bank arrays 280a to 280d received via the data I / O pad 299 may be provided from the memory controller to the data I / O buffer 295. The data DQ received via the data I / O pad 299 and provided to the data I / O buffer 295 may be written to one memory bank array via a write driver in the I / O gating circuit 290.

[0126] The control logic 210 may control the operation of the volatile memory 200. For example, the control logic 210 may generate a control signal for the volatile memory 200 to perform a data write operation or a data read operation. For example, the control logic 210 may include a command decoder 211 and a mode register 212.

[0127] Although the volatile memory is described based on DRAM, the volatile memory may be any volatile memory.

[0128] Fig.14 is a block diagram showing an example of a storage system. Figure 1 The repeated description will be omitted.

[0129] Reference Fig.14 , the memory system 100a includes a plurality of DRAM-less memory devices 130_1 to 130_K, at least one CXL memory expander 140, and a PLP capacitor 150. The memory system 100a may also include a host device 110, a bus 115, a host memory 120, and at least one accelerator 160.

[0130] In addition to the storage system 100a including at least one accelerator 160, the storage system 100a can be connected to Figure 1 The storage system 100 is substantially the same. For ease of explanation, Fig.14 Only one accelerator 160 is shown in FIG. 1 , however, the storage system 100 a may include two or more accelerators.

[0131] The accelerator 160, the plurality of DRAM-less memory devices 130_1 to 130_K, and the CXL memory expander 140 may be connected to each other and may communicate with each other through the bus 115. The accelerator 160 may be formed separately, independently, and individually from the host device 110, and may perform a data processing function. The accelerator 160 may include a processing unit PU that performs a data processing function and at least one nonvolatile memory NVM that performs a data storage function. For example, the processing unit PU may have a type different from that of the processing unit included in the host device 110. For example, the processing unit PU may be at least one of various processors (e.g., a graphics processing unit (GPU), a tensor processing unit (TPU), a neural processing unit (NPU), a visual processing unit (VPU), etc.).

[0132] The accelerator 160 (e.g., the processing unit PU included in the accelerator 160) may perform at least one of the erasure coding function EC and the end-to-end data protection function E2E on the plurality of DRAM-less memory devices 130_1 to 130_K, and thus, data integrity issues associated with data stored in the plurality of DRAM-less memory devices 130_1 to 130_K may be prevented. In other words, errors occurring in the data stored in the plurality of DRAM-less memory devices 130_1 to 130_K may be effectively recovered or restored by the erasure coding function EC and / or the end-to-end data protection function E2E.

[0133] In coding theory, erasure codes are forward error correction (FEC) codes that assume bit erasures (rather than bit errors) and transform a message of k symbols into a longer message (codeword) of n symbols so that the original message can be recovered from a subset of n symbols. The fraction r = k / n is called the code rate. The fraction k' / k is called the reception efficiency, where k' represents the number of symbols required for recovery.

[0134] End-to-end protection mechanisms protect security-related data exchanges from failures within the communication link at runtime. By using end-to-end protection mechanisms, failures in the communication link can be detected and handled at runtime. End-to-end encryption is a secure communication method that prevents third parties from accessing data while it is being transmitted from one end system or device to another. In end-to-end encryption, data is encrypted on the sender's system or device, and only the intended recipient can decrypt the data. When the message travels to the destination of the message, the message cannot be read or tampered with by the Internet Service Provider (ISP), application service provider, hacker, or any other entity or service.

[0135] Fig.15 Is used to describe Fig.14 An example diagram of the operation of a storage system of FIG. Figure 5A and Figure 5B The repeated description will be omitted.

[0136] Reference Fig.15 , showing the use of Fig.14 140. When the supply of the external power supply voltage PWR_EXT is blocked (e.g., when an SPO condition occurs), the data DD stored in the CXL memory expander 140 may be flushed to the accelerator 160. For example, the data DD stored in the volatile memory VM of the CXL memory expander 140 may be flushed to the nonvolatile memory NVM of the accelerator 160 (e.g., based on the auxiliary power supply voltage PWR_AUX supplied from the PLP capacitor 150).

[0137] Fig.16 is a block diagram showing an example of a storage system. Figure 1 and Fig.14 The repeated description will be omitted.

[0138] Reference Fig.16 , the memory system 100b includes a plurality of DRAM-less memory devices 130_1 to 130_K, at least one CXL memory expander 140, and a PLP capacitor 150. The memory system 100b may also include a host device 110, a bus 115, a host memory 120, and at least one computational memory device 170.

[0139] In addition to the storage system 100b including at least one computing storage device 170, the storage system 100b can be Figure 1 The storage system 100 is substantially the same. For ease of explanation, Fig.16 Only one computing storage device 170 is shown in FIG. 1 , however, the storage system 100 b may include two or more computing storage devices.

[0140] The computing storage device 170, the plurality of DRAM-less storage devices 130_1 to 130_K, and the CXL memory expander 140 may be connected to each other and may communicate with each other through the bus 115. The computing storage device 170 may be formed separately, independently, and individually from the plurality of DRAM-less storage devices 130_1 to 130_K, and may perform a data storage function and a data processing function together. The computing storage device 170 may include a computing storage controller CSTG CONT that controls the operation of the computing storage device 170, a plurality of nonvolatile memories NVM that store data, and a buffer memory BM that temporarily stores data.

[0141] Unlike general storage devices that only perform data storage functions, computing storage devices can perform data storage functions and data processing functions together. In order to perform data storage functions and data processing functions together, computing storage devices may include hardware elements and / or software programs for performing data processing functions.

[0142] The computing storage device 170 (e.g., a computing storage controller CSTGCONT included in the computing storage device 170) can perform at least one of an erasure coding function EC and an end-to-end data protection function E2E on multiple DRAM-less storage devices 130_1 to 130_K, so that data integrity issues associated with data stored in the multiple DRAM-less storage devices 130_1 to 130_K can be prevented.

[0143] Fig.17 is a diagram showing an example of a computing storage device included in a storage system. Figure 8 The repeated description will be omitted.

[0144] Reference Fig.17 , computing storage devices (e.g., Fig.16 The computing storage device 170 in the embodiment of the present invention may include a computing storage controller 700, a plurality of non-volatile memories 790, and a buffer memory 795. The computing storage controller 700 may include a processor 710, an FTL 720, an ECC engine 730, a buffer memory interface 740, a host interface 750, a program slot 760, a computing engine 770, and a non-volatile memory interface 780.

[0145] The processor 710, the FTL 720, the ECC engine 730, the host interface 750 and the non-volatile memory interface 780 can be respectively connected to Figure 8 The processor 310, FTL 320, ECC engine 330, host interface 340 and non-volatile memory interface 350 in the embodiment are substantially the same. The non-volatile memory 790 can be connected to Figure 8 The non-volatile memory 360 is similar to that of FIG. Fig.10 The nonvolatile memories described above are implemented similarly. For example, each nonvolatile memory 790 may include a single-level cell (SLC) storing 1 bit of data, or may include a multi-bit cell storing fewer data bits than the memory cells in the nonvolatile memory QLC NVM of the DRAM-less memory devices 130_1 to 130_K. The buffer memory 795 may be a volatile memory and may be implemented similarly to the nonvolatile memory described above. Fig.13 The described memories are implemented similarly.

[0146] The buffer memory interface 740 may exchange data with the buffer memory 795. The buffer memory interface 740 may transmit data to the buffer memory 795 or may receive data read from the buffer memory 795.

[0147] The program slot 760 may store a plurality of programs. For example, the plurality of programs may include various operators (such as filtering, summing, string concatenation, etc.), and may be implemented to perform an erasure coding function EC and / or an end-to-end data protection function E2E.

[0148] The computing engine 770 may execute multiple programs, and may generate and store the results of executing multiple programs. For example, the computing engine 770 may be implemented to execute an erasure code function EC and / or an end-to-end data protection function E2E. For example, the buffer memory 795 and the non-volatile memory 790 may be used to execute multiple programs. For example, the computing engine 770 may include various computing resources (such as NPU, GPU, digital signal processor (DSP), image signal processor (ISP), etc.).

[0149] As described above, the erasure coding function EC and / or the end-to-end data protection function E2E may be offloaded to a computing storage device (eg, to the computing storage controller 700 and the computing engine 770 ).

[0150] Offloading of programs or computations means transferring resource-intensive computational tasks to a separate processor (such as a hardware accelerator) or an external platform (such as a cluster, grid, or cloud). Offloading to a coprocessor can be used to accelerate applications including image rendering and mathematical calculations. Offloading computations to an external platform over a network can provide computing power and overcome hardware limitations of the device (such as limited computing power, storage, and energy).

[0151] Fig.18 Is used to describe Fig.16 Schematic diagram of the operation of the storage system. Figure 5A and Figure 5B The repeated description will be omitted.

[0152] Reference Fig.18 , showing the use of Fig.16 140. When the supply of the external power supply voltage PWR_EXT is blocked (e.g., when an SPO condition occurs), the data DD stored in the CXL memory expander 140 may be flushed to the computing storage device 170. For example, the data DD stored in the volatile memory VM of the CXL memory expander 140 may be flushed to the nonvolatile memory NVM of the computing storage device 170 (e.g., based on the auxiliary power supply voltage PWR_AUX supplied from the PLP capacitor 150).

[0153] Fig.19 is a block diagram showing an example of a storage system. Figure 1 The repeated description will be omitted.

[0154] Reference Fig.19 , the memory system 100c includes a plurality of DRAM-less memory devices 130_1c, 130_2c, . . . , 130_Kc, at least one CXL memory expander 140, and a PLP capacitor 150. The memory system 100c may further include a host device 110, a bus 115, and a host memory 120.

[0155] Except that the configuration of the plurality of DRAM-less memory devices 130_1c to 130_Kc is partially changed, the memory system 100c may be Figure 1 The storage system 100 is basically the same.

[0156] The plurality of DRAM-less memory devices 130_1c to 130_Kc may be implemented in an open channel form. For example, each of the plurality of DRAM-less memory devices 130_1c to 130_Kc may include an open channel memory controller OCSTG CONT that controls operations of the plurality of DRAM-less memory devices 130_1c to 130_Kc, instead of a memory controller STG CONT.

[0157] The open channel memory controller OCSTG CONT may perform an enhanced ECC function EECC on the plurality of DRAM-less memory devices 130_1c to 130_Kc, and thus data integrity issues associated with data stored in the plurality of DRAM-less memory devices 130_1c to 130_Kc may be prevented.

[0158] Fig. 20 and Fig.21 It is shown that the Fig.19 Schematic diagram of an example of a DRAM-less memory device in a memory system. Figure 8 and Fig. 9 The repeated description will be omitted.

[0159] Reference Fig. 20 , DRAM-less storage devices (e.g., Fig.19 The DRAM-less memory device 130_1c) in the embodiment includes an open channel memory controller 800 and a plurality of non-volatile memories 850. The open channel memory controller 800 may include a processor 810, an enhanced ECC engine 820, a host interface 830, and a non-volatile memory interface 840.

[0160] The processor 810, the host interface 830, the non-volatile memory interface 840 and the non-volatile memory 850 can be respectively connected to Figure 8 The processor 310, host interface 340, non-volatile memory interface 350 and non-volatile memory 360 in the same embodiment are substantially the same.

[0161] The enhanced ECC engine 820 may execute Figure 8 The ECC engine 330 in FIG. 1 is similar to the ECC encoding and ECC decoding in FIG. 1 , and can perform the same Figure 8 The enhanced ECC engine 820 can perform stronger error correction than the ECC engine 330 in FIG. 8. For example, when the ECC engine 330 performs 1-bit error correction, the enhanced ECC engine 820 can perform 2-bit error correction.

[0162] Reference Fig.21 , showing that a host device (e.g., Fig.19 The host OS 910 executed by the host device 110 in FIG. 1 and the DRAM-less storage device (eg, Fig.19 An example of a software hierarchical structure of the storage FW 930 executed by the DRAM-less storage device 130_1c) in FIG.

[0163] The host OS 910 may include an application 921, a file system 922, a block layer 923, a device driver 924, and an FTL 925. The storage FW 930 may include a HIL 941, a device manager 943, and a low-level driver 944. The application 921, the file system 922, the block layer 923, the device driver 924, the HIL 941, the FTL 925, the device manager 943, and the low-level driver 944 may be respectively Fig. 9 The application 421, file system 422, block layer 423, device driver 424, HIL 441, FTL 442, device manager 443 and low-level driver 444 are basically the same.

[0164] and Figure 8 Compared with the storage controller 300, the FTL 320 can be omitted, and the ECC engine 330 can be used Fig. 20 The enhanced ECC engine 820 in the open channel storage controller 800 is replaced. Fig. 9 Compared to the example of FTL 925, FTL 925 may include Fig.21 In other words, the FTL function of the plurality of DRAM-less memory devices 130_1c to 130_Kc may be performed by the host device, and the open channel memory controller 800 may perform the enhanced ECC function instead of the FTL function.

[0165] Fig. 22 Is used to describe Fig.19An example diagram of the operation of a storage system of FIG. Figure 5A and Figure 5B The repeated description will be omitted.

[0166] Reference Fig. 22 , showing the use of Fig.19 140. The example of the operation of supplying the auxiliary power supply voltage PWR_AUX from the PLP capacitor 150 in the CXL memory expander 140. When the supply of the external power supply voltage PWR_EXT is blocked (e.g., when the SPO situation occurs), the data DD stored in the CXL memory expander 140 may be flushed to at least one of the DRAM-less memory devices 130_1c to 130_Kc. For example, the data DD stored in the volatile memory VM of the CXL memory expander 140 may be flushed to the non-volatile memory QLC NVM of the DRAM-less memory device 130_1c (e.g., based on the auxiliary power supply voltage PWR_AUX supplied from the PLP capacitor 150).

[0167] DRAM-less storage devices include multi-bit cell non-volatile memory as a storage medium to reduce manufacturing costs. In this case, there is a relatively high possibility that data integrity is damaged due to multiple distributions of non-volatile memory.

[0168] In the memory systems 100a, 100b, and 100c, the erasure coding function EC and / or the end-to-end data protection function E2E may be performed by the accelerator 160 and / or the computational memory device 170 separate from the plurality of DRAM-less memory devices 130_1 to 130_K, or the plurality of DRAM-less memory devices 130_1c to 130_Kc may perform the enhanced ECC function EECC by themselves. Therefore, data integrity problems may be prevented.

[0169] Fig.23 and Fig.24 is a block diagram illustrating an example of a data center including a storage system.

[0170] Reference Fig.23, the data center 3000 may be a facility that collects various types of data and provides various services, and may be referred to as a data storage center or server system. The data center 3000 may be a system for operating a search engine and a database, and may be a computing system used by a company such as a bank or a government agency. The data center 3000 may include a plurality of application servers 3100_1, 3100_2, ..., 3100_N and a plurality of storage servers 3200_1, 3200_2, ..., 3200_M, wherein each of N and M is a positive integer greater than or equal to two. For example, a plurality of application servers 3100_1 to 3100_N may include a first application server to an Nth application server, and a plurality of storage servers 3200_1 to 3200_M may include a first storage server to an Mth storage server. The number of the application servers 3100_1 to 3100_N and the number of the storage servers 3200_1 to 3200_M may be variously selected, and the number of the application servers 3100_1 to 3100_N and the number of the storage servers 3200_1 to 3200_M may be different from each other.

[0171] Hereinafter, an example will be described based on the first storage server 3200_1 . The application servers 3100_1 to 3100_N and the storage servers 3200_1 to 3200_M may have similar structures, and the application servers 3100_1 to 3100_N and the storage servers 3200_1 to 3200_M may communicate with each other through the network 3300 .

[0172] The first storage server 3200_1 may include a first processor 3210_1, a first memory 3220_1, a first switch 3230_1, a first network interface card (NIC) 3240_1, a first DRAM-less storage device 3250_1, and a first CXL memory expander 3260_1. The first processor 3210_1 may control the overall operation of the first storage server 3200_1, and may access the first memory 3220_1 to execute instructions and / or data loaded in the first memory 3220_1. For example, the first memory 3220_1 may include at least one of a double data rate (DDR) synchronous dynamic random access memory (SDRAM), a high bandwidth memory (HBM), a hybrid memory cube (HMC), a dual in-line memory module (DIMM), an Optane DIMM, a non-volatile DIMM (NVDIMM), etc. The number of processors and the number of memories included in the first storage server 3200_1 may be selected differently.

[0173] In some embodiments, the first processor 3210_1 and the first memory 3220_1 may provide a processor-memory pair. In some embodiments, the number of processors and the number of memories included in the first storage server 3200_1 may be different from each other. The first processor 3210_1 may include a single-core processor or a multi-core processor. The above description of the first storage server 3200_1 may be similarly applied to each of the application servers 3100_1 to 3100_N.

[0174] The first switch 3230_1 may route or relay communications between various components included in the first storage server 3200_1. The first NIC 3240_1, the first DRAM-less storage device 3250_1, and the first CXL memory expander 3260_1 may be connected to the first switch 3230_1. The first NIC 3240_1 may communicate with other storage servers 3200_2 to 3200_M and / or other application servers 3100_1 to 3100_N through the network 3300. The first DRAM-less storage device 3250_1 may store data. The first CXL memory expander 3260_1 may operate as a buffer memory for the first DRAM-less storage device 3250_1.

[0175] The first storage server 3200_1 may be implemented in the form of a storage system. For example, the first processor 3210_1, the first memory 3220_1, the first DRAM-less storage device 3250_1, and the first CXL memory expander 3260_1 may correspond to Figure 1 The host device 110, the host memory 120, the DRAM-less memory devices 130_1 to 130_K, and the CXL memory expander 140 in the first storage server 3200_1. The first storage server 3200_1 may have improved performance with a relatively large storage capacity and a low manufacturing cost.

[0176] Reference Fig.24 The data center 3001 may be implemented using a rack scale architecture (RSA) and / or a disaggregated architecture. For ease of illustration, only some components included in the storage servers 3200_1 to 3200_M are shown.

[0177] The first storage server 3200_1 may include a first processor 3210_1, a first memory 3220_1, a first DRAM-less storage device 3250_1, and a first CXL memory expander 3260_1. The second storage server 3200_2 may include a second processor 3210_2, a second memory 3220_2, a second DRAM-less storage device 3250_2, and a second CXL memory expander 3260_2. The Mth storage server 3200_M may include an Mth processor 3210_M, an Mth memory 3220_M, an Mth DRAM-less storage device 3250_M, and an Mth CXL memory expander 3260_M.

[0178] The DRAM-less memory devices 3250_1 to 3250_M and the CXL memory expanders 3260_1 to 3260_M may be mounted on the first server rack 3500_1. The memories 3220_1 to 3220_M may be mounted on the second server rack 3500_2 formed separately from the first server rack 3500_1. The processors 3210_1 to 3210_M may be mounted on the third server rack 3500_3 formed separately from the first server rack 3500_1 and the second server rack 3500_2.

[0179] For efficient server resource management, a split server architecture has been studied and / or adopted. In a general server architecture, a processor, a memory, a storage device, etc. are placed in a server and are directly connected to each other. In contrast, in a split server architecture, components of the same type can be placed together to provide a shared pool, and the components can be connected to each other based on various interconnect technologies. For example, a split server architecture can be implemented in the form of a network-attached system in which components are connected to each other via various wired and wireless networks or a fabric-attached system in which components are connected to each other via various fabric interconnects.

[0180] The disclosed examples may be applied to various electronic devices and systems including storage devices and storage systems.

[0181] Although the present disclosure includes many specific implementation details, these should not be interpreted as limiting the scope of possible protection. Certain features described in the present disclosure in the context of separate embodiments may also be implemented in combination in a single embodiment. On the contrary, various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although the features may be described above as working in some combinations, one or more features from the combination may be deleted from the combination in some cases, and the combination may be directed to a sub-combination or a variation of the sub-combination.

[0182] The foregoing is an illustration of example embodiments and should not be construed as limiting thereof. Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the example embodiments without substantially departing from the novel teachings and advantages of the example embodiments. Therefore, all such modifications are intended to be included within the scope of the example embodiments defined in the claims. Therefore, it should be understood that the foregoing is an illustration of various example embodiments and should not be construed as being limited to the specific example embodiments disclosed, and modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the appended claims.

Claims

1. A storage system, comprising: a plurality of DRAM-less memory devices, each of the plurality of DRAM-less memory devices comprising a plurality of non-volatile memories; at least one Compute Express Link (CXL) memory expander electrically connected to the plurality of DRAM-less memory devices, the at least one CXL memory expander configured to: communicate via a CXL interface and operate as a buffer memory for the plurality of DRAM-less memory devices; as well as a power-off protection PLP capacitor electrically connected to the plurality of DRAM-less memory devices and the at least one CXL memory expander and disposed outside the plurality of DRAM-less memory devices, the PLP capacitor being configured to: supply an auxiliary power supply voltage to the plurality of DRAM-less memory devices and the at least one CXL memory expander under a sudden power-off SPO condition, wherein the at least one CXL memory expander comprises a first memory region allocated for the plurality of DRAM-less memory devices, and The first memory area is configured to store mapping data including mapping information corresponding to a plurality of user data stored in the plurality of nonvolatile memories included in the plurality of DRAM-less memory devices.

2. The storage system according to claim 1, wherein: The first memory area is set at an initial operation time of the memory system.

3. The storage system according to claim 1, further comprising: a host device configured to control the operation of the storage system, wherein the at least one CXL memory expander further comprises a second memory area different from the first memory area, and The second memory area is configured to be accessed and managed by the host device.

4. The storage system according to claim 1, further comprising: at least one accelerator electrically connected to the plurality of DRAM-less memory devices and the at least one CXL memory expander and formed separately from a host device that controls operation of the memory system, The at least one accelerator is configured to perform a data processing function and to perform at least one of an erasure coding function and an end-to-end data protection function on the plurality of DRAM-less storage devices.

5. The storage system according to claim 4, wherein: Under the SPO condition, data stored in the at least one CXL memory expander is flushed to the at least one accelerator.

6. The storage system according to claim 5, wherein: The at least one accelerator includes at least one non-volatile memory, and Wherein, under the SPO condition, data stored in the at least one CXL memory expander is flushed to the at least one non-volatile memory included in the at least one accelerator.

7. The storage system according to claim 1, further comprising: at least one computational memory device electrically connected to the plurality of DRAM-less memory devices and the at least one CXL memory expander and formed separately from the plurality of DRAM-less memory devices, The at least one computing storage device is configured to perform a data storage function and a data processing function together, and to perform at least one of an erasure coding function and an end-to-end data protection function on the plurality of DRAM-less storage devices.

8. The storage system according to claim 7, wherein: Under the SPO condition, data stored in the at least one CXL memory expander is flushed to the at least one computational storage device.

9. The storage system according to claim 8, wherein: The at least one computational storage device includes a plurality of non-volatile memories, and Wherein, under the SPO condition, data stored in the at least one CXL memory expander is flushed to at least one non-volatile memory of the plurality of non-volatile memories included in the at least one computational storage device.

10. The storage system according to claim 1, wherein: Each of the plurality of DRAM-less memory devices further includes a memory controller configured to control operations of the plurality of non-volatile memories, and The memory controller is configured to perform an enhanced error correction code (ECC) function on the plurality of DRAM-less memory devices.

11. The storage system according to claim 10, wherein: Flash translation layer (FTL) functions of the plurality of DRAM-less memory devices are performed by a host device that controls the operation of the memory system, and Therein, the storage controller is configured to perform an enhanced ECC function instead of an FTL function.

12. The storage system according to claim 10, wherein: Under the SPO condition, data stored in the at least one CXL memory expander is flushed to at least one nonvolatile memory among the plurality of nonvolatile memories included in the plurality of DRAM-less memory devices.

13. The storage system according to claim 1, wherein: write data to be written to at least one non-volatile memory of the plurality of non-volatile memories of the plurality of DRAM-less memory devices is temporarily stored in the at least one CXL memory expander, and Wherein, a write operation is performed using the write data temporarily stored in the at least one CXL memory expander, in which the write data is stored in the at least one non-volatile memory of the plurality of DRAM-less memory devices.

14. The storage system according to claim 1, wherein: The plurality of nonvolatile memories included in the plurality of DRAM-less memory devices include a plurality of memory cells, each of the plurality of memory cells storing data having two bits or more.

15. The storage system according to claim 14, wherein: Each of the plurality of memory cells is a quad level cell (QLC) configured to store 4-bit data.

16. The storage system according to any one of claims 1 to 15, further comprising: a first substrate on which the plurality of DRAM-less memory devices and the at least one CXL memory expander are mounted; as well as A second substrate on which the PLP capacitor is mounted is formed separately from the first substrate.

17. The storage system according to claim 16, wherein: The plurality of DRAM-less memory devices and the at least one CXL memory expander have a same form factor for mounting on a first substrate.

18. A data center, comprising: The plurality of application servers are configured to: receive a data writing request or a data reading request; as well as A plurality of storage servers are configured to: store write data corresponding to a data write request or output read data corresponding to a data read request, Wherein, the first storage server among the multiple storage servers includes: a plurality of first DRAM-less memory devices, each of the plurality of first DRAM-less memory devices comprising a plurality of non-volatile memories; at least one first compute express link (CXL) memory expander electrically connected to the plurality of first DRAM-less memory devices, the at least one first CXL memory expander configured to: communicate via a CXL interface and operate as a buffer memory for the plurality of first DRAM-less memory devices; and a first power-off protection PLP capacitor electrically connected to the plurality of first DRAM-less memory devices and the at least one first CXL memory expander and disposed outside the plurality of first DRAM-less memory devices, the first PLP capacitor being configured to supply an auxiliary power supply voltage to the plurality of first DRAM-less memory devices and the at least one first CXL memory expander under a sudden power-off SPO condition, wherein the at least one first CXL memory expander comprises a first memory region allocated for the plurality of first DRAM-less memory devices, and The first memory area is configured to store mapping data including mapping information corresponding to a plurality of user data stored in the plurality of nonvolatile memories included in the plurality of first DRAM-less memory devices.

19. The data center according to claim 18, wherein: The first storage server also includes a first host device, wherein a second storage server among the plurality of storage servers comprises a second host device, a plurality of second DRAM-less storage devices, and at least one second CXL memory expander, and The data center further includes: a first server rack, the first host device and the second host device being mounted on the first server rack; and A second server rack, the plurality of first DRAM-less memory devices, the at least one first CXL memory expander, the plurality of second DRAM-less memory devices, and the at least one second CXL memory expander are mounted on the second server rack, and the second server rack is formed separately from the first server rack.

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