Silicon wafer measurement method and system

Abstract

The application provides a silicon wafer measurement method and system. The method comprises the following steps: measuring the topography of the silicon wafer to obtain first topography data; pretreating the silicon wafer; measuring the topography of the pretreated silicon wafer to obtain second topography data; and calculating an anti-deformation index value for characterizing the anti-deformation capability of the silicon wafer based on the first topography data and the second topography data. The application quantifies the anti-deformation capability of the silicon wafer by measuring the topography change of the silicon wafer before and after pretreatment.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of silicon wafer measurement, and particularly relates to a silicon wafer measurement method and system. BACKGROUND

[0002] With the rapid development of semiconductor technology, the importance of 3D stacking technology gradually increases. In the 3D stacking technology, the silicon wafer needs to withstand high stress in the processing and application process, which puts higher requirements on the deformation resistance of the silicon wafer. Therefore, it is necessary to quantify the deformation resistance of the silicon wafer. However, most of the related deformation resistance test methods of the silicon wafer are based on the mechanical strength measurement of the material, including three-point bending test, tensile test and compression test. These methods are usually destructive testing and are difficult to apply non-destructively in mass production. In addition, these test methods are mostly based on the intrinsic properties of the material and do not fully consider the geometric changes of the front and back surfaces of the silicon wafer, so they cannot fully reflect the overall deformation of the silicon wafer under the condition of multi-layer stacking. In addition, the thin film stress measurement technology based on the Stoney formula indirectly measures the deformation resistance by the change of curvature, but due to the low precision, it is difficult to distinguish the silicon wafers with small differences in deformation resistance, and the non-destructive property is also poor. Therefore, the related methods are difficult to meet the strict requirements of high-end applications such as 3D stacking on the quality of the silicon wafer in terms of measurement accuracy, non-destructive testing and applicability.

[0003] Based on this, the present application provides a silicon wafer measurement method and system to improve the related technology. SUMMARY

[0004] The purpose of the present application is to provide a silicon wafer measurement method and system to quantify the deformation resistance of the silicon wafer.

[0005] The purpose of the present application is achieved by the following technical solutions:

[0006] In a first aspect, the present application provides a silicon wafer measurement method, which comprises: measuring the topography of the silicon wafer to obtain first topography data; pretreating the silicon wafer; measuring the topography of the pretreated silicon wafer to obtain second topography data; and calculating a deformation resistance index value for characterizing the deformation resistance of the silicon wafer based on the first topography data and the second topography data.

[0007] In some embodiments, the measuring the topography of the silicon wafer to obtain first topography data comprises: measuring the front and back topographies of the silicon wafer to obtain first topography data including first front topography data and first back topography data; and the measuring the topography of the pretreated silicon wafer to obtain second topography data comprises: measuring the front and back topographies of the pretreated silicon wafer to obtain second topography data including second front topography data and second back topography data.

[0008] In some embodiments, the anti-deformation index value for characterizing the anti-deformation capability of the silicon wafer is calculated based on the first topography data and the second topography data, including: calculating the out-of-plane deformation of each measurement point of the silicon wafer based on the first topography data, the first back surface topography data, the second topography data and the second back surface topography data; summing the absolute values of the out-of-plane deformations of the measurement points of the silicon wafer to obtain a deformation degree; and taking the negative value of the deformation degree as the anti-deformation index value for characterizing the anti-deformation capability of the silicon wafer.

[0009] In some embodiments, the out-of-plane deformation of each measurement point of the silicon wafer is calculated based on the first topography data, the first back surface topography data, the second topography data and the second back surface topography data, including: calculating the first mid-surface value of each measurement point of the silicon wafer based on the first topography data and the first back surface topography data; calculating the second mid-surface value of each measurement point of the silicon wafer based on the second topography data and the second back surface topography data; and calculating the difference between the first mid-surface value and the second mid-surface value of at least one measurement point to obtain the out-of-plane deformation of the measurement point.

[0010] In some embodiments, the measurement of the topography of the silicon wafer includes capacitive measurement and / or optical measurement.

[0011] In some embodiments, the measurement of the topography of the silicon wafer is determined according to the diffuse reflection parameter value and / or the roughness parameter value of the surface of the silicon wafer.

[0012] In some embodiments, when the diffuse reflection parameter value is greater than a first target value and / or the roughness parameter value is greater than a second target value, the measurement of the topography of the silicon wafer is capacitive measurement.

[0013] In some embodiments, the pretreatment includes heat treatment and / or thin film deposition.

[0014] In some embodiments, the method further includes: based on the anti-deformation index value, processing the production process of the silicon wafer.

[0015] In a second aspect, the present application provides a silicon wafer measurement system, which comprises a topography measurement module, a pretreatment module and a control module; the topography measurement module is configured to measure the topography of the silicon wafer to obtain first topography data; the pretreatment module is configured to pretreat the silicon wafer; the topography measurement module is further configured to measure the topography of the pretreated silicon wafer to obtain second topography data; and the control module is configured to calculate a deformation resistance index value for characterizing the deformation resistance of the silicon wafer based on the first topography data and the second topography data.

[0016] The present application provides a silicon wafer measurement method and system. First, the topography of the silicon wafer is measured to obtain first topography data. Next, the silicon wafer is pretreated. Then, the topography of the pretreated silicon wafer is measured to obtain second topography data. After that, a deformation resistance index value for characterizing the deformation resistance of the silicon wafer is calculated based on the first topography data and the second topography data. The present application quantifies the deformation resistance of the silicon wafer by measuring the topography change of the silicon wafer before and after pretreatment. When the pretreatment operation is required in the production process of the silicon wafer, the present application can accurately measure the deformation resistance of the silicon wafer without damage, and is particularly suitable for detecting silicon wafers with different characteristics in mass production environment. In addition, the calculated deformation resistance index value can be used to determine the process control measures in production, which is beneficial to improve the production efficiency and product yield of the silicon wafer. BRIEF DESCRIPTION OF DRAWINGS

[0017] The present application will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0018] Figure 1 is a flowchart of a silicon wafer measurement method provided by an embodiment of the present application.

[0019] Figure 2 is a box plot of the deformation resistance index value of a silicon wafer (different oxygen content gradient, different nitrogen content gradient) provided by an embodiment of the present application.

[0020] Figure 3 is a box plot of the deformation resistance index value of a silicon wafer (different boron doping amount) provided by an embodiment of the present application. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the accompanying drawings in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0022] In the description of the embodiments of the present application, it should be understood that the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise explicitly specified.

[0023] The planar transistor integration method has reached the physical limit, and the advanced transistor structure evolves in the 3D direction. The memory device based on the designed structure also has 3D stacking. Some advanced packaging technologies and products such as HBM also involve 3D stacking. In the past, silicon wafers were supplied for "planar integration or 3D stacking with a small number of layers". Under the action of thermal stress caused by mechanical stress and thermal history in 3D stacking, great deformation is caused, which restricts the limit of stacking. Therefore, it is urgent to quantify the anti-deformation ability of silicon wafers and develop silicon wafers with high anti-deformation ability.

[0024] In the related art, based on the consideration of the intrinsic properties of the material, the anti-deformation ability of the silicon wafer is equated to the mechanical strength of the silicon wafer, and the corresponding measurement method includes three-point bending test, tensile test, compression test, etc., but these test methods are not non-destructive and are difficult to apply to mass production. In addition, mechanically equating the anti-deformation ability to the mechanical strength ignores the influence of the geometric shape of the silicon wafer. Other measurement techniques, such as thin film stress measurement based on the Stony formula, have low measurement accuracy and cannot distinguish individuals with small differences in anti-deformation ability.

[0025] In order to improve the related art, it is urgent to develop an anti-deformation ability measurement method that not only quantifies the anti-deformation ability of the silicon wafer, but also controls the process in production based on the anti-deformation ability index.

[0026] The applicant found in practice that the out-of-plane deformation at any position of the silicon wafer is related to the thickness of the silicon wafer at this position, the intrinsic properties of the material Young's modulus, the geometric appearance and the stress distribution, which is described by formula (1) as follows.

[0027]

[0028] Wherein, the subscripts x, y represent the two-dimensional coordinates of the measurement points on the silicon wafer, z represents the out-of-plane deformation, h represents the thickness, E represents the intrinsic properties of the material Young's modulus, f represents the geometric appearance, and σ h represents the stress distribution. The absolute values of the out-of-plane deformations of all measurement points are summed to obtain the deformation degree, and the deformation degree is taken as negative to define the anti-deformation ability Rd. Rd can be used to represent the anti-deformation ability of the whole silicon wafer, and its expression is shown in formula (2).

[0029] Rd = -∑|z x,y | (2)

[0030] The greater the Rd, the smaller the degree of deformation and the stronger the deformation resistance; the smaller the Rd, the greater the degree of deformation and the weaker the deformation resistance. However, the out-of-plane deformation amount can also be obtained in actual measurement, and the embodiments of the present application will be described in detail below.

[0031] Referring to Figure 1 , Figure 1 is a flowchart of a silicon wafer measurement method provided by an embodiment of the present application.

[0032] The embodiment of the present application provides a silicon wafer measurement method, which comprises steps S101-S104.

[0033] Step S101: measuring the topography of the silicon wafer to obtain first topography data.

[0034] Step S102: pretreating the silicon wafer.

[0035] Step S103: measuring the topography of the pretreated silicon wafer to obtain second topography data.

[0036] Step S104: calculating a deformation resistance index value for characterizing the deformation resistance of the silicon wafer based on the first topography data and the second topography data.

[0037] In the above embodiment, the topography data can be regarded as geometric topography data, which can be measured by a topography measurement module, for example. The "first topography data" and the "second topography data" are both topography data, and the prefixes "first" and "second" only serve to distinguish. As an example, the topography measurement module can measure a plurality of measurement points of the silicon wafer to obtain topography information corresponding to each measurement point. That is, the topography data can include topography information corresponding to a plurality of measurement points. The topography information can be represented by a numerical value, and its symbol can be positive or negative. In actual application, the positive direction of the topography information can be set through the user interface of the topography measurement module.

[0038] In some embodiments, the pretreatment can include heat treatment and / or thin film deposition.

[0039] In the above embodiment, a process can be selected to pretreat the silicon wafer, which can be thin film deposition, heat treatment process, etc., and the above embodiment does not limit this. In some embodiments, the pretreatment operation adopted for all silicon wafers participating in measurement can be the same.

[0040] The above embodiment obtains the shape change of the silicon wafer under stress by measuring the shape data of the silicon wafer before and after pretreatment. Based on the first shape data and the second shape data, the anti-deformation index value of the silicon wafer is calculated, and the anti-deformation capability of the silicon wafer under mechanical stress and / or thermal stress is effectively quantified. This method can accurately measure the anti-deformation capability of the silicon wafer and is suitable for mass production detection.

[0041] In some embodiments, the measuring the shape of the silicon wafer to obtain the first shape data can include: measuring the front surface shape and the back surface shape of the silicon wafer to obtain the first shape data including the first front surface shape data and the first back surface shape data.

[0042] In some embodiments, the measuring the shape of the silicon wafer after pretreatment to obtain the second shape data can include: measuring the front surface shape and the back surface shape of the silicon wafer after pretreatment to obtain the second shape data including the second front surface shape data and the second back surface shape data.

[0043] The related art only focuses on single surface data and fails to reflect the overall effect of the shape change of the front surface and the back surface of the silicon wafer, and it is difficult to accurately characterize the anti-deformation capability of the silicon wafer in actual 3D stacking and complex processes. In the above embodiment, the front surface and the back surface of the silicon wafer are first measured to obtain the first shape data. Subsequently, one or more pretreatment operations such as heat treatment or thin film deposition are performed on the silicon wafer, and then the front surface and the back surface of the silicon wafer are measured again to obtain the second shape data. By comparing the shape data before and after the pretreatment, and considering the influence of the deformation of the front surface and the back surface of the silicon wafer on the overall anti-deformation capability, the overall shape change of the silicon wafer under different stresses is accurately reflected, the measurement accuracy is improved, and it is beneficial to distinguish individual silicon wafers with small differences in anti-deformation capability.

[0044] In some embodiments, the calculating the anti-deformation index value for characterizing the anti-deformation capability of the silicon wafer based on the first shape data and the second shape data can include: calculating the out-of-plane deformation amount of a plurality of measurement points of the silicon wafer based on the first front surface shape data, the first back surface shape data, the second front surface shape data, and the second back surface shape data; summing the absolute values of the out-of-plane deformation amounts of the plurality of measurement points of the silicon wafer to obtain a deformation degree; and taking the negative value of the deformation degree as the anti-deformation index value for characterizing the anti-deformation capability of the silicon wafer.

[0045] In the above embodiment, the out-of-plane deformation amount of each measurement point is calculated by comparing the shape data before and after the pretreatment, which represents the deformation of the measurement point under stress. Subsequently, the absolute values of the out-of-plane deformation amounts of the measurement points are added to obtain the deformation degree of the silicon wafer, and the negative value of the deformation degree is taken as the anti-deformation index value. The anti-deformation index value reflects the influence of the front surface and the back surface shape on the anti-deformation capability and accurately quantifies the overall deformation of the silicon wafer.

[0046] In some embodiments, the calculating the out-of-plane deformation of each measuring point of the silicon wafer based on the first front surface topography data, the first back surface topography data, the second front surface topography data and the second back surface topography data can comprise: calculating a first middle surface value of each measuring point of the silicon wafer based on the first front surface topography data and the first back surface topography data; calculating a second middle surface value of each measuring point of the silicon wafer based on the second front surface topography data and the second back surface topography data; and calculating the out-of-plane deformation of each measuring point by calculating the difference between the first middle surface value and the second middle surface value of the measuring point.

[0047] The middle surface value represents the deformation of the silicon wafer in the thickness direction. The first middle surface value and the second middle surface value are both middle surface values, and the prefixes "first" and "second" are only used for differentiation. The first middle surface value refers to the middle surface value before the pretreatment, and the second middle surface value refers to the middle surface value after the pretreatment.

[0048] In some embodiments, the first front surface topography data F1 can include the first front surface topography information f1(x, y) of the measuring point (x, y), the first back surface topography data B1 can include the first back surface topography information b1(x, y) of the measuring point (x, y), the second front surface topography data F2 can include the second front surface topography information f2(x, y) of the measuring point (x, y), and the second back surface topography data B2 can include the second back surface topography information b2(x, y) of the measuring point (x, y). As an example, for the measuring point (x, y), the average of the first front surface topography information f1(x, y) and the first back surface topography information b1(x, y) thereof is taken as the first middle surface value, and the first middle surface value is The average of the second front surface topography information f2(x, y) and the second back surface topography information b2(x, y) thereof is taken as the second middle surface value, and the second middle surface value is

[0049] The above embodiments can obtain the out-of-plane deformation of each measuring point by calculating the difference between the first middle surface value and the second middle surface value of the measuring point, which can accurately reflect the deformation degree of the silicon wafer in the thickness direction under different stress conditions. When the pretreatment operation is an operation required in the production process of the silicon wafer, this method can measure the anti-deformation ability of the silicon wafer with high precision and without damage, and is suitable for batch detection in mass production environment. By calculating the out-of-plane deformation of each measuring point, the deformation of each measuring point can be comprehensively considered, which provides a comprehensive basis for representing the overall anti-deformation ability of the silicon wafer.

[0050] In some embodiments, the measurement method of the topography of the silicon wafer can include a capacitive measurement and / or an optical measurement.

[0051] In the above embodiments, the topography data of the front side and back side of the silicon wafer can be measured by a capacitive measurement and / or an optical measurement. The capacitive measurement can utilize a capacitive sensor to detect the small height variations on the surface of the silicon wafer. The capacitive sensor detects the surface topography of the silicon wafer by sensing the distance variation between the probe and the surface of the silicon wafer. This method is sensitive to diffuse reflection surfaces and is suitable for detecting samples with high surface roughness or low reflectivity. The optical measurement can utilize optical instruments (e.g., interferometer or laser measurement device) to detect the topography of the silicon wafer. By analyzing the phase or interference pattern of the reflected light from the surface of the silicon wafer, the height difference of the surface of the silicon wafer can be measured with high precision, which is suitable for smooth and reflective silicon wafer surfaces.

[0052] In some embodiments, the measurement method of the topography of the silicon wafer can be determined according to the diffuse reflection parameter value and / or the roughness parameter value of the surface of the silicon wafer. In some embodiments, when the diffuse reflection parameter value is greater than a first target value and / or when the roughness parameter value is greater than a second target value, the measurement method of the topography of the silicon wafer can be a capacitive measurement.

[0053] The diffuse reflection parameter value represents the light scattering characteristics of the surface of the silicon wafer, and a higher diffuse reflection parameter value indicates a rough and non-smooth surface. The roughness parameter value is, for example, an average measure of the microscopic unevenness of the surface, and a higher roughness parameter value indicates a rough and non-smooth surface. In the above embodiments, the appropriate measurement method is selected based on the diffuse reflection degree (e.g., represented by the diffuse reflection parameter value) and / or the roughness (e.g., represented by the roughness parameter value) of the surface of the silicon wafer. As an example, capacitive measurement is selected in the case of strong diffuse reflection, and otherwise optical measurement is selected, so as to obtain the topography data of the silicon wafer.

[0054] The first target value and the second target value are values for judging the surface characteristics of the silicon wafer, and are used for selecting a suitable measurement mode. The capacitance type measurement is used preferentially when the diffuse reflection parameter value and the roughness parameter value exceed their corresponding target values. The diffuse reflection parameter value and / or the roughness parameter value of the surface of the silicon wafer are used as the basis for selecting the measurement mode in the above embodiment. When the diffuse reflection parameter value is higher than the first target value, and / or the roughness parameter value is higher than the second target value, it indicates that the surface of the silicon wafer is relatively rough and not smooth, and the capacitance type measurement can be selected. When both are lower than their corresponding target values, it indicates that the surface of the silicon wafer is relatively smooth, and the optical type measurement can be selected. The measurement mode is automatically selected based on the diffuse reflection parameter value and the roughness parameter value. This measurement mode automatic switching mechanism based on the surface characteristics of the silicon wafer facilitates the use of the corresponding measurement mode for silicon wafers with different surface characteristics, reduces measurement errors caused by different surface characteristics, and can significantly improve the adaptability and accuracy of silicon wafer topography measurement. Compared with the fixed measurement mode, the above embodiment provides higher accuracy in the case of varying surface characteristics of the silicon wafer, and is beneficial to realize non-destructive and efficient measurement of silicon wafers with complex surface types.

[0055] Referring to Figure 2 , Figure 2 is a box plot of a deformation resistance index value of a silicon wafer (different oxygen content gradients, different nitrogen content gradients). The deformation resistance Rd is the deformation resistance index value Rd, and its unit is, for example, μm (micrometer).

[0056] In one specific application scenario, silicon wafers with different characteristics (for example, different oxygen content gradients, different nitrogen content gradients) are taken, thin films are deposited thereon, topography data before and after the long film is measured, and the deformation resistance is calculated. The results are shown in Table 1 and Figure 2 .

[0057] Table 1

[0058]

[0059]

[0060] Among them, 3PCS N and 8PCS N represent different nitrogen content gradients, and 4.5ppma Oi and 10ppma Oi represent different oxygen content gradients. As can be seen from Figure 2 , the deformation resistance of silicon wafers with different characteristics is different. In the same characteristic group, the group difference of the calculated deformation resistance index value is small, which conforms to the actual situation, and indicates that this deformation resistance calculation method can accurately measure the deformation resistance of the silicon wafer with high precision.

[0061] Referring to Figure 3 , Figure 3is a box plot of a deformation resistance index value of a silicon wafer (different boron doping amounts) provided by an embodiment of the present application.

[0062] In another specific application scenario, 300pcs of polished silicon wafers with boron doping amounts of e15 and e17 respectively are taken, thin film deposition is performed, an epitaxial layer is grown, and an epitaxial wafer is obtained, for example, with an epitaxial layer thickness of 5μm. The topography data of the silicon wafers before and after epitaxial growth are measured respectively, the deformation resistance index value is calculated, and the results are shown in the box plot of FIG. 6. Figure 3 As can be seen, there is a difference in the deformation resistance of the lightly doped epitaxial wafer EPI (p / p-) and the heavily doped epitaxial wafer EPI (p / p+) with the same thickness. The deformation degree of the lightly doped silicon wafer (boron doping amount e15) is smaller, and the deformation resistance index value Rd is larger. The deformation degree of the heavily doped silicon wafer (boron doping amount e17) is larger, and the deformation resistance index value Rd is smaller. The measurement results are consistent with scientific reasoning, because the doping element (for example, boron) to some extent destroys the periodic crystal structure of the single crystal, resulting in a decrease in mechanical properties.

[0063] In some embodiments, the method can further include: based on the deformation resistance index value, processing the production process of the silicon wafer.

[0064] Processing the production process of the silicon wafer, for example, can take process adjustment or quality control measures according to the deformation resistance index value of the silicon wafer, aiming to optimize the production process. Specific processing operations may, for example, include adjusting process parameters, correcting process links, or screening silicon wafers, etc., to ensure that the finished product meets the design requirements of the deformation resistance performance.

[0065] In semiconductor production, the deformation resistance of the silicon wafer affects its stability and applicability in 3D stacking, precision packaging and other processes. However, the related art lacks real-time evaluation of the deformation resistance of the silicon wafer and production process control measures based on the evaluation results, making it difficult to effectively control the final quality of the silicon wafer, especially in mass production. The above embodiments calculate the deformation resistance index value by measuring the topography change of the silicon wafer, and use the deformation resistance index value as a benchmark for process control of the silicon wafer in production. For example, according to the deformation resistance index value, the production process parameters can be adjusted in time. For example, when the deformation resistance index value is lower than a predetermined value, the process parameters such as heat treatment time or deposition temperature are automatically adjusted to improve the deformation resistance performance of the silicon wafer, ensuring the stability of the deformation resistance performance of the silicon wafer and reducing the quality fluctuations caused by process differences. Based on the deformation resistance index value, the production process is intelligently and finely regulated in real time, significantly improving the deformation resistance performance consistency and finished product quality of the silicon wafer. Compared with the production method relying on fixed process parameters, this method can optimize the production process according to the specific deformation resistance performance requirements of each batch of silicon wafers, improve the flexibility and adaptability of the production line, and provide a reliable quality control means for high-precision 3D stacking and precision packaging processes, which is conducive to improving the overall production efficiency and product yield.

[0066] The embodiment of the present application also provides a silicon wafer measurement system, which comprises a topography measurement module, a pretreatment module and a control module. The topography measurement module is used for measuring the topography of the silicon wafer to obtain first topography data. The pretreatment module is used for pretreating the silicon wafer. The topography measurement module is also used for measuring the topography of the pretreated silicon wafer to obtain second topography data. The control module is used for calculating an anti-deformation index value for characterizing the anti-deformation capability of the silicon wafer based on the first topography data and the second topography data.

[0067] In some embodiments, the topography measurement module can comprise a capacitance measurement unit and / or an optical measurement unit. The capacitance measurement unit comprises, for example, a capacitance sensor. The optical measurement unit comprises, for example, an interferometer and / or a laser measurement device.

[0068] It should be noted that each of the embodiments in the present application is described in a progressive manner, and the same or similar parts of each of the embodiments can be referred to each other. Each of the embodiments focuses on the differences from other embodiments. In particular, the product embodiments are described more simply because they are basically similar to the method embodiments, and the relevant parts can be referred to the part of the method embodiments.

[0069] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning as understood by a person of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "include", "contain", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms do not mean physical or mechanical connection, but can include electrical connection, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like only represent relative positional relationships, and when the absolute positions of the described objects change, the relative positional relationships can also change accordingly.

[0070] It can be understood that when an element such as a layer, a film, a region, or a substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or an intermediate element can be present.

[0071] In the description of the above-described embodiments, specific features, structures, materials, or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0072] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A silicon wafer measurement method, characterized in that: The method comprises: measuring the topography of the silicon wafer to obtain first topography data; Pre-treating the silicon wafer; measuring the topography of the pre-processed silicon wafer to obtain second topography data; calculating, based on the first topography data and the second topography data, an anti-deformation index value for characterizing the anti-deformation capability of the silicon wafer; The measuring of the topography of the silicon wafer to obtain first topography data includes: measuring the front topography and the back topography of the silicon wafer to obtain first topography data including first front topography data and first back topography data; Measuring the topography of the pre-processed silicon wafer to obtain second topography data includes: measuring the topography of the front side and the back side of the pre-processed silicon wafer to obtain second topography data including second front side topography data and second back side topography data; The method of calculating an anti-deformation index value for characterizing the anti-deformation ability of the silicon wafer based on the first topography data and the second topography data includes: calculating the corresponding out-of-plane deformation amounts of multiple measurement points of the silicon wafer based on the first front-side topography data, the first back-side topography data, the second front-side topography data, and the second back-side topography data; summing the absolute values ​​of the corresponding out-of-plane deformation amounts of the multiple measurement points of the silicon wafer to obtain a deformation degree; and taking a negative value of the deformation degree as the anti-deformation index value for characterizing the anti-deformation ability of the silicon wafer.

2. The silicon wafer measurement method according to claim 1, characterized in that: The step of calculating the corresponding out-of-plane deformation amounts of a plurality of measurement points of the silicon wafer based on the first front surface topography data, the first back surface topography data, the second front surface topography data, and the second back surface topography data comprises: Calculating first mid-surface values ​​corresponding to a plurality of measurement points of the silicon wafer using the first front-side topography data and the first back-side topography data; Calculating second median surface values ​​corresponding to a plurality of measurement points of the silicon wafer using the second front surface topography data and the second back surface topography data; For at least one measuring point, a difference between a first median curved surface value and a second median curved surface value corresponding to the measuring point is calculated to obtain an out-of-plane deformation corresponding to the measuring point.

3. The silicon wafer measurement method according to claim 1, wherein: The measurement method of the silicon wafer topography includes capacitive measurement and / or optical measurement.

4. The silicon wafer measurement method according to claim 3, characterized in that: The method for measuring the topography of the silicon wafer is determined according to the diffuse reflection parameter value and / or the roughness parameter value of the silicon wafer surface.

5. The silicon wafer measurement method according to claim 4, characterized in that: When the diffuse reflection parameter value is greater than a first target value and / or the roughness parameter value is greater than a second target value, the topography of the silicon wafer is measured by capacitive measurement.

6. The silicon wafer measurement method according to claim 1, characterized in that: The pretreatment includes heat treatment and / or thin film deposition.

7. The silicon wafer measurement method according to claim 1, characterized in that: The method further comprises: Based on the anti-deformation index value, the production process of the silicon wafer is processed.

8. A silicon wafer measurement system, characterized in that: The system includes a shape measurement module, a preprocessing module and a control module; The topography measurement module is used to measure the topography of the silicon wafer to obtain first topography data; The pre-processing module is used to pre-process the silicon wafer; The topography measurement module is further used to measure the topography of the pre-processed silicon wafer to obtain second topography data; The control module is configured to calculate an anti-deformation index value for characterizing the anti-deformation capability of the silicon wafer based on the first topography data and the second topography data; The topography measurement module is used to measure the front and back topography of the silicon wafer to obtain first topography data including first front topography data and first back topography data; The topography measurement module is further used to measure the front and back topography of the pre-processed silicon wafer to obtain second topography data including second front topography data and second back topography data; The control module is used to calculate the corresponding out-of-plane deformation of multiple measurement points of the silicon wafer based on the first front side morphology data, the first back side morphology data, the second front side morphology data and the second back side morphology data; sum the absolute values ​​of the corresponding out-of-plane deformation of the multiple measurement points of the silicon wafer to obtain a deformation degree; and take a negative value of the deformation degree as an anti-deformation index value for characterizing the anti-deformation ability of the silicon wafer.

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