Three-dimensional integrated structure and manufacturing method thereof
By cutting edges of the beveled surface and clamping surface of the peripheral area in the three-dimensional integration process, the problems of poor photoresist coverage and fixture damage after cutting are solved, the complete coverage of the effective device area and stable clamping of the structure are achieved, and the quality of the three-dimensional integrated structure is improved.
Patent Information
- Application Number
- CN202411750324.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2022-07-27
- Publication Date
- 2025-03-18
AI Technical Summary
In the three-dimensional integration process, the edges of the stacked wafers after cutting edges form steep steps, making it difficult to cover the light resistance and forming excess solder blocks, affecting the subsequent process, and the existing process fixtures clamp the top surface easily cause damage.
By performing an edge cutting process on the peripheral area, a beveled surface adjacent to and surrounding the effective device area is formed, and a clamping surface is formed outside the beveled surface, so as to ensure that the connection area between the effective device area and the beveled surface is covered when applying the photoresist layer, avoiding the formation of the unresisted region, and stably clamping the stacked wafer through the clamping surface to avoid damage to the top surface of the fixture.
It effectively avoids the formation of excess solder blocks on the edge of the stacked wafer, ensures the integrity and area of the effective device area, avoids damage to the top surface by fixtures, and improves the quality of the three-dimensional integrated structure.
Smart Images
Figure CN119650514A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a three-dimensional integrated structure and a manufacturing method thereof. Background Art
[0002] Three-dimensional integration technology can realize high-performance integrated interconnection circuits and is a new technology for obtaining high-performance chips. In the three-dimensional integration process, multiple wafers are stacked and connected, and solder blocks are made on one side of the stacked wafers to connect to the outside. Before making the solder blocks, the edge portions of the stacked wafers are usually cut off at a certain depth (i.e., trimming depth) and a certain width (i.e., trimming width) by a trimming process. The trimming process can remove the poorly fitted portions of the stacked wafer edges, and help ensure that the edges of the stacked wafers are complete and smooth, and can also eliminate stress at the edges of the stacked wafers.
[0003] In the process of making solder bumps after the trimming process, it is necessary to coat the wafer surface with photoresist and form solder bumps in the non-photoresist area; however, Figure 1 As shown, in an existing process, after trimming, a steep and high step is formed at the edge of the stacked wafer 10, which makes it difficult for the photoresist PR to be stacked high to cover the corner of the step edge (such as Figure 1 When the solder block 11 is formed in the non-photoresist area, redundant solder blocks are easily formed at the corner, which affects the subsequent process. Figure 1 Reference numeral 12 indicates a clamp.
[0004] In order to avoid the formation of redundant solder bumps 11 at the edge of the stacked wafer 10, as shown in FIG. Figure 2 As shown, in another prior art process, when forming the solder bump 11 in the non-photoresist area, the clamp 12 is clamped on the top surface of the stacked wafer 10. However, with the development of the process, the number of wafers included in the stacked wafer 10 increases, and the trimming width and trimming depth required by the process increase. Figure 2 The method shown is likely to cause damage to the top surface of the stacked wafer 10, affecting the structure and area of the effective device area, and is difficult to meet process requirements. Summary of the invention
[0005] In order to avoid forming redundant structures (such as solder bumps) at the edges of stacked wafers and not affecting the structures in the effective device area and the area of the effective device area, the present invention provides a three-dimensional integrated structure and a method for manufacturing the three-dimensional integrated structure.
[0006] In one aspect, the present invention provides a method for manufacturing a three-dimensional integrated structure, comprising:
[0007] Obtaining a stacked wafer, the stacked wafer comprising an effective device region and a peripheral region located outside the effective device region;
[0008] A trimming process is performed corresponding to the peripheral area to form a beveled surface adjacent to and surrounding the effective device area and a clamping surface located outside the beveled surface and adjacent to the beveled surface, wherein from the edge of the effective device area to the outside, the thickness of the stacked wafer gradually decreases through the beveled surface, and the inclination of the clamping surface is smaller than the inclination of the beveled surface.
[0009] Optionally, forming the chamfered surface and the clamping surface comprises:
[0010] performing a first trimming process corresponding to the peripheral area to form the chamfered surface; and
[0011] A second trimming process is performed corresponding to at least a portion of the outer edge of the peripheral area to form a clamping surface, and a step difference is formed between the clamping surface and the chamfered surface on the inner side of the clamping surface.
[0012] Optionally, after forming the chamfered surface and the clamping surface, the manufacturing method further comprises:
[0013] Coating a photoresist layer on the surface of the stacked wafer, wherein the photoresist layer continuously covers the effective device area and the chamfered surface;
[0014] exposing and developing the photoresist layer to form an opening penetrating the photoresist layer in the effective device region; and
[0015] A solder bump is formed in the opening.
[0016] Optionally, a solder mass is formed in the opening by an electroplating process, and during the electroplating process, a clamp is used to clamp the stacked wafers on the clamping surface.
[0017] Optionally, the step height is smaller than the thickness of the photoresist layer.
[0018] On the one hand, the present invention provides a three-dimensional integrated structure, which includes a stacked wafer, wherein the stacked wafer includes an effective device area and a peripheral area located outside the effective device area, the peripheral area has a beveled surface adjacent to and surrounding the effective device area, and a clamping surface located outside the beveled surface and adjacent to the beveled surface, wherein, from the edge of the effective device area to the outside, the thickness of the stacked wafer gradually decreases through the beveled surface, and the inclination of the clamping surface is smaller than the inclination of the beveled surface.
[0019] Optionally, the clamping surface surrounds the chamfered surface, or the clamping surface is located at a portion of the outer edge of the chamfered surface.
[0020] Optionally, there is a step difference between the clamping surface and the chamfered surface on the inner side of the clamping surface.
[0021] Optionally, the stacked wafer includes at least one solder bump disposed in the active device area.
[0022] Optionally, the width of the clamping surface is 3 mm to 5 mm.
[0023] In the method for manufacturing a three-dimensional integrated structure provided by the present invention, a trimming process is performed corresponding to the peripheral area to form a beveled surface adjacent to and surrounding the effective device area, wherein, from the edge of the effective device area to the outside, the thickness of the stacked wafer is gradually reduced through the beveled surface, so that when a photoresist layer is subsequently coated, the connection area between the effective device area and the beveled surface is easily covered by the photoresist layer, thereby avoiding the formation of a non-photoresist area and affecting subsequent processes; and, in order to facilitate the stable clamping of the stacked wafers during subsequent processes and transportation, a clamping surface located outside the beveled surface and adjacent to the beveled surface is also formed through the trimming process. By utilizing the clamping surface, there is no need to clamp the clamp on the top surface of the stacked wafer, which can avoid the clamp causing damage to the top surface of the stacked wafer and causing adverse effects on the structure in the effective device area and the area of the effective device area, which is conducive to meeting process requirements.
[0024] In the three-dimensional integrated structure provided by the present invention, the peripheral area has a chamfer adjacent to and surrounding the effective device area and a clamping surface located on the outside of the chamfer and adjacent to the chamfer. In the process of forming a solder block or other processes that require covering the area outside the effective device area, the connection area between the effective device area and the chamfer is easily covered, avoiding the formation of a light-resistance-free area and the formation of unnecessary structures (such as solder blocks) in the area outside the effective device area. In addition, while utilizing the clamping surface to ensure that the stacked wafers can be stably clamped, it can be avoided that the clamp causes damage to the top surface of the stacked wafer and causes adverse effects on the structure in the effective device area and the area of the effective device area, which is beneficial to improving the quality of the three-dimensional integrated structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 The present invention is a schematic diagram of the cross-sectional structure of an existing process in which a photoresist layer is first formed on a stacked wafer after edge trimming and then a solder block is formed in an opening of the photoresist layer.
[0026] Figure 2 It is a schematic cross-sectional structure diagram of another existing process in which a photoresist layer is first formed on the stacked wafer after edge trimming and then a solder block is formed in the opening of the photoresist layer.
[0027] Figure 3 It is a schematic flow chart of a method for manufacturing a three-dimensional integrated structure according to an embodiment of the present invention.
[0028] FIG. 4A to FIG. 4EIt is a schematic diagram of a cross-sectional structure formed by multiple steps of a method for manufacturing a three-dimensional integrated structure according to an embodiment of the present invention.
[0029] Description of reference numerals:
[0030] 10, 20 - stacked wafers; 11, 22 - solder blocks; 12, 30 - fixtures; 211 - effective device area; 212 - peripheral area; 212a - beveled surface; 212b - clamping surface; 21 - photoresist layer; 21a - opening; 22 - solder blocks. DETAILED DESCRIPTION
[0031] The three-dimensional integrated structure and the manufacturing method thereof of the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be understood that the drawings in the specification are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0032] It should be noted that the terms "first", "second", etc., hereinafter are used to distinguish between similar elements, and are not necessarily used to describe a specific order or time sequence. It is to be understood that, where appropriate, these terms used in this manner are interchangeable, for example, so that the embodiments of the present invention described herein can be operated in a different order than that described or shown herein. Similarly, if the method described herein includes a series of steps, and the order of these steps presented herein is not necessarily the only order for performing these steps, some of the steps described may be omitted and / or some other steps not described herein may be added to the method.
[0033] See also Figure 3 , an embodiment of the present invention includes a method for manufacturing a three-dimensional integrated structure, the manufacturing method comprising:
[0034] S1: obtaining a stacked wafer, wherein a surface of the stacked wafer includes an effective device area and a peripheral area located outside the effective device area;
[0035] S2: performing a first trimming process corresponding to the peripheral area to form a chamfered surface adjacent to and surrounding the effective device area;
[0036] S3: performing a second trimming process corresponding to the outer edge of the peripheral area to form a clamping surface adjacent to and surrounding the chamfered surface, wherein the thickness of the stacked wafer gradually decreases from the edge of the effective device area to the outside through the chamfered surface and further decreases at the clamping surface;
[0037] S4: coating a photoresist layer on the surface of the stacked wafer, wherein the photoresist layer continuously covers the effective device area and the chamfered surface;
[0038] S5: exposing and developing the photoresist layer to form an opening penetrating the photoresist layer in the effective device region;
[0039] S6: forming a solder bump in the opening.
[0040] The following reference FIG. 4A to FIG. 4E right Figure 3 The production method shown is further explained.
[0041] Figure 4A FIG. 1 is a cross-sectional schematic diagram of a stacked wafer before a first trimming process is performed in one embodiment of the present invention. Figure 4A , the stacked wafer 20 in step S1 includes at least two wafers stacked together, which are, for example, silicon wafers. The stacked wafer 20 may include at least three wafers stacked in the thickness direction, for example, five or six wafers. In one embodiment, the number of wafers in the stacked wafer 20 may be more than ten. The stacked wafer 20 can be obtained by a known process. For example, a semiconductor process may be first performed on the first wafer W1 to form devices and / or circuits thereon according to design requirements, and then the second wafer W2 processed by the semiconductor process is bonded and electrically connected to the first wafer W1, and then, a third wafer W3 processed by the semiconductor process is selectively bonded on the side of the first wafer W1 away from the second wafer W2 or the side of the second wafer W2 away from the first wafer W1, and a fourth wafer W4, a fifth wafer W5, and a sixth wafer W6, etc., may be selectively stacked by a similar method, wherein the circuits of each wafer are connected to each other, and finally a stacked wafer 20 is obtained. During the formation of the stacked wafer 20 , at least a portion of the edges of the wafers may be trimmed as required.
[0042] like Figure 4A As shown, in this embodiment, the stacked wafer 20 includes, for example, six wafers stacked and electrically connected together. Circuit input / output terminals (or pads, not shown) are formed on the upper surface of the stacked wafer 20, and solder blocks for connecting to external circuits can be formed on the surface later. The surface to be trimmed here is, for example, a side surface formed with the circuit input / output terminals.
[0043] Specifically, the surface of the stacked wafer includes an effective device area 211 and a peripheral area 212 ( FIG. 4A to FIG. 4EOnly part of the effective device area 211 and part of the peripheral area 212 located on one side thereof are shown. The effective device area 211 is used to set devices and / or circuits useful for the three-dimensional stacked chip. In order to prevent the devices and / or circuits within the effective device area 211 from being affected by the trimming process, the effective device area 211 is not trimmed. The peripheral area 212 can be trimmed, and the peripheral area 212 surrounds the effective device area 211. The width of the peripheral area 212 is, for example, 6mm to 10mm. It should be understood that Figure 4A Shown are approximate extents and boundaries of the active device region 211 and the peripheral region 212, which are not drawn to scale.
[0044] Figure 4B FIG. 1 is a cross-sectional view of a stacked wafer edge after a chamfer is formed in an embodiment of the present invention. Figure 4B In step S2 , a first trimming process is performed corresponding to the peripheral region 212 to form a chamfered surface 212 a adjacent to and surrounding the effective device region 211 .
[0045] The beveled surface 212a can be obtained by adjusting the settings of the trimming equipment so that it grinds and trims the edge of the stacked wafer 20 at an angle. The beveled surface 212a makes the thickness of the stacked wafer 20 gradually decrease from the edge of the effective device area 211 to the outside, so that when the photoresist layer is subsequently coated, the connection area between the effective device area 211 and the beveled surface 212a is easily covered by the photoresist layer, which helps to avoid the formation of unnecessary structures (such as solder blocks) in the outer area of the effective device area 211 and affect subsequent processes. The beveled surface 212a may include at least one of a bevel and a curved surface. In this embodiment, the beveled surface 212a is, for example, a curved surface. From Figure 4B As shown in the longitudinal section, the arc surface may include one or more than two arcs.
[0046] Figure 4C FIG. 1 is a cross-sectional view of a wafer stack after a clamping surface is formed at the edge of the wafer stack in one embodiment of the present invention. Figure 4C In step S3, a second trimming process is performed corresponding to the outer edge of the peripheral area 212 to form a clamping surface 212b adjacent to and surrounding the chamfered surface 212a, wherein the thickness of the stacked wafer 20 gradually decreases from the effective device area 211 through the chamfered surface 212a and further decreases at the clamping surface 212b in a direction away from the effective device area 211. The clamping surface 212b can be used to clamp the stacked wafer 20. The width of the clamping surface 212b is, for example, 3 mm to 5 mm.
[0047] In this embodiment, the grinding angle of the second trimming process is different from that of the first trimming process. When the outer edge of the peripheral area 212 is trimmed by the second trimming process, for example, the edge portion of the stacked wafer 20 is removed as a whole along the thickness direction of the stacked wafer 20, so that the clamping surface 212b is a relatively flat surface relative to the chamfered surface 212a, which is convenient for clamping by a fixture. When the second trimming process is performed, part of the chamfered surface 212a located at the outer edge of the peripheral area 212 can be ground and converted into the clamping surface 212b. After the second trimming process, a step difference D is formed between the outer boundary of the chamfered surface 212a and the clamping surface 212b.
[0048] Figure 4D FIG. 1 is a cross-sectional schematic diagram of a patterned photoresist layer formed on the surface of a stacked wafer in one embodiment of the present invention. Figure 4D After forming the above-mentioned beveled surface 212a and the clamping surface 212b, this embodiment can also use step S4 to form a photoresist layer 21 on the surface of the stacked wafer 20, and the photoresist layer 21 continuously covers the above-mentioned effective device area 211 and the beveled surface 212a, and the photoresist layer 21 can also be formed on the clamping surface 212b. Thereafter, step S5 can be used to expose and develop the photoresist layer 21 to form an opening 21a penetrating the photoresist layer 21 corresponding to the effective device area 211.
[0049] Specifically, after the photoresist layer 21 is exposed and developed, the opening 21a may be formed corresponding to the position of each input / output terminal on the surface of the stacked wafer 20. In order to avoid the formation of a non-photoresist area at the corner where the chamfered surface 212a and the clamping surface 212b meet when the photoresist layer 21 is applied, which leads to the formation of redundant solder blocks, the step height D between the outer boundary of the chamfered surface 212a and the clamping surface 212b is preferably less than the thickness of the photoresist layer 21, for example, the step height D is greater than 0 and less than or equal to 60 μm, and further, the step height D may be less than 30 μm.
[0050] Figure 4E FIG. 1 is a cross-sectional view of a solder block formed on the surface of a stacked wafer in one embodiment of the present invention. Figure 4E, a solder block 22 is formed in the opening 21a of the photoresist layer 21 by step S6. The solder block 22 may be formed in the opening 21a by an electroplating process. As an example, a seed layer (such as a Ti / Cu layer) may be formed in the opening 21a of the photoresist layer 21, and then a clamp 30 is used to clamp the stacked wafer 20, and the stacked wafer 20 is placed in an electroplating tank for electroplating. The clamp 30 is clamped on the clamping surface 212b (before clamping, at least part of the photoresist on the clamping surface 212b may be removed). The solder block 22 may include at least one of tin, lead-tin alloy, tin-silver alloy, and tin-silver-copper alloy. After the solder block 22 is formed, the photoresist layer 21 may be removed, and a thermal reflow process may be performed to further form a solder ball (bump) on each solder block 22.
[0051] In the method for manufacturing a three-dimensional integrated structure introduced in this embodiment, after the first trimming process is performed corresponding to the peripheral area 212, a beveled surface 212a adjacent to and surrounding the effective device area 211 is formed, wherein from the edge of the effective device area 211 to the outside, the thickness of the stacked wafer 20 gradually decreases through the beveled surface 212a, so that when the photoresist layer 21 is subsequently coated, the connection area between the effective device area 211 and the beveled surface 212a is easily covered by the photoresist layer 21, avoiding the formation of a non-photoresist area, thereby avoiding the formation of unnecessary structures (such as solder blocks) in the outer area of the effective device area 211 to affect the subsequent process. In addition, in order to facilitate the stable clamping of the stacked wafer 20 during subsequent processes and transportation, a second trimming process is performed corresponding to the outer edge of the peripheral area 212 to form a clamping surface 212b adjacent to and surrounding the beveled surface 212a. The clamping surface 212b facilitates the clamp to clamp the stacked wafer 20, and there is no need to clamp the clamp on the top surface of the stacked wafer 20. This can prevent the clamp from damaging the top surface of the stacked wafer 20 and thereby causing adverse effects on the structure within the effective device area 211 and the area of the effective device area 211, which is beneficial to meeting process requirements.
[0052] The embodiment of the present invention also relates to a three-dimensional integrated structure, which can be formed by the manufacturing method described in the above embodiment. The three-dimensional integrated structure includes a stacked wafer 20, and the stacked wafer 20 may include at least three wafers stacked in the thickness direction, for example, five or six wafers. In one embodiment, the number of wafers in the stacked wafer 20 can reach more than ten.
[0053] Reference Figure 4EThe surface of the stacked wafer 20 includes an effective device area 211 and a peripheral area 212 located outside the effective device area 211, and the peripheral area 212 has a beveled surface 212a adjacent to and surrounding the effective device area 211, wherein the thickness of the stacked wafer 20 gradually decreases through the beveled surface 212a from the edge of the effective device area 211 to the outside.
[0054] The peripheral area 212 also has a clamping surface 212b adjacent to and surrounding the chamfered surface 212a, wherein, from the edge of the effective device area 211 outward, the thickness of the stacked wafer 20 gradually decreases through the chamfered surface 212a, and further decreases at the clamping surface 212b. The width of the clamping surface is, for example, 3mm to 5mm. The step height D between the clamping surface 212b and the edge of the chamfered surface 212a is, for example, greater than 0 and less than 60μm, and further can be less than 30μm. In addition, the stacked wafer 20 may include at least one solder block 22 arranged in the effective device area 211.
[0055] By utilizing the three-dimensional integrated structure provided by the present invention, in the process of forming a solder block or other processes that require covering the outer area of the effective device area 211, the connection area between the effective device area 211 and the beveled surface 212a can be easily covered, thereby avoiding the formation of unnecessary structures (such as solder blocks 22) in the outer area of the effective device area 211. In addition, while utilizing the clamping surface to ensure that the stacked wafers can be stably clamped, it can also avoid the clamp from damaging the top surface of the stacked wafer and causing adverse effects on the structure in the effective device area and the area of the effective device area, which is beneficial to improving the quality of the three-dimensional integrated structure.
[0056] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.
[0057] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.
Claims
1. A method for manufacturing a three-dimensional integrated structure, characterized in that: include: Obtaining a stacked wafer, the stacked wafer comprising an effective device region and a peripheral region located outside the effective device region; A trimming process is performed corresponding to the peripheral area to form a beveled surface adjacent to and surrounding the effective device area and a clamping surface located outside the beveled surface and adjacent to the beveled surface, wherein from the edge of the effective device area to the outside, the thickness of the stacked wafer gradually decreases through the beveled surface, and the inclination of the clamping surface is smaller than the inclination of the beveled surface.
2. The method according to claim 1, characterized in that: Forming the chamfered surface and the clamping surface comprises: performing a first trimming process corresponding to the peripheral area to form the chamfered surface; and A second trimming process is performed corresponding to at least a portion of the outer edge of the peripheral area to form a clamping surface, and a step difference is formed between the clamping surface and the chamfered surface on the inner side of the clamping surface.
3. The method according to claim 1 or 2, characterized in that: After forming the chamfered surface and the clamping surface, the method further comprises: Coating a photoresist layer on the surface of the stacked wafer, wherein the photoresist layer continuously covers the effective device area and the chamfered surface; exposing and developing the photoresist layer to form an opening penetrating the photoresist layer in the effective device region; and A solder bump is formed in the opening.
4. The method according to claim 3, characterized in that: A solder bump is formed in the opening by using an electroplating process, and during the electroplating process, a clamp is used to clamp the stacked wafers on the clamping surface.
5. The method according to claim 3, characterized in that: The step height is smaller than the thickness of the photoresist layer.
6. A three-dimensional integrated structure, characterized in that: The invention comprises a stacked wafer, wherein the stacked wafer comprises an effective device area and a peripheral area located outside the effective device area, wherein the peripheral area has a beveled surface adjacent to and surrounding the effective device area, and a clamping surface located outside the beveled surface and adjacent to the beveled surface, wherein, from the edge of the effective device area to the outside, the thickness of the stacked wafer gradually decreases through the beveled surface, and the inclination of the clamping surface is smaller than the inclination of the beveled surface.
7. The three-dimensional integrated structure according to claim 6, characterized in that: The clamping surface surrounds the chamfered surface, or the clamping surface is located at a partial outer edge of the chamfered surface.
8. The three-dimensional integrated structure according to claim 6, characterized in that: There is a step difference between the clamping surface and the chamfered surface on the inner side of the clamping surface.
9. The three-dimensional integrated structure according to claim 6, characterized in that: The stacked wafer includes at least one solder bump disposed in the active device area.
10. The three-dimensional integrated structure according to any one of claims 6 to 9, characterized in that: The width of the clamping surface is 3 mm to 5 mm.