Power semiconductor and packaging interface enhancement process thereof

Abstract

The invention relates to the field of power semiconductors, and discloses a power semiconductor and a packaging interface enhancement technology thereof.The power semiconductor comprises a conductive substrate, a plurality of metal nanowires are distributed on the conductive substrate, the power semiconductor further comprises a plastic package shell connected with the upper portion of the conductive substrate, the metal nanowires are wrapped with the plastic package shell, and the plastic package shell is in contact fit with the outer walls of the metal nanowires; the process method comprises the following steps: cleaning the surface; film covering; performing electrochemical deposition; cleaning the electroplating liquid; removing the covering film; surface cleaning and drying; and performing plastic packaging. The nanowire is directly embedded into the plastic package material after plastic package is completed, and the bonding strength of the plastic package material and the metal surface in the module can be enhanced to a great extent; in addition, metal copper is preferably selected as the nanowire, so that the cost is relatively low.

Description

Technical Field

[0001] The present invention relates to the field of power semiconductors, and in particular to a power semiconductor and a packaging interface enhancement process thereof. Background Art

[0002] With the development of the third-generation power semiconductors, the power density of power semiconductors continues to increase. In order to give full play to the chip performance of the third-generation semiconductors, higher requirements are also placed on the packaging of the module, that is, all packaging materials need to adapt to higher application temperatures and meet higher reliability requirements. The heat resistance and reliability of traditional transparent potting silicone are close to the development limit of new materials. Therefore, in view of the high-temperature characteristics of the third-generation power semiconductors, the industry application tends to use transfer molding epoxy materials, potting epoxy, etc. with better heat resistance. Moreover, after the power semiconductor is molded, the module itself will have a certain shape and mechanical strength, and there is no need to set up an additional protective shell for the module. Under large-scale mass production conditions, there is a packaging cost advantage. However, due to the mismatch between the epoxy material and other material parameters in the module, the module will be welded and installed at the client, in high junction temperature application scenarios, and even in various high-temperature tests or assessments before the module leaves the factory, internal interface stratification will occur.

[0003] At present, there are three main methods to prevent delamination inside epoxy-encapsulated power semiconductors and improve the interface bonding strength between epoxy materials and power semiconductors: 1. Develop epoxy materials with higher interface bonding strength; 2. Add glue locking ports, glue locking holes, glue locking grooves, and anti-slip patterns produced by ultrasonic bonding to the metal inserts inside the module; 3. Perform surface treatment on the inside of the module, such as performing special coating treatment on the internal surface of the module before the transfer molding process, applying high-strength adhesive glue pretreatment, and performing plasma cleaning treatment to increase the internal surface roughness of the module and thus increase the bonding interface area.

[0004] Among them, the cost of developing epoxy materials with higher interface bonding strength is too high and the cycle is too long; adding physical structures such as glue lock holes inside the module is convenient, fast and low-cost, but the coverage is limited; plasma cleaning and roughening the surface has extremely limited effect on improving interface bonding strength; high-strength adhesion glue pretreatment with relatively good enhancement effect is relatively good, but high-strength glue technology is often in the hands of a few companies and the cost is relatively high; and special coating treatment inside the module is relatively complicated, such as a direct selective adhesion enhancer plating disclosed in Patent No. CN111599692B.

[0005] Therefore, the applicant believes that a technical solution and a related process production method can be proposed to improve the interface bonding strength between the epoxy molding material and the metal surface inside the module. Summary of the invention

[0006] The present invention aims at the shortcomings of the prior art and provides a power semiconductor and a packaging interface enhancement process thereof.

[0007] In order to solve the above technical problems, the present invention is solved by the following technical solutions: A power semiconductor includes a conductive substrate on which a plurality of metal nanowires are distributed, and a plastic package shell connected to the upper portion of the conductive substrate, the plastic package shell wraps around the metal nanowires and contacts and cooperates with the outer wall of the metal nanowires.

[0008] A power semiconductor packaging interface enhancement process comprises the following steps: 1) Surface cleaning: Prepare a conductive substrate, clean its surface first, and remove the contamination layer or oxide layer on the surface; 2) Coating: Coating is performed on the surface of a conductive substrate, and the film has a regular micro-through-hole structure for growing metal nanowires; 3) Electrochemical deposition: prepare an electrolyte device and place it on a conductive substrate so that the electrolyte can completely cover the laminating area; grow metal nanowires on the surface of the conductive substrate by electrochemical deposition; 4) Electroplating solution cleaning: cleaning and removing the residual electrolyte solution on the surface of the substrate; 5) Removing the coating: removing the coating material in step 3) by physical means, laser, heating or chemical means, or a combination of these; 6) Surface cleaning and drying: rinse or spray with acetone, ethanol, isopropanol or water, or a mixture of these; 7) Plastic encapsulation: a plastic encapsulation shell is arranged on the treated conductive substrate. The plastic encapsulation shell can be encapsulated by transfer molding or multi-component plastic encapsulation material, so that the metal nanowires are directly embedded in the plastic encapsulation shell to form an interface reinforcement structure.

[0009] Preferably, the conductive substrate in step 1) is a metal copper conductive substrate; the surface of the conductive substrate is treated by plasma cleaning, grinding, or one or more cleaning methods of an acidic solution; the acidic solution includes one or more of hydrochloric acid, formic acid, acetic acid, oxalic acid, and citric acid.

[0010] Preferably, the micro-through holes in step 2) are evenly distributed on the film, with a pore size of 10 nm to 5 μm and a pore density of 30 to 90%; the cross-section of the micro-through holes is circular, elliptical or polygonal.

[0011] Preferably, in step 2), a coating is performed on a selected area on the surface of the conductive substrate; before coating, an electrically insulating material is used to mask the non-selected area.

[0012] Preferably, a polymer tape is used for masking in the non-selected area, or a polymer dry film is used for exposure and development to form an anti-corrosion layer in the non-selected area.

[0013] Preferably, in step 3), the material of the metal nanowires is one of copper, gold, silver, platinum and nickel; and the electrolyte is a metal compound solution corresponding to the material of the metal nanowires.

[0014] Preferably, when the metal nanowires are copper nanowires: the metal compound solution is a mixture of one or more of copper sulfate, cuprous chloride or cupric chloride, one or more of water, sulfuric acid, hydrochloric acid or imidazole derivative sulfonate, a surfactant and a whitening agent.

[0015] Preferably, in step 4), acetone, ethanol, isopropanol or water, or a mixture thereof, is used to remove residual electrolyte on the substrate surface; residual electrolyte on the substrate surface is removed by spraying, immersing or ultrasonic treatment once or multiple times.

[0016] Preferably, the physical method in step 5) includes peeling and grinding; the chemical method in step 5) includes using potassium hydroxide or sodium hydroxide solution.

[0017] The present invention has significant technical effects due to the adoption of the above technical solution: the nanowires in the present application are directly embedded in the plastic packaging material after the plastic packaging is completed, which can greatly enhance the bonding strength between the plastic packaging material and the metal surface inside the module; in addition, the nanowires are preferably made of metallic copper, which has relatively low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a process flow chart of the present invention.

[0019] Figure 2 It is a schematic diagram of the structure of a power semiconductor of the present invention. DETAILED DESCRIPTION

[0020] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0021] Example 1

[0022] A power semiconductor, as shown in the figure, includes a conductive substrate with multiple metal nanowires distributed on the conductive substrate, and also includes a plastic packaging shell connected to the upper part of the conductive substrate, the plastic packaging shell wraps around the metal nanowires and contacts and cooperates with the outer wall of the metal nanowires.

[0023] Example 2

[0024] A power semiconductor packaging interface enhancement process, as shown in the figure, includes the following steps: 1) Surface cleaning: Prepare a conductive substrate, clean its surface first, and remove the contamination layer or oxide layer on the surface; 2) Coating: Coating is performed on the surface of a conductive substrate, and the film has a regular micro-through-hole structure for growing metal nanowires; 3) Electrochemical deposition: prepare an electrolyte device and place it on a conductive substrate so that the electrolyte can completely cover the laminating area; grow metal nanowires on the surface of the conductive substrate by electrochemical deposition; 4) Electroplating solution cleaning: cleaning and removing the residual electrolyte solution on the surface of the substrate; 5) Removing the coating: removing the coating material in step 3) by physical means, laser, heating or chemical means, or a combination of these; 6) Surface cleaning and drying: rinse or spray with acetone, ethanol, isopropanol or water, or a mixture of these; 7) Plastic encapsulation: a plastic encapsulation shell is arranged on the treated conductive substrate. The plastic encapsulation shell can be encapsulated by transfer molding or multi-component plastic encapsulation material, so that the metal nanowires are directly embedded in the plastic encapsulation shell to form an interface reinforcement structure.

[0025] Example 3

[0026] The same as Example 2, except that the conductive substrate in step 1) is a metal copper conductive substrate; the surface of the conductive substrate is treated by plasma cleaning, grinding, or one or more cleaning methods of an acidic solution; the acidic solution includes one or more of hydrochloric acid, formic acid, acetic acid, oxalic acid, and citric acid.

[0027] Example 4

[0028] The same as Example 2, except that the micro-through holes in step 2) are evenly distributed on the film, with a pore diameter of 3000 nm and a pore density of 60%; the cross-section of the micro-through holes is circular, elliptical or polygonal.

[0029] Example 5

[0030] The same as Example 2, except that in step 2), only the selected area on the surface of the conductive substrate is coated; before coating, the non-selected area is masked with an electrical insulating material. A polymer tape is used to mask the non-selected area; or a polymer dry film is used to form an anti-corrosion layer in the non-selected area through exposure and development.

[0031] In step 5), the coating material in step 3) is removed by physical means, laser, heating or chemical means, or a combination of these means. Physical means include peeling and grinding; chemical means include using potassium hydroxide or sodium hydroxide solution.

[0032] Example 6

[0033] The same as Example 2, except that in step 3), the material of the metal nanowire is one of copper, gold, silver, platinum and nickel; and the electrolyte is a metal compound solution corresponding to the material of the metal nanowire.

[0034] When the metal nanowires are copper nanowires: the metal compound solution is a mixture of one or more of copper sulfate, cuprous chloride or cupric chloride, one or more of water, sulfuric acid, hydrochloric acid or imidazole derivative sulfonate, a surfactant and a whitening agent.

[0035] Example 7

[0036] The same as Example 2, except that in step 4), acetone, ethanol, isopropanol or a mixture of one or more of them in water are used to remove the residual electrolyte on the surface of the substrate; the residual electrolyte on the surface of the substrate is removed by one or more treatments such as spraying, immersion or ultrasound.

[0037] Example 8

[0038] The same as Example 2, except that the physical method in step 5) includes peeling and grinding; the chemical method in step 5) includes using potassium hydroxide or sodium hydroxide solution.

[0039] In conclusion, the above is only a preferred embodiment of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the patent of the present invention.

Claims

1. A power semiconductor, characterized in that: It includes a conductive substrate, on which a plurality of metal nanowires are distributed, and a plastic package shell connected to the upper part of the conductive substrate, the plastic package shell wraps around the metal nanowires and contacts and cooperates with the outer wall of the metal nanowires.

2. A power semiconductor packaging interface enhancement process, characterized in that: The following steps are involved: 1) Surface cleaning: Prepare a conductive substrate, clean its surface first, and remove the contamination layer or oxide layer on the surface; 2) Coating: Coating is performed on the surface of a conductive substrate, and the film has a regular micro-through-hole structure for growing metal nanowires; 3) Electrochemical deposition: prepare an electrolyte device and place it on a conductive substrate so that the electrolyte can completely cover the laminating area; grow metal nanowires on the surface of the conductive substrate by electrochemical deposition; 4) Electroplating solution cleaning: cleaning and removing the residual electrolyte solution on the surface of the substrate; 5) Removing the coating: removing the coating material in step 3) by physical means, laser, heating or chemical means, or a combination of these; 6) Surface cleaning and drying: rinse or spray with acetone, ethanol, isopropanol or water, or a mixture of these; 7) Plastic encapsulation: a plastic encapsulation shell is arranged on the treated conductive substrate. The plastic encapsulation shell can be encapsulated by transfer molding or multi-component plastic encapsulation material, so that the metal nanowires are directly embedded in the plastic encapsulation shell to form an interface reinforcement structure.

3. A power semiconductor package interface enhancement process according to claim 2, characterized in that: The conductive substrate in step 1) is a metal copper conductive substrate; the surface of the conductive substrate is treated by plasma cleaning, grinding, or one or more cleaning methods of an acidic solution; the acidic solution includes one or more of hydrochloric acid, formic acid, acetic acid, oxalic acid, and citric acid.

4. The power semiconductor package interface enhancement process according to claim 2, characterized in that: The micro-through holes in step 2) are evenly distributed on the film, with a pore size of 10 nm to 5 μm and a pore density of 30 to 90%; the cross-section of the micro-through holes is circular, elliptical or polygonal.

5. The power semiconductor package interface enhancement process according to claim 2, characterized in that: In step 2), a coating is performed on a selected area on the surface of the conductive substrate; before coating, an electrically insulating material is used to mask the non-selected area.

6. A power semiconductor package interface enhancement process according to claim 5, characterized in that: Use polymer tape to mask in non-selected areas; or use polymer dry film to form an anti-corrosion layer in non-selected areas through exposure and development.

7. A power semiconductor package interface enhancement process according to claim 2, characterized in that: In step 3), the material of the metal nanowire is one of copper, gold, silver, platinum and nickel; and the electrolyte is a metal compound solution corresponding to the material of the metal nanowire.

8. A power semiconductor package interface enhancement process according to claim 7, characterized in that: When the metal nanowires are copper nanowires: the metal compound solution is a mixture of one or more of copper sulfate, cuprous chloride or cupric chloride, one or more of water, sulfuric acid, hydrochloric acid or imidazole derivative sulfonate, a surfactant and a whitening agent.

9. A power semiconductor package interface enhancement process according to claim 2, characterized in that: In step 4), use acetone, ethanol, isopropanol or water, or a mixture of the two or more to remove the residual electrolyte on the substrate surface; remove the residual electrolyte on the substrate surface by spraying, immersing or ultrasonic treatment once or multiple times.

10. The power semiconductor package interface enhancement process according to claim 2, characterized in that: The physical method in step 5) includes peeling and grinding; the chemical method in step 5) includes using potassium hydroxide or sodium hydroxide solution.

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