Micro-channel packaging structure based on cooling liquid cooling and packaging method thereof

Abstract

The invention belongs to the technical field of integrated circuit packaging, and particularly relates to a micro-channel packaging structure based on cooling liquid cooling and a packaging method thereof. Comprising a packaging body, a plurality of grooves are symmetrically formed in the upper surface and the lower surface of the packaging body, functional chips are mounted in the grooves, and active bonding pads of the functional chips face the outer side; the metal wiring layers are respectively arranged on the surfaces of the functional chips on the upper side and the lower side; the silicon through holes are vertically formed in the left side and the right side of the packaging body respectively, copper layers are filled in the silicon through holes to form a silicon through hole structure, and the metal wiring layers on the upper side and the lower side are conducted through the silicon through hole structure; the micro-channel groove is formed between the functional chips on the upper side and the lower side in the left-right direction, and the two ends of the micro-channel groove extend in the vertical direction and are exposed to the outside. Liquid helium is introduced to improve the heat dissipation effect of the double-sided chip, double-sided interconnection is realized by using the silicon through hole structure, and the heat dissipation problem of the high-performance chip can be effectively solved while the integration degree is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit packaging, and in particular relates to a microchannel packaging structure based on coolant cooling and a packaging method thereof. Background Art

[0002] With the rapid development of modern electronic devices, miniaturization has become the mainstream trend of the development of modern electronic devices, and the characteristic size of electronic devices has been continuously reduced. As the core component, the chip has been continuously reduced in size and its performance has been continuously improved, and the heat dissipation problem has become increasingly prominent. Efficient heat dissipation technology has become one of the key factors to ensure the stable operation of the chip and extend its service life. The commonly used heat dissipation solution at present is microfluidics. This heat dissipation structure is to prepare microfluidics on the back of the packaging structure to achieve chip heat dissipation by increasing the heat dissipation area. Under the current high-density integration conditions, conventional microfluidic heat dissipation is no longer suitable for chips with high heat flux density. Summary of the invention

[0003] The purpose of the present invention is to provide a microfluidic packaging structure based on coolant cooling and a packaging method thereof, wherein a closed microfluidic channel is formed by wafer bonding, liquid helium is introduced to increase the heat dissipation effect of double-sided chips, and a through silicon via structure is used to achieve double-sided interconnection, thereby effectively solving the heat dissipation problem of high-performance chips while improving the integration.

[0004] In order to solve the above technical problems, the present invention provides a microfluidic packaging structure based on coolant cooling, comprising: A package body, wherein a plurality of grooves are symmetrically formed on the upper and lower surfaces of the package body, and a functional chip is mounted in the groove with the active pad of the functional chip facing outward; Metal wiring layers are respectively arranged on the surfaces of the functional chips at the upper and lower sides; Through silicon vias are vertically opened on the left and right sides of the package body, and the through silicon vias are filled with a copper layer to form a through silicon via structure, through which the metal wiring layers on the upper and lower sides are connected; A microfluidic channel groove is opened between the functional chips on the upper and lower sides along the left-right direction, and both ends of the microfluidic channel groove extend in the vertical direction and are exposed to the outside to form a liquid inlet and a liquid outlet for the circulation of liquid helium coolant; The vertical spacing between the microchannel groove and the functional chips on the upper and lower sides is 10 μm to 50 μm; the opening width and opening spacing of the microchannel groove are 10 μm to 500 μm.

[0005] Preferably, the groove is a straight groove or an oblique groove structure, the cross section of the groove is a rectangle or a trapezoid; and the depth of the groove is adapted to the size of the packaged chip.

[0006] Preferably, it further comprises an insulating layer, which is deposited on the inner wall surface of the groove, the upper and lower surfaces of the package body, and the inner wall surface of the through silicon via respectively.

[0007] Preferably, it also includes an adhesive layer, through which the functional chip is bonded and mounted in the groove.

[0008] Preferably, it also includes a filling layer, which fills the gap between the groove and the functional chip, and covers the insulating layer at the upper and lower surfaces of the package body; wherein the filling layer is a polyamide, or polyimide and resin polymer.

[0009] Preferably, the functional chip is a high-density I / O interface chip, and the metal wiring layer is a multi-layer wiring structure. The cross-sectional shape of the microfluidic groove is rectangular, triangular, trapezoidal, semicircular, teardrop-shaped or needle-shaped, and the groove wall of the microfluidic groove also includes spoiler protrusions evenly arranged along the S-shaped path.

[0010] Preferably, it further comprises metal layer pads and bumps, wherein the metal layer pads and the bumps are respectively arranged on the metal wiring layer at the upper and lower sides, and the metal layer pads and the bumps are arranged one by one in the vertical direction.

[0011] Preferably, it further comprises a solder resist layer, wherein the solder resist layer covers the upper and lower surfaces of the package body, and the solder resist layer has a plurality of openings so that the metal layer pads and the bumps are exposed at the openings.

[0012] Preferably, the package body is assembled by a wafer-level bonding process using two silicon substrates 1 and 2 arranged one above the other.

[0013] The present invention also provides a packaging method for a microfluidic packaging structure based on coolant cooling, and preparing a microfluidic packaging structure based on coolant cooling as described above comprises the following steps: Step S1: etching a groove on a surface of a silicon substrate, and depositing an insulating layer on the inner wall of the groove; Step S2: etching a through silicon via on a surface of the silicon substrate, and depositing an insulating layer on the inner wall of the through silicon via; Step S3: mounting the functional chip in the groove through the adhesive layer, with the active pad of the functional chip facing outwards; Step S4: filling the groove with a filling layer, and opening the positions of the active pad and the through silicon via by a photolithography process; Step S5: After the through silicon via is filled with copper, metal wiring is performed to form a metal wiring layer; Step S6: temporarily bonding the metal wiring layer to the carrier by using a temporary bonding adhesive; Step S7: exposing the back side through silicon vias through back side thinning, etching and chemical mechanical polishing processes; Step S8: etching a microchannel groove on the surface away from the metal wiring layer by dry etching; Step S9: debonding, removing the carrier, cleaning the temporary bonding glue, and making bumps on the metal wiring layer; Step S10: repeating the above steps S1 to S7 to complete the exposure of the back side through silicon via of another silicon substrate 2; Step S11: dry-etching the microchannel grooves on the second silicon substrate to correspond to the positions of the microchannel grooves on the first silicon substrate; Step S12: Debonding, removing the carrier, cleaning the temporary bonding glue, and making metal layer pads corresponding to the bumps on the metal wiring layer; Step S13: Assemble the silicon substrate 1 and the silicon substrate 2 through a wafer-level bonding process to finally complete the packaging structure.

[0014] Compared with the prior art, the present invention has the following beneficial effects: 1. The present invention further increases the heat dissipation effect by circulating liquid helium coolant in a microchannel structure that increases the specific surface area to achieve heat dissipation. In addition, the present invention shortens the path of heat conduction from the inside of the chip to the cooling fluid by setting the spacing between the microchannel groove and the upper and lower functional chips in the vertical direction to 10μm~50μm. This creative value range improves the heat conduction efficiency and reduces the temperature gradient, which is beneficial to the heat dissipation of the chip and avoids local overheating. At the same time, the opening width and opening spacing of the microchannel groove are 10μm~500μm, which can optimize the flow state of the fluid in the groove, reduce the fluid resistance, and increase the fluid flow rate, thereby enhancing the heat dissipation effect, thereby achieving the effect of ensuring sufficient heat dissipation area and avoiding excessive fluid resistance. The cross-sectional shape of the microchannel groove is rectangular, triangular, trapezoidal, semicircular, teardrop-shaped or needle-shaped, and the groove wall of the microchannel groove also includes spoiler protrusions evenly arranged along the S-shaped path. In the microchannel groove, the fluid temperature gradually increases along the length direction of the channel to form a thermal boundary layer. By controlling the size and shape of the grooves, the fluid boundary layer can be broken and the turbulence of the fluid flow can be enhanced to enhance the convective heat transfer effect.

[0015] 2. The present invention connects double-sided chips through a through silicon via structure to achieve double-sided wiring, thereby improving device integration and reliability and reducing package size.

[0016] 3. The microchannel structure of the present invention is located on the back of the double-sided active chip, has high heat dissipation efficiency and does not require an additional heat dissipation structure, reduces the packaging volume, increases chip integration, and reduces production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of etching a groove on a surface of a silicon substrate according to the present invention.

[0018] Figure 2 The figure is a schematic diagram of etching a through silicon via on a surface of a silicon substrate according to the present invention.

[0019] Figure 3 It is a schematic diagram of mounting a chip in a groove according to the present invention.

[0020] Figure 4 It is a schematic diagram of filling a filling layer in a groove according to the present invention.

[0021] Figure 5 Schematic diagram of copper filling of through silicon vias of the present invention.

[0022] Figure 6 This is a schematic diagram of temporarily bonding the metal wiring layer to the carrier according to the present invention.

[0023] Figure 7 It is a schematic diagram of thinning the back surface until the through silicon via is exposed according to the present invention.

[0024] Figure 8 It is a schematic diagram of etching microfluidic channel grooves according to the present invention.

[0025] Fig. 9 This is a schematic diagram of the present invention for removing bonds and making bumps on the metal wiring layer.

[0026] Fig.10 This is a schematic diagram of the invention completing the exposure of the through silicon via on the second back side of the silicon substrate.

[0027] Fig.11 The present invention is a schematic diagram of etching microchannel grooves on a silicon substrate by dry etching.

[0028] Fig.12 A schematic diagram of manufacturing a metal layer pad according to the present invention.

[0029] Fig.13 It is a schematic diagram of the packaging structure completed by wafer bonding assembly of the present invention.

[0030] In the figure: 1-package, 101-silicon substrate 1, 102-silicon substrate 2, 2-groove, 3-functional chip, 31-active pad, 4-metal wiring layer, 5-through silicon via, 6-microchannel groove, 61-liquid inlet, 62-liquid outlet, 7-insulating layer, 8-adhesive layer, 9-filling layer, 10-metal layer pad, 11-bump, 12-solder mask, 13-carrier, 14-temporary bonding glue. DETAILED DESCRIPTION

[0031] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. Embodiment 1

[0032] like Fig.13 As shown, an embodiment of the present invention provides a microfluidic packaging structure based on coolant cooling, including: A package body 1, wherein a plurality of grooves 2 are symmetrically provided on the upper and lower surfaces of the package body 1, and a functional chip 3 is mounted in the groove 2, with the active pad 31 of the functional chip 3 facing outward; Metal wiring layers 4 are arranged on the surfaces of the upper and lower functional chips 3 respectively; Through silicon vias 5 are vertically opened on the left and right sides of the package body 1, and the through silicon vias 5 are filled with a copper layer to form a through silicon via structure, through which the metal wiring layers 4 on the upper and lower sides are connected; The microfluidic groove 6 is opened between the upper and lower functional chips 3 along the left-right direction, and both ends of the microfluidic groove 6 extend vertically and are exposed to the outside to form a liquid inlet 61 and a liquid outlet 62 for the circulation of liquid helium coolant.

[0033] Since the narrower the width of the microchannel groove 6, the faster the coolant flows, the better the heat dissipation effect, but at the same time it will increase the flow resistance, resulting in an increase in pump work. Too wide grooves will also affect the temperature distribution. Similarly, the groove spacing also affects the flow characteristics and heat transfer performance of the coolant. The smaller the groove spacing, the higher the flowability and heat transfer performance of the coolant. Therefore, the opening width and spacing of the microchannel groove 6 are 10μm~500μm. The smaller the spacing between the microchannel groove 6 and the functional chip 3, the higher the heat conduction efficiency and the smaller the temperature gradient, which is beneficial to the heat dissipation of the chip and avoidance of local overheating. However, reducing the spacing will increase the difficulty and cost of the manufacturing process. It is necessary to weigh the relationship between heat dissipation performance and manufacturing cost and select the optimal spacing value. Therefore, the spacing between the microchannel groove 6 and the upper and lower functional chips 3 in the vertical direction is 10μm~50μm.

[0034] The groove 2 is a straight groove or an oblique groove structure, and the cross section of the groove 2 is a rectangle or a trapezoid; and the depth of the groove 2 is adapted to the size of the packaged chip and is within a range of 10 μm.

[0035] The package body 1 further comprises an insulating layer 7 , which is deposited on the inner wall surface of the groove 2 , the upper and lower surfaces of the package body 1 , and the inner wall surface of the through silicon via 5 .

[0036] It also includes an adhesive layer 8 , through which the functional chip 3 is bonded and mounted in the groove 2 .

[0037] It also includes a filling layer 9, which fills the gap between the groove 2 and the functional chip 3, and covers the insulating layer 7 on the upper and lower surfaces of the package body 1; wherein the filling layer 9 is a polyamide, or polyimide and resin polymer.

[0038] The functional chip 3 is a high-density I / O interface chip, and the metal wiring layer 4 is a multi-layer wiring structure. For high-density I / O interface chips, multi-layer wiring can be used, that is, adding another layer of passivation and then redistributing a second layer of metal redistribution layer on it for packaging, which can effectively reduce the package size.

[0039] The cross-sectional shape of the microchannel groove 6 is rectangular, triangular, trapezoidal, semicircular, teardrop-shaped or needle-like. Different shapes have different effects on the heat dissipation effect and fluid pressure drop, which need to be considered comprehensively. The groove wall of the microchannel groove 6 also includes flow-disturbing protrusions evenly arranged along the S-shaped path. In the microchannel groove, the fluid temperature will gradually increase along the length of the channel to form a thermal boundary layer. By controlling the size and shape of the groove, the fluid boundary layer can be broken and the turbulence of the fluid flow can be enhanced to enhance the convective heat transfer effect.

[0040] It also includes metal layer pads 10 and bumps 11, which are arranged on the metal wiring layer 4 at the upper and lower sides respectively, and the metal layer pads 10 and the bumps 11 are arranged one by one in the vertical direction.

[0041] The package body 1 further includes a solder resist layer 12 , which covers the upper and lower surfaces of the package body 1 , and has a plurality of openings, so that the metal layer pads 10 and the bumps 11 are exposed at the openings.

[0042] The package body 1 is assembled by a wafer-level bonding process using two silicon substrates 101 and 102 arranged one above the other. Embodiment 2

[0043] like Figures 1 to 13 As shown, the present invention also provides a packaging method for a microfluidic packaging structure based on coolant cooling, and preparing a microfluidic packaging structure based on coolant cooling as described above includes the following steps: Step S1: etching a groove 2 on the surface of the silicon substrate 101, and depositing an insulating layer 7 on the inner wall of the groove 2; Step S2: etching a through silicon via 5 on the surface of the silicon substrate 101, and depositing an insulating layer 7 on the inner wall of the through silicon via 5; Step S3: mounting the functional chip 3 in the groove 2 through the adhesive layer 8, with the active pad 31 of the functional chip 3 facing outwards; Step S4: filling the groove 2 with a filling layer 9, and opening the positions of the active pad 31 and the through silicon via 5 by a photolithography process; Step S5: After the through silicon via 5 is filled with copper, metal wiring is performed to form a metal wiring layer 4; Step S6: temporarily bonding the end surface of the metal wiring layer 4 to the carrier 13 by means of a temporary bonding adhesive 14; the carrier 13 may be made of silicon or glass, and may have a wafer-level or board-level size; Step S7: exposing the back-side through silicon via 5 by back-side thinning, etching and chemical mechanical polishing processes; Step S8: then depositing an insulating layer 7 on the surface thereof, and etching a microchannel groove 6 on the surface away from the metal wiring layer 4 by dry etching; Step S9: Debonding, removing the carrier 13, cleaning the temporary bonding glue 14, and making bumps 11 on the metal wiring layer 4; Step S10: repeat the above steps S1 to S7 to complete the exposure of the back side through silicon via 5 of another silicon substrate 102; Step S11: dry-etching the microchannel groove 6 of the second silicon substrate 102 so that the position of the microchannel groove 6 corresponds to that of the first silicon substrate 101; Step S12: dismantle the bonding, remove the carrier 13, clean the temporary bonding glue 14, and make metal layer pads 10 corresponding to the bumps 11 on the metal wiring layer 4; used to connect electrical components such as capacitors and resistors; Step S13: Assemble the silicon substrate 1 101 and the silicon substrate 2 102 through a wafer-level bonding process, connect the through-silicon via structure and the double-sided microchannel groove 6 through wafer bonding, realize the transmission of electrical signals and the inlet, outlet and circulation of the cooling liquid, and finally complete the packaging structure.

[0044] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A microfluidic packaging structure based on coolant cooling, characterized in that: include: A package body, wherein a plurality of grooves are symmetrically formed on the upper and lower surfaces of the package body, and a functional chip is mounted in the groove with the active pad of the functional chip facing outward; Metal wiring layers are respectively arranged on the surfaces of the functional chips at the upper and lower sides; Through silicon vias are vertically opened on the left and right sides of the package body, and the through silicon vias are filled with a copper layer to form a through silicon via structure, through which the metal wiring layers on the upper and lower sides are connected; The microfluidic groove is opened between the functional chips on the upper and lower sides in an S-shaped path along the left-right direction, and the two ends of the microfluidic groove extend in the vertical direction and are exposed to the outside to form a liquid inlet and a liquid outlet for the circulation of liquid helium coolant; The vertical spacing between the microchannel groove and the functional chips on the upper and lower sides is 10 μm to 50 μm; the opening width and opening spacing of the microchannel groove are 10 μm to 500 μm.

2. A microfluidic packaging structure based on coolant cooling as claimed in claim 1, characterized in that: The groove is a straight groove or an oblique groove structure, and the cross-sectional shape of the groove is a rectangle or a trapezoid; and the depth of the groove is adapted to the size of the packaged chip.

3. A microfluidic packaging structure based on coolant cooling as claimed in claim 1, characterized in that: The invention also comprises an insulating layer, which is respectively deposited on the inner wall surface of the groove, the upper and lower surfaces of the package body, and the inner wall surface of the through silicon via.

4. A microfluidic packaging structure based on coolant cooling as claimed in claim 1, characterized in that: It also includes an adhesive layer, through which the functional chip is bonded and mounted in the groove.

5. The microfluidic packaging structure based on coolant cooling according to claim 3, characterized in that: It also includes a filling layer, which fills the gap between the groove and the functional chip, and covers the insulating layer at the upper and lower surfaces of the package body; wherein the filling layer is a polyamide, or polyimide and resin polymer.

6. The microfluidic packaging structure based on coolant cooling according to claim 1, characterized in that: The functional chip is a high-density I / O interface chip, and the metal wiring layer is a multi-layer wiring structure. The cross-sectional shape of the microfluidic groove is rectangular, triangular, trapezoidal, semicircular, teardrop-shaped or needle-shaped, and the groove wall of the microfluidic groove also includes spoiler protrusions evenly arranged along an S-shaped path.

7. The microfluidic packaging structure based on coolant cooling according to claim 1, characterized in that: It also includes metal layer pads and bumps, which are arranged on the metal wiring layer at the upper and lower sides respectively, and the metal layer pads and the bumps are arranged one by one in the vertical direction.

8. A microfluidic packaging structure based on coolant cooling as claimed in claim 7, characterized in that: It also includes a solder resist layer, which covers the upper and lower surfaces of the package body, and has a plurality of openings so that the metal layer pads and the bumps are exposed at the openings.

9. The microfluidic packaging structure based on coolant cooling according to claim 1, characterized in that: The package body is assembled by a wafer-level bonding process using two silicon substrates, a first silicon substrate and a second silicon substrate, which are arranged one above the other.

10. A packaging method for a microfluidic packaging structure based on coolant cooling, characterized in that: The preparation of a microfluidic packaging structure based on coolant cooling as described in any one of claims 1 to 9 comprises the following steps: Step S1: etching a groove on a surface of a silicon substrate, and depositing an insulating layer on the inner wall of the groove; Step S2: etching a through silicon via on a surface of the silicon substrate, and depositing an insulating layer on the inner wall of the through silicon via; Step S3: mounting the functional chip in the groove through the adhesive layer, with the active pad of the functional chip facing outwards; Step S4: filling the groove with a filling layer, and opening the positions of the active pad and the through silicon via by a photolithography process; Step S5: After the through silicon via is filled with copper, metal wiring is performed to form a metal wiring layer; Step S6: temporarily bonding the metal wiring layer to the carrier by using a temporary bonding adhesive; Step S7: exposing the back side through silicon vias through back side thinning, etching and chemical mechanical polishing processes; Step S8: etching a microchannel groove on the surface away from the metal wiring layer by dry etching; Step S9: debonding, removing the carrier, cleaning the temporary bonding glue, and making bumps on the metal wiring layer; Step S10: repeating the above steps S1 to S7 to complete the exposure of the back side through silicon via of another silicon substrate 2; Step S11: dry-etching the microchannel grooves on the second silicon substrate to correspond to the positions of the microchannel grooves on the first silicon substrate; Step S12: Debonding, removing the carrier, cleaning the temporary bonding glue, and making metal layer pads corresponding to the bumps on the metal wiring layer; Step S13: Assemble the silicon substrate 1 and the silicon substrate 2 through a wafer-level bonding process to finally complete the packaging structure.

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