Impedance matching circuit and method for single-branch RRAM resistor network

Abstract

The present invention relates to the technical field of integrated circuits, and provides an impedance matching circuit and method for a single-branch RRAM resistor network, wherein the impedance matching circuit of the single-branch RRAM resistor network includes a positive impedance calibration module, a negative impedance calibration module, a user impedance calibration module and a DCI adjustment module, characterized in that the positive impedance calibration module, the negative impedance calibration module and the user impedance calibration module all include an RRAM resistor network structure; the positive impedance calibration module includes a precise matching resistor, a switch tube, a post-stage comparator and the RRAM resistor network structure; the negative impedance calibration module includes a precise matching resistor, a switch tube, a post-stage comparator and the RRAM resistor network structure; the user impedance calibration module includes a switch tube and an RRAM resistor network structure. The present invention simplifies the circuit of the impedance matching resistor network, saves chip area occupancy, and saves circuit power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an impedance matching circuit and method for a single-branch RRAM resistor network. Background Art

[0002] Field-Programmable Gate Array (FPGA) is a programmable integrated circuit that can configure its internal logic structure and connection relationships through programming according to user needs to realize various digital functions.

[0003] Nowadays, the output transmission rate of FPGA is getting higher and higher, and the data throughput is getting larger and larger. The IO interface circuit is the bridge for data interaction between FPGA chip and peripheral circuit. Its circuit performance and the quality of transmission signal are one of the important indicators of the chip. In the process of high-speed signal transmission, in order to reduce signal reflection in different transmission media, impedance matching technology is performed at the signal output end or receiving end to ensure that the signal can be transmitted to the load without distortion.

[0004] Nowadays, most of the related technical fields use digitally controlled impedance (DCI) technology to adjust the IO impedance by selectively turning on or off the transistors in the IO to adjust the impedance to match the external reference resistor. The general implementation method of the resistor network in DCI is to distribute the resistor width-to-length ratio or the number of resistors in parallel as 1, 2, 4, ..., 2n-1, 2n. This resistor network not only occupies a large area in the integrated circuit, but also has a large number of uses and inaccurate resistance values. Summary of the invention

[0005] The present invention provides an impedance matching circuit for a single-branch RRAM resistor network, the main purpose of which is to simplify the circuit of the impedance matching resistor network, save chip area, and save circuit power consumption.

[0006] To achieve the above object, the impedance matching circuit of a single-branch RRAM resistor network provided by the present invention includes a positive impedance calibration module, a negative impedance calibration module, a user impedance calibration module and a DCI adjustment module, wherein the positive impedance calibration module, the negative impedance calibration module and the user impedance calibration module all include an RRAM resistor network structure;

[0007] The positive electrode impedance calibration module includes a precise matching resistor, a switch tube, a post-stage comparator and the RRAM resistor network structure, and is used to adjust the resistor connection state in the RRAM resistor network structure in the positive electrode impedance calibration module according to the adjustment information of the DCI adjustment module, and record the positive electrode impedance adjustment signal during the adjustment process;

[0008] The negative electrode impedance calibration module includes a precise matching resistor, a switch tube, a post-stage comparator and the RRAM resistor network structure, and is used to adjust the resistor connection state in the RRAM resistor network structure in the negative electrode impedance calibration module according to the adjustment information of the DCI adjustment module, and record the negative electrode impedance adjustment signal during the adjustment process;

[0009] The user impedance calibration module includes a switch tube and an RRAM resistor network structure, which is used to adjust the resistance of the RRAM resistor network structure in the user impedance calibration module according to the positive impedance adjustment signal and the negative impedance adjustment signal to achieve impedance matching between the pre-built FPGA and the external circuit.

[0010] In addition, the circuit comprises:

[0011] The DCI adjustment module is used to determine whether the impedance of the positive impedance calibration module and the negative impedance calibration module needs to be adjusted according to the feedback information, and obtain adjustment information;

[0012] The RRAM resistor network structure is used to initialize the number of resistors and is also used to adjust the connection state of the resistors of the RRAM in the RRAM resistor network structure according to the adjustment information;

[0013] The positive impedance calibration module is used to compare the PAD voltage generated by the RRAM resistor network structure according to the resistor connection state with a pre-built reference voltage using the post-stage comparator to obtain a comparison result, and send the comparison result as feedback information to the DCI adjustment module;

[0014] The negative electrode impedance calibration module is used to compare the PAD voltage generated by the RRAM resistor network structure according to the resistor connection state with the reference voltage using the post-stage comparator to obtain a comparison result, and send the comparison result as feedback information to the DCI adjustment module;

[0015] The user impedance calibration module is used to obtain the adjustment information recorded in the positive impedance calibration module to obtain a positive impedance adjustment signal when the adjustment information indicates that no adjustment is required, and to obtain the adjustment information recorded in the negative impedance calibration module to obtain a negative impedance adjustment signal, and to configure the positive impedance adjustment signal on the positive RRAM resistor network structure in the user impedance calibration module, and to configure the negative impedance adjustment signal on the negative RRAM resistor network structure in the user impedance calibration module, wherein, in the user impedance calibration module, the negative RRAM resistor network structure and the positive RRAM resistor network structure intersect on a pre-constructed PAD line, wherein the PAD line has a PAD output line impedance, and the PAD output line impedance is used to achieve impedance matching between the FPGA and an external circuit.

[0016] In addition, the positive impedance calibration module includes a positive adjustment structure, a precision matching resistor and a post-stage comparator;

[0017] The positive regulation structure includes two switch tubes and an RRAM resistor network structure, wherein two ends of the RRAM resistor network structure are each connected to a switch tube;

[0018] The positive regulation structure pulls up a default voltage source, and the other end of the positive regulation structure is connected to the PAD line;

[0019] The precise matching resistor pulls down a ground line, and the other end of the precise matching resistor is connected to the PAD line;

[0020] The first access terminal of the post-stage comparator is connected to the PAD line, the second access terminal of the post-stage comparator is connected to a reference voltage, and the output terminal of the post-stage comparator is connected to the DCI adjustment module.

[0021] In addition, the negative electrode impedance calibration module includes a negative adjustment structure, a precision matching resistor and a post-stage comparator;

[0022] The negative regulation structure includes two switch tubes and an RRAM resistor network structure, wherein two ends of the RRAM resistor network structure are each connected to a switch tube;

[0023] In the negative electrode impedance calibration module, the negative adjustment structure pulls down a ground line, and the other end of the negative adjustment structure is connected to the PAD line;

[0024] The precise matching resistor pulls up a default voltage source, and the other end of the precise matching resistor is connected to the PAD line;

[0025] The first access terminal of the post-stage comparator is connected to the PAD line, the second access terminal of the post-stage comparator is connected to a reference voltage, and the output terminal of the post-stage comparator is connected to the DCI adjustment module.

[0026] In addition, the user impedance calibration module includes a positive adjustment structure and a negative adjustment structure;

[0027] The positive regulation structure pulls up a default voltage source, and the negative regulation structure pulls down a ground line;

[0028] The positive regulatory structure is connected to the negative regulatory structure.

[0029] In addition, the RRAM resistor network structure includes:

[0030] When the RRAM in the RRAM resistor network structure is adjusted, the switch tubes at both ends of the RRAM resistor network structure are turned off;

[0031] When the RRAM in the RRAM resistor network structure is adjusted, the switch tubes at both ends of the RRAM resistor network structure are turned on.

[0032] In addition, the positive electrode impedance calibration module includes:

[0033] Calculate the positive voltage division value of the positive impedance calibration module on the PAD line according to the resistance value in the positive impedance calibration module;

[0034] Determining whether the positive divided voltage value is less than the reference voltage;

[0035] When the positive voltage division value is less than the reference voltage, the output result of the post-stage comparator in the positive impedance calibration module is that adjustment is required;

[0036] When the positive voltage division value is greater than or equal to the reference voltage, the output result of the post-stage comparator in the positive electrode impedance calibration module is that no adjustment is required.

[0037] In addition, the negative electrode impedance calibration module includes:

[0038] Calculate the negative voltage division value of the negative electrode impedance calibration module on the PAD line according to the resistance value in the negative electrode impedance calibration module;

[0039] Determining whether the negative divided voltage value is less than the reference voltage;

[0040] When the negative voltage division value is greater than or equal to the reference voltage, the output result of the post-stage comparator in the negative electrode impedance calibration module is that adjustment is required;

[0041] When the negative voltage division value is less than the reference voltage, the output result of the post-stage comparator in the negative electrode impedance calibration module is that no adjustment is required.

[0042] To achieve the above object, the present invention further provides an impedance matching circuit method for a single-branch RRAM resistor network, characterized in that the method comprises:

[0043] Obtaining a pre-built positive impedance calibration module, a negative impedance calibration module, a user impedance calibration module and a DCI adjustment module, wherein the positive impedance calibration module, the negative impedance calibration module and the user impedance calibration module all include a pre-built RRAM resistor network structure;

[0044] Using the positive electrode impedance calibration module, according to the adjustment information of the DCI adjustment module, the resistor connection state in the RRAM resistor network structure in the positive electrode impedance calibration module is adjusted, and the positive electrode impedance adjustment signal in the adjustment process is recorded;

[0045] Using the negative electrode impedance calibration module, according to the adjustment information of the DCI adjustment module, the resistor connection state in the RRAM resistor network structure in the negative electrode impedance calibration module is adjusted, and the negative electrode impedance adjustment signal in the adjustment process is recorded;

[0046] The user impedance calibration module is used to adjust the resistance of the RRAM resistor network structure in the user impedance calibration module according to the positive impedance adjustment signal and the negative impedance adjustment signal, so as to achieve impedance matching between the pre-built FPGA and the external circuit.

[0047] In addition, the method further comprises:

[0048] Using the DCI adjustment module, according to the feedback information, it is determined whether the impedance of the positive impedance calibration module and the negative impedance calibration module needs to be adjusted, and adjustment information is obtained;

[0049] Using the RRAM resistor network structure, and adjusting the resistor connection state of the RRAM in the RRAM resistor network structure according to the adjustment information;

[0050] Using the positive impedance calibration module and the post-stage comparator, the PAD voltage generated by the RRAM resistor network structure according to the resistor connection state is compared with a pre-built reference voltage to obtain a comparison result, and the comparison result is sent to the DCI adjustment module as feedback information;

[0051] Using the negative electrode impedance calibration module and the post-stage comparator, the PAD voltage generated by the RRAM resistor network structure according to the resistor connection state is compared with the reference voltage to obtain a comparison result, and the comparison result is sent to the DCI adjustment module as feedback information;

[0052] Utilizing the user impedance calibration module, when the adjustment information is that no adjustment is required, the adjustment information recorded in the positive impedance calibration module is obtained to obtain a positive impedance adjustment signal, and the adjustment information recorded in the negative impedance calibration module is obtained to obtain a negative impedance adjustment signal, and the positive impedance adjustment signal is configured on the positive RRAM resistor network structure in the user impedance calibration module, and the negative impedance adjustment signal is configured on the negative RRAM resistor network structure in the user impedance calibration module, wherein, in the user impedance calibration module, the negative RRAM resistor network structure and the positive RRAM resistor network structure intersect on a pre-constructed PAD line, wherein the PAD line has a PAD output line impedance, and the PAD output line impedance is used to achieve impedance matching between the FPGA and an external circuit.

[0053] The present invention solves the problem described in the background technology. The present invention constructs an RRAM resistor network structure, which includes multiple RRAMs, and can read and write the resistance value of each RRAM according to the high and low levels, thereby changing the resistance value of the overall RRAM resistor network structure, thereby replacing the parallel resistor network structure in the positive and negative impedance calibration networks in the traditional impedance matching network, and finding the positive impedance adjustment signal and the negative impedance adjustment signal faster and with lower consumption, thereby facilitating impedance matching on the user side. Therefore, the present invention simplifies the circuit of the impedance matching resistor network, saves chip area occupancy, and saves circuit power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 A schematic diagram of the structure of an impedance matching circuit of a single-branch RRAM resistor network provided by an embodiment of the present invention;

[0055] Figure 2 A schematic diagram of the structure of a conventional impedance matching circuit provided by an embodiment of the present invention;

[0056] Figure 3 A schematic diagram of an RRAM resistor network structure in an impedance matching circuit of a single-branch RRAM resistor network provided in an embodiment of the present invention;

[0057] Figure 4A Schematic diagram of the single RRAM impedance calibration structure for N-side reference IO;

[0058] Figure 4BA schematic diagram of the impedance calibration structure of a single RRAM with reference IO on the P side;

[0059] Figure 5A A schematic diagram of the impedance matching waveform of a single pull-down RRAM for the N-side reference IO;

[0060] Figure 5B A schematic diagram of the impedance matching waveform of a single pull-up RRAM for the P-side reference IO;

[0061] Figure 6 A schematic flow chart of an impedance matching circuit method for a single-branch RRAM resistor network provided by an embodiment of the present invention.

[0062] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0063] In order to make the purpose, technical solution and advantages of the present application more obvious, the exemplary embodiments according to the present application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application, and it should be understood that the present application is not limited to the exemplary embodiments described here.

[0064] An embodiment of the present application relates to an impedance matching circuit of a single-branch RRAM resistor network, which mainly includes a positive impedance calibration module, a negative impedance calibration module, a user impedance calibration module and a DCI adjustment module, wherein the positive impedance calibration module, the negative impedance calibration module and the user impedance calibration module all include an RRAM resistor network structure;

[0065] The positive electrode impedance calibration module includes a precise matching resistor, a switch tube, a post-stage comparator and the RRAM resistor network structure, and is used to adjust the resistor connection state in the RRAM resistor network structure in the positive electrode impedance calibration module according to the adjustment information of the DCI adjustment module, and record the positive electrode impedance adjustment signal during the adjustment process;

[0066] The negative electrode impedance calibration module includes a precise matching resistor, a switch tube, a post-stage comparator and the RRAM resistor network structure, and is used to adjust the resistor connection state in the RRAM resistor network structure in the negative electrode impedance calibration module according to the adjustment information of the DCI adjustment module, and record the negative electrode impedance adjustment signal during the adjustment process;

[0067] The user impedance calibration module includes a switch tube and an RRAM resistor network structure, which is used to adjust the resistance of the RRAM resistor network structure in the user impedance calibration module according to the positive impedance adjustment signal and the negative impedance adjustment signal to achieve impedance matching between the pre-built FPGA and the external circuit.

[0068] Among them, the RRAM is a new type of non-volatile memory. The more mature structure is the metal / semiconductor / metal MIM structure, which has a simple structure, low write voltage, fast read and write speed, and its biggest advantage is that it can store multiple resistance states and the states can be maintained for a long time.

[0069] The DCI adjustment module refers to a functional block in the FPGA that adjusts the impedance to match the external reference resistor.

[0070] The FPGA is a programmable integrated circuit whose internal logic structure and connection relationship can be configured by programming according to user needs to realize various digital functions.

[0071] The precise matching resistor is used to provide a component with a fixed or adjustable precise resistance value.

[0072] Among them, the switching tube is a component used to control the on and off of current in an electronic circuit. By changing the input signal, the switching tube can switch between the two states of "on" (equivalent to the switch being closed) and "off" (equivalent to the switch being open).

[0073] The post-stage comparator refers to a component that receives a signal processed by a previous-stage circuit (such as a PAD voltage), compares the signal with a reference value or other input signal (such as a reference voltage VREF), and then outputs a high level or a low level (digital logic, 0 or 1) as a result.

[0074] The present invention Figure 1 The structure diagram shows the calculation method of the user-side IO impedance of the traditional DCI output. Figure 1 The following is a representative structural diagram of the improved impedance matching circuit of this scheme.

[0075] refer to Figure 2 From the DCI application structure diagram in FPGA, we can see that traditional DCI selectively adjusts the output (negative) impedance or the input (positive) impedance to match the external reference resistor. This can compensate for the IO impedance changes caused by process deviations. DCI also continuously adjusts the IO impedance to compensate for the impedance changes caused by temperature changes and power supply voltage fluctuations.

[0076] DCI uses two IOs in each BANK as reference IOs to control the driving impedance or parallel terminal impedance of all IOs in the BANK. The N-side (negative) reference IO (VRN) is pulled up to the power supply voltage by a reference resistor, while the P-side (positive) reference IO (VRP) is pulled down to ground by another reference resistor. The user-side IO (USER IO) data comes from VRN (ground) and VRP (ground). The resistance value of the reference resistor should be equal to the characteristic impedance (Z0) of the PCB circuit board trace, or a multiple of this value.

[0077] However, the matching resistor network in the existing technology is generally constructed using multiple parallel resistors or resistors with different width-to-length ratios. For example, the resistors are distributed according to the width-to-length ratios of 2nR, 2n-1R, ..., 4R, 2R, R or the parallel resistors are distributed as 1, 2, 4, ..., 2n-1, 2n. This type of resistor network is not only used in large numbers in integrated circuits and occupies a large area, but also this binary resistor network will limit the algorithm and is not flexible enough.

[0078] Therefore, reference Figure 3 As shown, in the embodiment of the present invention, a RRAM resistor network structure is constructed according to the working principle of RRAM.

[0079] Specifically, the adjustable resistor RRAM of the present invention can realize resistance values ​​of multiple resistance states, omitting the serial-to-parallel conversion of data, and can directly write the resistance adjustment pulse sequence into the RRAM, and can realize impedance matching after adjustment. It can solve the multi-path problem of the resistor network and greatly reduce the area of ​​the resistor network.

[0080] Specifically, refer to Figure 3 The RRAM resistor network structure is shown in the figure. The RRAM resistor network structure can be used for the pull-up network RRAM_PU or the pull-down network RRAM_PD. The RRAM resistor network structure can include n+1 RRAMs, and the value of n can be selected according to actual needs. The RRAM adjustment process is to cycle to BL in turn. <0> and BLN <0> Between, BL <1> and BLN <1> Between, BL <2> and BLN <2> Between... BL <n>and BLN <n>The RRAM write signal between them (as shown in the dotted line 0, 1, 2, n in sequence) is cycled until the RRAM network meets the matching requirements.

[0081] Furthermore, in the embodiment of the present invention, after the RRAM resistor network structure is constructed, it can be used to replace the traditional DCI circuit with parallel resistors to form the impedance matching circuit of the single-branch RRAM resistor network.

[0082] In detail, in an embodiment of the present invention, the circuit includes:

[0083] The DCI adjustment module is used to determine whether the impedance of the positive impedance calibration module and the negative impedance calibration module needs to be adjusted according to the feedback information, and obtain adjustment information;

[0084] The RRAM resistor network structure is used to initialize the number of resistors and is also used to adjust the connection state of the resistors of the RRAM in the RRAM resistor network structure according to the adjustment information;

[0085] The positive impedance calibration module is used to compare the PAD voltage generated by the RRAM resistor network structure according to the resistor connection state with a pre-built reference voltage using the post-stage comparator to obtain a comparison result, and send the comparison result as feedback information to the DCI adjustment module;

[0086] The negative electrode impedance calibration module is used to compare the PAD voltage generated by the RRAM resistor network structure according to the resistor connection state with the reference voltage using the post-stage comparator to obtain a comparison result, and send the comparison result as feedback information to the DCI adjustment module;

[0087] The user impedance calibration module is used to obtain the adjustment information recorded in the positive impedance calibration module to obtain a positive impedance adjustment signal when the adjustment information indicates that no adjustment is required, and to obtain the adjustment information recorded in the negative impedance calibration module to obtain a negative impedance adjustment signal, and to configure the positive impedance adjustment signal on the positive RRAM resistor network structure in the user impedance calibration module, and to configure the negative impedance adjustment signal on the negative RRAM resistor network structure in the user impedance calibration module, wherein, in the user impedance calibration module, the negative RRAM resistor network structure and the positive RRAM resistor network structure intersect on a pre-constructed PAD line, wherein the PAD line has a PAD output line impedance, and the PAD output line impedance is used to achieve impedance matching between the FPGA and an external circuit.

[0088] Among them, the PAD / PAD line refers to the input / output pin interface module on the FPGA chip, which is a direct interface between external signals and the internal logic of the FPGA. It can be understood that the PAD corresponds to the actual I / O pin (or solder ball).

[0089] Specifically, in the embodiment of the present invention, the DCI adjustment module is unchanged and will not be described in detail here, while the positive impedance calibration module, the negative impedance calibration module, and the user impedance calibration module are all improved through the RRAM resistor network structure.

[0090] In detail, in the embodiment of the present invention, the positive electrode impedance calibration module includes a positive adjustment structure, a precision matching resistor and a post-stage comparator;

[0091] The positive regulation structure includes two switch tubes and an RRAM resistor network structure, wherein two ends of the RRAM resistor network structure are each connected to a switch tube;

[0092] The positive regulation structure pulls up a default voltage source, and the other end of the positive regulation structure is connected to the PAD line;

[0093] The precise matching resistor pulls down a ground line, and the other end of the precise matching resistor is connected to the PAD line;

[0094] The first access terminal of the post-stage comparator is connected to the PAD line, the second access terminal of the post-stage comparator is connected to a reference voltage, and the output terminal of the post-stage comparator is connected to the DCI adjustment module.

[0095] Specifically, refer to Figure 4A As shown, VRP represents the P-side reference IO, VCCO represents the default voltage source, PMOS represents the switch tube, RRAM-PU represents the pull-up RRAM resistor network structure, Rref represents the precise matching resistor, PAD represents the PAD voltage on the PAD line, DCI_COMP represents the post-stage comparator, and VRP represents the ground line.

[0096] In detail, in the embodiment of the present invention, the negative electrode impedance calibration module includes a negative adjustment structure, a precise matching resistor and a post-stage comparator;

[0097] The negative regulation structure includes two switch tubes and an RRAM resistor network structure, wherein two ends of the RRAM resistor network structure are each connected to a switch tube;

[0098] In the negative electrode impedance calibration module, the negative adjustment structure pulls down a ground line, and the other end of the negative adjustment structure is connected to the PAD line;

[0099] The precise matching resistor pulls up a default voltage source, and the other end of the precise matching resistor is connected to the PAD line;

[0100] The first access terminal of the post-stage comparator is connected to the PAD line, the second access terminal of the post-stage comparator is connected to a reference voltage, and the output terminal of the post-stage comparator is connected to the DCI adjustment module.

[0101] Specifically, refer to Figure 4B As shown, VRN represents the N-side reference IO, NMOS represents the switch tube, and the difference from VRP is that the RRAM resistor network structure is connected to the ground line.

[0102] In detail, in an embodiment of the present invention, the user impedance calibration module includes a positive adjustment structure and a negative adjustment structure;

[0103] The positive regulation structure pulls up a default voltage source, and the negative regulation structure pulls down a ground line;

[0104] The positive regulatory structure is connected to the negative regulatory structure.

[0105] Specifically, refer to Figure 1 The structure shown connects the default voltage source and the ground line in parallel by connecting the two respectively, and a PAD output line impedance is generated at the parallel junction.

[0106] In detail, in an embodiment of the present invention, the RRAM resistor network structure includes:

[0107] When the RRAM in the RRAM resistor network structure is adjusted, the switch tubes at both ends of the RRAM resistor network structure are turned off;

[0108] When the RRAM in the RRAM resistor network structure is adjusted, the switch tubes at both ends of the RRAM resistor network structure are turned on.

[0109] In detail, in the embodiment of the present invention, the positive electrode impedance calibration module includes:

[0110] Calculate the positive voltage division value of the positive impedance calibration module on the PAD line according to the resistance value in the positive impedance calibration module;

[0111] Determining whether the positive divided voltage value is less than the reference voltage;

[0112] When the positive voltage division value is less than the reference voltage, the output result of the post-stage comparator in the positive impedance calibration module is that adjustment is required;

[0113] When the positive voltage division value is greater than or equal to the reference voltage, the output result of the post-stage comparator in the positive electrode impedance calibration module is that no adjustment is required.

[0114] Among them, PAD in the figure represents a positive partial pressure value.

[0115] In detail, in the embodiment of the present invention, the negative electrode impedance calibration module includes:

[0116] Calculate the negative voltage division value of the negative electrode impedance calibration module on the PAD line according to the resistance value in the negative electrode impedance calibration module;

[0117] Determining whether the negative divided voltage value is less than the reference voltage;

[0118] When the negative voltage division value is greater than or equal to the reference voltage, the output result of the post-stage comparator in the negative electrode impedance calibration module is that adjustment is required;

[0119] When the negative voltage division value is less than the reference voltage, the output result of the post-stage comparator in the negative electrode impedance calibration module is that no adjustment is required.

[0120] Wherein, PAD in the figure represents a negative partial pressure value.

[0121] Specifically, in the embodiment of the present invention, the N-side impedance calibration process is as follows:

[0122] (1) Turn off the two NMOS tubes to prevent the influence of external signals on RRAM_PD;

[0123] (2) The regulation signal flows from the BL terminal through the BLN terminal in sequence according to Figure 2 The regulation process cyclically adjusts the resistance of each row in the RRAM_PD network;

[0124] (3) After the adjustment is completed, the adjustment signal is turned off, the two NMOS tubes are turned on, and the PAD is compared with the reference voltage VREF through the comparator (DCI_COMP). The comparison result is fed back to the DCI adjustment module to determine whether to terminate the input;

[0125] (4) Loop (1)-(3) until the comparator result flips and the input signal stops;

[0126] (5) When the input of the adjustment signal stops, the number of adjustment signals input to RRAM_PD at this time is recorded, and USER IO is prepared to be updated.

[0127] Furthermore, in the embodiment of the present invention, the P-side impedance calibration process is as follows:

[0128] (1) Turn off the two PMOS tubes to prevent the influence of external signals on RRAM_PU;

[0129] (2) The adjustment signal is in accordance with Figure 2 The regulation process cyclically adjusts each row resistance in the RRAM_PU network;

[0130] (3) After the adjustment is completed, the BL signal is turned off, the PMOS tube is turned on, and the PAD is compared with the reference voltage VREF through the comparator (DCI_COMP). The result is fed back to the DCI adjustment module to determine whether to terminate the input;

[0131] (4) Loop (1)-(3) until the comparator result flips and the input signal stops;

[0132] (5) When the input of the adjustment signal stops, the number of adjustment signals input to RRAM_PU at this time is recorded, and USER IO is prepared to be updated.

[0133] Furthermore, the parallel calibration process on the user side:

[0134] The regulated signal data stored in VRN and VRP are transmitted to RRAM_PU and RRAM_PD in sequence (i.e., the execution Figure 4A The input signal recorded when the RRAM_PD tube is adjusted is input to Figure 1 In the RRAM_PD, the Figure 4B The input signal of the RRAM_PU tube is recorded when inputting Figure 1 of RRAM_PU).

[0135] When USER IO is used for termination impedance matching, the PMOS tube and the NMOS tube are turned on at the same time. At this time, RRAM_PU and RRAM_PD are connected in parallel. The output line impedance of the PAD can be matched through the parallel RRAM.

[0136] Furthermore, in the embodiment of the present invention, Figure 5A The figure is a schematic diagram of the impedance matching waveform of a single pull-down RRAM of VRN. When RRAM_PD is adjusted, the overall resistance value of the RRAM resistor network is continuously adjusted and reduced under the action of the power supply voltage. At the same time, the voltage division of the PAD line gradually decreases and gradually approaches VREF. When the PAD voltage is less than VREF, the comparison result of the DCI comparator changes from 1 to 0. The signal is fed back to the front of the adjustment circuit to stop the input adjustment signal and start updating USER IO.

[0137] Figure 5B The figure is a schematic diagram of the impedance matching waveform of a single pull-up RRAM of VRP. When RRAM_PU is adjusted, the overall resistance value of the RRAM resistance network is continuously adjusted and reduced under the action of the power supply voltage. At the same time, the voltage division of the PAD line gradually increases and gradually approaches VREF. When the PAD voltage is greater than VREF, the comparison result of the DCI comparator changes from 0 to 1. The signal is fed back to the front of the adjustment circuit to stop the input adjustment signal and start updating USER IO.

[0138] The present invention solves the problem described in the background technology. The present invention constructs an RRAM resistor network structure, which includes multiple RRAMs, and can read and write the resistance value of each RRAM according to the high and low levels, thereby changing the resistance value of the overall RRAM resistor network structure, thereby replacing the parallel resistor network structure in the positive and negative impedance calibration networks in the traditional impedance matching network, and finding the positive impedance adjustment signal and the negative impedance adjustment signal faster and with lower consumption, thereby facilitating impedance matching on the user side. Therefore, the present invention simplifies the circuit of the impedance matching resistor network, saves chip area occupancy, and saves circuit power consumption.

[0139] Further, see Figure 6 As shown, the embodiment of the present invention also provides a method for utilizing Figure 1 The impedance matching circuit method of the single-branch RRAM resistor network shown includes:

[0140] S1. Obtain a pre-built positive impedance calibration module, a negative impedance calibration module, a user impedance calibration module and a DCI adjustment module, wherein the positive impedance calibration module, the negative impedance calibration module and the user impedance calibration module all include a pre-built RRAM resistor network structure.

[0141] S2. Using the positive electrode impedance calibration module, according to the adjustment information of the DCI adjustment module, adjust the resistor connection state in the RRAM resistor network structure in the positive electrode impedance calibration module, and record the positive electrode impedance adjustment signal during the adjustment process.

[0142] S3. Using the negative electrode impedance calibration module, according to the adjustment information of the DCI adjustment module, adjust the resistor connection state in the RRAM resistor network structure in the negative electrode impedance calibration module, and record the negative electrode impedance adjustment signal during the adjustment process.

[0143] S4. Using the user impedance calibration module, according to the positive impedance adjustment signal and the negative impedance adjustment signal, the resistance of the RRAM resistor network structure in the user impedance calibration module is adjusted to achieve impedance matching between the pre-built FPGA and the external circuit.

[0144] The DCI adjustment module refers to a functional block in the FPGA that adjusts the impedance to match the external reference resistor. The FPGA is a programmable integrated circuit that can configure its internal logic structure and connection relationship through programming according to user needs to realize various digital functions.

[0145] The positive electrode impedance calibration module includes a precise matching resistor, a switch tube, a post-stage comparator and the RRAM resistor network structure, and is used to adjust the resistor connection state in the RRAM resistor network structure according to the adjustment information of the DCI adjustment module to obtain a positive electrode impedance adjustment signal;

[0146] The negative electrode impedance calibration module includes a precise matching resistor, a switch tube, a post-stage comparator and the RRAM resistor network structure, and is used to adjust the resistor connection state in the RRAM resistor network structure according to the adjustment information of the DCI adjustment module to obtain a negative electrode impedance adjustment signal;

[0147] The user impedance calibration module includes a switch tube and an RRAM resistor network structure, which is used to achieve impedance matching between the pre-built FPGA and the external circuit according to the positive impedance adjustment signal and the negative impedance adjustment signal.

[0148] Among them, the RRAM is a new type of non-volatile memory. The more mature structure is the metal / semiconductor / metal MIM structure, which has a simple structure, low write voltage, fast read and write speed, and its biggest advantage is that it can store multiple resistance states and the states can be maintained for a long time.

[0149] Specifically, in the embodiment of the present invention, when the DCI adjustment module sends out adjustment information, the adjustment information can be represented by digital logic according to the high and low levels, and then the binary adjustment information is sent to the RRAM resistor network structure to change the connection state of each RRAM. When the connection state of the RRAM is stable, the positive impedance adjustment signal and the negative impedance adjustment signal can be obtained, and the PAD output line impedance can be obtained by parallel calculation according to the traditional DCI algorithm. The PAD output line impedance can be the same as the resistance value of the external circuit, thereby avoiding information transmission problems caused by resistance changes.

[0150] The PAD refers to the input / output pin interface module on the FPGA chip, which is a direct interface between external signals and the internal logic of the FPGA. It can be understood that the PAD corresponds to the actual I / O pin (or solder ball).

[0151] In detail, in an embodiment of the present invention, the method further includes:

[0152] Using the DCI adjustment module, according to the feedback information, it is determined whether the impedance of the positive impedance calibration module and the negative impedance calibration module needs to be adjusted, and adjustment information is obtained;

[0153] Using the RRAM resistor network structure, and adjusting the resistor connection state of the RRAM in the RRAM resistor network structure according to the adjustment information;

[0154] Using the positive impedance calibration module and the post-stage comparator, the PAD voltage generated by the RRAM resistor network structure according to the resistor connection state is compared with a pre-built reference voltage to obtain a comparison result, and the comparison result is sent to the DCI adjustment module as feedback information;

[0155] Using the negative electrode impedance calibration module and the post-stage comparator, the PAD voltage generated by the RRAM resistor network structure according to the resistor connection state is compared with the reference voltage to obtain a comparison result, and the comparison result is sent to the DCI adjustment module as feedback information;

[0156] Utilizing the user impedance calibration module, when the adjustment information is that no adjustment is required, the adjustment information recorded in the positive impedance calibration module is obtained to obtain a positive impedance adjustment signal, and the adjustment information recorded in the negative impedance calibration module is obtained to obtain a negative impedance adjustment signal, and the positive impedance adjustment signal is configured on the positive RRAM resistor network structure in the user impedance calibration module, and the negative impedance adjustment signal is configured on the negative RRAM resistor network structure in the user impedance calibration module, wherein, in the user impedance calibration module, the negative RRAM resistor network structure and the positive RRAM resistor network structure intersect on a pre-constructed PAD line, wherein the PAD line has a PAD output line impedance, and the PAD output line impedance is used to achieve impedance matching between the FPGA and an external circuit.

[0157] Specifically, in the embodiment of the present invention, the P-side impedance calibration process is as follows:

[0158] (1) Turn off the two PMOS tubes to prevent the influence of external signals on RRAM_PU;

[0159] (2) The adjustment signal is in accordance with Figure 2 The regulation process cyclically adjusts each row resistance in the RRAM_PU network;

[0160] (3) After the adjustment is completed, the BL signal is turned off, the PMOS tube is turned on, and the PAD is compared with the reference voltage VREF through the comparator (DCI_COMP). The result is fed back to the DCI adjustment module to determine whether to terminate the input;

[0161] (4) Loop (1)-(3) until the comparator result flips and the input signal stops;

[0162] (5) When the input of the adjustment signal stops, the number of adjustment signals input to RRAM_PU at this time is recorded, and USER IO is prepared to be updated.

[0163] When adjusting RRAM_PU, the overall resistance value of the RRAM resistance network is continuously adjusted and reduced under the action of the power supply voltage. At the same time, the voltage division of the PAD line gradually increases and gradually approaches VREF. When the PAD voltage is greater than VREF, the comparison result of the DCI comparator changes from 0 to 1. The signal is fed back to the front driver of the adjustment circuit to stop inputting the adjustment signal and start updating USER IO.

[0164] It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0165] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.< / n> < / n>

Claims

1. An impedance matching circuit of a single-branch RRAM resistor network, comprising a positive impedance calibration module, a negative impedance calibration module, a user impedance calibration module and a DCI adjustment module, characterized in that: The positive electrode impedance calibration module, the negative electrode impedance calibration module, and the user impedance calibration module all include an RRAM resistor network structure; The positive electrode impedance calibration module includes a precise matching resistor, a switch tube, a post-stage comparator and the RRAM resistor network structure, and is used to adjust the resistor connection state in the RRAM resistor network structure in the positive electrode impedance calibration module according to the adjustment information of the DCI adjustment module, and record the positive electrode impedance adjustment signal during the adjustment process; The negative electrode impedance calibration module includes a precise matching resistor, a switch tube, a post-stage comparator and the RRAM resistor network structure, and is used to adjust the resistor connection state in the RRAM resistor network structure in the negative electrode impedance calibration module according to the adjustment information of the DCI adjustment module, and record the negative electrode impedance adjustment signal during the adjustment process; The user impedance calibration module includes a switch tube and an RRAM resistor network structure, which is used to adjust the resistance of the RRAM resistor network structure in the user impedance calibration module according to the positive impedance adjustment signal and the negative impedance adjustment signal to achieve impedance matching between the pre-built FPGA and the external circuit.

2. The impedance matching circuit of the single-branch RRAM resistor network according to claim 1, characterized in that: The circuit comprises: The DCI adjustment module is used to determine whether the impedance of the positive impedance calibration module and the negative impedance calibration module needs to be adjusted according to the feedback information, and obtain adjustment information; The RRAM resistor network structure is used to initialize the number of resistors and is also used to adjust the connection state of the resistors of the RRAM in the RRAM resistor network structure according to the adjustment information; The positive impedance calibration module is used to compare the PAD voltage generated by the RRAM resistor network structure according to the resistor connection state with a pre-built reference voltage using the post-stage comparator to obtain a comparison result, and send the comparison result as feedback information to the DCI adjustment module; The negative electrode impedance calibration module is used to compare the PAD voltage generated by the RRAM resistor network structure according to the resistor connection state with the reference voltage using the post-stage comparator to obtain a comparison result, and send the comparison result as feedback information to the DCI adjustment module; The user impedance calibration module is used to obtain the adjustment information recorded in the positive impedance calibration module to obtain a positive impedance adjustment signal when the adjustment information indicates that no adjustment is required, and to obtain the adjustment information recorded in the negative impedance calibration module to obtain a negative impedance adjustment signal, and to configure the positive impedance adjustment signal on the positive RRAM resistor network structure in the user impedance calibration module, and to configure the negative impedance adjustment signal on the negative RRAM resistor network structure in the user impedance calibration module, wherein, in the user impedance calibration module, the negative RRAM resistor network structure and the positive RRAM resistor network structure intersect on a pre-constructed PAD line, wherein the PAD line has a PAD output line impedance, and the PAD output line impedance is used to achieve impedance matching between the FPGA and an external circuit.

3. The impedance matching circuit of the single-branch RRAM resistor network according to claim 2, characterized in that: The positive electrode impedance calibration module includes a positive adjustment structure, a precision matching resistor and a post-stage comparator; The positive regulation structure includes two switch tubes and an RRAM resistor network structure, wherein two ends of the RRAM resistor network structure are each connected to a switch tube; The positive regulation structure pulls up a default voltage source, and the other end of the positive regulation structure is connected to the PAD line; The precise matching resistor pulls down a ground line, and the other end of the precise matching resistor is connected to the PAD line; The first access terminal of the post-stage comparator is connected to the PAD line, the second access terminal of the post-stage comparator is connected to a reference voltage, and the output terminal of the post-stage comparator is connected to the DCI adjustment module.

4. The impedance matching circuit of a single-branch RRAM resistor network according to claim 2, wherein: The negative electrode impedance calibration module includes a negative adjustment structure, a precision matching resistor and a post-stage comparator; The negative regulation structure includes two switch tubes and an RRAM resistor network structure, wherein two ends of the RRAM resistor network structure are each connected to a switch tube; In the negative electrode impedance calibration module, the negative adjustment structure pulls down a ground line, and the other end of the negative adjustment structure is connected to the PAD line; The precise matching resistor pulls up a default voltage source, and the other end of the precise matching resistor is connected to the PAD line; The first access terminal of the post-stage comparator is connected to the PAD line, the second access terminal of the post-stage comparator is connected to a reference voltage, and the output terminal of the post-stage comparator is connected to the DCI adjustment module.

5. The impedance matching circuit of the single-branch RRAM resistor network according to claim 2, characterized in that: The user impedance calibration module includes a positive adjustment structure and a negative adjustment structure; The positive regulation structure pulls up a default voltage source, and the negative regulation structure pulls down a ground line; The positive regulatory structure is connected to the negative regulatory structure.

6. The impedance matching circuit of a single-branch RRAM resistor network according to claim 1, wherein: The RRAM resistor network structure comprises: When the RRAM in the RRAM resistor network structure is adjusted, the switch tubes at both ends of the RRAM resistor network structure are turned off; When the RRAM in the RRAM resistor network structure is adjusted, the switch tubes at both ends of the RRAM resistor network structure are turned on.

7. The impedance matching circuit of the single-branch RRAM resistor network according to claim 6, characterized in that: The positive electrode impedance calibration module includes: Calculating the positive voltage division value of the positive impedance calibration module on the pre-constructed PAD line according to the resistance value in the positive impedance calibration module; Determining whether the positive divided voltage value is less than a reference voltage connected to the subsequent comparator; When the positive voltage division value is less than the reference voltage, the output result of the post-stage comparator in the positive impedance calibration module is that adjustment is required; When the positive voltage division value is greater than or equal to the reference voltage, the output result of the post-stage comparator in the positive electrode impedance calibration module is that no adjustment is required.

8. The impedance matching circuit of the single-branch RRAM resistor network according to claim 7, characterized in that: The negative electrode impedance calibration module comprises: Calculate the negative voltage division value of the negative electrode impedance calibration module on the PAD line according to the resistance value in the negative electrode impedance calibration module; Determining whether the negative divided voltage value is less than the reference voltage; When the negative voltage division value is greater than or equal to the reference voltage, the output result of the post-stage comparator in the negative electrode impedance calibration module is that adjustment is required; When the negative voltage division value is less than the reference voltage, the output result of the post-stage comparator in the negative electrode impedance calibration module is that no adjustment is required.

9. An impedance matching circuit method for a single-branch RRAM resistor network, characterized in that: The method comprises: Obtaining a pre-built positive impedance calibration module, a negative impedance calibration module, a user impedance calibration module and a DCI adjustment module, wherein the positive impedance calibration module, the negative impedance calibration module and the user impedance calibration module all include a pre-built RRAM resistor network structure; Using the positive electrode impedance calibration module, according to the adjustment information of the DCI adjustment module, the resistor connection state in the RRAM resistor network structure in the positive electrode impedance calibration module is adjusted, and the positive electrode impedance adjustment signal in the adjustment process is recorded; Using the negative electrode impedance calibration module, according to the adjustment information of the DCI adjustment module, the resistor connection state in the RRAM resistor network structure in the negative electrode impedance calibration module is adjusted, and the negative electrode impedance adjustment signal in the adjustment process is recorded; The user impedance calibration module is used to adjust the resistance of the RRAM resistor network structure in the user impedance calibration module according to the positive impedance adjustment signal and the negative impedance adjustment signal, so as to achieve impedance matching between the pre-built FPGA and the external circuit.

10. The impedance matching circuit method of a single-branch RRAM resistor network according to claim 9, characterized in that: The method further comprises: Using the DCI adjustment module, according to the feedback information, it is determined whether the impedance of the positive impedance calibration module and the negative impedance calibration module needs to be adjusted, and adjustment information is obtained; Using the RRAM resistor network structure, and adjusting the resistor connection state of the RRAM in the RRAM resistor network structure according to the adjustment information; Using the positive impedance calibration module and a pre-built post-stage comparator, the PAD voltage generated by the RRAM resistor network structure according to the resistor connection state is compared with a pre-built reference voltage to obtain a comparison result, and the comparison result is sent to the DCI adjustment module as feedback information; Using the negative electrode impedance calibration module and the post-stage comparator, the PAD voltage generated by the RRAM resistor network structure according to the resistor connection state is compared with the reference voltage to obtain a comparison result, and the comparison result is sent to the DCI adjustment module as feedback information; Utilizing the user impedance calibration module, when the adjustment information is that no adjustment is required, the adjustment information recorded in the positive impedance calibration module is obtained to obtain a positive impedance adjustment signal, and the adjustment information recorded in the negative impedance calibration module is obtained to obtain a negative impedance adjustment signal, and the positive impedance adjustment signal is configured on the positive RRAM resistor network structure in the user impedance calibration module, and the negative impedance adjustment signal is configured on the negative RRAM resistor network structure in the user impedance calibration module, wherein, in the user impedance calibration module, the negative RRAM resistor network structure and the positive RRAM resistor network structure intersect on a pre-constructed PAD line, wherein the PAD line has a PAD output line impedance, and the PAD output line impedance is used to achieve impedance matching between the FPGA and an external circuit.

Images