Data transmission circuit and method suitable for high-frequency clock to low-frequency clock
By designing a data transmission circuit for the high-frequency clock domain to the low-frequency clock domain, the data delay processing module and the data storage module are used to solve the problems of timing deviation, data jitter and power consumption increase in data transmission, and efficient and accurate data acquisition across clock rate is achieved.
Patent Information
- Application Number
- CN202411721160.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-28
- Publication Date
- 2025-03-18
AI Technical Summary
In the data transmission from the high-frequency clock domain to the low-frequency clock domain, data loss, data error, timing deviation, data jitter, and increased power consumption may occur, resulting in uncertainty and timing errors in data transmission.
A data transmission circuit is designed, including a data delay processing module and a data storage module. By calculating the frequency multiple value between the high-frequency signal and the low-frequency signal, determining the number of delays, delaying the input data signal in the high-frequency clock domain, generating an equal amount of delay signals, and collecting the input data signal and delay signals in the low-frequency clock domain.
This solution can centrally collect and process multiple high-frequency clock signals in the low-frequency clock domain, improve the efficiency and accuracy of data acquisition across clock rates, avoid data transmission uncertainty and timing errors caused by clocks of different frequency, reduce timing deviation, data jitter and noise, and reduce power consumption.
Smart Images
Figure CN119652293A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of data transmission, and in particular relates to a data transmission circuit and method suitable for high-frequency clock to low-frequency clock. Background Art
[0002] Data transmission from high-frequency clock domain to low-frequency clock domain is common in optical fiber communication and wireless communication. In digital design of logic circuits, data transmission between clocks of different frequencies may cause clock synchronization problems. Clocks of different frequencies may cause uncertainty and timing errors in data transmission. At the same time, data loss or errors may also occur. The phase relationship between the sending clock and the receiving clock is constantly changing, causing problems in data sampling and recovery. As well as the delay change of data during transmission or the timing deviation during data recovery, data jitter or noise, power consumption and delay increase. Summary of the invention
[0003] In view of the above problems, the present invention proposes a data transmission circuit and method suitable for high-frequency clock to low-frequency clock, which can effectively solve the problems of data loss, data error, timing deviation, data jitter, increased power consumption, etc. that may occur during data transmission.
[0004] In order to achieve the above technical objectives and the above technical effects, the present invention is implemented through the following technical solutions:
[0005] In a first aspect, the present invention provides a data transmission circuit suitable for high-frequency clock to low-frequency clock, comprising:
[0006] A data delay processing module, which calculates the number of delays based on the frequency multiples between the high-frequency signal and the low-frequency signal, performs delay processing on the input data signal input into the high-frequency clock domain based on the number of delays, generates a number of delayed signals equal to the number of delays, and collects the input data signal and the delayed signal in the low-frequency clock domain;
[0007] The data storage module is connected to the data delay processing module and stores the output signal of the data delay processing module.
[0008] In combination with the first aspect, optionally, the relationship between the delay times and the frequency multiplier is:
[0009] D=MAG-1
[0010] Where D is the number of delays and MAG is the frequency multiplier.
[0011] In combination with the first aspect, optionally, the frequency multiplier is calculated as follows:
[0012]
[0013] in, is the clock period of the high frequency signal, is the clock period of the low-frequency signal.
[0014] In combination with the first aspect, optionally, the clock period of the high-frequency signal is obtained by calculating the distance between two rising edges of the high-frequency clock signal.
[0015] In combination with the first aspect, optionally, the clock period of the low-frequency signal is obtained by calculating according to the distance between two rising edges of the low-frequency clock signal.
[0016] In a second aspect, the present invention provides a data transmission method applicable to a high-frequency clock to a low-frequency clock, comprising:
[0017] Calculate the number of delays based on the frequency multiple of the high-frequency signal and the low-frequency signal using the data delay processing module, perform delay processing on the input data signal input into the high-frequency clock domain based on the number of delays, generate delay signals equal to the number of delays, and collect the input data signal and the delay signal in the low-frequency clock domain;
[0018] The output signal of the data delay processing module is stored by using a data storage module connected to the data delay processing module.
[0019] In combination with the first aspect, optionally, the relationship between the delay times and the frequency multiplier is:
[0020] D=MAG-1
[0021] Where D is the number of delays and MAG is the frequency multiplier.
[0022] In combination with the first aspect, optionally, the frequency multiplier is calculated as follows:
[0023]
[0024] in, is the clock period of the high frequency signal, is the clock period of the low-frequency signal.
[0025] In combination with the first aspect, optionally, the clock period of the high-frequency signal is obtained by calculating the distance between two rising edges of the high-frequency clock signal.
[0026] In combination with the first aspect, optionally, the clock period of the low-frequency signal is obtained by calculating according to the distance between two rising edges of the low-frequency clock signal.
[0027] Compared with the prior art, the present invention has the following beneficial effects:
[0028] The present invention performs delay processing on high-frequency clock data signals, can collect multiple high-frequency clock signals in a low-frequency clock, and centrally process the multiple high-frequency clock signals, thereby improving the efficiency and accuracy of cross-clock rate data collection.
[0029] In the digital design of logic circuits, data transmission between clocks of different frequencies may cause clock synchronization problems. The present invention can avoid the uncertainty and timing errors that may be caused by clocks of different frequencies in data transmission. At the same time, the present invention delays the high-frequency clock data to generate multiple delayed data signals to reduce timing deviation, data jitter and noise, and multiple data are processed in parallel to reduce power consumption and other problems. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative labor, among which:
[0031] Figure 1 A principle block diagram of a data transmission circuit from a high-frequency clock to a low-frequency clock according to an embodiment of the present invention;
[0032] Figure 2 The present invention is a flowchart of a data transmission method from a high-frequency clock to a low-frequency clock according to an embodiment of the present invention. DETAILED DESCRIPTION
[0033] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0034] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.
[0035] Example 1
[0036] The embodiment of the present invention provides a data transmission circuit suitable for high-frequency clock to low-frequency clock, such as Figure 1 As shown, it includes: a data delay processing module and a data storage module;
[0037] The data delay processing module calculates the delay times based on the frequency multiples between the high-frequency signal and the low-frequency signal, performs delay processing on the input data signal input into the high-frequency clock domain based on the delay times, generates a number of delay signals equal to the delay times, and collects the input data signal and the delay signal in the low-frequency clock domain; in the specific implementation process, the delay processing can utilize the existing technology, introduce a data cache buffer or introduce asynchronous processing, and the operation generates a number of delay signals equal to the delay times;
[0038] The data storage module is connected to the data delay processing module and stores the output signal of the data delay processing module.
[0039] The data transmission circuit in the embodiment of the present invention can collect multiple high-frequency clock signals in a low-frequency clock by delaying the high-frequency clock data signal, and centrally process the multiple high-frequency clock signals, thereby improving the efficiency and accuracy of cross-clock rate data collection.
[0040] The data transmission circuit in the embodiment of the present invention can avoid the uncertainty and timing errors in data transmission that may be caused by clocks of different frequencies. At the same time, the present invention can solve the problems of delay variation of data during transmission or timing deviation during data recovery, data jitter or noise, increase in power consumption and delay, etc.
[0041] In a specific implementation of the embodiment of the present invention, the relationship between the delay times and the frequency multiplier is:
[0042] D=MAG-1
[0043] Where D is the number of delays and MAG is the frequency multiple. This design can realize the parameterization of delay processing and avoid blocking the main thread due to data delay. Data can be processed independently in the background while the main thread continues to execute other tasks.
[0044] In a specific implementation of the embodiment of the present invention, the calculation formula of the frequency multiplier is:
[0045]
[0046] Among them, among them, is the clock period of the high frequency signal, is the clock period of the low-frequency signal.
[0047] In a specific implementation of the embodiment of the present invention, the clock period of the high-frequency signal is obtained by calculating the distance between two rising edges of the high-frequency clock signal.
[0048] In a specific implementation of the embodiment of the present invention, the clock period of the low-frequency signal is obtained by calculating according to the distance between two rising edges of the low-frequency clock signal.
[0049] The working process of the data transmission circuit in the embodiment of the present invention is described in detail below in conjunction with a specific implementation manner.
[0050] 1) Calculate the frequency of the high-frequency clock. The specific method is to calculate the period of the high-frequency clock according to the distance between the two rising edges of the high-frequency clock signal, and then calculate the period of the high-frequency clock according to the high-frequency clock frequency formula. Calculate the frequency of the high-frequency clock, the frequency That is, the number of times the clock signal changes per second, measured in Hertz; is the clock cycle, that is, the time required for a complete clock signal change, in seconds (s).
[0051] 2) Calculate the frequency of the low-frequency clock. The specific method is to calculate the period of the low-frequency clock according to the distance between the two rising edges of the low-frequency clock signal, and then calculate the period of the low-frequency clock according to the low-frequency clock frequency formula. Calculate the frequency of the low-frequency clock, the frequency That is, the number of times the clock signal changes per second, measured in Hertz. is the clock cycle, that is, the time required for a complete clock signal change, in seconds (s).
[0052] 3) Divide the two frequencies of the clocks calculated in step 1) and step 2) to calculate the multiplication value MAG between the two clocks.
[0053] 4) Delay the input data signal data of the high-frequency clock domain. The number of delay processing is determined by the magnification value MAG calculated in step 3), and the number of delay processing is MAG-1. For example, if the magnification between the high-frequency clock and the low-frequency clock is 4, the data signal input to the high-frequency clock domain is delayed 3 times, thereby obtaining a three-stage register delay chain and three delayed signals data_dly1, data_dly2, and data_dly3.
[0054] 5) Sample the high-frequency clock domain input data signal data and three delayed signals data_dly1, data_dly2, and data_dly3 in the low-frequency clock domain, that is, simultaneously collect the high-frequency clock domain input data signal data and three delayed signals data_dly1, data_dly2, and data_dly3 in the low-frequency clock domain, a total of four high-frequency data signals, and store the four high-frequency data signals in the men array at the same time.
[0055] Example 2
[0056] The embodiment of the present invention provides a data transmission method suitable for high-frequency clock to low-frequency clock, such as Figure 2 As shown, the following steps are included:
[0057] (1) using a data delay processing module to calculate the number of delays based on the frequency multiple of the high-frequency signal and the low-frequency signal, performing delay processing on the input data signal input into the high-frequency clock domain based on the delay number, generating a number of delayed signals equal to the number of delays, and collecting the input data signal and the delayed signal in the low-frequency clock domain; in the specific implementation process, the delay processing can utilize existing technologies, introduce a data cache buffer or introduce asynchronous processing, and this operation generates a number of delayed signals equal to the number of delays;
[0058] (2) Using a data storage module connected to the data delay processing module to store the output signal of the data delay processing module.
[0059] The data transmission method in the embodiment of the present invention can collect multiple high-frequency clock signals in a low-frequency clock by delaying the high-frequency clock data signal, and centrally process the multiple high-frequency clock signals, thereby improving the efficiency and accuracy of cross-clock rate data collection.
[0060] The data transmission method in the embodiment of the present invention can avoid the uncertainty and timing errors in data transmission that may be caused by clocks of different frequencies. At the same time, the present invention can solve the problems of delay variation of data during transmission or timing deviation during data recovery, data jitter or noise, increase in power consumption and delay, etc.
[0061] In a specific implementation of the embodiment of the present invention, the relationship between the delay times and the frequency multiplier is:
[0062] D=MAG-1
[0063] Where D is the number of delays and MAG is the frequency multiple. This design can realize the parameterization of delay processing and avoid blocking the main thread due to data delay. Data can be processed independently in the background while the main thread continues to execute other tasks.
[0064] In a specific implementation of the embodiment of the present invention, the calculation formula of the frequency multiplier is:
[0065]
[0066] in, is the clock period of the high frequency signal, is the clock period of the low-frequency signal.
[0067] In a specific implementation of the embodiment of the present invention, the clock period of the high-frequency signal is obtained by calculating the distance between two rising edges of the high-frequency clock signal.
[0068] In a specific implementation of the embodiment of the present invention, the clock period of the low-frequency signal is obtained by calculating according to the distance between two rising edges of the low-frequency clock signal.
[0069] The working process of the data transmission method in the embodiment of the present invention is described in detail below in conjunction with a specific implementation manner.
[0070] 1) Calculate the frequency of the high-frequency clock. The specific method is to calculate the period of the high-frequency clock according to the distance between the two rising edges of the high-frequency clock signal, and then calculate the period of the high-frequency clock according to the high-frequency clock frequency formula. Calculate the frequency of the high-frequency clock, the frequency That is, the number of times the clock signal changes per second, measured in Hertz; is the clock cycle, that is, the time required for a complete clock signal change, in seconds (s).
[0071] 2) Calculate the frequency of the low-frequency clock. The specific method is to calculate the period of the low-frequency clock according to the distance between the two rising edges of the low-frequency clock signal, and then calculate the period of the low-frequency clock according to the low-frequency clock frequency formula. Calculate the frequency of the low-frequency clock, the frequency That is, the number of times the clock signal changes per second, measured in Hertz. is the clock cycle, that is, the time required for a complete clock signal change, in seconds (s).
[0072] 3) Divide the two frequencies of the clocks calculated in step 1) and step 2) to calculate the multiplication value MAG between the two clocks.
[0073] 4) Delay the input data signal data of the high-frequency clock domain. The number of delay processing is determined by the magnification value MAG calculated in step 3), and the number of delay processing is MAG-1. For example, if the magnification between the high-frequency clock and the low-frequency clock is 4, the data signal input to the high-frequency clock domain is delayed 3 times, thereby obtaining a three-stage register delay chain and three delayed signals data_dly1, data_dly2, and data_dly3.
[0074] 5) Sample the high-frequency clock domain input data signal data and three delayed signals data_dly1, data_dly2, and data_dly3 in the low-frequency clock domain, that is, simultaneously collect the high-frequency clock domain input data signal data and three delayed signals data_dly1, data_dly2, and data_dly3 in the low-frequency clock domain, a total of four high-frequency data signals, and store the four high-frequency data signals in the men array at the same time.
[0075] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.
[0076] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0077] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0078] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0079] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which all fall within the protection of the present invention.
[0080] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.
Claims
1. A data transmission circuit suitable for high-frequency clock to low-frequency clock, characterized in that: include: A data delay processing module, which calculates the number of delays based on the frequency multiples between the high-frequency signal and the low-frequency signal, performs delay processing on the input data signal input into the high-frequency clock domain based on the number of delays, generates a number of delayed signals equal to the number of delays, and collects the input data signal and the delayed signal in the low-frequency clock domain; The data storage module is connected to the data delay processing module and stores the output signal of the data delay processing module.
2. A data transmission circuit suitable for high-frequency clock to low-frequency clock according to claim 1, characterized in that: The relationship between the delay times and the frequency multiplier is: D = MAG-1; Where D is the number of delays and MAG is the frequency multiplier.
3. A data transmission circuit suitable for high-frequency clock to low-frequency clock according to claim 1 or 2, characterized in that: The calculation formula of the frequency multiple is: ； in, is the clock period of the high frequency signal, is the clock period of the low-frequency signal.
4. The data transmission circuit suitable for high-frequency clock to low-frequency clock according to claim 3, characterized in that: The clock period of the high-frequency signal is obtained by calculating the distance between two rising edges of the high-frequency clock signal.
5. The data transmission circuit suitable for high-frequency clock to low-frequency clock according to claim 1, characterized in that: The clock period of the low-frequency signal is obtained by calculating the distance between two rising edges of the low-frequency clock signal.
6. A data transmission method suitable for high-frequency clock to low-frequency clock, characterized in that: include: Calculate the number of delays based on the frequency multiple of the high-frequency signal and the low-frequency signal using the data delay processing module, perform delay processing on the input data signal input into the high-frequency clock domain based on the number of delays, generate delay signals equal to the number of delays, and collect the input data signal and the delay signal in the low-frequency clock domain; The output signal of the data delay processing module is stored by using a data storage module connected to the data delay processing module.
7. A data transmission method suitable for high-frequency clock to low-frequency clock according to claim 6, characterized in that: The relationship between the delay times and the frequency multiplier is: D = MAG-1; Where D is the number of delays and MAG is the frequency multiplier.
8. A data transmission method suitable for high-frequency clock to low-frequency clock according to claim 6 or 7, characterized in that: The calculation formula of the frequency multiple is: ； in, is the clock period of the high frequency signal, is the clock period of the low-frequency signal.
9. The data transmission method from a high frequency clock to a low frequency clock according to claim 6, characterized in that: The clock period of the high-frequency signal is obtained by calculating the distance between two rising edges of the high-frequency clock signal.
10. The data transmission method from a high frequency clock to a low frequency clock according to claim 6, characterized in that: The clock period of the low-frequency signal is obtained by calculating the distance between two rising edges of the low-frequency clock signal.