Multi-rate convolutional code sequence decoder and decoding method

Abstract

The invention discloses a multi-rate convolutional code sequence decoder and decoding method, and relates to the technical field of communication decoding, the multi-rate convolutional code sequence decoder comprises a data storage module, a branch measurement module, a parallel processing module, a shift register, a convolutional coding module and a main control module; receiving and storing a coding rate identification bit and to-be-decoded data in the input data; selecting a non-systematic code generator according to the coding rate identification bit, and performing convolution processing according to the shift data of the preset bit number and the non-systematic code generator to obtain a convolution code; acquiring to-be-decoded data according to the non-system code generator, and calculating a branch metric value according to the coding rate identification bit, the to-be-decoded data and the convolutional code; determining a decoding result of the to-be-decoded data according to the branch metric value and the total metric value, and updating the total metric value; updating the shift data in the shift register according to the updated total metric value; the shift data is stored. The input data can be efficiently processed, and the overall data processing speed and efficiency are improved.

Description

Technical Field

[0001] The present application relates to the field of communication decoding technology, and more specifically, to a multi-rate convolutional code sequence decoder and a decoding method. Background Art

[0002] Low-frequency (10kHz-100kHz) radio propagates in the earth-ionosphere waveguide. It has stable propagation, is not affected by nuclear explosions and ionosphere disturbances, has low propagation attenuation in the atmosphere (-3dB / 1000km), can penetrate deep seawater and the earth, and is suitable for long-distance communication, underwater communication, and ground-penetrating communication. After long-distance transmission and seawater attenuation, the low-frequency signal itself is already very weak, and the signal-to-noise ratio is very low. Therefore, in the processing of low-frequency signals, it is necessary to select a decoder and decoding method with better decoding performance to improve the reliability of communication.

[0003] Existing convolutional code decoding technologies are roughly divided into two categories: algebraic decoding and probabilistic decoding. Generally, algebraic decoding has a certain algebraic structure, simple decoding, and easy implementation; probabilistic decoding has strong error correction capabilities. The currently widely used Viterbi decoding method is a type of probabilistic decoding, also known as the maximum likelihood decoding method. Its advantages are strong error correction capabilities, and when the decoding constraints are small, the computational complexity is lower than other probabilistic decoding methods.

[0004] However, the existing convolutional code decoding technology has high decoding complexity. When implemented in conventional DSP and CPU, it takes a long time and cannot meet the requirements of low-frequency communication systems. In some high-speed communication situations, the computational complexity is still too high to meet the needs of real-time decoding. Therefore, further improvements are needed to significantly reduce the computational complexity without affecting the error correction capability, so as to achieve fast and real-time decoding and output data. Summary of the invention

[0005] In response to at least one defect or improvement need in the prior art, the present invention provides a multi-rate convolutional code sequence decoder and a decoding method, which are used to solve the problems that the convolutional code decoding technology in the prior art has high decoding complexity, takes a long time to implement in a conventional DSP or CPU, cannot meet the requirements of a low-frequency communication system, and cannot meet the needs of real-time decoding.

[0006] To achieve the above object, according to a first aspect of the present invention, a multi-rate convolutional code sequence decoder is provided, comprising: a data storage module, a branch metric module, a parallel processing module, a shift register, a convolutional coding module and a main control module; the main control module is respectively connected to the data storage module, the branch metric module, the parallel processing module, the shift register and the convolutional coding module; the parallel processing module is connected to the branch metric module; the convolutional coding module is respectively connected to the branch metric module and the shift register;

[0007] The data storage module is used to receive and store the coding rate identification bit and the data to be decoded in the input data;

[0008] The convolutional coding module is used to select a non-systematic code generator according to a coding rate identification bit, and perform convolution processing on the non-systematic code generator according to the shift data of a preset number of bits to obtain a convolutional code;

[0009] The branch metric module is used to obtain the data to be decoded according to the non-systematic code generator, and calculate the branch metric value according to the coding rate identification bit, the data to be decoded and the convolutional coding;

[0010] The parallel processing module is used to determine the decoding result of the data to be decoded according to the branch metric value and the total metric value, and update the total metric value;

[0011] The main control module is used to update the shift data in the shift register according to the updated total measurement value;

[0012] Shift registers are used to store shift data.

[0013] According to a second aspect of the present invention, a multi-rate convolutional code sequence decoding method is also provided, based on the multi-rate convolutional code sequence decoder as described above, comprising:

[0014] Receive and store the coding rate identification bit and the data to be decoded in the input data;

[0015] Selecting a non-systematic code generator according to a coding rate identification bit, and obtaining data to be decoded according to the non-systematic code generator;

[0016] Convolution processing is performed on the shift data of a preset number of bits and a non-systematic code generator to obtain a convolution code;

[0017] Calculate branch metric values ​​according to the coding rate flag, the data to be decoded and the convolutional coding;

[0018] Determine the decoding result of the data to be decoded according to the branch metric value and the total metric value, and update the total metric value;

[0019] The shift data in the shift register is updated according to the updated total metric value.

[0020] In a possible implementation, receiving and storing the coding rate identification bit and the data to be decoded in the input data, and then initializing the parameters of the multi-rate convolutional code sequence decoder; specifically including:

[0021] Initialize the shift register to zero; initialize the number of nodes and the number of calculations stored in the main control module to zero; initialize the total metric value stored in the parallel processing module to zero; and set a preset total metric value change.

[0022] In a possible implementation, selecting a non-systematic code generator according to a coding rate identification bit, and obtaining to-be-decoded data according to the non-systematic code generator includes:

[0023] When selecting a non-systematic code generator of a first rate according to the coding rate identification bit, obtaining a first amount of data to be decoded;

[0024] When selecting a non-systematic code generator of a second rate according to the coding rate identification bit, obtaining a second amount of data to be decoded;

[0025] When a non-systematic code generator of a third rate is selected according to the coding rate identification bit, a third amount of data to be decoded is obtained.

[0026] In a possible implementation, performing convolution processing on shift data of a preset number of bits and a non-systematic code generator to obtain convolution coding includes:

[0027] Convolutionally processing the shifted data of a preset number of bits and the non-systematic code generator to obtain a first convolutional code;

[0028] The first value and the second value are respectively added to the left end of the shifted data of the preset number of bits and convolved with the non-systematic code generator to obtain the second convolution code and the third convolution code.

[0029] In a possible implementation, calculating a branch metric value according to a coding rate identification bit, data to be decoded, and convolution coding includes:

[0030] Calculating a first branch metric value according to a first rate, a first amount of data to be decoded, and a convolutional code;

[0031] Calculating a second branch metric value according to a second rate, a second amount of data to be decoded, and the convolutional coding;

[0032] A third branch metric value is calculated according to a third rate, a third amount of data to be decoded, and the convolutional coding.

[0033] In a possible implementation, determining a decoding result of the to-be-decoded data according to the branch metric value and the total metric value, and updating the total metric value, includes:

[0034] When the sum of the branch metric value of the second convolutional coding and the total metric value is greater than zero, the decoding result of the data to be decoded is zero, and the total metric value is updated by the sum of the total metric value and the branch metric value of the second convolutional coding;

[0035] When the sum of the branch metric value of the second convolutional coding and the total metric value is less than or equal to zero, and the sum of the branch metric value of the third convolutional coding and the total metric value is greater than zero, the decoding result of the data to be decoded is one, and the total metric value is updated by the sum of the total metric value and the branch metric value of the third convolutional coding;

[0036] When neither of the above two situations is satisfied, if the number of nodes is zero or the number of nodes is greater than zero and the difference between the total metric value and the branch metric value of the first convolutional code is less than zero, then the total metric value is updated by the sum of the total metric value and the preset total metric value change; otherwise, go back to the previous node and update the total metric value by the difference between the total metric value and the branch metric value of the first convolutional code.

[0037] In a possible implementation, updating the shift data in the shift register according to the updated total metric value includes:

[0038] When the total metric value is updated by the sum of the total metric value and the branch metric value of the second convolutional code, zero is shifted rightward into the shift register, the number of nodes is incremented by one, and the number of calculations is incremented by one;

[0039] When the total metric value is updated by the sum of the total metric value and the branch metric value of the third convolutional code, one is shifted rightward into the shift register, the number of nodes is incremented by one, and the number of calculations is incremented by one;

[0040] When the total metric value is updated by the difference between the total metric value and the branch metric value of the first convolutional code, zero is shifted to the left into the shift register, the number of nodes is reduced by one, and the number of calculations is increased by one;

[0041] When the total metric value is updated by adding the total metric value to the preset total metric value change, the number of calculations is incremented by one.

[0042] According to the third aspect of the present invention, there is also provided a multi-rate convolutional code sequence decoding device, which comprises at least one processing unit and at least one storage unit, wherein the storage unit stores a computer program, and when the computer program is executed by the processing unit, the processing unit executes the steps of any one of the multi-rate convolutional code sequence decoding methods described above.

[0043] According to a fourth aspect of the present invention, there is also provided a storage medium storing a computer program executable by an access authentication device, wherein when the computer program is run on the access authentication device, the access authentication device executes the steps of any one of the multi-rate convolutional code sequence decoding methods described above.

[0044] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects compared with the prior art:

[0045] The present invention provides a multi-rate convolutional code sequence decoder, in which a data storage module can receive and store a large amount of input data, including a coding rate identification bit and data to be decoded, and provide a reliable data source for subsequent processing. The convolutional coding module selects a non-systematic code generator according to the coding rate identification bit, performs convolution processing, and generates convolutional coding, so that the system can be flexibly adjusted according to different coding rate requirements, thereby improving the efficiency of data processing. The branch metric module calculates the branch metric value according to the non-systematic code generator, the coding rate identification bit and the data to be decoded, and provides an accurate decoding basis for the parallel processing module. The parallel processing module determines the decoding result using the branch metric value and the total metric value, and updates the total metric value. This parallel processing method improves the speed and accuracy of decoding and reduces the decoding error rate. The main control module updates the shift data in the shift register according to the updated total metric value, realizes the dynamic update and optimization of the data, enables the system to be adaptively adjusted according to different decoding results and states, and improves the stability and performance of the system. By integrating data storage module, branch metric module, parallel processing module, shift register, convolutional coding module and main control module, it is able to select non-systematic code generators according to different coding rate identification bits and support complex convolutional coding and decoding algorithms. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1 A schematic diagram of the structure of an embodiment of a multi-rate convolutional code sequence decoder provided by the present invention;

[0048] Figure 2 A schematic diagram of a flow chart of an embodiment of a multi-rate convolutional code sequence decoding method provided by the present invention;

[0049] Figure 3 A schematic diagram of the structure of a multi-rate convolutional code sequence decoding device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0051] The terms "first", "second", "third", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0052] The present invention provides a multi-rate convolutional code sequence decoder and a decoding method, which are respectively described below.

[0053] See also Figure 1 , Figure 1 A schematic diagram of a structure of an embodiment of a multi-rate convolutional code sequence decoder provided by the present invention. In a specific embodiment of the present invention, a multi-rate convolutional code sequence decoder 100 is disclosed, comprising: a data storage module 110, a branch metric module 120, a parallel processing module 130, a shift register 140, a convolutional coding module 150 and a main control module 160; the main control module 160 is respectively connected to the data storage module 110, the branch metric module 120, the parallel processing module 130, the shift register 140 and the convolutional coding module 150; the parallel processing module 130 is connected to the branch metric module 120; the convolutional coding module 150 is respectively connected to the branch metric module 120 and the shift register 140;

[0054] The data storage module 110 is used to receive and store the coding rate identification bit and the data to be decoded in the input data;

[0055] The convolutional coding module 150 is used to select a non-systematic code generator according to the coding rate identification bit, and perform convolution processing on the shift data of a preset number of bits and the non-systematic code generator to obtain a convolutional code;

[0056] The branch metric module 120 is used to obtain the data to be decoded according to the non-systematic code generator, and calculate the branch metric value according to the coding rate identification bit, the data to be decoded and the convolutional coding;

[0057] The parallel processing module 130 is used to determine the decoding result of the data to be decoded according to the branch metric value and the total metric value, and update the total metric value;

[0058] The main control module 160 is used to update the shift data in the shift register 140 according to the updated total metric value;

[0059] The shift register 140 is used to store shift data.

[0060] In the above embodiment, the data storage module 110 is responsible for receiving and properly storing data input from the outside, which includes the coding rate identification bit and the data to be decoded. The coding rate identification bit is a key identifier for distinguishing different coding rates, which is crucial for the selection of non-systematic code generators in subsequent steps. The data to be decoded is the core information that needs to be decoded, and they are securely stored inside the module for quick call in subsequent processing.

[0061] The convolutional coding module 150 intelligently selects the corresponding non-systematic code generator according to the received coding rate identification bit, and then uses the shift data of a preset number of bits and the non-systematic code generator to accurately generate the convolutional code through complex convolution operations, which not only enhances the redundancy of the data and improves the anti-interference ability, but also provides important reference information for the subsequent decoding process.

[0062] The branch metric module 120 first extracts the data to be decoded from the data storage module 110 according to the non-systematic code generator, and then obtains the branch metric value through precise calculation in combination with the coding rate identification bit, the data to be decoded and the convolutional coding. The metric value provides strong support for subsequent decoding decisions.

[0063] The parallel processing module 130 makes full use of the parallel processing capabilities of modern computing technology, and can simultaneously process branch metric values ​​and total metric values ​​of multiple coding rates with different rates, and update the total metric value in real time through the branch metric values ​​and the total metric values. This parallel processing method greatly improves the decoding speed and efficiency, and ensures the real-time and accuracy of the decoding process.

[0064] The main control module 160 is responsible for coordinating the data interaction and collaborative work between the various modules. According to the updated total metric value, the shift data in the shift register 140 is dynamically adjusted to ensure that the decoder can perform adaptive adjustment and optimization according to the current decoding state and results, thereby further improving the decoding performance.

[0065] The shift register 140 is a data storage unit in the decoding process, which is responsible for storing and managing shift data. These data are continuously updated and optimized during the decoding process. Through the continuous iteration and update of the shift register 140, the decoder can gradually approach the actual decoding result and improve the accuracy and reliability of the decoding.

[0066] Compared with the prior art, the multi-rate convolutional code sequence decoder 100 provided in this embodiment, the data storage module 110 can receive and store a large amount of input data, including the coding rate identification bit and the data to be decoded, and provide a reliable data source for subsequent processing. The convolutional coding module 150 selects the non-systematic code generator according to the coding rate identification bit, and performs convolution processing to generate convolutional coding, so that the system can be flexibly adjusted according to different coding rate requirements, thereby improving the efficiency of data processing. The branch metric module 120 calculates the branch metric value according to the non-systematic code generator, the coding rate identification bit and the data to be decoded, and provides an accurate decoding basis for the parallel processing module 130. The parallel processing module 130 determines the decoding result using the branch metric value and the total metric value, and updates the total metric value. This parallel processing method improves the speed and accuracy of decoding and reduces the decoding error rate. The main control module 160 updates the shift data in the shift register 140 according to the updated total metric value, realizes the dynamic update and optimization of the data, enables the system to be adaptively adjusted according to different decoding results and states, and improves the stability and performance of the system. By integrating the data storage module 110, the branch metric module 120, the parallel processing module 130, the shift register 140, the convolutional coding module 150 and the main control module 160, it is possible to select non-systematic code generators according to different coding rate identification bits and support complex convolutional coding and decoding algorithms.

[0067] See also Figure 2 , Figure 2 The flowchart of an embodiment of the multi-rate convolutional code sequence decoding method provided by the present invention is as follows. According to the second aspect of the present invention, a multi-rate convolutional code sequence decoding method is also provided, based on the multi-rate convolutional code sequence decoder 100 as described above, comprising:

[0068] S201, receiving and storing the coding rate identification bit and the data to be decoded in the input data;

[0069] S202, selecting a non-systematic code generator according to the coding rate identification bit, and obtaining data to be decoded according to the non-systematic code generator;

[0070] S203, performing convolution processing on the shift data of a preset number of bits and a non-systematic code generator to obtain a convolution code;

[0071] S204, calculating a branch metric value according to a coding rate flag, the data to be decoded, and the convolutional coding;

[0072] S205, determining a decoding result of the data to be decoded according to the branch metric value and the total metric value, and updating the total metric value;

[0073] S206: Update the shift data in the shift register according to the updated total metric value.

[0074] In the above embodiment, the decoder first receives a data stream from the outside, which includes a coding rate identification bit and data to be decoded. The coding rate identification bit can distinguish different coding rates, which is crucial for the selection of non-systematic code generators in subsequent steps. The data to be decoded is the core information that needs to be decoded. They are securely stored in the data storage module 110 for calling and processing in subsequent steps.

[0075] The input data also includes the decoding information length, which refers to the actual length of the data sequence to be decoded. It is crucial for the decoder to correctly understand and process the input data. The decoding information length helps the decoder determine the data range that needs to be processed. After receiving the input data, the decoder will extract the corresponding length of the data to be decoded from the input data for processing based on the decoding information length. If there is no clear decoding information length, the decoder may continue to process subsequent irrelevant data in the input data, resulting in misdecoding. Therefore, the decoding information length is an important factor in ensuring decoding accuracy.

[0076] After receiving the coding rate identification bit, the decoder will select the corresponding non-systematic code generator from the preset code book according to this information. The non-systematic code generator is a key parameter in the convolutional coding and decoding process, which determines the redundancy of the coding and the accuracy of the decoding. At the same time, according to the selected non-systematic code generator, the decoder will extract the corresponding data to be decoded from the data storage module 110 to prepare for the subsequent convolution processing and branch metric calculation.

[0077] The decoder performs convolution processing based on preset shift data (these data usually come from shift register 140) and non-systematic code generators. Convolution processing is a linear operation that generates redundant convolution codes by performing specific combinations and shift operations on the data to be decoded and the non-systematic code generators. This not only enhances the data's anti-interference ability, but also provides important reference information for the subsequent decoding process.

[0078] After obtaining the convolutional code, the decoder will calculate the branch metric value based on the coding rate flag, the data to be decoded and the convolutional code. The branch metric value is an important indicator to measure the degree of match between the data to be decoded and the convolutional code. By calculating the branch metric values ​​at different coding rates, it provides a basis for subsequent decoding decisions.

[0079] After obtaining all possible branch metric values, the decoder will use the parallel processing module 130 to compare and screen these branch metric values. By comparing the branch metric values ​​and the total metric values ​​of different coding rates, the decoder can determine the decoding result of the data to be decoded and update the total metric value to reflect this result, thereby determining the accuracy and reliability of the decoding result.

[0080] After determining the decoding result of the data to be decoded and updating the total metric value, the decoder will update the shift data in the shift register 140 based on this information. The updated data will be used as the input for the next convolution processing and decoding process, thereby forming a closed-loop iterative process. By continuously updating the shift data, the decoder can gradually approach the actual decoding result and improve the accuracy and efficiency of decoding.

[0081] In some embodiments of the present invention, receiving and storing the coding rate identification bit and the data to be decoded in the input data, and then including: initializing the parameters of the multi-rate convolutional code sequence decoder 100; specifically including:

[0082] Initialize the shift register 140 to zero; initialize the number of nodes and the number of calculations stored in the main control module 160 to zero; initialize the total metric value stored in the parallel processing module 130 to zero; and set a preset total metric value change.

[0083] In the above embodiment, the length of the shift register 140 is N bits, and the shift register 140 is initialized to zero. The shift register 140 is used to store and manage the shift data in the decoding process. These data will be continuously updated during the decoding process. Initializing to zero can ensure that the decoding process starts from a clean state and avoid previous data interfering with the current decoding.

[0084] The node number Num and the calculation times T stored in the main control module 160 are initialized to zero. The node number Num indicates the number of nodes that need to be considered in the decoding process, and the calculation times T records the number of calculations performed in the decoding process. Initializing them to zero can ensure that the decoding process starts from a brand new state and accurately records each calculation and each node in the decoding process.

[0085] The total metric value Tsum stored in the parallel processing module 130 is initialized to zero. The total metric value Tsum is used to evaluate the decoding result of the data to be decoded. Initializing it to zero can ensure that the decoding process starts from a non-preferred state. By gradually calculating and comparing the metric values ​​of different paths, the decoding result of the data to be decoded is finally determined.

[0086] The total metric value change delta can be set according to actual needs, and the present invention does not impose further restrictions on this. As a preferred embodiment, the total metric value change delta in the present invention is set to 3.

[0087] In some embodiments of the present invention, selecting a non-systematic code generator according to a coding rate identification bit, and obtaining data to be decoded according to the non-systematic code generator includes:

[0088] When selecting a non-systematic code generator of a first rate according to the coding rate identification bit, obtaining a first amount of data to be decoded;

[0089] When selecting a non-systematic code generator of a second rate according to the coding rate identification bit, obtaining a second amount of data to be decoded;

[0090] When a non-systematic code generator of a third rate is selected according to the coding rate identification bit, a third amount of data to be decoded is obtained.

[0091] In the above embodiment, the first rate, the second rate, and the third rate are 1 / 2 rate, 1 / 3 rate, and 1 / 4 rate, respectively, and the first number, the second number, and the third number are 2, 3, and 4, respectively. That is, when the non-systematic code generator of 1 / 2 rate is selected, 2 data to be decoded are taken out, which are recorded as D0D1; when the non-systematic code generator of 1 / 3 rate is selected, 3 data to be decoded are taken out, which are recorded as D0D1D2; when the non-systematic code generator of 1 / 4 rate is selected, 4 data to be decoded are taken out, which are recorded as D0D1D2D3.

[0092] In some embodiments of the present invention, convolution processing is performed on shift data of a preset number of bits and a non-systematic code generator to obtain convolution coding, including:

[0093] Convolutionally processing the shifted data of a preset number of bits and the non-systematic code generator to obtain a first convolutional code;

[0094] The first value and the second value are respectively added to the left end of the shifted data of the preset number of bits and convolved with the non-systematic code generator to obtain the second convolution code and the third convolution code.

[0095] In the above embodiment, the preset number of bits can be 1-N, the first value and the second value are 0 and 1 respectively, the convolutional coding module 150 takes the 1st-Nth bit data in the shift register 140, adds 0 or 1 to the left end of the data respectively, and convolves with the non-systematic code generator to obtain two groups of convolutional codes, which are recorded as Tu0' (second convolutional code) and Tu1' (third convolutional code); the convolutional coding module 150 takes the 1st-Nth bit data in the shift register 140, and convolves with the non-systematic code generator to obtain a group of convolutional codes, which is recorded as Td' (first convolutional code); when the non-systematic code generator of 1 / 2 rate is selected, Tu0', Tu1' and Td' are all 2-bit data composed of 0 or 1, which are recorded as (Tu 00, Tu01), (Tu10, Tu11) and (Td0, Td1); when the 1 / 3 rate non-systematic code generator is selected, Tu0', Tu1' and Td' are all 3-bit data composed of 0 or 1, and are recorded as (Tu00, Tu01, Tu02), (Tu10, Tu11, Tu12) and (Td0, Td1, Td2) respectively; when the 1 / 4 rate non-systematic code generator is selected, Tu0', Tu1' and Td' are all 4-bit data composed of 0 or 1, and are recorded as (Tu00, Tu01, Tu02, Tu03), (Tu10, Tu11, Tu12, Tu13) and (Td0, Td1, Td2, Td3) respectively.

[0096] In some embodiments of the present invention, calculating a branch metric value according to a coding rate identification bit, data to be decoded, and convolution coding includes:

[0097] Calculating a first branch metric value according to a first rate, a first amount of data to be decoded, and a convolutional code;

[0098] Calculating a second branch metric value according to a second rate, a second amount of data to be decoded, and the convolutional coding;

[0099] A third branch metric value is calculated according to a third rate, a third amount of data to be decoded, and the convolutional coding.

[0100] In the above embodiment, when a non-systematic code generator of 1 / 2 rate is selected, the branch metric values ​​corresponding to Tu0', Tu1', and Td' can be respectively expressed as:

[0101] Tu0=(2×Tu00-1)×D0+(2×Tu01-1)×D1;

[0102] Tu1=(2×Tu10-1)×D0+(2×Tu11-1)×D1;

[0103] Td=(2×Td0-1)×D0+(2×Td1-1)×D1;

[0104] When a non-systematic code generator with a rate of 1 / 3 is selected, the branch metrics corresponding to Tu0', Tu1', and Td' can be expressed as:

[0105] Tu0=(3×Tu00-1)×D0+(3×Tu01-1)×D1+(3×Tu02-1)×D2;

[0106] Tu1=(3×Tu10-1)×D0+(3×Tu11-1)×D1+(3×Tu12-1)×D2;

[0107] Td=(3×Td0-1)×D0+(3×Td1-1)×D1+(3×Td2-1)×D2;

[0108] When a 1 / 4 rate non-systematic code generator is selected, the branch metrics corresponding to Tu0', Tu1', and Td' can be expressed as:

[0109] Tu0=(4×Tu00-1)×D0+(4×Tu01-1)×D1+(4×Tu02-1)×D2+(4×Tu03-1)×D3;

[0110] Tu1=(4×Tu10-1)×D0+(4×Tu11-1)×D1+(4×Tu12-1)×D2+(4×Tu13-1)×D3;

[0111] Td=(4×Td0-1)×D0+(4×Td1-1)×D1+(4×Td2-1)×D2+(4×Td3-1)×D3.

[0112] Through the above calculation, three branch metric values ​​Tu0, Tu1, and Td can be obtained.

[0113] In some embodiments of the present invention, determining a decoding result of the to-be-decoded data according to the branch metric value and the total metric value, and updating the total metric value, includes:

[0114] When the sum of the branch metric value of the second convolutional coding and the total metric value is greater than zero, the decoding result of the data to be decoded is zero, and the total metric value is updated by the sum of the total metric value and the branch metric value of the second convolutional coding;

[0115] When the sum of the branch metric value of the second convolutional coding and the total metric value is less than or equal to zero, and the sum of the branch metric value of the third convolutional coding and the total metric value is greater than zero, the decoding result of the data to be decoded is one, and the total metric value is updated by the sum of the total metric value and the branch metric value of the third convolutional coding;

[0116] When neither of the above two situations is satisfied, if the number of nodes is zero or the number of nodes is greater than zero and the difference between the total metric value and the branch metric value of the first convolutional code is less than zero, then the total metric value is updated by the sum of the total metric value and the preset total metric value change; otherwise, go back to the previous node and update the total metric value by the difference between the total metric value and the branch metric value of the first convolutional code.

[0117] In the above embodiment, when Tu0+Tsum>0, the decoding result of the data to be decoded is 0, and Tsum=Tu0+Tsum;

[0118] When Tu0+Tsum≤0 and Tu1+Tsum>0, the decoding result of the data to be decoded is 1, Tsum=Tu1+Tsum;

[0119] When both of the above situations are not satisfied, if (Num=0) or (Num>0 and Tsum-Td<0), then take Tsum=Tsum+delta; otherwise, go back to the previous node and take Tsum=Tsum-Td.

[0120] In some embodiments of the present invention, updating the shift data in the shift register 140 according to the updated total metric value includes:

[0121] When the total metric value is updated by the sum of the total metric value and the branch metric value of the second convolutional code, zero is shifted rightward into the shift register 140, the number of nodes is incremented by one, and the number of calculations is incremented by one;

[0122] When the total metric value is updated by the sum of the total metric value and the branch metric value of the third convolutional code, one is shifted rightward into the shift register 140, the number of nodes is incremented by one, and the number of calculations is incremented by one;

[0123] When the total metric value is updated by the difference between the total metric value and the branch metric value of the first convolutional code, zero is shifted leftward into the shift register 140, the number of nodes is reduced by one, and the number of calculations is increased by one;

[0124] When the total metric value is updated by adding the total metric value to the preset total metric value change, the number of calculations is incremented by one.

[0125] In the above embodiment, when Tsum=Tu0+Tsum, 0 is shifted rightward into the shift register 140; the number of nodes Num is incremented by 1, and the number of calculations T is incremented by 1;

[0126] When Tsum=Tu1+Tsum, 1 is shifted rightward into the shift register 140; the number of nodes Num is incremented by 1, and the number of calculations T is incremented by 1;

[0127] When Tsum=Tsum-Td, 0 is shifted to the left into the shift register 140; the number of nodes Num is decremented by 1, and the number of calculations T is incremented by 1;

[0128] When Tsum=Tsum+delta, the number of calculations T is incremented by 1.

[0129] Determine whether the number of nodes Num is equal to the length of the decoded information. If they are equal, the decoding is completed and the main control module 160 takes out the result in the shift register 140; otherwise, determine whether the number of calculations T is less than the set threshold value. If so, re-acquire the data to be decoded and continue decoding. Otherwise, it is considered that the decoding is unsuccessful and the main control module 160 gives a decoding overflow flag.

[0130] See also Figure 3 , Figure 3 The schematic diagram of the structure of the multi-rate convolutional code sequence decoding device provided by the embodiment of the present invention. Based on the above multi-rate convolutional code sequence decoding method, the present invention also provides a multi-rate convolutional code sequence decoding device, which can be a computing device such as a mobile terminal, a desktop computer, a notebook, a palm computer and a server. The multi-rate convolutional code sequence decoding device 300 includes a processor 310, a memory 320 and a display 330. Figure 3 Only some components of the synchronous tracking flying welding equipment for real-time measurement of battery height are shown, but it should be understood that it is not required to implement all the components shown, and more or fewer components may be implemented instead.

[0131] In some embodiments, the memory 320 may be an internal storage unit of the multi-rate convolutional code sequence decoding device 300, such as a hard disk or memory of the multi-rate convolutional code sequence decoding device 300. In other embodiments, the memory 320 may also be an external storage device of the multi-rate convolutional code sequence decoding device 300, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the multi-rate convolutional code sequence decoding device 300. Further, the memory 320 may also include both the internal storage unit of the multi-rate convolutional code sequence decoding device 300 and an external storage device. The memory 320 is used to store application software and various data installed in the multi-rate convolutional code sequence decoding device 300, such as the program code for installing the multi-rate convolutional code sequence decoding device 300. The memory 320 may also be used to temporarily store data that has been output or is to be output. In one embodiment, a multi-rate convolutional code sequence decoding program 340 is stored in the memory 320. The multi-rate convolutional code sequence decoding program 340 can be executed by the processor 310, thereby implementing the multi-rate convolutional code sequence decoding method of each embodiment of the present application.

[0132] In some embodiments, the processor 310 may be a central processing unit (CPU), a microprocessor or other data processing chip, used to run program codes stored in the memory 320 or process data, such as executing a multi-rate convolutional code sequence decoding method.

[0133] In some embodiments, the display 330 may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, an OLED (Organic Light-Emitting Diode) touch device, etc. The display 330 is used to display information on the multi-rate convolutional code sequence decoding device 300 and to display a visual user interface. The components 310-330 of the multi-rate convolutional code sequence decoding device 300 communicate with each other via a system bus.

[0134] In one embodiment, when the processor 310 executes the multi-rate convolutional code sequence decoding program 340 in the memory 320, the steps in the multi-rate convolutional code sequence decoding method described above are implemented.

[0135] This embodiment further provides a computer-readable storage medium, on which a multi-rate convolutional code sequence decoding program is stored. When the multi-rate convolutional code sequence decoding program is executed by a processor, the following steps are implemented:

[0136] Receive and store the coding rate identification bit and the data to be decoded in the input data;

[0137] Selecting a non-systematic code generator according to a coding rate identification bit, and obtaining data to be decoded according to the non-systematic code generator;

[0138] Convolution processing is performed on the shift data of a preset number of bits and a non-systematic code generator to obtain a convolution code;

[0139] Calculate branch metric values ​​according to the coding rate flag, the data to be decoded and the convolutional coding;

[0140] Determine the decoding result of the data to be decoded according to the branch metric value and the total metric value, and update the total metric value;

[0141] The shift data in the shift register 140 is updated according to the updated total metric value.

[0142] In summary, the present invention provides a multi-rate convolutional code sequence decoder 100, the data storage module 110 can receive and store a large amount of input data, including coding rate identification bits and data to be decoded, and provide a reliable data source for subsequent processing. The convolutional coding module 150 selects a non-systematic code generator according to the coding rate identification bit, and performs convolution processing to generate convolutional coding, so that the system can be flexibly adjusted according to different coding rate requirements, thereby improving the efficiency of data processing. The branch metric module 120 calculates the branch metric value according to the non-systematic code generator, the coding rate identification bit and the data to be decoded, and provides an accurate decoding basis for the parallel processing module 130. The parallel processing module 130 determines the decoding result using the branch metric value and the total metric value, and updates the total metric value. This parallel processing method improves the speed and accuracy of decoding and reduces the decoding error rate. The main control module 160 updates the shift data in the shift register 140 according to the updated total metric value, realizes dynamic update and optimization of data, enables the system to be adaptively adjusted according to different decoding results and states, and improves the stability and performance of the system. By integrating the data storage module 110, the branch metric module 120, the parallel processing module 130, the shift register 140, the convolutional coding module 150 and the main control module 160, it is possible to select non-systematic code generators according to different coding rate identification bits and support complex convolutional coding and decoding algorithms.

[0143] The present application also provides a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, the steps of the above method are implemented. The computer-readable storage medium may include, but is not limited to, any type of disk, including a floppy disk, an optical disk, a DVD, a CD-ROM, a micro drive, and a magneto-optical disk, a ROM, a RAM, an EPROM, an EEPROM, a DRAM, a VRAM, a flash memory device, a magnetic card or an optical card, a nanosystem (including a molecular memory IC), or any type of medium or device suitable for storing instructions and / or data.

[0144] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0145] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0146] In the several embodiments provided in the present application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0147] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0148] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0149] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory, including a number of instructions to enable a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned memory includes: U disk, read-only memory (ROM), random access memory (RAM), mobile hard disk, disk or optical disk and other media that can store program code.

[0150] A person of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable memory, which can include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0151] The above is only an exemplary embodiment of the present disclosure, and the scope of the present disclosure cannot be limited thereto. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the specification and practicing the disclosure here, those skilled in the art will easily think of the implementation scheme of the present disclosure. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the technical field not recorded in the present disclosure. The description and examples are regarded as exemplary only, and the scope and spirit of the present disclosure are defined by the claims.

[0152] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0153] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A multi-rate convolutional code sequence decoder, characterized in that: include: A data storage module, a branch metric module, a parallel processing module, a shift register, a convolutional coding module and a main control module; the main control module is respectively connected to the data storage module, the branch metric module, the parallel processing module, the shift register and the convolutional coding module; the parallel processing module is connected to the branch metric module; the convolutional coding module is respectively connected to the branch metric module and the shift register; Wherein, the data storage module is used to receive and store the coding rate identification bit and the data to be decoded in the input data; The convolutional coding module is used to select a non-systematic code generator according to the coding rate identification bit, and perform convolution processing on the shift data of a preset number of bits and the non-systematic code generator to obtain a convolutional code; The branch metric module is used to obtain the data to be decoded according to the non-systematic code generator, and calculate the branch metric value according to the coding rate identification bit, the data to be decoded and the convolutional coding; The parallel processing module is used to determine the decoding result of the data to be decoded according to the branch metric value and the total metric value, and update the total metric value; The main control module is used to update the shift data in the shift register according to the updated total metric value; The shift register is used to store shift data.

2. A method for decoding a multi-rate convolutional code sequence, based on the multi-rate convolutional code sequence decoder as claimed in claim 1, characterized in that: include: Receive and store the coding rate identification bit and the data to be decoded in the input data; Selecting a non-systematic code generator according to the coding rate identification bit, and obtaining data to be decoded according to the non-systematic code generator; Performing convolution processing on the shift data of a preset number of bits and the non-systematic code generator to obtain convolution coding; Calculating a branch metric value according to the coding rate identification bit, the data to be decoded and the convolutional coding; Determine a decoding result of the data to be decoded according to the branch metric value and the total metric value, and update the total metric value; The shift data in the shift register is updated according to the updated total metric value.

3. The method for decoding a multi-rate convolutional code sequence as claimed in claim 2, wherein: The receiving and storing of the coding rate identification bit and the data to be decoded in the input data, then includes: initializing the parameters of the multi-rate convolutional code sequence decoder; specifically including: Initialize the shift register to zero; initialize the number of nodes and the number of calculations stored in the main control module to zero; initialize the total metric value stored in the parallel processing module to zero; and set a preset total metric value change.

4. The method for decoding a multi-rate convolutional code sequence as claimed in claim 3, wherein: The selecting a non-systematic code generator according to the coding rate identification bit, and obtaining to-be-decoded data according to the non-systematic code generator, comprises: When selecting a non-systematic code generator of a first rate according to the coding rate identification bit, obtaining a first amount of data to be decoded; When selecting a non-systematic code generator of a second rate according to the coding rate identification bit, obtaining a second amount of data to be decoded; When a non-systematic code generator of a third rate is selected according to the coding rate identification bit, a third amount of data to be decoded is obtained.

5. The method for decoding a multi-rate convolutional code sequence as claimed in claim 4, wherein: The convolution processing is performed on the shift data of the preset number of bits and the non-systematic code generator to obtain the convolution coding, including: Convolutionally processing the shifted data of a preset number of bits and the non-systematic code generator to obtain a first convolutional code; The first value and the second value are respectively added to the left end of the shifted data of the preset number of bits, and are convolved with the non-systematic code generator to obtain the second convolution code and the third convolution code.

6. The method for decoding a multi-rate convolutional code sequence as claimed in claim 5, wherein: The calculating the branch metric value according to the coding rate identification bit, the data to be decoded and the convolutional coding includes: Calculating a first branch metric value according to the first rate, the first amount of data to be decoded, and the convolutional coding; Calculating a second branch metric value according to the second rate, the second amount of data to be decoded, and the convolutional coding; A third branch metric value is calculated according to the third rate, the third amount of data to be decoded, and the convolutional coding.

7. The method for decoding a multi-rate convolutional code sequence as claimed in claim 5, wherein: Determining a decoding result of the to-be-decoded data according to the branch metric value and the total metric value, and updating the total metric value, including: When the sum of the branch metric value of the second convolutional coding and the total metric value is greater than zero, the decoding result of the to-be-decoded data is zero, and the total metric value is updated by the sum of the total metric value and the branch metric value of the second convolutional coding; When the sum of the branch metric value and the total metric value of the second convolutional coding is less than or equal to zero, and the sum of the branch metric value and the total metric value of the third convolutional coding is greater than zero, the decoding result of the data to be decoded is one, and the total metric value is updated by the sum of the total metric value and the branch metric value of the third convolutional coding; When neither of the above two situations is satisfied, if the number of nodes is zero or the number of nodes is greater than zero and the difference between the total metric value and the branch metric value of the first convolutional code is less than zero, then the total metric value is updated by the sum of the total metric value and the preset total metric value change; otherwise, go back to the previous node and update the total metric value by the difference between the total metric value and the branch metric value of the first convolutional code.

8. The method for decoding a multi-rate convolutional code sequence as claimed in claim 7, wherein: The updating of the shift data in the shift register according to the updated total metric value comprises: When the total metric value is updated by the sum of the total metric value and the branch metric value of the second convolutional code, zero is shifted rightward into the shift register, the number of nodes is incremented by one, and the number of calculations is incremented by one; When the total metric value is updated by the sum of the total metric value and the branch metric value of the third convolutional code, one is shifted rightward into the shift register, the number of nodes is incremented by one, and the number of calculations is incremented by one; When updating the total metric value by the difference between the total metric value and the branch metric value of the first convolutional code, zero is shifted leftward into the shift register, the number of nodes is reduced by one, and the number of calculations is increased by one; When the total metric value is updated by the sum of the total metric value and the preset total metric value change, the number of calculations is increased by one.

9. A multi-rate convolutional code sequence decoding device, characterized in that: It comprises at least one processing unit and at least one storage unit, wherein the storage unit stores a computer program, and when the computer program is executed by the processing unit, the processing unit executes the steps of the multi-rate convolutional code sequence decoding method according to any one of claims 2 to 8.

10. A storage medium, characterized in that: It stores a computer program executable by an access authentication device. When the computer program runs on the access authentication device, the access authentication device executes the steps of the multi-rate convolutional code sequence decoding method according to any one of claims 2 to 8.

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