Soft start power-on circuit and NFC device
The soft startup circuit in NFC devices addresses current shocks by gradually increasing the output current of LDO circuits, enhancing the power-up process and reducing electrical stress.
Patent Information
- Application Number
- CN202411713433.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-27
- Publication Date
- 2025-03-18
AI Technical Summary
In NFC devices, the difference in reference voltages and large load transients between two LDO circuits can cause significant current shocks to the load capacitance and LDO circuits during the power-up process.
A soft startup circuit is introduced, comprising a bias voltage source, buffer circuit, LDO circuit, and RC circuit, with a soft startup control mechanism that gradually increases the reference voltage or output current from zero to a target value, reducing current shocks by controlling the LDO circuit's output current.
The soft startup circuit effectively minimizes current shocks to the LDO circuits during power-up by gradually increasing the output current, ensuring a smoother power-up process and reducing electrical stress on the LDO circuits.
Smart Images
Figure CN119653340A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of near field communication, for example, to a soft start power-on circuit and an NFC device. Background Art
[0002] At present, with the continuous development of wireless communication technology, Near Field Communication (NFC) has become a new focus of attention. In smart electronic devices, NFC technology has been widely used. The internal power supply of NFC devices needs to support a larger load and a larger input voltage range in high power consumption mode; while in low power consumption mode, the LDO (Low Dropout Regulator) itself consumes less power and needs to support a smaller load, so the input voltage range is small.
[0003] In the related art, two LDO circuits are provided in the power supply system of the NFC device, and the outputs of the two LDO circuits are connected. When the system is powered on, the enables of the two LDO circuits are turned on at the same time, and they jointly participate in establishing the output voltage.
[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:
[0005] When the reference voltages of the two LDO circuits are different and the load jump of the output voltage is large, it will cause greater interference to the load capacitance and produce a large current impact on the LDO circuit.
[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.
[0008] The embodiments of the present disclosure provide a soft-start power-on circuit and an NFC device to reduce the current impact on the LDO circuit during the power-on process.
[0009] In some embodiments, the soft start power-on circuit includes: a bandgap reference voltage source, configured to generate a bandgap reference voltage; a buffer circuit, configured to generate a reference voltage based on the bandgap reference voltage; an LDO circuit, configured to generate an output current based on the reference voltage and an input voltage; an RC circuit, configured to generate an output voltage based on the output current; a soft start circuit, arranged in the buffer circuit, configured to perform soft start control on the buffer circuit so that the reference voltage increases linearly from zero to a target voltage value; or, arranged in the LDO circuit, configured to perform soft start control on the LDO circuit so that the output current increases linearly from zero to a target current value.
[0010] Optionally, the reference voltage includes a first reference voltage and a second reference voltage; the LDO circuit includes: a first LDO circuit, configured to generate a first output current based on the first reference voltage and the first input voltage; a second LDO circuit, configured to generate a second output current based on the second reference voltage and the second input voltage; the first output current and the second output current are connected in parallel to the output end of the LDO circuit to form an output current.
[0011] Optionally, the first LDO circuit includes a first power tube, and the first output current is the current flowing through the first power tube; the second LDO circuit includes a second power tube, and the second output current is the current flowing through the second power tube.
[0012] Optionally, when the soft start circuit is set in the LDO circuit, the soft start circuit includes: a first soft start circuit, set in the first LDO circuit, configured to perform soft start control on the first LDO circuit, so that the first output current increases linearly from zero to a first target current value; a second soft start circuit, set in the second LDO circuit, configured to perform soft start control on the second LDO circuit, so that the second output current increases linearly from zero to a second target current value.
[0013] Optionally, the soft start circuit includes: a start circuit, an amplifier circuit, and an output drive circuit; the start circuit is configured to output a linearly increasing start signal according to a first control signal, and output a power supply voltage when the start signal reaches a threshold voltage; the amplifier circuit is configured to control the output signal of the output drive circuit according to the start signal and the bias voltage; the bias voltage is controlled by the second control signal; the first control signal is a delay signal of the second control signal; and the control output drive circuit is configured to output a voltage signal that linearly increases from zero to a preset voltage value under the control of the amplifier circuit.
[0014] Optionally, the startup circuit includes: a first current source, a first switch tube, a second switch tube, a third switch tube, a first capacitor, and a voltage detection circuit; the first current source is connected to a power supply; the output end of the first current source is connected to the first end of the first switch tube; the second end of the first switch tube is connected to the first end of the second switch tube, the first end of the first capacitor, and the first end of the third switch tube, and serves as the output end of the startup circuit; the second end of the second switch tube and the second end of the first capacitor are grounded; the second end of the third switch tube is connected to the power supply; the voltage detection circuit is used to detect the capacitor voltage of the first capacitor and control the third switch tube according to the detection signal; the first control signal is used to control the first switch tube and the second switch tube; when the circuit is enabled, the first control signal controls the first switch tube to close and the second switch tube to open, the first current source charges the first capacitor and outputs the capacitor voltage; the voltage detection circuit detects the capacitor voltage, and when the capacitor voltage is lower than the threshold voltage, the third switch tube is opened, and when the capacitor voltage is higher than or equal to the threshold voltage, the third switch tube is closed to pull the capacitor voltage up to the power supply voltage.
[0015] Optionally, the amplifier circuit includes: a second current source, a first PMOS tube, a second PMOS tube, a third PMOS tube, a second capacitor, and a load; the second current source is connected to the power supply; the output end of the second current source is connected to the source of the first PMOS tube, the source of the second PMOS tube, and the source of the third PMOS tube; the gate of the first PMOS tube is connected to the output end of the startup circuit; the gate of the second PMOS tube is connected to the first end of the second capacitor and to the bias voltage; the second end of the second capacitor is grounded; the gate of the third PMOS tube serves as the output end of the amplifier circuit; the drain of the first PMOS tube, the drain of the second PMOS tube, and the drain of the third PMOS tube are all connected to the load.
[0016] Optionally, the output drive circuit includes: a fourth switch tube, a third power tube, a first resistor, and a second resistor; the first end of the fourth switch tube is connected to the power supply, and the second end is connected to the gate of the third power tube; the source of the third power tube is connected to the power supply; the drain of the third power tube is connected to the first end of the first resistor and serves as the output end of the output drive circuit; the second end of the first resistor is connected to the first end of the second resistor and is connected to the output end of the amplifier circuit; the second end of the second resistor is grounded; the fourth switch tube is controlled by the first control signal.
[0017] Optionally, the RC circuit includes: a third capacitor and a third resistor; the first end of the third capacitor and the first end of the third resistor are both connected to the output end of the LDO circuit and serve as the output end of the soft start power-on circuit; the second end of the third capacitor and the second end of the third resistor are both grounded.
[0018] In some embodiments, the NFC device includes a soft start power-up circuit as described above.
[0019] The soft start power-on circuit and NFC device provided in the embodiments of the present disclosure can achieve the following technical effects:
[0020] In the disclosed embodiment, the soft start power-on circuit includes a bandgap reference voltage source, a buffer circuit, an LDO circuit, an RC circuit and a soft start circuit. In different embodiments, the soft start circuit can be arranged in the buffer circuit or the LDO circuit, and is configured to perform soft start control on the buffer circuit or the LDO circuit. When the soft start circuit is arranged in the buffer circuit, the soft start circuit can adjust the reference circuit output by the buffer circuit so that the reference voltage can achieve a soft start from zero linearly increased to the target voltage value. Since the reference voltage is gradually increased, the reference voltage acts on the LDO circuit, and the output current generated is also gradually increased, thereby reducing the current impact on the LDO circuit during the power-on process. If the soft start circuit is arranged in the LDO circuit, the output current of the LDO circuit can be directly adjusted so that the output current can achieve a soft start from zero linearly increased to the target current value, and the output current is also gradually increased, which can also reduce the current impact on the LDO circuit during the power-on process. Therefore, according to different needs, the soft start circuit can be arranged in the buffer circuit or the LDO circuit to control the output current of the LDO circuit to gradually increase, thereby reducing the current impact on the LDO circuit during the power-on process.
[0021] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:
[0023] Figure 1 It is a circuit framework schematic diagram of a soft start power-on circuit provided by an embodiment of the present disclosure;
[0024] Figure 2 It is a circuit framework schematic diagram of another soft start power-on circuit provided by an embodiment of the present disclosure;
[0025] Figure 3 is a circuit diagram of a soft start power-on circuit provided by an embodiment of the present disclosure;
[0026] Figure 4 is a circuit diagram of another soft start power-on circuit provided by an embodiment of the present disclosure;
[0027] Figure 5 is a circuit diagram of a soft start circuit in a soft start power-on circuit provided by an embodiment of the present disclosure;
[0028] Figure 6 is a timing diagram of various signals in a soft start power-on circuit provided by an embodiment of the present disclosure;
[0029] Figure 7 This is a timing diagram of various signals in another soft start power-on circuit provided by an embodiment of the present disclosure. DETAILED DESCRIPTION
[0030] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.
[0031] The terms "first", "second", etc. in the technical solutions described in this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the disclosed embodiments described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.
[0032] Unless otherwise stated, the term "plurality" means two or more.
[0033] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.
[0034] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.
[0035] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.
[0036] Combination Figure 1 and Figure 2 As shown, an embodiment of the present disclosure provides a soft start power-on circuit, including: a bandgap reference voltage source 10 , a buffer circuit 20 , an LDO circuit 30 , an RC circuit 40 , and a soft start circuit 50 .
[0037] The bandgap reference voltage source 10 is configured to generate a bandgap reference voltage VREF. The buffer circuit 20 is configured to generate a reference voltage VREF_X according to the bandgap reference voltage VREF. The LDO circuit 30 is configured to generate an output current I_SS according to the reference voltage VREF_X and an input voltage. The RC circuit 40 is configured to generate an output voltage VOUT according to the output current I_SS. The soft start circuit 50 is provided in the buffer circuit 20 and is configured to perform soft start control on the buffer circuit 20 so that the reference voltage VREF_X increases linearly from zero to a target voltage value; or, it is provided in the LDO circuit 30 and is configured to perform soft start control on the LDO circuit 30 so that the output current I_SS increases linearly from zero to a target current value.
[0038] In the embodiment of the present disclosure, the soft start circuit 50 can be arranged in the buffer circuit 20 or the LDO circuit 30, and is configured to perform soft start control on the buffer circuit 20 or the LDO circuit 30. When the soft start circuit 50 is arranged in the buffer circuit 20, the soft start circuit 50 can adjust the reference voltage output by the buffer circuit 20, so that the reference voltage VREF_X can achieve soft start from zero linear increase to the target voltage value. Since the reference voltage VREF_X is gradually increased, the reference voltage VREF_X acts on the LDO circuit 30, and the output current I_SS generated is also gradually increased, thereby reducing the current impact on the LDO circuit 30 during the power-on process. If the soft start circuit 50 is arranged in the LDO circuit 30, the output current I_SS of the LDO circuit 30 can be directly adjusted, so that the output current I_SS can achieve soft start from zero linear increase to the target current value, and the output current I_SS is also gradually increased, which can also reduce the current impact on the LDO circuit 30 during the power-on process. Therefore, according to different requirements, the soft start circuit 50 can be set in the buffer circuit 20 or the LDO circuit 30 to control the output current I_SS of the LDO circuit 30 to gradually increase, thereby reducing the current impact on the LDO circuit 30 during the power-on process.
[0039] Optionally, combined Figure 3 and Figure 4 As shown, the reference voltage VREF_X includes a first reference voltage VREF_LP and a second reference voltage VREF_HP; the LDO circuit 30 includes: a first LDO circuit 31, configured to generate a first output current according to the first reference voltage VREF_LP and the first input voltage; a second LDO circuit 32, configured to generate a second output current according to the second reference voltage VREF_HP and the second input voltage; the first output current and the second output current are connected in parallel to the output end of the LDO circuit 30 to form an output current I_SS.
[0040] In this embodiment, according to different actual conditions, one or more different LDO circuits can be set in the soft start power-on circuit, and the output ends of all LDO circuits are connected in parallel to obtain an output current I_SS of one or more current addition. The embodiment of the present disclosure illustrates the soft start power-on circuit with two different LDO circuits. Among them, the first LDO circuit 31 is in low power consumption mode, and the second LDO circuit 32 is in high power consumption mode. Therefore, the voltage range of the second input voltage [0, VIN1+VIN2] is greater than the voltage range of the first input voltage [0, VIN1]. When the system is powered on, the first LDO circuit 31 and the second LDO circuit 32 are enabled at the same time, and jointly participate in the establishment of the output voltage VOUT. After the output voltage VOUT is established, the switches of the first LDO circuit 31 and the second LDO circuit 32 are controlled according to system needs, or the second input voltage of the second LDO circuit 32 is controlled through the switch tube S0.
[0041] Optionally, the first LDO circuit 31 includes a first power tube, and the first output current is the current flowing through the first power tube; the second LDO circuit 32 includes a second power tube, and the second output current is the current flowing through the second power tube.
[0042] In this embodiment, the first LDO circuit 31 and the second LDO circuit 32 are respectively provided with a first power tube and a second power tube. Therefore, it is necessary to control the current flowing through the first power tube and the second power tube to be within a safe current range.
[0043] Combination Figure 3As shown, in the case where the soft start circuit 50 is arranged in the buffer circuit 20, after the bandgap reference voltage source 10 generates the bandgap reference voltage VREF, the first soft start reference voltage VREF_SS_LP and the second soft start reference voltage VREF_SS_HP are generated through the buffer circuit 20. The first soft start reference voltage VREF_SS_LP and the second soft start reference voltage VREF_SS_HP are respectively increased linearly from zero to the target voltage value, and the voltage rise time of the two soft start reference voltages is the same, and the rise speed is proportional to the target voltage value of the reference voltage. The first soft start reference voltage VREF_SS_LP and the second soft start reference voltage VREF_SS_HP are respectively used as the reference voltage VREF_X of the first LDO circuit 31 and the second LDO circuit 32, and the first output current and the second output current are generated through the first power tube and the second power tube. Since the reference voltage VREF_X of the first LDO circuit 31 and the second LDO circuit 32 is linearly increased, the first output current and the second output current are also linearly increased. By adjusting the boost speed of the first soft start reference voltage VREF_SS_LP and the second soft start reference voltage VREF_SS_HP, it can be ensured that the current flowing through the first power tube and the second power tube is within the safe current range. Through the internal power consumption configuration, the buffer circuit 20 can work in different power consumption modes. The soft start circuit 50 is set in the buffer circuit 20, and the entire soft start power-on circuit only needs to set up an additional soft start circuit 50, and the circuit area is smaller.
[0044] Optionally, combined Figure 4 As shown, when the soft start circuit 50 is arranged in the LDO circuit 30, the soft start circuit 50 includes: a first soft start circuit 51, which is arranged in the first LDO circuit 31 and is configured to perform soft start control on the first LDO circuit 31, so that the first output current increases linearly from zero to a first target current value; a second soft start circuit 52, which is arranged in the second LDO circuit 32 and is configured to perform soft start control on the second LDO circuit 32, so that the second output current increases linearly from zero to a second target current value.
[0045] In this embodiment, when the first soft start circuit 51 and the second soft start circuit 52 are respectively arranged in the first LDO circuit 31 and the second LDO circuit 32, after the bandgap reference voltage source 10 generates the bandgap reference voltage VREF, the first reference voltage VREF_LP and the second reference voltage VREF_HP are generated through the buffer circuit 20. The first reference voltage VREF_LP and the second reference voltage VREF_HP are respectively used as reference voltages for the first LDO circuit 31 and the second LDO circuit 32, and the first output current and the second output current are generated through the first power tube and the second power tube. Through the soft start control logic in the first LDO circuit 31 and the second LDO circuit 32, the voltage on the first power tube and the second power tube can be linearly increased from zero. Therefore, the first output current and the second output current flowing through the first power tube and the second power tube also rise linearly. By adjusting the voltage boost speed of the voltage on the first power tube and the second power tube, it can be ensured that the current flowing through the first power tube and the second power tube is within the safe current range. The first soft start circuit 51 and the second soft start circuit 52 are respectively arranged in the first LDO circuit 31 and the second LDO circuit 32, so as to control the current flowing through the first power tube and the second power tube respectively, thereby flexibly controlling the rising speed of the current.
[0046] Optionally, combined Figure 5 As shown, the soft start circuit 50 includes: a start circuit 60, an amplifier circuit 70, and an output drive circuit 80. The start circuit 60 is configured to output a linearly increasing start signal SS according to a first control signal EN_D, and output a power supply voltage when the start signal SS reaches a threshold voltage. The amplifier circuit 70 is configured to control the output signal of the output drive circuit 80 according to the start signal SS and the bias voltage BV; the bias voltage BV is controlled by the second control signal EN; the first control signal EN_D is a delayed signal of the second control signal EN. The control output drive circuit 80 is configured to output a voltage signal that increases linearly from zero to a preset voltage value under the control of the amplifier circuit 70.
[0047] In this embodiment, the start-up circuit 60 can generate a linearly changing start-up signal SS, and after the start-up signal SS reaches the threshold voltage, the start-up signal SS is pulled up to the power supply voltage. When the start-up signal SS does not reach the threshold voltage, the amplifier circuit 70 controls the output drive circuit 80 to output a voltage signal that increases linearly from zero; when the start-up signal SS reaches the threshold voltage, the amplifier circuit 70 controls the output drive circuit 80 to output a voltage signal that stops rising.
[0048] Optionally, combined Figure 5As shown, the startup circuit 60 includes: a first current source I1, a first switch tube S1, a second switch tube S2, a third switch tube S3, a first capacitor C1, and a voltage detection circuit VT; the first current source I1 is connected to a power supply; the output end of the first current source I1 is connected to a first end of the first switch tube S1; the second end of the first switch tube S1 is connected to a first end of the second switch tube S2, a first end of the first capacitor C1, and a first end of the third switch tube S3, and serves as an output end of the startup circuit 60; the second end of the second switch tube S2 and the second end of the first capacitor C1 are grounded; the second end of the third switch tube S3 is connected to the power supply; the voltage detection circuit V T is used to detect the capacitor voltage of the first capacitor C1, and control the third switch tube S3 according to the detection signal; the first control signal EN_D is used to control the first switch tube S1 and the second switch tube S2; when the circuit is enabled, the first control signal EN_D controls the first switch tube S1 to be closed, the second switch tube S2 to be opened, the first current source I1 charges the first capacitor C1, and outputs the capacitor voltage; the voltage detection circuit VT detects the capacitor voltage, when the capacitor voltage is lower than the threshold voltage, the third switch tube S3 is opened, when the capacitor voltage is higher than or equal to the threshold voltage, the third switch tube S3 is closed, and the capacitor voltage is pulled up to the power supply voltage.
[0049] In this embodiment, the capacitor voltage of the first capacitor C1 is the start signal SS output by the start circuit 60, and therefore, the rising speed of the start signal SS is determined by the first current source I1 and the first capacitor C1. By adjusting the parameters of the first current source I1 and the first capacitor C1, the rising speed of the start signal SS can be adjusted, thereby adjusting the rising speed of the voltage signal output by the output drive circuit 80. In addition, when the circuit is closed, the first switch tube S1 is turned on, and the second switch tube S2 is closed, and the first capacitor C1 can be discharged through the second switch tube S2 to ensure that the initial voltage of the first capacitor C1 is 0V.
[0050] Optionally, combined Figure 5 As shown, the amplifier circuit 70 includes: a second current source I2, a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a second capacitor C2, and a load L; the second current source I2 is connected to the power supply; the output end of the second current source I2 is connected to the source of the first PMOS transistor PM1, the source of the second PMOS transistor PM2, and the source of the third PMOS transistor PM3; the gate of the first PMOS transistor PM1 is connected to the output end of the startup circuit 60; the gate of the second PMOS transistor PM2 is connected to the first end of the second capacitor C2 and is connected to the bias voltage BV; the second end of the second capacitor C2 is grounded; the gate of the third PMOS transistor PM3 serves as the output end of the amplifier circuit 70; the drain of the first PMOS transistor PM1, the drain of the second PMOS transistor PM2, and the drain of the third PMOS transistor PM3 are all connected to the load L.
[0051] Optionally, combined Figure 5 As shown, the output drive circuit 80 includes: a fourth switch tube S4, a third power tube Mp, a first resistor R1, and a second resistor R2; the first end of the fourth switch tube S4 is connected to the power supply, and the second end is connected to the gate of the third power tube Mp; the source of the third power tube Mp is connected to the power supply; the drain of the third power tube Mp is connected to the first end of the first resistor R1 and serves as the output end of the output drive circuit 80; the second end of the first resistor R1 is connected to the first end of the second resistor R2, and is connected to the output end of the amplifier circuit; the second end of the second resistor R2 is grounded; the fourth switch tube S4 is controlled by the first control signal EN_D.
[0052] In this embodiment, when the circuit is enabled, the second control signal EN controls the bias voltage BV to rise rapidly, and controls the bias voltage BV to be the voltage value when the circuit is working stably. After delaying the second control signal EN, the first control signal EN_D is obtained. The first control signal EN_D controls the start circuit 60 to output the start signal SS, so that the start signal SS gradually rises, and at the same time, the first signal controls the fourth switch tube S4 to close. When the start signal SS is just output, the start signal SS is less than the bias signal, and the gate-source voltage of the first PMOS tube PM1 is greater than the gate-source voltage of the second PMOS tube PM2, so the second PMOS tube PM2 is disconnected, and the first PMOS tube PM1 and the third PMOS tube PM3 form a differential pair tube. At this time, the output OUT of the output drive circuit 80 follows the start signal SS to increase. With the increase of the start signal SS, when the start signal SS rises to the same level as the bias voltage BV, a current appears in the second PMOS tube PM2, and the differential pair tube formed by the first PMOS tube PM1 and the third PMOS tube PM3 is no longer matched, and the output OUT of the output drive circuit 80 The boost speed is slower than the start signal SS. When the start signal SS is boosted to the threshold voltage, it is pulled up to the power supply voltage, and the first PMOS tube PM1 is turned off. At this time, the second PMOS tube PM2 and the third PMOS tube PM3 form a differential pair tube, and the soft start process ends. The output OUT of the output drive circuit 80 follows the bias voltage BV and remains unchanged. In addition, the second control signal EN is used to control the bias voltage BV of the amplifier circuit 70. The first control signal EN_D is a delayed signal of the second control signal EN, which is used to control the start circuit 60 and the output drive circuit 80. Through the delay between the first control signal EN_D and the second control signal EN, the start circuit 60 and the output drive circuit 80 can be released after the bias of the amplifier circuit 70 is established. In this way, it can be prevented that when the circuit starts to power on and the bias of the amplifier circuit 70 is established, the gate voltage of the third power tube Mp is out of control, causing a large current to appear in the third power tube Mp. When the start signal SS is pulled up to the power supply voltage, the source voltage of the PMOS tube will have burrs due to the influence of parasitic capacitance. The burrs are eliminated by setting the second capacitor C2 at the input end of the bias voltage BV.
[0053] Optionally, combined Figure 3 and Figure 4 As shown, the RC circuit 40 includes: a third capacitor C3 and a third resistor R3; the first end of the third capacitor C3 and the first end of the third resistor R3 are both connected to the output end of the LDO circuit 30 and serve as the output end of the soft start power-on circuit; the second end of the third capacitor C3 and the second end of the third resistor R3 are both grounded.
[0054] The soft start power-on circuit provided in the embodiment of the present disclosure can realize two different soft start power-on schemes by setting the soft start circuit 50 in different circuits. Figure 3 and Figure 6 As shown, when the soft start circuit 50 is set in the buffer circuit 20, the second control signal EN is used as the circuit enable signal. After the second control signal EN is enabled, the bandgap reference voltage source 10 generates the bandgap reference voltage VREF, and at the same time, a bias is established in the amplifier circuit 70. After a delay, the first control signal EN_D is enabled, and the start circuit 60 and the output drive circuit 80 start to work, thereby outputting a gradually rising first soft start reference voltage VREF_SS_LP and a second soft start reference voltage VREF_SS_HP in the buffer circuit 20. The two reference voltages act on the first LDO circuit 31 and the second LDO circuit 32 respectively, and finally obtain a gradually rising output voltage VOUT. Combined with Figure 4 and Figure 7 As shown, when the soft start circuit 50 is provided in the LDO circuit 30, after the second control signal EN is enabled, the bandgap reference voltage source 10 generates the bandgap reference voltage VREF, and simultaneously generates the first reference voltage VREF_LP and the second reference voltage VREF_HP through the buffer circuit 20. After a delay, the first control signal EN_D is enabled, and the start-up circuit 60 and the output drive circuit 80 start to work, thereby obtaining a gradually rising output voltage VOUT in the first LDO circuit 31 and the second LDO circuit 32.
[0055] An embodiment of the present disclosure further provides an NFC device, including the soft start power-on circuit as described above.
[0056] The above description and accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent possible changes only. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the technical solutions recorded in this application. As used in the technical solutions recorded in this application, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.
Claims
1. A soft start power-on circuit, characterized in that: include: a bandgap reference voltage source configured to generate a bandgap reference voltage; a buffer circuit configured to generate a reference voltage based on a bandgap reference voltage; The LDO circuit is configured to generate an output current according to a reference voltage and an input voltage; an RC circuit configured to generate an output voltage according to the output current; A soft start circuit is provided in the buffer circuit and is configured to perform soft start control on the buffer circuit so that the reference voltage increases linearly from zero to a target voltage value; Or, it is set in the LDO circuit and configured to perform soft-start control on the LDO circuit so that the output current increases linearly from zero to a target current value.
2. The soft start power-on circuit according to claim 1, characterized in that: The reference voltage includes a first reference voltage and a second reference voltage; and the LDO circuit includes: A first LDO circuit is configured to generate a first output current according to a first reference voltage and a first input voltage; The second LDO circuit is configured to generate a second output current according to a second reference voltage and a second input voltage; the first output current and the second output current are connected in parallel to the output end of the LDO circuit to form an output current.
3. The soft start power-on circuit according to claim 2, characterized in that: The first LDO circuit includes a first power tube, and the first output current is a current flowing through the first power tube; The second LDO circuit includes a second power tube, and the second output current is the current flowing through the second power tube.
4. The soft start power-on circuit according to claim 2, characterized in that: When the soft start circuit is provided in the LDO circuit, the soft start circuit includes: A first soft start circuit is provided in the first LDO circuit and is configured to perform soft start control on the first LDO circuit so that the first output current increases linearly from zero to a first target current value; The second soft start circuit is provided in the second LDO circuit and is configured to perform soft start control on the second LDO circuit so that the second output current increases linearly from zero to a second target current value.
5. The soft start power-on circuit according to claim 1, characterized in that: The soft start circuit includes: a start circuit, an amplifier circuit, and an output drive circuit; The startup circuit is configured to output a linearly increasing startup signal according to the first control signal, and output a power supply voltage when the startup signal reaches a threshold voltage; The amplifier circuit is configured to control the output signal of the output driving circuit according to the start signal and the bias voltage; the bias voltage is controlled by the second control signal; the first control signal is a delayed signal of the second control signal; The control output drive circuit is configured to output a voltage signal that increases linearly from zero to a preset voltage value under the control of the amplifier circuit.
6. The soft start power-on circuit according to claim 5, characterized in that: The startup circuit includes: a first current source, a first switch tube, a second switch tube, a third switch tube, a first capacitor, and a voltage detection circuit; The first current source is connected to the power supply; the output end of the first current source is connected to the first end of the first switch tube; the second end of the first switch tube is connected to the first end of the second switch tube, the first end of the first capacitor, and the first end of the third switch tube, and serves as the output end of the startup circuit; the second end of the second switch tube and the second end of the first capacitor are grounded; the second end of the third switch tube is connected to the power supply; the voltage detection circuit is used to detect the capacitor voltage of the first capacitor, and control the third switch tube according to the detection signal; the first control signal is used to control the first switch tube and the second switch tube; When the circuit is enabled, the first control signal controls the first switch tube to close, the second switch tube to open, the first current source charges the first capacitor, and outputs the capacitor voltage; the voltage detection circuit detects the capacitor voltage, and when the capacitor voltage is lower than the threshold voltage, the third switch tube is opened, and when the capacitor voltage is higher than or equal to the threshold voltage, the third switch tube is closed to pull the capacitor voltage up to the power supply voltage.
7. The soft start power-on circuit according to claim 5, characterized in that: The amplifier circuit includes: a second current source, a first PMOS tube, a second PMOS tube, a third PMOS tube, a second capacitor, and a load; The second current source is connected to the power supply; the output end of the second current source is connected to the source of the first PMOS tube, the source of the second PMOS tube, and the source of the third PMOS tube; the gate of the first PMOS tube is connected to the output end of the startup circuit; the gate of the second PMOS tube is connected to the first end of the second capacitor and is connected to the bias voltage; the second end of the second capacitor is grounded; the gate of the third PMOS tube serves as the output end of the amplifier circuit; the drain of the first PMOS tube, the drain of the second PMOS tube, and the drain of the third PMOS tube are all connected to the load.
8. The soft start power-on circuit according to claim 5, characterized in that: The output drive circuit includes: a fourth switch tube, a third power tube, a first resistor, and a second resistor; The first end of the fourth switch tube is connected to the power supply, and the second end is connected to the gate of the third power tube; the source of the third power tube is connected to the power supply; the drain of the third power tube is connected to the first end of the first resistor and serves as the output end of the output drive circuit; the second end of the first resistor is connected to the first end of the second resistor and connected to the output end of the amplifier circuit; the second end of the second resistor is grounded; the fourth switch tube is controlled by the first control signal.
9. The soft start power-on circuit according to any one of claims 1 to 8, characterized in that: The RC circuit includes: a third capacitor and a third resistor; The first end of the third capacitor and the first end of the third resistor are both connected to the output end of the LDO circuit and serve as the output end of the soft start power-on circuit; the second end of the third capacitor and the second end of the third resistor are both grounded.
10. An NFC device, characterized in that: The invention comprises a soft start power-on circuit as claimed in any one of claims 1 to 9.