Conductive backside layer for mitigating warpage

Abstract

A method for holding a semiconductor wafer clamped to an electrostatic chuck is provided. A semiconductor wafer may have a conductive backside layer deposited on the backside of the wafer by backside deposition. The conductive layer can increase an electrostatic force between the wafer and the electrostatic chuck and counteract an internal stress that the wafer may have due to front-side processing, thereby maintaining the wafer substantially flat.

Description

Incorporated by Reference

[0001] The PCT application form is filed concurrently with this specification as a part of this application. Each application identified in the concurrently filed PCT application form to which this application claims the benefit or priority is incorporated herein by reference in its entirety and for all purposes. Background Art

[0002] During semiconductor processing operations, a semiconductor wafer is typically supported on a susceptor within a processing chamber. The semiconductor wafer may be held in position relative to the susceptor using a "chuck," which is a device that augments gravity with some other type of clamping force that increases the friction load between the wafer and the susceptor / chuck to prevent relative motion between the wafer and the susceptor / chuck. One type of chuck used in such operations is an "electrostatic chuck," or ESC. This article discusses improvements related to the clamping force between a semiconductor wafer and an ESC.

[0003] The background description provided here is for the purpose of generally presenting the context of the present disclosure. The work of the presently designated inventors is neither explicitly nor implicitly admitted to be prior art against the present disclosure to the extent that it is described in this background section and to aspects of the specification that could not be determined as prior art at the time of filing the application. Summary of the invention

[0004] Certain aspects of the present disclosure relate to a method for processing a semiconductor substrate during the manufacture of an electronic device. The method is characterized by the following operations: (a) depositing one or more front layers on the semiconductor substrate, the front layers having a front internal stress that, if not compensated, would cause the semiconductor substrate to warp; and (b) depositing one or more back layers on the semiconductor substrate, the back layers having a back internal stress that counteracts the front internal stress of the one or more front layers and reduces or eliminates the warp, wherein the one or more back layers have a sheet resistance equal to or less than about 5000 ohm / sq.

[0005] In some embodiments, the method further comprises an operation (c) of clamping the semiconductor substrate having the one or more backside layers by an electrostatic chuck. This method may further comprise an operation (d) of etching the semiconductor substrate while clamping the semiconductor substrate to the electrostatic chuck. In some embodiments, operations (a), (b) and (c) (and optionally (d)) are each performed in a different chamber.

[0006] In certain embodiments, the one or more front side layers include a hard mask.

[0007] In some embodiments, the thickness of the one or more back layers is about 1 μm to about 10 μm. In some embodiments, the sheet resistance of one of the one or more back layers is about 150 ohm / sq to about 300 ohm / sq. In some embodiments, at least one of the one or more back layers includes doped polysilicon. Examples of dopants in the doped polysilicon include phosphorus, carbon, boron, tungsten, nitrogen, or any combination of two or more thereof. In some embodiments, the back internal stress of the one or more back layers is about -300 MPa to about 300 MPa.

[0008] In some embodiments, the operation of depositing one or more backside layers includes depositing a first backside layer and a second backside layer, wherein the second backside layer is disposed closer to the outside of the semiconductor substrate than the first backside layer. In such embodiments, the sheet resistance of the first backside layer is lower than the sheet resistance of the second backside layer.

[0009] In some embodiments, the operation of depositing one or more backside layers includes exposing the semiconductor substrate to a process gas including a silicon precursor and a dopant precursor. In some cases, the method further includes an operation of annealing the semiconductor substrate at a temperature of about 700° C. to about 900° C. to convert the deposited doped silicon layer into a doped polysilicon layer.

[0010] Certain aspects of the present disclosure relate to a semiconductor substrate or an electronic device characterized by the following features: (a) one or more front layers having a front internal stress that, if not compensated, would cause the semiconductor substrate or the electronic device to warp; and (b) one or more back layers having a back internal stress that offsets the front internal stress of the one or more front layers and reduces or eliminates the warping, wherein the sheet resistance of the one or more back layers is equal to or less than about 5000 ohm / sq.

[0011] In certain embodiments, the thickness of the one or more back layers is about 1 μm to about 10 μm. In certain embodiments, the sheet resistance of the one or more back layers is about 500 ohm / sq or less. In certain embodiments, the sheet resistance of the one or more back layers is about 150 ohm / sq to about 300 ohm / sq.

[0012] In some embodiments, at least one of the one or more back layers comprises doped polysilicon. For example, the doped polysilicon is doped with a dopant comprising phosphorus, carbon, boron, tungsten, nitrogen, or any combination of two or more thereof.

[0013] In certain embodiments, the backside internal stress of the one or more backside layers is from about -300 MPa to about 300 MPa.

[0014] In some embodiments, the one or more back side layers include a first back side layer and a second back side layer, wherein the second back side layer is disposed closer to the outside of the semiconductor substrate than the first back side layer, and the sheet resistance of the first back side layer is lower than the sheet resistance of the second back side layer.

[0015] Certain aspects of the present disclosure relate to a method for processing a semiconductor substrate during the manufacture of an electronic device. The method is characterized by the following operations: (a) receiving a warp-compensated semiconductor substrate; (b) clamping the warp-compensated semiconductor substrate by an electrostatic chuck; and (c) patterning the warp-compensated semiconductor substrate. The warp-compensated semiconductor substrate includes: (i) one or more front layers, the front layers having a front internal stress that, if not compensated, would cause the semiconductor substrate or the electronic device to warp, and (ii) one or more back layers, the back layers having a back internal stress that offsets the front internal stress of the one or more front layers and reduces or eliminates the warp, wherein the sheet resistance of the one or more back layers is equal to or less than 5000 ohm / sq.

[0016] In certain embodiments, the method further comprises the operation of (d) etching the warp-compensated semiconductor substrate while it is clamped to the electrostatic chuck.

[0017] In certain embodiments, the thickness of the one or more back layers is from about 1 μm to about 10 μm. In certain embodiments, the sheet resistance of one of the one or more back layers is about 500 ohm / sq or less. In certain embodiments, the sheet resistance of one of the one or more back layers is from about 150 ohm / sq to about 300 ohm / sq.

[0018] In some embodiments, at least one of the one or more back layers comprises doped polysilicon. Examples of the dopant include phosphorus, carbon, boron, tungsten, nitrogen, or any combination of two or more thereof. In some embodiments, the back internal stress of the one or more back layers is about -300 MPa to about 300 MPa.

[0019] In some embodiments, the one or more back side layers include a first back side layer and a second back side layer, wherein the second back side layer is arranged closer to the outside of the semiconductor substrate than the first back side layer, and the sheet resistance of the first back side layer is lower than the sheet resistance of the second back side layer.

[0020] Certain aspects of the present disclosure relate to an apparatus comprising: (a) a processing chamber; (b) a substrate support; (c) a showerhead; (d) a gas source fluidly connected to the showerhead; and (e) a controller configured to: (i) receive a semiconductor substrate having a front layer, the front layer having a front internal stress that, if not compensated, would cause warping of the semiconductor substrate; and (ii) deposit one or more back layers on the semiconductor substrate, the back layers having a back internal stress that offsets the front internal stress of the one or more front layers and reduces or eliminates the warping, wherein the one or more back layers have a sheet resistance equal to or less than about 5000 ohm / sq.

[0021] The controller may also be configured to cause one or more of the operations described herein for the method aspects of the present disclosure.

[0022] These and other features of the present disclosure are described in further detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1A and 1B Examples of non-warped and warped semiconductor wafers on an electrostatic chuck are shown.

[0024] Figure 2 An example cross section of a semiconductor wafer is shown with an example front side layer and an example back side layer.

[0025] Figure 3 An example cross section of a semiconductor wafer on an electrostatic chuck is shown.

[0026] Figure 4A and 4B An example of a semiconductor wafer having an example front side layer and one or more example back side layers is shown.

[0027] Figure 5A and 5B An example cross section of a semiconductor wafer on an electrostatic chuck is shown.

[0028] Figure 6 is a process flow diagram illustrating certain operations in a method for depositing.

[0029] Fig. 7A and 7B is a graph showing the results of thin film properties after the annealing operation.

[0030] Figure 8 is a process flow diagram illustrating certain operations in semiconductor wafer processing.

[0031] Fig.9A-E is a schematic diagram of an example cross-section of a semiconductor wafer during semiconductor processing according to various embodiments.

[0032] Fig.10 is a process flow diagram that illustrates certain operations in semiconductor wafer processing.

[0033] Fig.11A -G is a schematic diagram of an example cross-section of a semiconductor wafer during semiconductor processing according to various embodiments.

[0034] Fig. 12A and 12B A block diagram of an example substrate processing system is shown.

[0035] Fig.13A An example cross section of a showerhead-base edge is shown.

[0036] Fig. 13B A top view of an example carrier ring is shown.

[0037] Fig.14 A schematic diagram of an example processing system that may be used to perform the methods described herein is shown. DETAILED DESCRIPTION the term

[0038] The following terms are used throughout this manual:

[0039] The terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially fabricated integrated circuit" may be used interchangeably. One of ordinary skill in the art understands that the term "partially fabricated integrated circuit" may refer to a semiconductor wafer at any of the many stages of integrated circuit fabrication performed thereon. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, 300 mm, or 450 mm. Examples of semiconductor substrate materials include silicon (Si), gallium arsenide (GaAs), and silicon germanium (SiGe). In addition to semiconductor wafers, other workpieces that may utilize the disclosed embodiments include various items such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, display devices or components, such as backplanes for pixelated display devices, flat panel displays, micromechanical devices, and the like. The workpiece may have a variety of shapes, sizes, and materials.

[0040] As used herein, "semiconductor device manufacturing operations" are operations performed during the manufacture of semiconductor devices. Typically, the entire manufacturing process includes multiple semiconductor device manufacturing operations, each of which is performed in its own semiconductor manufacturing tool (e.g., plasma reactor, plating tank, chemical mechanical planarization tool, wet etching tool, etc.). Categories of semiconductor device manufacturing operations include subtractive processes, such as etching processes and planarization processes, and material addition processes, such as deposition processes (e.g., physical vapor deposition, chemical vapor deposition, atomic layer deposition, electrochemical deposition, electroless deposition). In the context of etching processes, substrate etching processes include processes that etch mask layers, or more generally, processes that etch any layer of material previously deposited on the substrate surface and / or otherwise residing on the substrate surface. Such etching processes can etch stacked layers in the substrate.

[0041] "Fabrication equipment" refers to equipment in which fabrication processes are performed. Fabrication equipment typically has a processing chamber in which a workpiece resides during processing. Typically, when in use, fabrication equipment performs one or more semiconductor device fabrication operations. Examples of fabrication equipment used for semiconductor device fabrication include deposition reactors, such as plating tanks, physical vapor deposition reactors, chemical vapor deposition reactors, and atomic layer deposition reactors, and subtractive processing reactors, such as dry etch reactors (e.g., chemical and / or physical etch reactors), wet etch reactors, and ashers.

[0042] As used herein, "electrostatic chuck" (ESC) refers to a chuck to which a wafer is clamped using electrostatic force during processing. An ESC can use one or more electrodes. A voltage can be applied to each of the one or more electrodes. The applied voltage can cause a current to flow, thereby causing charge migration through a dielectric layer between the chuck and the wafer or substrate being processed. Therefore, the opposite charge accumulated at the electrode relative to the wafer causes the wafer to be clamped or clamped to the chuck by electrostatic force. In some cases, the electrode can be integrated into the ESC or can be separated from the ESC. In some embodiments, an ESC can refer to an electrode that generates an electrostatic force.

[0043] As used herein, "platen" refers to the top surface of the ESC on which the wafer being fabricated is located. There may be a gap between the wafer and the platen surface (eg, upper surface), which gap is generally referred to herein as "d".

[0044] As used herein, "base" may refer to a structure or housing that supports or includes the platen.

[0045] As used herein, "wafer warpage" may refer to deformation of a wafer. The deformation may have radial and / or azimuthal components. Examples of types of wafer warpage include dome-shaped, dish-shaped, and potato chip-shaped. Wafer warpage may occur during manufacturing, for example, due to stress applied to the wafer during deposition of material on the active surface of the wafer substrate. Wafer warpage may occur during various types of manufacturing, such as when a large amount of stack material is deposited. Wafer warpage may complicate subsequent processing steps. For example, if the amount of warpage is too large, the wafer may not be properly clamped. In addition, if certain processing steps (e.g., photolithography) are performed on an overly warped wafer, undesirable results may result.

[0046] Wafer warpage can be measured as the deviation of the average or median distance of the wafer surface from a reference plane. The point of the wafer median surface can be the center point (e.g., in the case of concave or dome warpage), or the edge point of the wafer and / or the average edge point of the wafer (e.g., in the case of warp or convex warpage).

[0047] As used herein, "wafer unclamping" refers to a state in which a wafer is no longer clamped to a platen of an electrostatic chuck (ESC). As used herein, a wafer may be considered to have been unclamped from an ESC when wafer warpage is detected during the manufacture or processing of the wafer or when wafer warpage exceeding a threshold amount is detected. It should be noted that wafer warpage, as used herein, may be associated with a numerical value indicating the degree of warpage. In contrast, wafer unclamping may be a binary classification indicating whether a wafer is clamped to a platen. Electrostatic chuck

[0048] An electrostatic chuck (ESC) may be used to hold a wafer in place within a semiconductor processing chamber via the electrostatic chuck. Figure 1A A semiconductor substrate 102 is shown on an ESC 104. Some ESCs hold a wafer, which may be electrostatically charged due to processing operations, in place by applying a single direct current ("DC") voltage to one or more clamping electrodes within the ESC so that the clamping electrodes and the wafer act as all or part of a capacitive circuit. In some embodiments, such as some monopolar ESCs, the capacitive circuit is completed by the presence of a plasma within the chamber. The clamping electrodes are typically planar structures that are parallel to the entire plane of the wafer and typically extend across an area commensurate with the size of the wafer. The electrostatic forces generated due to the capacitive effect provide the clamping force.

[0049] Some ESCs can be clamped even in the absence of plasma, such as in a chamber where a plasma environment is not generated during processing. In such an implementation, plasma cannot be relied upon to complete the capacitive circuit, and the ESC electrodes can instead include one or more cathodes and one or more anodes. The anode and cathode can occupy different areas of the ESC facing the wafer, for example, anodes and cathodes occupying opposing semicircular areas below the wafer, or anodes or cathodes arranged as a central circular electrode and concentric outer electrodes (in the case where the wafer is used as an anode). The anode and cathode in such an ESC are electrically isolated from each other within the ESC, but when the wafer is placed on the ESC, the wafer completes two capacitive circuits - one capacitive circuit is the anode where the wafer is the ESC cathode, and one capacitive circuit is the cathode where the wafer is the ESC anode. Such ESC designs may be referred to as bipolar (in the case of one anode and one cathode) or multipolar (in the case of three or more electrodes).

[0050] The ESC may have a dielectric layer or other insulator interposed between the clamping electrode and the wafer; the dielectric layer or insulating layer is used to prevent short circuits between the clamping electrode and the other half of the capacitive circuit (i.e., the wafer) and to define a gap that controls the capacitive characteristics of the capacitive circuit formed by the ESC and the wafer. In some embodiments, the ESC has a pit or minimum contact area (MCA) that supports the wafer but leaves a significant gap between the wafer and the electrostatic chuck over most of the surface area of ​​the wafer. The gap may serve at least in part as a dielectric for the capacitor.

[0051] Other common features of ESCs include gas distribution holes and lifting holes, depending on the specific needs of semiconductor processing. Gas distribution holes can be used to flow a thermally conductive inert gas (such as helium) into the gap between the wafer and the ESC during processing. Since the wafer is clamped to the ESC by electrostatic force, the surface of the ESC is usually not completely flat, because it may be necessary to reduce the actual contact amount of the wafer with the ESC. For example, the top surface of the ESC may have one or more thin concentric raised rings and one or more thin raised radial spokes that actually contact the wafer, but the gaps between these raised rings and spokes may not contact the wafer. During processing in a vacuum or near-vacuum environment, this may cause heat concentration flowing through the wafer area that is actually in contact with the ESC, resulting in non-uniformity in the wafer. To prevent this, a thermally conductive inert gas can be flowed into these gaps to provide a distributed heat conduction path, thereby reducing the heat flow concentration through the physical contact area. Even in a flat-top ESC designed without raised / recessed areas, the physical contact between the wafer and the ESC may be intermittent at the microscopic level, so even in these cases, the introduction of a thermally conductive gas between the wafer and the ESC may be beneficial for heat conduction. The thermally conductive gas may also provide an additional layer of protection against process gases - if the thermally conductive gas flows into the gap between the wafer and the ESC during processing, it will flow toward the edge of the wafer to escape, which may prevent the process gas from reaching the bottom surface of the wafer and the portion of the ESC below the wafer, thereby protecting these areas from unwanted etching or deposition, as the case may be. Lift holes may be provided to allow lift pins to extend through the ESC and lift the wafer from the ESC. The ESC lift pins may be configured to fully retract into the ESC lift pin holes so that one ESC lift pin does not extend beyond the position of the ESC. In particular, these lift pins and their corresponding holes allow a robotic end effector or other mechanical device to place a wafer on and / or remove a wafer from the ESC without contacting and / or interfering with the ESC. Warped wafer

[0052] Semiconductor device manufacturing typically involves depositing a stack of layers on a wafer substrate. Typically, most deposition and other processing to form the device occurs on one side of the substrate, often referred to as the front or front side of the wafer. As the deposited layers accumulate, they introduce stresses into the wafer. Large net compressive or tensile stresses can cause the wafer to warp, which is undesirable.

[0053] Warping is particularly prone to occur when a large amount of stack material is deposited, such as in 3D-NAND devices. Figure 1BA warped semiconductor substrate 102 is shown placed on an ESC 104. When the warp is severe, it can have adverse effects on subsequent processing steps. For example, if the warp is too great, the wafer may not be properly clamped. In addition, certain processing steps, such as photolithography, are very precise and can produce poor results if the wafer is not substantially flat. The problem may manifest as defocusing of the photolithography.

[0054] One example stack that may cause these problems is a stack with alternating oxide and nitride layers (e.g., silicon oxide / silicon nitride / silicon oxide / silicon nitride, etc.). Another example stack that may cause warpage includes alternating oxide and polysilicon layers (e.g., silicon oxide / polysilicon / silicon oxide / polysilicon, etc.). Other examples of stack materials that may be problematic include, but are not limited to, tungsten and titanium nitride.

[0055] The materials in the stack may be deposited by chemical vapor deposition (CVD) techniques, such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), or by direct metal deposition (DMD), etc. These examples are not intended to be limiting. Certain disclosed embodiments may be useful when wafer stress and / or warpage is introduced due to the presence of materials on the front side of the wafer.

[0056] Various techniques have been devised to combat warpage. When warpage is moderate, electrostatic clamping can overcome warpage by flattening an otherwise warped wafer while clamping. When warpage is more severe, the deposition process can be adjusted to reduce or counteract internal stresses in the deposited layers. However, any such adjustments should not interfere with the process requirements of the manufacturing equipment. One common technique used to counteract warpage is to deposit a film on the back side of the wafer.

[0057] Backside deposition can form highly stressed dielectric films. Figure 2 is a cross-sectional view of a wafer 202 having a front side layer 208 and a back side layer 210. If the back side layer 210 has an internal stress that is opposite and comparable in magnitude to the internal stress generated on the front side, the back side film can effectively counteract and correct the warpage.

[0058] A typical scenario might involve the following: 1. Deposition of one or more front-side layers with high internal stress resulting in significant warping (chamber A). 2. Deposit a backside layer with internal stress that counteracts the internal stress of one or more frontside layers and reduces or eliminates warpage (Chamber B). 3. Patterning the front side of the non-warped substrate by photolithography. 4. Etch the non-warped patterned substrate (Chamber C). Each of chambers A, B, and C may be different, but this is not always the case. For example, in some embodiments, chambers A and C are the same.

[0059] Examples of high stress backside films currently in use include the following: amorphous silicon, silicon oxide, silicon nitride, and silicon oxynitride. Current backside films have high internal stress and are able to relieve the stress applied to the wafer from the front side layer to reduce or eliminate wafer warpage. Typically, the backside layer is made of a dielectric film with high stress and very high resistivity.

[0060] Until recently, backside film thicknesses have remained relatively thin (e.g., <2 um). Therefore, downstream processes at prior technology nodes generally do not encounter the problems addressed by the embodiments herein. However, modern IC manufacturing techniques can produce substrates with frontside layers that have much higher internal stress than prior nodes. One manufacturing technique that leads to this problem is the use of thick hard mask layers in operations where the etch selectivity between the hard mask and the etched material is limited, but deep trenches or vias are still etched.

[0061] Due to the higher internal stresses, certain problems arise. These problems include: (i) partial / complete de-clamping due to a significant reduction in clamping force due to the thick dielectric film, and / or (ii) partial / complete de-clamping due to a significant increase in warpage due to the significantly thicker front side. To address this issue, the clamping force can be increased by increasing the ESC clamping voltage. However, increasing the ESC clamping voltage is limited to a strict control window. If the voltage is too low, the ESC clamping force is too low, resulting in wafer slippage and / or de-clamping. If the voltage is too high, punch-through damage will occur on the back side of the wafer, damaging the wafer. Alternatively, the contact area can be increased by increasing the number of pits and / or increasing the surface area of ​​the pits. However, an ESC with an increased contact surface can increase the clamping force, but the risk of the wafer slipping on the ESC is significantly increased due to air trapped between the back side of the wafer and the ESC pressure plate.

[0062] Therefore, some technologies require the backside film thickness to be approximately 4 times that of the previous node (e.g., ~7-8 um). Figure 2 , the overall warpage of the wafer increases significantly due to, for example, the thicker front layer 208, so the back layer 210 increases significantly to compensate for the overall warpage. Although the overall warpage problem can be solved by a thicker back layer 210, a problem begins to appear that does not exist when using a thinner back film.

[0063] Processing using a high stress dielectric film on the back side of the wafer creates a charge vacancy layer between the back side of the wafer and the pedestal due to the insulating properties of the dielectric layer. Thicker dielectric films result in a larger charge vacancy layer, which reduces the clamping force generated between the wafer and the ESC.

[0064] Figure 3 304. The back layer 310 on the wafer 302 is located on a pressure plate 312 of the ESC 304. In the embodiment shown, the pressure plate 312 has dimples 314 to prevent air pockets from being created when the wafer 302 is placed on the ESC 304. As described above, the ESC secures the wafer by electrostatic charge. The pressure plate 312 of the ESC 304 and the wafer 302 each act as a charged plate in a capacitor. In the embodiment shown, the pressure plate 312 is positively charged and the wafer 302 is negatively charged. The electrostatic clamping force between the wafer 302 and the ESC 304 can be expressed by the following equation, Therefore, the electrostatic clamping force between the wafers is a function of the distance between the positively charged platen 312 and the negatively charged wafer 302. As the distance increases, the electrostatic clamping force decreases exponentially. Figure 3 In the example of FIG. 3 , the distance between the two charged plates includes the air gap (g) between the back layer 310 and the pressure plate 312 plus the back layer thickness (d). As the dielectric back layer 310 becomes thicker, the separation distance between the charged plates (i.e., the surface of the pressure plate 312 and the conductive surface of the wafer 302) increases, thereby reducing the electrostatic clamping force between the two.

[0065] Due to the thick dielectric backside film, downstream processing utilizing electrostatic clamping may suffer from partial or complete ESC clamping failure due to weakened clamping force between the susceptor and the wafer backside. In addition, thick dielectric films on the wafer backside may cause clamping failure due to trapped charge, which cannot dissipate in the dielectric film. Conductive layer

[0066] Disclosed herein are methods, systems, and techniques for maintaining wafer clamping on an ESC and reducing wafer warpage, even for wafers with relatively high internal stresses. Specifically, the wafer may have a conductive backside layer. The conductive backside layer may reduce the gap between the charged plate surface of the ESC and the charged surface connected to the wafer substrate, thereby increasing the electrostatic clamping force between the wafer and the ESC. In certain embodiments, the conductive backside layer is used together with an insulating backside layer.

[0067] Figure 4A4 shows a wafer 402 having a front layer 408 and a conductive back layer 410. As described above, due to modern IC manufacturing techniques, the front layer 408 may have a higher internal stress than previous manufacturing nodes. Therefore, the conductive back layer 410 typically has a correspondingly higher internal stress. By creating a conductive back layer 410 with a corresponding internal stress, the back layer can reduce and / or eliminate any wafer warpage caused by the internal stress generated by the front layer 408. In some cases, the front layer 408 has an internal stress of about -1000 MPa to 1000 MPa. If not compensated, the warpage of the wafer 402 may be about 200 μm to 1 mm. Wafers with warpage greater than about 150 μm or greater than about 200 μm may cause problems in subsequent manufacturing steps. For example, a wafer with warpage greater than 150 μm may not be properly clamped to the ESC. Many process steps (such as photolithography) require high precision, and wafers that are not completely flat will produce poor results due to focus variations and other optical problems.

[0068] In many embodiments, the internal stress of the conductive back layer matches or approximately matches the internal stress of one or more front layers. Thus, in some embodiments, the internal stress of the conductive back layer 410 is about -1000 MPa to 1000 MPa.

[0069] The conductive backside layer increases the clamping force between the wafer and the ESC because it reduces the effective distance between the conductive portion of the wafer and the ESC. Figure 5A A cross section of how charges are located on an ESC 504 is shown in the case where a wafer 502 has a conductive back layer 510. The ESC 504 has a pressure plate 512 with a dimple 514. The dimple 514 is in contact with the conductive back layer 510. In the illustrated embodiment, the pressure plate 512 and the conductive back layer 510 of the ESC 504 each act as a charged plate in a capacitor. The pressure plate 512 is a positively charged plate and the conductive back layer 510 is a negatively charged plate. The distance between the positively charged pressure plate 512 and the negatively charged surface of the conductive back layer 510 is the air gap (g) caused by the dimple. By reducing the distance between the positively charged pressure plate 512 and the charged surface connected to the wafer 502 (i.e., the conductive back layer 510), the electrostatic clamping force remains relatively strong. By having a conductive back layer 510, the thickness of the conductive back layer 510 is a minimal concern for keeping the wafer 502 clamped to the ESC 504. In some embodiments, the thickness of the back conductive layer 410 can be about 1 μm to 10 μm, for example, about 1.5 μm to 3 μm, about 3 μm to 6 μm, or about 6 μm to 9 μm.

[0070] Figure 5B Various embodiments are shown with a conductive back layer 510. As described below, the conductive back layer 510 may not be a perfectly conductive material. , α represents the conductivity of the conductive back layer 510, d represents the thickness of the back layer, and g represents the gap between the bottom of the back layer and the pressure plate 512. When the conductive back layer 510 is not highly insulating, some negative charges 524 will remain on the wafer 502, close to the back surface 520 of the wafer 502, and some negative charges will move to the conductive back layer 510. As the conductivity of the conductive layer increases, a higher percentage of negative charges 524 will leave the wafer 502 and move to the conductive back layer 510, toward the ESC 504, and close to the positively charged pressure plate 512, thereby reducing the distance between the charges. In the case where the conductive back layer 510 is highly conductive, α tends to 0, and the negative charges are concentrated on the conductive back layer 510. When the conductive back layer 510 is highly conductive, the distance between the two charged plates is the air gap (g) between the pressure plate 512 and the back layer 510. In the case where the conductive back layer 510 is highly insulating, α tends to 1, and negative charges are retained on the back surface 520 of the main part of the wafer 502. As the thickness of the back layer increases, the electrostatic clamping force between the wafer 502 and the ESC 504 weakens, as shown in FIG. Figure 3 The distance between the two charged plates is the distance (d+g) between the back surface 520 of the wafer 502 and the pressure plate 512. In practice, α is between 0 and 1, depending on the conductivity of the conductive back layer 510. In order to ensure sufficient electrostatic clamping force to fix the wafer 502 to the ESC 504, a higher conductive back layer with low resistance is required.

[0071] The conductive back layer can be made of various materials. In some embodiments, it is made of a doped polysilicon film. Examples of doped polysilicon films include doped polysilicon films. The dopant can be a p-dopant or an n-dopant. Examples of dopants include carbon, boron, tungsten, phosphorus, nitrogen, arsenic, and any combination of two or more thereof. For example, the conductive back layer can be a phosphorus-doped polysilicon film.

[0072] The conductive back film thickness may have a wafer-wide (WiW) non-uniformity of about 15% or less. In some embodiments, the WiW non-uniformity is about 7% or less. In yet other embodiments, the WiW non-uniformity is about 3% or less. In some embodiments, the conductive back layer has a sheet resistance of about 1000 ohm / sq or less. In some other embodiments, the conductive back layer has a sheet resistance of about 500 ohm / sq or less. In some embodiments, the conductive back layer has a sheet resistance of about 250 ohm / sq or less. In one example, the conductive back layer has a sheet resistance of about 150 ohm / sq to about 300 ohm / sq.

[0073] According to the application, in some embodiments, the wafer can have a homogenous back layer, for example, it includes a single material. In some embodiments, the back layer can be heterogeneous, for example, with a variety of materials. In some cases, a variety of materials can form a plurality of layers, each layer having a composition. In some embodiments, a plurality of layers include a first back layer, which is adjacent to the base semiconductor substrate or closer to the base semiconductor substrate than the second back layer. In other words, the second back layer is closer to the outside of the complete semiconductor substrate than the first back layer. In such an embodiment, the first back layer can be more conductive (or have a lower sheet resistance) than the second back layer.

[0074] Figure 4A A wafer 402 is shown with a homogenous backside layer 410. The wafer 402 has a single backside layer made of a highly conductive material (e.g., doped amorphous silicon). In some embodiments, the backside layer 410 is made of multiple sub-layers. The sub-layers can be made of a single material (e.g., a highly conductive material), or they can be made of different materials or have different compositions.

[0075] Figure 4B A wafer 402 having a heterogeneous backside layer 415 made of two or more materials is shown. In the example shown, the heterogeneous backside layer 415 has two backside sublayers, a first backside layer 416 and a second backside layer 418, the second backside layer 418 being closer to the outside of the semiconductor substrate than the first backside layer. The first backside layer 416 may have one or more highly conductive material (e.g., doped polysilicon) sublayers in contact with or very close to the bottom surface 420 of the wafer 402, while the second backside layer 418 may have one or more less conductive or dielectric material sublayers on the back side of the substrate. In some embodiments, the backside may have three or more layers, which may be optionally made of different materials. In certain embodiments, when the wafer 402 has a heterogeneous backside, the most conductive layer may be located closest to the wafer 402. In some embodiments, the backside layer may be in direct contact with the backside surface of the wafer 402. In some embodiments (not shown), a thin layer of silicon dioxide (USG) or another dielectric material may be located between the first backside layer 416 and the surface of the wafer 402. Figure 4A and Figure 4B The front layer 408 in FIG. 4 is depicted as a single layer. It should be understood that the front layer 408 can be a single layer or a multi-layer stack. Backside deposition process

[0076] Figure 66 is a process flow diagram showing an example method for depositing a conductive layer on the back side of a semiconductor wafer. Method 600 first exposes the back side of a semiconductor wafer to one or more precursors of a conductive back side film in operation 610. The exposure is performed in a manner that a conductive film is deposited on the back side of the wafer. In certain embodiments, the deposited film is doped amorphous silicon, and the precursor includes a silicon precursor and a dopant precursor. The remainder of the process flow describes amorphous silicon involving doping, but other conductive materials may be used. In various embodiments, the deposition process is similar to the process conventionally used to deposit an insulating back side film, except that the process gas includes a precursor for a conductive film. Examples of deposition processes for forming a back side layer include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), epitaxial growth, and plasma enhanced versions of any of these processes. The dopant precursor may be present in the process gas at a concentration of about 0.1 to 99% (volume percentage) (or about 0.1 to 20%) of the concentration of the silicon precursor. Examples of dopant precursors include phosphine (PH3), propylene (C3H6), diborane (B2H6), tungsten hexafluoride (WF6), and ammonia (NH3). In some embodiments, the dopant precursor can be a combination of two or more thereof. Examples of silicon precursors include silane (SiH4) and its variants (Si x H y ), such as disilane or trisilane.

[0077] After the film is deposited, the wafer may be annealed in operation 620. For example, the deposited silicon film may be annealed to convert the silicon from an amorphous state to a polycrystalline state. The annealing may be performed at a temperature of about 550° C. to 950° C., for example, about 700° C. to 900° C. The annealing may be performed for a time of about 15 to 60 minutes. The annealing may be performed under an inert gas. The annealing process of the film on the back side of the semiconductor wafer reduces the resistance of the film, thereby making the layer conductive, for example, having a sheet resistance of about 5000 ohm / sq or less. In some embodiments, the annealing process may reduce the sheet resistance to about 500 ohm / sq or less. In some embodiments, the annealing process may reduce the sheet resistance to about 250 ohm / sq or less. The sheet resistance may be about 150 ohm / sq to 300 ohm / sq. Annealing may also improve the uniformity of the film, so that the intra-wafer non-uniformity of the film is about 15% or less. In some embodiments, the annealing process can reduce the stress of the backside layer such that the internal stress is about 500 MPa to 500 MPa.

[0078] Fig. 7A shows the sheet resistance, Figure 7B It shows that using Figure 6 Internal stress in the backside film deposited by the described operation. Fig. 7AAn example of the relationship between the sheet resistance and dopant concentration of an amorphous silicon film after annealing is shown. The film can be tuned by adjusting the amount of dopant in the process gas and the temperature at which the film is annealed. The graph shows the sheet resistance of films annealed at two different temperatures; the red line represents a film annealed at a higher temperature than the film represented by the blue line. The sheet resistance of each film annealed at each temperature is compared to the amount of dopant used in the film. In both films, the resistance of each film decreases as the dopant is introduced. A certain concentration of dopant allows the film to reach its minimum resistance. As the amount of dopant introduced into the film continues to increase, the resistance of the film may begin to increase, as shown in Figure 1. Fig. 7A As shown in each figure.

[0079] Figure 7B The stress of the film annealed at a lower temperature was compared with the dopant level. As shown, the internal stress of the film peaks at a specific dopant level. As more dopant is introduced into the film, the internal stress within the film decreases. At higher dopant levels, the internal stress may decrease. The amount of dopant introduced into the film can be varied depending on the internal stress required in the back film to offset the internal stress of the front layer. Overall process sequence

[0080] In general, the overall process using the backside film of the present disclosure first forms a warp compensation substrate with a backside film, and then electrostatically clamps the warp compensation substrate during subsequent operations. Examples of subsequent operations include photolithography, etching, planarization, further deposition, etc. Example etching processes include plasma etching, reactive ion etching, chemical etching, atomic layer etching, etc. Examples of further deposition operations include CVD (thermal and / or plasma enhanced), ALD, and epitaxial growth.

[0081] Figure 8 A first example process for processing a semiconductor wafer is shown. Figure 8Start by depositing one or more front layers on a semiconductor wafer in operation 810. The front layer can be deposited by using ALD, plasma enhanced ALD, CVD, plasma enhanced CVD, PVD or epitaxial growth. ALD is a surface mediated deposition technique in which the doses of precursors and reactants are sequentially introduced into a first chamber. In an exemplary CVD process, the precursor and the reducing agent are in the gas phase together in the first chamber. The plasma enhanced process can be used to fill features and / or increase the deposition rate at a lower temperature. The deposited front layer can be a single layer or a multilayer. The front layer on the semiconductor wafer may have internal stress, which may cause the semiconductor wafer to warp if it is not compensated. In some embodiments, the internal stress of the deposited front layer may be about -1000MPa to about 1000MPa. In some embodiments, the internal stress of the deposited front layer is about -450MPa to about 450MPa, for example, about -300MPA to about 300MPa.

[0082] After depositing one or more front layers on the semiconductor wafer, one or more back layers are deposited on the semiconductor wafer in operation 820. Figure 6The back layer is deposited using the process flow described in 810. The back layer can be deposited using ALD, plasma enhanced ALD, CVD, plasma enhanced CVD or epitaxial growth. The deposition can be performed in a second chamber designed for deposition on the back side of the wafer. At least one of the one or more back layers deposited is a conductive layer. The conductive layer can be, for example, doped polysilicon. It can be doped with dopants described elsewhere herein. As described above, the conductive layer can have a sheet resistance of about 5000 ohm / sq or less, such as a sheet resistance of about 1000 ohm / sq or less, about 500 ohm / sq or less. In some embodiments, the conductive layer can have a sheet resistance of about 150 ohm / sq to about 300 ohm / sq. One or more back layers can generate internal stress. In some embodiments, the internal stress generated can offset the internal stress generated by the front layer deposited in 810. In these embodiments, the stress from the front layer causes the semiconductor wafer to warp. The back layer of deposition can produce internal stress, which offsets the stress caused by the front side and reduces and / or eliminates the wafer warpage caused by the stress from the front layer, so that the wafer remains substantially flat. In some embodiments, the back layer of deposition can have an internal tensile stress of about -1000MPa to about 1000MPa, such as an internal tensile stress of about -450MPa to -450MPa, about -300MPa to about 300MPa. As described above, the back side can be a single layer or can be a multilayer. In some embodiments, the back side is homogeneous. In some embodiments, the back side layer can be heterogeneous. In these embodiments, the first sublayer can have a lower sheet resistance than the second sublayer. In some embodiments, the first sublayer is located between the second sublayer and the wafer substrate. In some embodiments, the second sublayer is located between the first sublayer and the wafer substrate. In homogeneous and heterogeneous embodiments, at least a portion of the back layer is conductive.

[0083] In operation 830, after depositing the backside layer, the front side of the non-warped wafer is patterned by, for example, photolithography. The front side may include a target layer and a hard mask. The hard mask may be patterned during the photolithography step to protect selective areas of the front side layer during a subsequent etching operation.

[0084] In operation 840, the semiconductor wafer is placed in an etching chamber and clamped to the ESC through one or more back layers. In some embodiments, the etching chamber can be the same as the first chamber that causes operation 810 to occur. In some embodiments, the etching chamber can be a chamber different from the first chamber. As discussed in operation 820, at least a portion of the back layer is a conductive layer. The semiconductor wafer can be clamped to the ESC through the conductive layer. As described above, the conductive layer can act as a first plate, and the ESC can act as a second plate of a capacitor. The charge between the two plates generates an electrostatic force that can generate a clamping force between the back layer of the semiconductor wafer and the electrostatic chuck. The clamping force can hold the semiconductor wafer on the ESC through subsequent processing operations. In order to clamp to the ESC, the semiconductor wafer should be substantially flat, for example, with a warpage of about 1 mm or less. However, wafers with warpage values ​​at the higher end of this range (e.g., about 200 μm to 1 mm) require a higher voltage ESC, which may damage the wafer.

[0085] In operation 850, the semiconductor wafer is etched while clamped to the ESC. The etching process can occur in an etching chamber. In some embodiments, the etching chamber can be the same as the first chamber in which operation 810 is performed. In some embodiments, the etching chamber can be a different chamber from the first chamber. During the etching process, the semiconductor wafer can be clamped to the ESC. Example etching processes include plasma etching, reactive ion etching, chemical etching, atomic layer etching, etc. Etching can selectively etch portions of the front layer.

[0086] Figures 9A-9E Shows Figure 8 Schematic diagram of the method described in . Fig.9A The semiconductor wafer 902 is shown after the front side layer 908 is deposited in operation 810. Although the front side layer 908 is depicted as Fig.9A The individual layers in can be a single layer or multiple sub-layers. In some embodiments, the deposited front layer can include a hard mask 926. The deposited front layer 908 may have internal stress, which may cause the wafer to warp. Fig.9A In the example of FIG. 9 , the front side layer 908 and the semiconductor wafer 902 are warped, indicating that the deposited front side layer has internal stress.

[0087] Fig. 9B The semiconductor wafer 902 is shown after the backside layer 910 is deposited in operation 820. The backside layer 910 has internal stress that can offset the internal stress of the frontside layer 908 and may cause the semiconductor wafer 902 to become substantially flat, as shown. Fig. 9B910 is shown as a single layer, but it can be a single layer or multiple sublayers. Depending on the application, in some embodiments, the back layer 910 can be a homogeneous back layer, such as a single material. In these embodiments, the back layer 910 is made of a conductive material. In some embodiments, the back layer 910 can be heterogeneous, such as composed of two or more materials. When the back layer is heterogeneous, at least one material is a conductive material. In some embodiments of the heterogeneous back layer, one of the materials can be a dielectric material.

[0088] Fig. 9C The semiconductor wafer 902 is shown after the front layer 908 has been patterned by photolithography in operation 830. In the embodiment shown, the front layer 908 has a hard mask 926. The photolithography operation patterns the hard mask 926 in preparation for a subsequent etching operation.

[0089] Fig.9D A semiconductor wafer 902 is shown clamped to an ESC 904. The semiconductor wafer 902 is held by electrostatic forces between the ESC 904 and a backing layer 910. The electrostatic forces secure the semiconductor wafer 902 to the ESC 904, thereby preventing the semiconductor wafer from detaching or sliding off the ESC during subsequent operations.

[0090] Fig.9E The semiconductor wafer 902 is shown after the etching operation in 850 has occurred. As shown, the semiconductor wafer 902 can be clamped to the ESC 904. The etching operation can be, for example, plasma etching, reactive ion etching, chemical etching, or atomic layer etching. In the embodiment shown, the etching operation etches the front layer 908, which follows the pattern created in the hard mask 926 by photolithography in operation 830.

[0091] Fig.10 A second example of processing a semiconductor wafer is shown. Fig.10 Beginning in operation 1010, a first portion of one or more front layers is deposited on a semiconductor wafer. The front layers may be deposited by ALD, plasma enhanced ALD, CVD, plasma enhanced CVD, or epitaxial growth. In some embodiments, the deposited front layers are monolayers. In some embodiments, the deposited front layers are multilayers. The front layers may create internal stresses in the semiconductor wafer that, if not compensated for, may cause the semiconductor wafer to warp. In some embodiments, the internal stresses in the deposited front layers may be similar to those described above. Figure 8 The stress discussed in , is about -1000 MPa to 1000 MPa, for example, about -450 MPa to 450 MPa, about -300 MPa to about 300 MPa.

[0092] After depositing one or more front layers on the semiconductor wafer, the method continues to deposit a portion of one or more back layers on the semiconductor wafer in operation 1020. The back layer can be deposited using ALD, plasma enhanced ALD, CVD, plasma enhanced CVD, or epitaxial growth. The deposition can be performed in a second chamber designed for deposition on the back side of the wafer. At least one of the one or more back layers deposited is a conductive layer. As described above, the conductive layer can have a sheet resistance of about 5000 ohm / sq or less, such as about 100 ohm / sq or less, about 500 ohm / sq or less. In some embodiments, the resistance is about 150 ohm / sq to about 300 ohm / sq. One or more back layers can generate internal stress. In some embodiments, the internal stress generated may be able to offset the internal stress generated by the front layer deposited in 1010. In these embodiments, the stress of the front layer causes the semiconductor wafer to warp. The deposited back layer can generate internal stress that offsets the stress caused by the front side. The internal stress caused by the back side can reduce and / or eliminate the wafer warpage caused by the internal stress of the front layer. By counteracting the internal stress, the wafer can remain substantially flat. In some embodiments, the deposited back layer can have internal stress. The internal stress can be a tensile force of about -1000MPa to about 1000MPa, such as a tensile force of about -450MPa to about 450MPa, about -300MPa to about 300MPa. As described above, the back side can be a single layer or can be a multilayer. In some embodiments, the back side is homogeneous. In some embodiments, the back side layer can be heterogeneous. In any embodiment, a portion of the back side deposited can be a conductive layer. The example of a conductive layer is doped polysilicon. Doped polysilicon can be doped with the dopants listed above.

[0093] In operation 1030, a subsequent portion of the front side is deposited onto the semiconductor substrate. The subsequent portion of the front side can be deposited on top of a previously deposited portion of the front side. For example, the previously deposited portion can be the first portion of the front side deposited in operation 1010. In some embodiments, the previously deposited portion of the front side layer can be a portion deposited after the first portion of the front side layer. This will be discussed in more detail below.

[0094] Subsequent portions of the front layer can be deposited by any suitable technique, such as by ALD, plasma enhanced ALD, CVD, plasma enhanced CVD or epitaxial growth deposition. Subsequent portions of the front layer can be deposited in the first chamber. In some embodiments, the subsequent portions of the deposited front layer are monolayers. In some embodiments, the subsequent portions of the deposited front layer are multilayers. The front side may generate internal stresses on the semiconductor wafer, which may cause the semiconductor wafer to warp if not compensated. The internal stress caused by the front layer may be the internal stress caused by the subsequent portions of the front side and all previously deposited portions. In some embodiments, the total internal stress of the deposited front layer may be from about 1000 MPa to about -1000 MPa, for example, from about -450 MPa to about 450 MPa, from about -300 MPa to about 300 MPa.

[0095] In operation 1040, a subsequent portion of the back side is deposited onto the semiconductor substrate. The subsequent portion of the back side may be deposited on top of the previously deposited portion of the back side. For example, the previously deposited portion may be the first portion of the back side deposited in operation 1020. In some embodiments, the previously deposited portion of the back side layer may be a portion deposited after the first portion of the back side layer. The subsequent portion of the back side layer may be deposited by ALD, plasma enhanced ALD, CVD, plasma enhanced CVD, or epitaxial growth. The subsequent portion may be deposited in the second chamber. In some embodiments, the subsequent portion of the deposited back side layer is a single layer. In some embodiments, the subsequent portion of the deposited back side layer is a multilayer. In some embodiments, the subsequent portion may be the same material as the material of the previously deposited portion. For example, both the previously deposited portion and the subsequent portion may be conductive materials, such as doped polycrystalline films. Similar to operation 1020, the conductive layer may have a sheet resistance of about 5000 ohm / sq or less, such as about 1000 ohm / sq or less, about 500 ohm / sq or less. For example, the conductive layer may have a sheet resistance of about 150 ohm / sq to about 300 ohm / sq. In some embodiments, the subsequent portion and the previously deposited portion may be different materials. In these embodiments, the resistance of one portion or layer may be lower than that of the second portion or layer. For example, the previously deposited portion may be a conductive material, such as doped polysilicon, and the subsequent portion may be a dielectric material, such as silicon nitride. In some embodiments, the previously deposited portion may be a heterogeneous material, and the material of the subsequent portion may be a single material. In some such embodiments, the material may match a material in the deposited portion. For example, the previously deposited portion may have a conductive layer and a dielectric layer. The subsequent portion of the deposition may be a dielectric layer. In another embodiment, the deposited portion may be a homogeneous material, and the subsequent portion may be two or more materials. For example, the previously deposited portion may be a conductive material. The subsequent portion may have multiple layers, wherein one or more layers are conductive materials, and the other layers are another material, such as a dielectric material.

[0096] The back side of the deposition can produce internal stress opposite to the stress caused by the front side. The back side internal stress of the deposition can be a combination of the internal stress produced by the previously deposited part and the internal stress produced by the subsequent part. The internal stress caused by the back side of the deposition can reduce and / or eliminate the wafer warpage caused by the internal stress of the front layer. By offsetting the front internal stress with the internal stress of the back side, the wafer can be substantially flat. In some embodiments, the back side layer of the deposition may have internal stress. The internal stress can be a force of about 1000MPa to about 1000MPa, for example, a force of about -450MPa to about 450MPa, about -300MPa to about 300Mpa.

[0097] Operations 1030 and 1040 may be repeated until the front side is completely deposited. The front side may be deposited one portion at a time, starting with the first portion in operation 1010, and then one or more subsequent portions are deposited in operation 1030. Each portion may be followed by a back side portion that may offset the stress generated by the front side portion deposited in the immediately preceding operation. Depending on the application, the process may cycle multiple cycles between operations 810 (for front side layer deposition) and 820 (for back side layer deposition), such as 2 cycles, 3 cycles, 5 cycles, 10 cycles, 20 cycles, 50 cycles, 100 cycles, etc. In some embodiments, the process may cycle between chambers, i.e., the semiconductor wafer may be in a first chamber to deposit material on the front side, and may be in a second chamber to deposit material on the back side of the semiconductor wafer. Once the front side is completely deposited and the back side is deposited, such that the internal stress on the back side can offset the internal stress from the front side, making the wafer substantially flat, the process may proceed to operation 1050.

[0098] In operation 1050, the front side of the non-warped wafer is patterned by photolithography. The front side may include a target layer and a hard mask. The hard mask may be patterned during the photolithography step to protect selective areas of the front side layer during a subsequent etching operation.

[0099] In operation 1060, the semiconductor wafer is placed in an etching chamber and clamped to the ESC through one or more back layers. In some embodiments, the etching chamber can be the same as the first chamber in which operations 1010 and 1030 are performed. In some embodiments, the etching chamber can be a chamber different from the first chamber. As described above, at least a portion of the back side is a conductive layer. The conductive layer acts as the first plate of a capacitor, and the ESC acts as the second plate of the capacitor. The charge between the two plates generates an electrostatic force, which can clamp the semiconductor wafer to the electrostatic chuck by subsequent processing operations. The conductive layer and the ESC act as a capacitor, wherein the conductive layer acts as the first plate of the capacitor, and the pressure plate of the ESC acts as the second plate of the capacitor. This generates an electrostatic force, which can clamp the semiconductor wafer to the electrostatic chuck by subsequent processing operations. In order to facilitate clamping, the semiconductor wafer should be substantially flat.

[0100] In operation 1070, the semiconductor wafer is etched while clamped to the ESC, as described in operation 1050. Example etching processes include plasma etching, reactive ion etching, chemical etching, atomic layer etching, etc. The etching operation occurs in an etching chamber.

[0101] Figures 11A-11G Shows Fig.10 An example schematic diagram of the method shown in . Fig.11AThe semiconductor wafer 1102 is shown after depositing a front side first portion 1128 of the front side layer 1108 in operation 1010. Examples of materials for the semiconductor wafer 1102 are described above. Fig.11A It is depicted as a single layer, but can be a single layer or multiple sub-layers. The deposited front first portion 1128 may have internal stresses, which may cause the wafer to warp. Fig.11A In the example shown, the front side layer 1108 and the semiconductor wafer 1102 are warped, which indicates that the deposited front side first portion 1128 has internal stress.

[0102] Fig. 11B The semiconductor wafer 1102 is shown after the backside first portion 1116 of the backside layer 1110 is deposited in operation 1020. The backside first portion 1116 has an internal stress that can offset the internal stress of the frontside first portion 11288 and can cause the semiconductor wafer 1102 to become substantially flat. In the example shown, the semiconductor wafer 1102, the frontside layer 1108, and the backside layer 1110 are flat. Although the backside layer 1110 is Fig. 11B 1116 is shown as a single layer, but can be a single layer or multiple sub-layers. Depending on the application, in some embodiments, the back first portion 1116 can be homogenous. In some embodiments, the back first portion 1116 can be heterogeneous. In the embodiment where the back first portion 1116 is homogenous, the back layer can be a conductive material or a dielectric material. Examples of conductive materials and dielectric materials are described above.

[0103] Fig. 11C The semiconductor wafer 1102 is shown after a front side subsequent portion 1130 is deposited onto the front side layer 1108 in operation 1030. Fig.11A 1126. The deposited front subsequent portion 1130 may have internal stress. The internal stress of the front layer 1108 may be a combination of the internal stresses of each front portion (e.g., the front first portion 1128 and the front subsequent portion 1130) deposited on the semiconductor wafer 1102. After depositing the front subsequent portion 1130, the internal stress of the front layer 1108 may be greater than the internal stress of the back layer 1110. Due to the unequal amounts of stress on the front layer 1108 and the back layer 1110, the semiconductor wafer 1102 may warp, as shown in FIG. Fig. 11C shown.

[0104] Fig.11DThe semiconductor wafer 1102 is shown after the back subsequent portion 1118 is deposited onto the back layer 1110 in operation 1040. The back subsequent portion 1118 may have internal stress. The internal stress of the back layer 1110 may be a combination of the internal stresses of each back portion (e.g., the back first portion 1116 and the back subsequent portion 1118) deposited on the semiconductor wafer. The new internal stress of the back layer 1110 may be able to offset the internal stress caused by the front layer 1108 and may cause the semiconductor wafer 1102 to become substantially flat. In the example shown, the semiconductor wafer 1102, the front layer 1108, and the back layer 1110 are flat. Depending on the application, in some embodiments, the back first portion 1116 may be homogenous. In some embodiments, the back first portion 1116 may be heterogeneous. In embodiments where the back first portion 1116 is homogenous, the back layer may be a conductive material or a dielectric material. The back layer 1110 may be homogenous or heterogeneous. When the back layer 1110 is homogenous, the back layer is made of a conductive material. When the back layer 1110 is heterogeneous, the back layer has at least one sublayer made of a conductive material. For a heterogeneous back side, the back layer has two or more layers. In this embodiment, at least the sheet resistance of the first back side layer is lower than the sheet resistance of the second back side layer. In some embodiments of a heterogeneous back side layer (e.g., back side layer 1110), one sublayer can be a dielectric. In general, for a heterogeneous back side layer (e.g., back side layer 1110) having a conductive material and a dielectric material, the conductive material may be closer to the semiconductor wafer 1102. For example, if the back side layer 1110 is Fig.11D If the back surface is heterogeneous, the first back surface portion 1116 can be a conductive material, and the subsequent back surface portion 1118 can be a dielectric material.

[0105] Fig.11E The semiconductor wafer 1102 is shown after the front side layer 1108 has been patterned by photolithography in operation 1050. In the embodiment shown, the front side layer 1108 has a hard mask 1126. The photolithography operation patterns the hard mask 1126 in preparation for a subsequent etching operation.

[0106] Fig.11F Semiconductor wafer 1102 is shown clamped to ESC 1104 as described in operation 1060. Semiconductor wafer 1102 is held by electrostatic forces between ESC 1104 and backside layer 1110. The electrostatic forces secure semiconductor wafer 1102 to ESC 1104, preventing the semiconductor wafer from detaching or sliding off the ESC during subsequent operations.

[0107] Fig.11GSemiconductor wafer 1102 is shown after an etching operation has occurred in 1070. Example etching operations are described above. In the embodiment shown, the etching operation etches front side layer 1108 following the pattern created in hard mask 1126 by photolithography in operation 1050. Device

[0108] Fig. 12A 1 is a block diagram of a substrate processing system 1200 for performing processing on a wafer 1202 (also referred to as a wafer) according to some embodiments. As shown, the substrate processing system may include a chamber 1234. A central column may be configured to support a pedestal while a top surface of the wafer 1202 is being processed (e.g., a film is being formed on the top surface of the wafer 1202 or on the back side of the wafer 1202). According to some embodiments disclosed herein, the pedestal may be referred to as a showerhead pedestal ("ShoPed") 1206. A showerhead 1236 may be disposed above the showerhead 1206.

[0109] In some embodiments, the showerhead 1236 can be electrically coupled to a power supply 1238 via a matching network 1240. The power supply 1238 can be controlled by a control module 1242, such as a controller. In some embodiments, power can be provided to the showerhead 1206 instead of the showerhead 1236. The control module 1242 can be configured to operate the substrate processing system 1232 by executing process inputs and controls for a particular process recipe. Depending on whether the top surface of the wafer 1202 is receiving a deposited film or whether the bottom surface of the wafer 1202 is receiving a deposited film, the controller module 1242 can set a number of operational inputs for the process recipe, such as power levels, timing parameters, process gases, mechanical movement of the wafer 1202, and / or the height of the wafer 1202 relative to the showerhead 1206.

[0110] In some embodiments, the center column may also include lift pins that are controlled by a lift pin controller. These lift pins may be used to lift the wafer 1202 from the nozzle holder 1206 to allow an end effector (not shown) to pick up the wafer and lower the wafer 1202 after the wafer 1202 is placed by the end effector. The end effector may also place the wafer 1202 over the spacer 1244. As will be described below, the spacer 1244 may be sized to provide a controlled separation of the wafer 1202 between the top surface of the nozzle 1236 (facing the wafer) and the top surface of the nozzle holder 1206 (facing the wafer).

[0111] In some embodiments, the substrate processing system 1232 can further include a first gas manifold 1246 connected to a first gas source 1248 (e.g., a gas chemical and / or an inert gas supplied from a facility). Depending on the process being performed above the top surface of the wafer 1202, the control module 1242 can control the delivery of the first gas source 1248 through the first gas manifold 1246. The selected gas can then flow into the showerhead 1236 and be distributed in the volume of space defined between the surface of the showerhead 1236 facing the wafer 1202 when the wafer is positioned above the susceptor.

[0112] In some embodiments, the substrate processing system 1232 can further include a second gas manifold 1250 connected to a second gas source 1252 (e.g., a gas chemical and / or an inert gas supplied from a facility). Depending on the process being performed above the bottom surface of the wafer 1202, the control module 1242 can control the delivery of the second gas source 1252 through the second gas manifold 1250. The selected gas can then flow into the showerhead 1236 and be distributed in the volume of space defined between the surface of the showerhead 1206 facing the lower surface or underside (backside) of the wafer 1202 when the wafer is placed above the spacer 1244. The spacer 1244 can provide separation that optimizes deposition on the lower surface of the wafer 1202 and reduces deposition above the top surface of the wafer 1202. In some embodiments, when the deposition target is the lower surface of wafer 1202, an inert gas may flow over the top surface of wafer 1202 via showerhead 1236, which may push reactant gas away from the top surface and enable reactant gas provided from showerhead 1206 to be directed to the lower surface of wafer 1202.

[0113] Further, the gases may be premixed or not. Appropriate valves and mass flow control mechanisms may be employed to ensure that the correct gases are delivered during the deposition and plasma processing phases of the process. The process gases may exit the chamber 1234 via an outlet. A vacuum pump (e.g., a single or two-stage mechanical dry pump and / or a turbomolecular pump) may pump the process gases out and maintain an appropriate low pressure within the reactor through a closed loop flow restriction device (e.g., a throttle valve or a pendulum valve).

[0114] In some embodiments, the carrier ring 1254 may surround an outer region of the nozzle seat 1206. When the top surface of the wafer 1202 is being processed, for example, when a material is being deposited thereon, the carrier ring 1254 may be configured to be located above a carrier ring support area that is stepped downward from a wafer support area in the center of the nozzle seat 1206. The top surface of the carrier ring 1254 is generally coplanar with the top surface of the wafer 1202. The carrier ring 1254 may include an outer edge side (e.g., an outer radius) of its disk structure and a wafer edge side (e.g., an inner radius) of its disk structure that is closest to where the wafer 1202 is located. The carrier ring 1254 may be associated with an inner diameter (ID). The ID may extend to the inner periphery of the carrier ring and generally surround the substrate (e.g., wafer 1202) in the processing chamber. The wafer edge side of the carrier ring 1254 may also include a plurality of contact support structures or "tabs" that may be configured to elevate the wafer 1202 when the carrier ring 1254 is held by the spacer 1244. The carry ring 1254 may include a plurality of tabs, the number of which is selected from a range that supports the wafer 1202 during processing. Additional details regarding the tab embodiments are as follows.

[0115] Fig. 12B 1 is a block diagram illustrating another substrate handling system 1232 for performing processing on a wafer 1202 according to some embodiments. In some embodiments, spoke forks 1256 may be used to raise and hold a carry ring 1254 at its processing height, e.g., to allow deposition on the lower surface (backside) of the wafer 1202. Thus, the carry ring 1254 may be raised along with the wafer 1202. In some embodiments, the carry ring 1254 may be rotated to another station, e.g., in a multi-station system.

[0116] Broadly, embodiments disclosed herein are systems for depositing PECVD films on selected surfaces (front and / or back) of a wafer by dynamic control. Some embodiments may include dual gas flow electrodes for defining a capacitively coupled PECVD system. The system may include a gas flow showerhead (e.g., showerhead 1236) and a showerhead 126. In some embodiments, the gas flow base (i.e., showerhead) is a combination of a showerhead and a base that performs deposition on the back side of the wafer. The electrode geometry combines features of the showerhead (e.g., gas mixing plenum, holes, hole patterns, anti-gas spray baffles) and features of the base. Examples of base features include embedded controlled heaters, wafer lifting mechanisms, the ability to hold a plasma suppression ring, and movability. This enables transfer of wafers and handling of gases to be performed with or without RF power from the base.

[0117] In some embodiments, the system may have a wafer lift mechanism that tightly controls the parallelism of the substrate relative to the electrodes. In one example, this can be achieved by setting the lift mechanism (e.g., a spindle or lift pin mechanism) parallel to the two electrodes and controlling manufacturing tolerances. In another example, the lift can be achieved by raising the wafer lift component. This option may not allow for dynamic control of the side where deposition is performed.

[0118] In some configurations, the lift mechanism may allow for dynamic control of substrate position during processing (before plasma, during plasma, after plasma) to control the side of deposition, the profile of deposition, and deposited film properties. The system may further allow for selective activation / deactivation of the side of reactant flow. One side may flow reactants and the other side may flow inert gas to suppress deposition and plasma.

[0119] In some embodiments, the gap between the side of the wafer where plasma / deposition is not desired can be strictly controlled. The distance can be controlled to suppress plasma. If the distance is not controlled, the wafer may be susceptible to plasma damage. For example, the system can allow a minimum gap of about 2 mm to about 0.5 mm, and in another embodiment about 1 mm to about 0.05 mm (limited by wafer warpage), and such a gap can be controlled. The gap can be controlled according to processing conditions.

[0120] In some embodiments, the gas flow base (i.e., nozzle base) can achieve, but is not limited to: (a) thermal stabilization of the wafer to the processing temperature before processing; (b) selective design of the hole pattern on the nozzle base to selectively deposit films on different areas of the back side of the wafer; (c) replaceable rings can be attached to achieve appropriate plasma confinement and hole pattern; (d) stable wafer transfer mechanism within the chamber for transferring the wafer out to another chamber or wafer boat - such as lift pins, RF coupling features, minimum contact arrays; (e) implementation of gas mixing features, such as internal gas chambers, baffles, and manifold pipeline openings; and (f) providing compartments in the gas flow base (i.e., nozzle base) to enable selective gas flow to different areas on the back side of the wafer, and control the flow rate through flow controllers and / or multiple gas chambers.

[0121] In another embodiment, dynamic gap control using a wafer lift mechanism is achieved: (a) controlling the distance from the deposition or reactant flow electrode to the side or middle of the wafer where deposition is desired so that deposition can be performed on both sides; and (b) a lift mechanism for dynamically controlling the distance during processing (before plasma, during plasma, after plasma) to control the side of deposition, deposition profile, and deposited film properties. In another embodiment, for deposition modes used to deposit on the back side of the wafer, film edge exclusion control is highly desirable to avoid overlay issues associated with lithography. The lift mechanism used in this system is accomplished by a carrier ring 124 that has design features for shielding deposition on the edge. This specifies edge exclusion control through the design and shape of the carrier ring.

[0122] Fig.13A A cross-sectional view of an edge region of the nozzle seat 1206 is shown. This view provides a cross-sectional representation of the carrier ring 1254, which has a carrier ring inner radius 1254a and a carrier ring outer radius 1254b. In some embodiments, the carrier ring 1254 includes a support extension 1254c that extends below the substantially flat surface of the carrier ring 1254.

[0123] The support extension 1254c is configured to fit and be located within a support surface defined in the top surface of the spacer 1244. The support surface provides a complementary mating surface to the support extension 1254c, thereby preventing the carrier ring 1254 from sliding or moving when supported by the spacer 1244. Fig. 13B Three spacers 1244 are shown in FIG. 1 , but it is contemplated that any number of spacers may be provided so long as the carrier ring can be supported substantially parallel to the surface of the nozzle holder 1206 and the spacing is defined to support the wafer 1202 in a spaced relationship with the top surface of the pedestal 1206.

[0124] It is further shown that the top surface of the nozzle seat 1206 will include a hole pattern 1206a distributed across the surface to provide uniform distribution and output of gas during operation. In one embodiment, the hole pattern 1206a is distributed into a plurality of concentric rings starting at the center of the top surface of the nozzle seat 1206 and extending to the outer periphery of the nozzle seat 1206. At least one hole pattern 1206a is disposed at an edge hole region 1207 of the hole pattern, and the orifices defined in the edge hole region 1207 are preferably angled to provide gas non-perpendicular to the nozzle seat 1206 surface.

[0125] In one example, the angle or tilt of the orifices in the edge hole region 1207 is defined to be tilted or angled away from the center of the nozzle holder 106. In one embodiment, the angle is about 45° from horizontal. In other embodiments, the angle can vary from 20° from horizontal to about 80° from horizontal. In one embodiment, by providing angled orifices in the edge hole region 1207, additional distribution of process gases can be provided during deposition on the back side of the wafer 1202. In one embodiment, the remaining orifices 1206d of the hole pattern 1206a are oriented substantially perpendicular to the nozzle holder 106 surface and pointed toward the underside of the wafer 1202.

[0126] Fig. 13B It is shown that when the wafer 1202 is held by the carry ring 1254, the edge of the wafer 1202 will be located on an edge region closer to the carry ring inner radius 1254a of the carry ring 1254. When positioned using the spacer 1244, the surface of the showerhead 1236 facing the top surface of the wafer 1202 can be substantially close to prevent deposition during a mode in which deposition is performed on the back side of the wafer 1202.

[0127] For example, the distance between the top of the wafer 1202 and the surface of the showerhead 1236 is preferably between about 2 mm and about 0.5 mm, and in some embodiments about 1 mm to about 0.5 mm, depending on the wafer warpage. That is, if the wafer is significantly warped, the spacing will be about 0.5 mm or more. If the wafer has not been significantly warped, the spacing may be less than about 0.5 mm. In one embodiment, it is preferred that when a material layer is being deposited on the back side of the substrate, the spacing is minimized to prevent deposition on the top side of the substrate. In some embodiments, the showerhead 1236 is configured to supply an inert gas flow over the top side of the wafer 1202 during deposition on the back side of the substrate and supplying deposition gas through the showerhead 1206.

[0128] Any suitable chamber may be used to implement the disclosed embodiments. Exemplary deposition apparatus include various systems, such as the and Max, or any of a variety of other commercially available processing systems.

[0129] In some embodiments, the first deposition may be performed at a first station, which is one of two, five, or even more deposition stations located within a single deposition chamber. Thus, for example, hydrogen (H2) and tungsten hexafluoride (WF6) may be directed to the surface of the semiconductor substrate in alternating pulses at the first station using a separate gas supply system that creates a localized atmosphere at the substrate surface. Another station may be used for NF3 treatment, and a third and / or fourth station for subsequent ALD bulk fill.

[0130] Fig.14 Schematic diagram of a processing system suitable for performing deposition processing according to an embodiment. System 1400 includes a transfer module 1403. Transfer module 1403 provides a clean, pressurized environment to minimize the risk of contamination of substrates being processed as they are moved between various reactor modules. Mounted on transfer module 1403 is a multi-station reactor 1409 capable of performing ALD, treatment, and CVD according to various embodiments. Multi-station reactor 1409 may include a plurality of stations 1411, 1413, 1415, and 1417, which may perform operations sequentially according to the disclosed embodiments. For example, multi-station reactor 1409 may be configured such that station 1411 performs front deposition using a precursor and a reducing agent, station 1413 performs an ALD bulk deposition of a conformal layer using a reducing agent, station 1415 performs a NF3 treatment operation, and station 1417 may perform a bulk ALD fill after treatment using a reducing agent.

[0131] The station may include a heated pedestal or substrate support, one or more gas inlets or showerheads, or a distribution plate.

[0132] return Fig.14 , one or more single-station or multi-station modules 1407 capable of performing plasma or chemical (non-plasma) pre-cleaning, other deposition operations, or etching operations may also be mounted on the transfer module 1403. The modules may also be used for various processes, for example, to prepare substrates for deposition processes. The system 1400 also includes one or more wafer source modules 1401, where wafers are stored before and after processing. An atmospheric robot (not shown) in the atmospheric transfer chamber 1419 may first move the wafers from the source module 1401 to the load lock 1421. The wafer transfer device (typically a robot arm unit) in the transfer module 1403 moves the wafers from the load lock 1421 to the modules mounted on the transfer module 1403 and moves the wafers between these modules.

[0133] In various embodiments, a system controller 1442 is used to control the process conditions during the deposition process. The controller 1442 will typically include one or more memory devices and one or more processors. The processor may include a CPU or computer, analog and / or digital input / output connections, a stepper motor controller board, etc.

[0134] The controller 1442 can control all activities of the deposition apparatus. The system controller 1442 runs system control software, which includes instruction sets for controlling timing, gas mixture, chamber pressure, chamber temperature, wafer temperature, radio frequency (RF) power level, wafer chuck or pedestal position, and other parameters of a particular process. In some embodiments, other computer programs stored on a memory device associated with the controller 1442 may be used.

[0135] Typically, there will be a user interface associated with the controller 1442. The user interface may include a display screen, a graphical software display of the device and / or processing conditions, and a user input device such as a pointing device, keyboard, touch screen, microphone, or the like.

[0136] The system control logic may be configured in any suitable manner. In general, the logic may be designed or configured in hardware and / or software. The instructions for controlling the drive circuit may be hard-coded or provided as software. The instructions may be provided by "programming". Such programming is understood to include any form of logic including hard-coded logic in digital signal processors, application specific integrated circuits, and other devices having specific algorithms implemented as hardware. Programming is also understood to include software or firmware instructions that can be executed on a general purpose processor. The system control software may be encoded in any suitable computer readable programming language.

[0137] The computer program code for controlling the germanium-containing reducing agent pulses, hydrogen gas flow, and tungsten-containing precursor pulses and other processes in the process sequence can be written in any conventional computer-readable programming language: for example, assembly language, C, C++, Pascal, Fortran, or others. The compiled object code or script is executed by the processor to perform the tasks identified in the program. As also indicated, the program code can be hard-coded.

[0138] Controller parameters relate to process conditions such as, for example, process gas composition and flow rate, temperature, pressure, cooling gas pressure, substrate temperature and chamber wall temperature. These parameters are provided to the user in the form of a recipe and can be input using a user interface.

[0139] Signals used to monitor the process may be provided through analog and / or digital input connections of system controller 1442. Signals used to control the process are output through analog and digital output connections of device 1400.

[0140] The system software may be designed or configured in different ways. For example, a plurality of chamber component subroutines or control objects may be written to control the operation of chamber components required to perform deposition processes according to the disclosed embodiments. Examples of programs or program segments for this purpose include substrate positioning code, process gas control code, pressure control code, and heater control code.

[0141] In some embodiments, the system controller 1442 is part of a system, which can be part of the above-described embodiments. Such a system includes a semiconductor processing device, which includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems can be integrated with electronic devices to control the operation of these systems before, during, or after the processing of semiconductor wafers or substrates. The electronic device can be referred to as a "controller" that can control various components or sub-parts of one or more systems. Depending on the processing requirements and / or the type of system, the system controller 1442 can be programmed to control any of the processes disclosed in the present invention, including controlling the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings in some systems, RF matching circuit settings, frequency settings, flow rate settings, plasma pulse frequency settings, fluid delivery settings, position and operation settings, wafer entry and exit tools and other transport tools and / or delivery of load locks connected to or interfaced with a particular system.

[0142] Broadly speaking, a controller can be defined as an electronic device with various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, can perform cleaning operations, can perform endpoint measurements, etc. The integrated circuit may include a chip storing program instructions in the form of firmware, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions delivered to a controller or system in the form of various different settings (or program files), and different settings (or program files) define operating parameters for specific processing on or for semiconductor wafers. In some embodiments, the operating parameters may be a part of a recipe defined by a process engineer to complete one or more processing steps in the manufacturing process of one or more (kinds) layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or bare chips of a wafer.

[0143] In some embodiments, the system controller 1442 can be a part of or coupled to a computer that is integrated with the system, coupled, or connected to the system or a combination thereof through a network. For example, the system controller 1442 can be in the "cloud" or all or part of a wafer factory (fab) main computer system, which can allow remote access to wafer processing. The computer can enable remote access to the system to monitor the current progress of the manufacturing operation, check the history of past manufacturing operations, check the trends or performance standards of multiple manufacturing operations, change the parameters of the current processing, set the processing steps to follow the current processing or start a new processing. In some embodiments, a remote computer (e.g., a server) can provide a processing recipe to the system through a network, which can include a local network or the Internet. The remote computer can include a user interface that allows input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify the parameters of each processing step to be performed during one or more operations. It should be understood that these parameters can be for the type of processing to be performed and the type of tool, and the controller is configured to connect or control the tool type. Thus, as described above, the controller may be distributed, for example, by including one or more discrete controllers that are networked together and work toward a common goal (e.g., the processing and control described herein). An example of a distributed controller for these purposes would be one or more integrated circuits in the room that communicate with one or more remote integrated circuits (e.g., at the platform level or as part of a remote computer) that combine to control the processing in the room.

[0144] Exemplary systems may include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, chamfer edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, CVD chambers or modules, ALD chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that may be associated with or used in the preparation and / or manufacture of semiconductor wafers.

[0145] As described above, depending on one or more processing steps to be performed by the tool, the controller can communicate with one or more other tool circuits or modules, other tool components, combination tools, other tool interfaces, adjacent tools, adjacent tools, tools located throughout the factory, a host computer, another controller, or tools used in material handling to move containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing facility.

[0146] The system controller 1442 may include different programs. The substrate positioning program may include program code for controlling chamber components that are used to load the substrate onto a pedestal or chuck and control the spacing between the substrate and other components of the chamber, such as a gas inlet and / or a target. The process gas control program may include code for controlling gas composition, flow rate, pulse time, and optionally for flowing gas into the chamber to stabilize the pressure in the chamber before deposition. The pressure control program may include code for controlling the pressure in the chamber by adjusting, for example, a throttle valve in an exhaust system in the chamber. The heater control program may include code for controlling the current of a heating unit used to heat the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas, such as helium, to a wafer chuck.

[0147] Examples of chamber sensors that can be monitored during deposition include mass flow controllers, pressure sensors such as manometers, and thermocouples located in the pedestal or chuck. Appropriately programmed feedback and control algorithms can be used with data from these sensors to maintain desired processing conditions.

[0148] The foregoing describes implementations of the present invention as implemented in a single-chamber or multi-chamber semiconductor processing tool. The apparatus and processes described herein can be used in conjunction with lithography patterning tools or processes, for example, to prepare or manufacture semiconductor devices, displays, LEDs, photovoltaic panels, etc. Typically, although not necessarily, these tools / processes will be used or operated together in a common manufacturing facility. Photolithographic patterning of films typically includes some or all of the following steps, each of which enables multiple available tools: (1) coating a workpiece, i.e., a substrate, with photoresist using a spin coating or spray coating tool; (2) curing the photoresist using a hot plate or oven or a UV curing tool; (3) exposing the photoresist to visible light or UV light or X-rays using a tool such as a wafer stepper; (4) developing the resist to selectively remove the resist and thereby pattern it using a tool such as a wet cleaning station; (5) transferring the resist pattern to an underlying film or workpiece by using a dry or plasma assisted etching tool; and (6) removing the resist using a tool such as a radio frequency or microwave plasma resist stripper. in conclusion

[0149] Although the above embodiments have been described in some detail for the purpose of clear understanding, it is apparent that certain variations and modifications may be implemented within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and devices of the embodiments of the present invention. Therefore, the embodiments of the present invention should be considered illustrative rather than restrictive, and these embodiments are not limited to the details given herein.

Claims

1. A method for processing a semiconductor substrate during the manufacture of an electronic device, the method comprising: (a) depositing one or more front-side layers on the semiconductor substrate, the front-side layers having front-side internal stresses which, if not compensated, would cause warping of the semiconductor substrate; as well as (b) depositing one or more back layers on the semiconductor substrate, the back layers having a back internal stress that offsets the front internal stress of the one or more front layers and reduces or eliminates the warping, wherein the sheet resistance of the one or more back layers is equal to or less than about 5000 ohm / sq. 2 . The method of claim 1 , further comprising (c) clamping the semiconductor substrate having the one or more backside layers by an electrostatic chuck. 3 . The method of claim 2 , further comprising (d) etching the semiconductor substrate while the semiconductor substrate is clamped to the electrostatic chuck.

4. The method of claim 2, wherein operations (a), (b) and (c) are each performed in a different chamber. The method of claim 1 , wherein the one or more front side layers comprise a hard mask. The method of claim 1 , wherein the one or more backside layers have a thickness of about 1 μm to about 10 μm.

7. The method of claim 1, wherein one of the one or more backside layers has a sheet resistance of about 150 ohm / sq to about 300 ohm / sq.

8. The method of claim 1, wherein at least one of the one or more backside layers comprises doped polysilicon.

9. The method of claim 8, wherein the doped polysilicon is doped with a dopant comprising phosphorus, carbon, boron, tungsten, nitrogen, or any combination of two or more thereof.

10. The method of claim 1, wherein the backside internal stress of the one or more backside layers is from about -300 MPa to about 300 MPa.

11. The method of claim 1 , wherein depositing one or more back side layers comprises depositing a first back side layer and a second back side layer, wherein the second back side layer is disposed closer to the outside of the semiconductor substrate than the first back side layer, and wherein the sheet resistance of the first back side layer is lower than the sheet resistance of the second back side layer.

12. The method of claim 1, wherein depositing one or more backside layers on the semiconductor substrate comprises exposing the semiconductor substrate to a process gas comprising a silicon precursor and a dopant precursor, and The method further includes annealing the semiconductor substrate at a temperature of about 700° C. to about 900° C. to convert the deposited doped silicon layer into a doped polysilicon layer.

13. A semiconductor substrate or an electronic device, comprising: (a) one or more front-side layers having front-side internal stresses which, if not compensated, would result in warping of the semiconductor substrate or the electronic device; and (b) one or more back layers having a back internal stress that counteracts the front internal stress of the one or more front layers and reduces or eliminates the warping, wherein the one or more back layers have a sheet resistance equal to or less than about 5000 ohm / sq. 14 . The semiconductor substrate or electronic device of claim 13 , wherein the one or more backside layers have a thickness of about 1 μm to about 10 μm.

15. The semiconductor substrate or electronic device of claim 13, wherein the sheet resistance of the one or more backside layers is about 500 ohm / sq or less.

16. The semiconductor substrate or electronic device of claim 13, wherein the sheet resistance of the one or more backside layers is from about 150 ohm / sq to about 300 ohm / sq.

17. The semiconductor substrate or electronic device of claim 13, wherein at least one of the one or more backside layers comprises doped polysilicon.

18. The semiconductor substrate or electronic device according to claim 17, wherein the doped polysilicon is doped with a dopant, the dopant comprising phosphorus, carbon, boron, tungsten, nitrogen or any combination of two or more thereof.

19. The semiconductor substrate or electronic device of claim 13, wherein the backside internal stress of the one or more backside layers is from about -300 MPa to about 300 MPa.

20. A semiconductor substrate or electronic device according to claim 13, wherein the one or more back side layers include a first back side layer and a second back side layer, the second back side layer is arranged to be closer to the outside of the semiconductor substrate than the first back side layer, and the sheet resistance of the first back side layer is lower than the sheet resistance of the second back side layer.

21. A method of processing a semiconductor substrate during the manufacture of an electronic device, the method comprising: (a) receiving a warpage-compensated semiconductor substrate, the substrate comprising: (i) one or more front side layers having front side internal stresses which, if not compensated, would result in warping of the semiconductor substrate or the electronic device, and (ii) one or more backside layers having a backside internal stress that counteracts the frontside internal stress of the one or more frontside layers and reduces or eliminates the warping, wherein the one or more backside layers have a sheet resistance of 5000 ohm / sq or less; (b) clamping the warpage-compensated semiconductor substrate by an electrostatic chuck; and (c) Patterning the warp-compensated semiconductor substrate.

22. The method of claim 21, further comprising (d) etching the warp-compensated semiconductor substrate while it is clamped to the electrostatic chuck.

23. The method of claim 21, wherein the one or more backside layers have a thickness of about 1 μm to about 10 μm.

24. The method of claim 21, wherein the sheet resistance of one of the one or more backside layers is about 500 ohm / sq or less.

25. The method of claim 21, wherein the sheet resistance of one of the one or more backside layers is from about 150 ohm / sq to about 300 ohm / sq.

26. The method of claim 21, wherein at least one of the one or more backside layers comprises doped polysilicon.

27. The method of claim 26, wherein the doped polysilicon is doped with a dopant comprising phosphorus, carbon, boron, tungsten, nitrogen, or any combination of two or more thereof.

28. The method of claim 21, wherein the backside internal stress of the one or more backside layers is from about -300 MPa to about 300 MPa.

29. The method of claim 21, wherein the one or more back side layers include a first back side layer and a second back side layer, the second back side layer is disposed closer to the outside of the semiconductor substrate than the first back side layer, and the sheet resistance of the first back side layer is lower than the sheet resistance of the second back side layer.

30. An apparatus comprising: Processing room; a substrate support; Sprinklers; a gas source fluidly connected to the showerhead; as well as A controller configured to cause: (a) receiving a semiconductor substrate having one or more front-side layers, the front-side layers having front-side internal stresses that, if not compensated, would cause warping of the semiconductor substrate; as well as (b) depositing one or more back layers on the semiconductor substrate, the back layers having a back internal stress that offsets the front internal stress of the one or more front layers and reduces or eliminates the warping, wherein the sheet resistance of the one or more back layers is equal to or less than about 5000 ohm / sq.

31. The device of claim 30, wherein the one or more backside layers have a thickness of about 1 μm to about 10 μm.

32. The device of claim 30, wherein the sheet resistance of one of the one or more backside layers is about 500 ohm / sq or less.

33. The device of claim 30, wherein the sheet resistance of one of the one or more backside layers is about 150 ohm / sq to about 300 ohm / sq.

34. The device of claim 30, wherein at least one of the one or more backside layers comprises doped polysilicon.

35. The device of claim 30, wherein the backside internal stress of the one or more backside layers is from about -300 MPa to about 300 MPa.

36. A device according to claim 30, wherein the one or more back side layers include a first back side layer and a second back side layer, the second back side layer is arranged closer to the outside of the semiconductor substrate than the first back side layer, and the sheet resistance of the first back side layer is lower than the sheet resistance of the second back side layer.

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