Power semiconductor module and power conversion device

Abstract

The invention provides a power semiconductor module which is not provided with a base plate serving as a supporting part of an insulating substrate and a heat radiator, and can effectively inhibit the crack of the insulating substrate, which is easily generated when the sealing resin is cooled and solidified, in the resin sealing type power semiconductor module. In a resin-sealed power semiconductor module having no support member for an insulating substrate, the resin-sealed power semiconductor module is characterized by being provided with: an insulating substrate; a first conductor layer pattern disposed on the insulating substrate; a second conductor layer pattern disposed on the insulating substrate and electrically insulated from the first conductor layer pattern; a third conductor layer pattern disposed on the insulating substrate and electrically insulated from the first conductor layer pattern and the second conductor layer pattern; a first semiconductor chip group having one or more semiconductor chips bonded to the first conductor layer pattern; a second semiconductor chip group having one or more semiconductor chips bonded to the second conductor layer pattern; a first lead frame that electrically connects the second conductor layer pattern and the side of the first semiconductor chip group opposite to the joining surface of the first conductor layer pattern; and a second lead frame that electrically connects the third conductor layer pattern and the side of the second semiconductor chip group that is opposite the joining surface with the second conductor layer pattern, the first lead frame and the second lead frame being disposed so as to respectively span a slit between the first conductor layer pattern and the second conductor layer pattern. The lead frame is disposed so as to be one layer in a direction perpendicular to the surface on which the conductor layer patterns of the insulating substrate are disposed.

Description

Technical Field

[0001] The present invention relates to the structure of a power semiconductor module, and more particularly to a technique that is effective when applied to a resin-sealed power semiconductor module manufactured without including a base plate serving as a supporting member of an insulating substrate and a heat sink. Background Art

[0002] Power semiconductor modules are used in power control and motor control of industrial machinery, electric railway vehicles, automobiles, home appliances, etc. The power semiconductor modules use switching elements such as power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), semiconductor elements such as freewheeling diodes, etc. In recent years, especially due to the popularity of electric vehicles, the necessity of power semiconductor modules for vehicle inverters has increased. In order to improve the power utilization efficiency of vehicle inverters while providing them at a low price, power semiconductor modules are required to achieve low losses while also being low-cost.

[0003] In order to achieve low-loss characteristics, there are many options for power semiconductor chips, such as the use of new materials such as GaN (gallium nitride) and SiC (silicon carbide), and the application of new Si (silicon) IGBTs with reverse conductivity. On the other hand, there are also various technical directions for methods to reduce the cost of power semiconductor modules. Cost reduction can be achieved by replacing the components that make up the module with cheap components, changing the method of molding the module's appearance from the existing external body method to the manufacturing method of molding resin sealing with a low unit price, etc. However, in reality, there will be manufacturing obstacles.

[0004] Insulating substrates, one of the structural components of the module, are mainly made of ceramic substrates to ensure their insulation properties. Silicon nitride (SiN) substrates with high toughness and aluminum nitride (AlN) substrates with high thermal conductivity have excellent characteristics, but they are expensive. In particular, in power semiconductor modules for automotive inverters that are mass-produced in large quantities, it is hoped that inexpensive aluminum oxide (Al2O3) substrates will be used, but there are problems such as weak bending strength.

[0005] In addition, in the process of molding the module's outer shape, in order to achieve further cost reduction by introducing resin sealing using transfer molding or potting, a module structure that can withstand the shrinkage stress generated during the resin cooling and solidification process is required. In other words, even if a cheap ceramic substrate with weak bending strength is used, it is important to have a technology that suppresses the cracks in the ceramic substrate caused by the stress generated during the resin sealing process.

[0006] Even in a power semiconductor module sealed with resin, in the case of a structure with supporting components such as a base plate and a heat sink with high mechanical rigidity, problems such as cracks in the ceramic substrate caused by the above-mentioned stress are not obvious. However, in a vehicle inverter that combines multiple small power semiconductor modules to meet the required rated current, most of them adopt a simple structure in which semiconductor switching elements are mounted on an insulating substrate and sealed with resin. Therefore, in the manufacturing process of the power semiconductor module, in the case of a base plate, a heat sink, etc. that serve as supporting components of the insulating substrate, it is necessary to overcome the problems caused by stress such as cracks in the ceramic substrate and improve the manufacturing yield.

[0007] As a background technology in this technical field, there is a technology such as Patent Document 1. Patent Document 1 shows a structure that can reduce surge voltage more than the prior art. A ceramic substrate is used, and a plurality of electrode rods are used to connect the circuit patterns on the substrate. The electrode rods are arranged in a stacked structure to reduce inductance and suppress surge voltage. Although there is no record related to sealing resin, in Patent Document 1, Figure 1 A laminated electrode rod structure is disclosed in which a laminated electrode rod is arranged at the center of a ceramic substrate to improve rigidity.

[0008] In addition, Patent Document 2 describes a terminal housing 88 formed of a thermosetting resin that determines the outer shape of a semiconductor module 100, and discloses the following structure: in order to improve the thermal balance of multiple semiconductor chips arranged on a ceramic substrate, a bridge-like component is used to span the narrow gaps generated between wiring patterns on the substrate.

[0009] Prior art literature

[0010] Patent Literature

[0011] Patent Document 1: Japanese Patent Application Publication No. 2004-214452

[0012] Patent Document 2: International Publication No. 2020 / 071102 Summary of the invention

[0013] Problems to be solved by the invention

[0014] Referring to the above-mentioned Patent Document 1 Figure 1 , the chip arrangement of the IGBT and the diode constituting the half-bridge circuit and the shapes of the electrode rods 32, 33, and 34 electrically connecting them are shown. It is described that a plurality of electrode rods are arranged close to each other via an insulator.

[0015] In addition, referring to the above-mentioned patent document 2 Figure 2, the following structure is described: the wiring patterns on the ceramic substrate are connected through a lead frame composed of a chip bonding portion 180, a wiring bonding portion 182, leg portions 185 and 186, and a bridge portion 184.

[0016] However, the above-mentioned conventional techniques have many problems from the viewpoint of preventing cracks in the ceramic substrate.

[0017] In the structure of Patent Document 1, if it is assumed that the module shape is formed by resin sealing, it becomes a structure in which the electrode rods are overlapped with the plane of the ceramic substrate. Therefore, it is easy to infer that the thickness of the resin has to be thickened in order to seal the entire module. Therefore, there is a problem of increased shrinkage stress due to an increase in the total amount of resin and high cost. Therefore, as described above, it can be said that it is difficult to apply it to an on-vehicle inverter that aims at a small and inexpensive power semiconductor module.

[0018] In addition, Patent Document 2 discloses a structure in which a lead frame including a bridge-shaped portion spans the slits generated between the wiring patterns 164-1 to 3, which can be said to be a structure that strengthens the rigidity of the ceramic substrate. However, the configuration of the lead frame is limited. For example, a lead frame is not configured for the longest slit in the central part of the ceramic substrate. In order to strengthen the rigidity of the ceramic substrate, it is necessary to implement countermeasures based on the location where the greatest stress is generated during cooling and solidification after resin sealing and where cracks are likely to occur. Therefore, in the structure of Patent Document 2 in which the long slit in the central part of the substrate is not processed, it is considered difficult to prevent cracks from occurring in the ceramic substrate.

[0019] Therefore, the object of the present invention is to provide a power semiconductor module and an electric power conversion device using the same, which can effectively suppress cracks in the insulating substrate that are easily generated when the sealing resin is cooled and solidified in a resin-sealed power semiconductor module that does not use a base plate or a heat sink that serves as a supporting component of the insulating substrate.

[0020] Solutions to Solve Problems

[0021] In order to solve the above-mentioned problems, the present invention is a resin-sealed power semiconductor module having a supporting member without an insulating substrate, characterized in that it comprises: an insulating substrate; a first conductor layer pattern, which is arranged on the insulating substrate; a second conductor layer pattern, which is arranged on the insulating substrate and is electrically insulated from the first conductor layer pattern; a third conductor layer pattern, which is arranged on the insulating substrate and is electrically insulated from the first conductor layer pattern and the second conductor layer pattern; a first semiconductor chip group, which has one or more semiconductor chips bonded to the first conductor layer pattern; a second semiconductor chip group, which has one or more semiconductor chips bonded to the second conductor layer pattern; One or more semiconductor chips on the body layer pattern; a first lead frame, which electrically connects the side of the first semiconductor chip group opposite to the bonding surface of the first conductor layer pattern and the second conductor layer pattern; and a second lead frame, which electrically connects the side of the second semiconductor chip group opposite to the bonding surface of the second conductor layer pattern and the third conductor layer pattern, the first lead frame and the second lead frame are respectively arranged across the slit between the first conductor layer pattern and the second conductor layer pattern, and are arranged in a manner that the lead frames form a layer in a direction perpendicular to the arrangement surface of each of the conductor layer patterns of the insulating substrate.

[0022] Effects of the Invention

[0023] According to the present invention, a power semiconductor module and a power conversion device using the same can be realized. In a resin-sealed power semiconductor module that does not use a base plate or a heat sink that serves as a supporting component of an insulating substrate, cracks in the insulating substrate that are easily generated when the sealing resin is cooled and solidified can be effectively suppressed.

[0024] As a result, an alumina (Al 2 O 3 ) substrate can be used as an insulating substrate of a power semiconductor module, thereby achieving improved manufacturing yield and cost reduction of the power semiconductor module and cost reduction of the power conversion device.

[0025] Problems, structures, and effects other than those described above will become more apparent from the following description of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a top view of the power semiconductor module according to the first embodiment of the present invention.

[0027] Figure 2 yes Figure 1 A-A' section view.

[0028] Figure 3 yes Figure 1 BB' section view.

[0029] Figure 4 FIG. 1 is a top view of a conventional power semiconductor module.

[0030] Figure 5 yes Figure 4 C-C' section view.

[0031] Figure 6 This is a diagram showing an example of the analysis results of stress in a ceramic substrate.

[0032] Fig. 7A Yes means Figure 6 A diagram showing an overview of the analysis model of . (Existing example)

[0033] Figure 7B Yes means Figure 6 Figure 1 is a diagram showing an overview of the analytical model of (the present invention)

[0034] Figure 8 It is a top view of a power semiconductor module according to a second embodiment of the present invention.

[0035] Fig. 9 It is conceptually expressed Figure 8 Graph of mutual inductance in the D-D' section.

[0036] Fig.10 It is an external view of the power semiconductor module according to the first embodiment and the second embodiment of the present invention.

[0037] Fig.11 This is a block diagram showing a circuit configuration of a power conversion device according to a third embodiment of the present invention.

[0038] Fig.12 It is conceptually expressed Figure 1 Graph of mutual inductance in section A-A'.

[0039] Fig.13 Yes means Figure 1 Equivalent circuit diagram of the main circuit inductance path in .

[0040] Fig.14 Yes means Figure 8 Equivalent circuit diagram of the main circuit inductance path in . DETAILED DESCRIPTION

[0041] Hereinafter, embodiments of the present invention will be described using the drawings. In addition, in each of the drawings, the same reference numerals are given to the same structures or structures having similar functions, and detailed descriptions of the overlapping parts are omitted.

[0042] Example 1

[0043] Reference Figures 1 to 7B as well as Fig.10, a power semiconductor module according to a first embodiment of the present invention is described. In this embodiment, in a power semiconductor module formed using a ceramic insulating substrate, a module structure is shown that suppresses the generation of cracks in the ceramic insulating substrate when the sealing resin is cooled and solidified, and the effect of reducing the stress applied to the ceramic insulating substrate is described.

[0044] 《Overview Structure》

[0045] Figure 1 The schematic structure of the power semiconductor module 200 of this embodiment is shown. Figure 1 In the top view of FIG. 1 , for convenience, the configuration of the components of the lower layer that are originally invisible due to the sealing resin 60 is described in advance, and the configuration is clearly shown on the premise of being transparent. Figure 1 2 is a top view of the power semiconductor module 200 as viewed from above. Figure 2 as well as Figure 3 The cross-sectional structures are respectively shown along the section line AA′ and the section line BB′ described in the plan view.

[0046] 《Plane Structure》

[0047] Figure 1 The power semiconductor module 200 of the present embodiment shown in the figure forms a half-bridge circuit on a single insulating substrate (ceramic substrate) 50. The range of the sealing resin 60 indicated by the dotted line represents the outer shape of the power semiconductor module.

[0048] like Figure 1 As shown, the power semiconductor module 200 of the present embodiment is a so-called 2-in-1 type power semiconductor module having two sets of IGBT chips and diode chips (reference numerals 31 and 32 , reference numerals 33 and 34 ), and has three external main terminals 1 , 2 , 3 .

[0049] The external main terminal 1 functions as a high voltage power supply terminal and the external main terminal 3 functions as a low voltage power supply terminal to supply a DC voltage to the half bridge circuit on the insulating substrate 50 . The external main terminal 2 functions as an AC voltage terminal to supply a load current to the outside.

[0050] The three external main terminals 1 , 2 , and 3 are respectively arranged on the insulating substrate 50 , and are connected to three conductor layer patterns 11 , 12 , and 13 that are electrically insulated from each other.

[0051] The conductor layer pattern 11 is arranged in a region on one side of the insulating substrate 50 (in the region on which the conductor layer pattern 11 extends along one side of the insulating substrate 50 in the Y direction). Figure 1 The conductor layer pattern 12 is arranged in the other region of the insulating substrate 50 (in the region on the right side of the insulating substrate 50) so as to extend along the other side of the Y direction of the insulating substrate 50. Figure 171 is formed between the conductor layer pattern 11 and the conductor layer pattern 12. The conductor layer pattern 11 and the conductor layer pattern 12 are separated by the slit 71 and are electrically insulated from each other.

[0052] The conductor layer pattern 13 extends along one side of the insulating substrate 50 in the X direction, and a portion of the conductor layer pattern 13 is disposed in a region on one side of the insulating substrate 50 (in the region on which the conductor layer pattern 13 extends). Figure 1 The other part is arranged in the area on the other side (in the area on the right side of the insulating substrate 50). Figure 1 7. The left side region of the insulating substrate 50 is shown in FIG. 7. A slit 72 is formed between the conductor layer pattern 11 and the conductor layer pattern 12 and the conductor layer pattern 13. The conductor layer pattern 11 and the conductor layer pattern 12 and the conductor layer pattern 13 are separated by the slit 72 and are electrically insulated.

[0053] The external main terminal 1 is electrically connected to the conductor layer pattern 11 bonded to the insulating substrate 50. Figure 1 In the embodiment, an IGBT chip 31 as a semiconductor switch element and a diode chip 32 as a semiconductor diode element are connected in reverse parallel on the conductor layer pattern 11 to form an upper branch circuit. The collector electrode of the IGBT chip 31 and the cathode electrode of the diode chip 32 are electrically and mechanically connected to the conductor layer pattern 11 via solder and sintering material. The signal terminals 5 and 6 are the gate control terminal and emitter sensing terminal for controlling the switch of the IGBT chip 31. The terminals connected to the conductor layer patterns 15 and 16 are connected to the gate electrode 303 and the emitter electrode 302 on the IGBT chip 31 via bonding wires 25 and 26.

[0054] The emitter electrode 302 of the IGBT chip 31 and the anode electrode 304 of the diode chip 32 are electrically and mechanically connected to the conductor layer pattern 12 to which the potential of the AC voltage terminal is applied via the lead frame 21. The connection method is the same as that of the collector electrode of the IGBT chip 31 and the cathode electrode of the diode chip 32, which is a method via solder and sintered material.

[0055] The conductor layer pattern 12 is connected to an external main terminal 2 as an AC voltage terminal together with the collector electrode of the IGBT chip 33 and the cathode electrode of the diode chip 34 constituting the lower arm circuit. The lead frame 22 is connected to the emitter electrode 302 of the IGBT chip 33 and the anode electrode 304 of the diode chip 34, and is connected to the conductor layer pattern 13.

[0056] Similar to the upper branch circuit, the signal terminal (gate control terminal) 7 and the signal terminal (emitter sense terminal) 8 control the switching of the IGBT chip 33 .

[0057] Here, the so-called sintered material is a material formed by a plurality of single crystals having a particle size of 0.1 nm or more and 10 nm or less, and includes a sintered copper bonding material containing copper nanoparticles, and the copper nanoparticles have a copper oxide layer formed on the surface thereof. The sintered copper bonding technology uses the above-mentioned copper nanoparticles as a bonding material for semiconductor chips, and forms a sintered copper bonding layer by sintering the copper nanoparticles with each other. Copper has a higher destructive resistance than existing solder and silver. For example, even in high-temperature use above 175°C, the destructive life of the bonding can be extended. In addition, the sintered copper bonding material has a higher bonding property to non-precious metals such as copper and nickel, and the electrode material as the bonding object does not require a high gold or silver plating film, so the cost required for bonding can be suppressed.

[0058] The present invention is characterized by the configuration of the lead frame 21 and the lead frame 22 with respect to the slit 71 generated between the conductor layer pattern 11 and the conductor layer pattern 12. The lead frame 21 and the lead frame 22 are respectively arranged along the configuration direction ( Figure 1 After being stretched in the Y direction in the middle (in the Y direction), it becomes an L-shape, and becomes a shape that spans at a right angle to the slit 71. In addition, the angle is not necessarily limited to a right angle (90°), and may also be a shape that spans at a substantially right angle or an inclined angle.

[0059] The two chip groups of IGBT chip 31 and diode chip 32, and IGBT chip 33 and diode chip 34 are approximately point-symmetrical with the center position of the substrate of the slit 71 as the starting point, so the two L-shaped lead frames 21 and 22 are also Figure 1 As shown in FIG. 1 , the slit 71 is arranged point-symmetrically with the center of the substrate as the starting point. The lead frame 21 and the lead frame 22 form a structure with a so-called bridge reinforcement structure. By adopting this arrangement, the length of the slit 71 can be increased from Figure 1 The distance Y1 is shown decreasing towards Y2.

[0060] 《Section Structure》

[0061] Figure 2 as well as Figure 3 Respectively Figure 1 The module structure in the section line AA' and the section line BB' is shown. In addition, in order to facilitate the understanding of the internal structure of the power semiconductor module 200, some structural components in the depth direction observed from the AA' section and the BB' section are also shown. Figure 2 The AA′ cross-sectional view of FIG. 5 shows the arrangement relationship between the lead frame 21 and the lead frame 22 and the slit 71 and the slit 72 . The conductor layer pattern 14 is a conductor layer pattern bonded to the lower surface of the insulating substrate 50 .

[0062] Figure 2The AA' cross-sectional view is viewed from the direction from the lead frame 22 toward the lead frame 21, and it can be seen that the bridge structure of the conductor formed by the semiconductor chip (diode chip 32, IGBT chip 33) and the lead frames 21, 22 spans the slit 71. In the outer shape of the power semiconductor module 200 formed by the sealing resin 60, the length Z1 shown in the figure is defined as the height of the power semiconductor module 200.

[0063] Figure 3 The BB' cross-sectional view shows the cross-sectional structure of the region where the lead frames 21 and 22 are not arranged on the slit 71. The cross-sectional shape of the lead frames 21 and 22 is set to a two-stage shape, and the lower half connected to each electrode of the semiconductor chip (IGBT chip 31, diode chip 34) is set to a shape corresponding to the width of the semiconductor chip electrode.

[0064] like Figure 3 As shown, in the power semiconductor module 200 of the present embodiment, the outer shape of the sealing resin 60 is characterized to suppress the contraction stress that gives mechanical stress to the slit 71. Since the lead frame 21 and the lead frame 22 are shaped to surround the center of the insulating substrate 50, the shape of the sealing resin 60 is partially deformed in the central portion where there is no lead frame, and the sealing resin 60 is provided. Figure 3 The recessed shape 61 (width X4) is shown. The height of the power semiconductor module 200 in the recessed shape 61 is defined as Z1a.

[0065] Thus, the structure of this embodiment can simultaneously realize the arrangement of the lead frame for rigid reinforcement across the slit 71 formed in the insulating substrate 50 and the shape in which the thickness of the sealing resin 60 is suppressed to be thin in the center portion of the substrate where the rigid reinforcement of the lead frame is not achieved.

[0066] Fig.10 The figure shows the external shape of the power semiconductor module 200 after molding. There is a recessed shape 61 in the center of the figure, and its plane shape is a rectangle. The recessed shape 61 is formed in a roughly rectangular area surrounded by the lead frame 21 and the lead frame 22. The length X4 of its short side is a value determined by reflecting the interval between the lead frames, but in order to obtain the thinning effect, it is desired to be set to 4 mm or more. In addition, if the values ​​of the height Z1 and Z1a of the above-mentioned power semiconductor module 200 are exemplified, Z1=5 mm and Z1a=3 mm, as a result, the recessed height of the recessed shape 61 is a difference of 2 mm. The recessed height (depth) of the recessed shape 61 is desired to be 2 mm or more.

[0067] also, Fig.10 The outer shape of the power semiconductor module 200 shown in the figure is in the second embodiment described later ( Figure 8 The same is also true for the power semiconductor module 202.

[0068] As an example of quantitative evaluation of rigidity, a rough estimate is shown below.

[0069] Assume that the insulating substrate 50 uses an alumina (Al2O3) substrate, its thickness is set to 0.3 mm, and the Young's modulus is set to 300 GPa. The lead frame is made of copper, the thickness is set to 1.5 mm, and the Young's modulus is set to 130 GPa. The rigidity can be estimated by the product of the thickness and the Young's modulus. Therefore, when the alumina substrate and the lead frame are assumed to have the same width, the rigidity of the copper lead frame is enhanced by 200% of the alumina substrate, but if the total width of the lead frame is assumed to be 40% of the width of the slit 71 dominated by the rigidity of the alumina substrate, the rigidity enhancement amount caused by the introduction of the lead frame can be estimated to be 80% of the increase before the introduction.

[0070] In addition, the lead frame exerts rigidity through the power semiconductor chip (IGBT chip and diode chip) and its bonding material, so the selection of chip type and bonding material for chip bonding is important. It goes without saying that the effect of the present invention will be more significant by selecting a SiC chip with high hardness instead of a Si chip and selecting a bonding method of sintered copper or sintered silver that can ensure more than twice the bonding strength instead of solder.

[0071] 《Example of existing lead frame structure》

[0072] In order to more easily understand the structure and effect of this embodiment, use Figure 4 as well as Figure 5 , a structural example of a conventional power semiconductor module is described.

[0073] Figure 4 is a top view of a conventional power semiconductor module 201. Figure 5 yes Figure 4 In addition, Figure 2 as well as Figure 3 Similarly, in order to facilitate understanding of the internal structure of the power semiconductor module 201 , a portion of the structural components in the depth direction as viewed from the CC′ cross section is also shown.

[0074] Figure 4 The conventional power semiconductor module 201 shown is an example of a power semiconductor module implemented on an insulating substrate 50. Figure 1 The module structure of the same half-bridge circuit uses the lead frame 21 and the lead frame 22, but shows the form of a conventional example.

[0075] Compared with this embodiment ( Figure 1) has a different structure, has no rigid reinforcement structure, and a slit 71 of length Y3 is generated in the center of the insulating substrate 50. When the sealing resin 60 is cooled and solidified, stress is generated around the slit 71, and there is a high risk of cracks in the central part of the insulating substrate 50.

[0076] Qualitative tendencies based on analytical results

[0077] use Figures 6 to 7B , the stress in the central portion of the insulating substrate 50 is described.

[0078] Figure 6 The results of analyzing the stress N in the center of the ceramic substrate using a simulator are shown. Fig. 7A as well as Figure 7B Yes means Figure 6 The schematic diagram of the analysis model shows the cross-sectional structure simulating the structure of the conventional example and the structure of the present invention.

[0079] Conductive layer patterns 11, 12, 14 made of copper and having a thickness of 0.4 mm are arranged on insulating substrate (ceramic substrate) 50 of aluminum oxide (Al2O3). The stress N is observed at the center of insulating substrate (ceramic substrate) 50 having a thickness of 0.3 mm and directly below slit 71.

[0080] Simulating the structure of the present invention Figure 7B 71 is covered with a copper plate LF corresponding to a lead frame. Fig. 7A as well as Figure 7B In the figure, it is assumed that epoxy resin is disposed on the conductor layer patterns 11 and 12 with a thickness of T as the sealing resin 60. Figure 6 The dependence of the stress N when the T value is changed is shown. Here, a T value of 4 mm to 7 mm is used. The T value shown is about 4 mm, and if the thickness of the insulating substrate 50 and the conductor layer patterns 11 and 12 are taken into account, the overall thickness of the power semiconductor module sealed with resin is about 5 mm.

[0081] Relative to Figure 6 The change in the thickness T of the resin shown on the horizontal axis shows that in the simulation Fig. 7A In the case of the cross-sectional structure of the conventional example shown in FIG. 1 (the plot of ▲ in the figure), even when the thickness T of the resin is reduced, the stress N does not decrease and the height is stopped. Figure 7B In the cross-sectional structure of the structure of the present invention shown (the plotted 0 in the figure), it can be seen that the stress N decreases as the stress N itself decreases and the thickness T of the resin becomes thinner, compared with the structure of the prior art example.

[0082] This tendency shows that the combination of adding a lead frame with a structure that strengthens rigidity and thinning the thickness of a local resin layer described in this embodiment is effective. Figure 6 As shown in the data of the prior art example, it is found that the stress reduction effect cannot be expected even if the thickness T of the resin is simply reduced. The tendency of these analysis results varies due to the relationship between the thermal expansion coefficient of the resin and the copper conductive layer pattern and their respective thicknesses. Although it is not a permanent tendency, it shows the effect of the present invention.

[0083] As described above, the power semiconductor module of the present embodiment is a resin-sealed power semiconductor module that does not have a base plate, a heat sink, etc. that serve as a supporting member of the insulating substrate 50, and comprises: an insulating substrate 50; a first conductor layer pattern 11, which is arranged on the insulating substrate 50; a second conductor layer pattern 12, which is arranged on the insulating substrate 50 and is electrically insulated from the first conductor layer pattern 11; a third conductor layer pattern 13, which is arranged on the insulating substrate 50 and is electrically insulated from the first conductor layer pattern 11 and the second conductor layer pattern 12; a first semiconductor chip group (IGBT chip 31, diode chip 32), which has one or more semiconductor chips bonded to the first conductor layer pattern 11; a second semiconductor chip group (IGBT chip 33, diode chip 34) A first lead frame 21 electrically connects the first semiconductor chip group on the opposite side of the bonding surface with the first conductor layer pattern 11 to the second conductor layer pattern 12; and a second lead frame 22 electrically connects the second semiconductor chip group on the opposite side of the bonding surface with the second conductor layer pattern 12 to the third conductor layer pattern 13, the first lead frame 21 and the second lead frame 22 are respectively arranged across the slit 71 between the first conductor layer pattern 11 and the second conductor layer pattern 12, and are arranged in a manner that the lead frames 21 and 22 do not overlap each other in a direction perpendicular to the arrangement surface of the conductor layer patterns 11, 12, and 13 of the insulating substrate 50, that is, in a manner that the lead frames 21 and 22 form a layer.

[0084] The slit 71 is disposed in the center of the insulating substrate 50 and has the longest length among the plurality of slits formed between the conductor layer patterns 11 , 12 , and 13 on the insulating substrate 50 .

[0085] Furthermore, the thickness of the sealing resin 60 in a region including at least a portion of the slit 71 is thinner than the thickness of the sealing resin 60 in other regions.

[0086] In addition, only the sealing resin 60 is arranged on the first lead frame 21 and the second lead frame 22 in a direction perpendicular to the arrangement surface of the insulating substrate 50 where the conductor layer patterns 11 , 12 , 13 are arranged.

[0087] This can effectively suppress cracks in the insulating substrate 50 that are likely to occur when the sealing resin 60 is cooled and solidified.

[0088] Example 2

[0089] Reference Figure 8 as well as Fig. 9 , Figure 12 to Figure 14 , a power semiconductor module according to a second embodiment of the present invention is described. In addition, Fig.12 as well as Fig.13 This is a diagram related to Example 1 and is shown for comparison with this example.

[0090] Figure 8 2 is a top view of the power semiconductor module 202 of this embodiment. Figure 1 ) structure, the terminal shape of the external main terminal 1 and the external main terminal 3 and the shape of the conductor layer pattern around them are changed. The shape of the lead frame 21 and the lead frame 22A relative to the slit 71 is different from that of the embodiment 1 ( Figure 1 )same.

[0091] The lead frame 22A has an L-shaped frame shape and is also configured to have the same function as that of the first embodiment ( Figure 1 ) is a functional shape of the external main terminal 3 shown in FIG. By setting it to such a shape, a path from the IGBT chip 33 to the external main terminal 3A can be formed by a uniform and thick conductor. For example, the conductor layer patterns 11 to 13 are copper circuit patterns, and their thickness is 0.4 mm. On the other hand, the lead frame 21 and the lead frame 22A are independent of the thickness of the conductor layer patterns 11 to 13, and thick copper lead frames can be used, so their thickness can be set to 1.0 mm to 1.5 mm.

[0092] External main terminal 1A and embodiment 1 ( Figure 1 ) is compared with the external main terminal 1 of FIG. 1 , and is set to a shape that extends the length on the insulating substrate 50 to the vicinity of the diode chip 32 and passes through the upper part of the conductor layer pattern 13.

[0093] Fig. 9 express Figure 8 By adopting the above-mentioned form of the present embodiment, the external main terminal 3A (also serving as the lead frame 22A) as a low voltage power supply terminal can have the following two features relative to the external main terminal 1A as a high voltage power supply terminal: (1) it can be arranged in parallel with each other with a thicker conductor cross-section shape, and (2) a region arranged in parallel with the conductor layer pattern 13 on the plane is generated. That is, the external main terminal 1A can be arranged in parallel with the lead frame 22A with a thicker conductor cross-section shape, and can be arranged in parallel with the conductor layer pattern 13 with a wider width.

[0094] The external main terminal 1A and the external main terminal 3A are wiring paths that constitute the main circuit inductance Ls that affects the switching characteristics of the power semiconductor module 202 . Fig.14 express Figure 8 The equivalent circuit of the main circuit inductance path of the power semiconductor module 202 of this embodiment is shown. The external main terminal 1A corresponds to Term1A in the figure, and the external main terminal 3A corresponds to Term3A.

[0095] Term1A is connected to the IGBT chip 31 and the diode chip 32 via L1A and L1B corresponding to the inductance generated by the external main terminal 1A. These semiconductor chips are connected to the IGBT chip 33 and the diode chip 34 via the inductance L21 corresponding to the lead frame 21, and are connected to Term3A via the inductances L22A, L22B, and L13 corresponding to the lead frame 22A and the conductor layer pattern 13, and L3 representing the inductance of the external main terminal 3A.

[0096] The total inductance of the path from Term1A to Term3A is the main circuit inductance Ls. The smaller the value of the inductance Ls, the more surge voltage and the like during switching can be reduced, thereby reducing switching losses.

[0097] according to Fig. 9 as well as Fig.14 In the equivalent circuit shown in FIG. 1 , in the structure of this embodiment, mutual inductances M1-13, M1-22, and M1-3 are generated between the conductor layer pattern 13 and the lead frame 22A (also serving as the external main terminal 3A) with respect to the inductances L1A and L1B. Fig. 9 As shown, the currents flowing between the external main terminal 1A and the external main terminal 3A flow in opposite directions, thereby generating a mutual inductance M and reducing the value of the main circuit inductance Ls. The main circuit inductance Ls is reduced because the sign of the mutual inductance M is opposite to the negative sign of the conductor layer pattern and the lead frame self-inductance constituting Ls.

[0098] Here, use Fig.12 as well as Fig.13 , and Example 1 ( Figure 1 ) structures for comparison.

[0099] exist Fig.12 The cross-sectional structure of Example 1 shown ( Figure 1 In the AA′ cross section of FIG. 1 , a mutual inductance M11 - 13 is generated between the laminated structure of the conductor layer pattern 13 and the lead frame 22 with respect to the conductor layer pattern 11 .

[0100] Fig.13 Example 1 ( Figure 1) is an equivalent circuit of the main circuit inductance path of the power semiconductor module 200. If the main circuit inductance path is focused on, relative to the inductances L1 and L11 generated between the external main terminal 1 and the conductor layer pattern 11, a mutual inductance M1-3 is generated between the conductor layer pattern 13 and the external main terminal 3 in addition to the above-mentioned M11-13.

[0101] If Example 1 ( Figure 1 ) and Example 2 ( Figure 8 ), the lengths of the external main terminal, the conductor layer pattern, and the lead frame are equal, but according to Fig.13 and Fig.14 If the difference in mutual inductance between Example 1 and Example 2 is compared in magnitude, the relationship of formula (1) holds.

[0102] |M1-13+M1-22|>|M11-13|···(Formula 1)

[0103] That is, compared with Example 1 ( Figure 1 ) and the arrangement of the external main terminal 1 and the external main terminal 3, as well as the surrounding conductor layer pattern and the lead frame, by adopting the present embodiment ( Figure 8 ) can increase the value of the mutual inductance that affects the main circuit inductance Ls. Therefore, in this embodiment, the main circuit inductance Ls can be suppressed to be smaller than that of Example 1.

[0104] As described above, the power semiconductor module of this embodiment has an external main terminal 1A electrically connected to the first conductor layer pattern 11, and a portion of the external main terminal 1A is configured to be opposite to the second lead frame 22A via the sealing resin 60 in the configuration surface of each conductor layer pattern 11, 12, and 13 of the insulating substrate 50, and to be opposite to the third conductor layer pattern 13 via the sealing resin 60.

[0105] In addition, the external main terminal 3A is formed integrally with the second lead frame 22A.

[0106] In the present embodiment, the main circuit inductance Ls can be reduced by alleviating stress on the insulating substrate (ceramic substrate) 50 and changing the shape of the external main terminal.

[0107] Therefore, although alumina (Al2O3) substrates are cheap, insulating substrates with weak bending strength can be introduced into resin-sealed power semiconductor modules, reducing the risk of substrate cracks and manufacturing with high yield, thereby achieving low cost of power semiconductor modules.

[0108] In addition, since the main circuit inductance can be reduced, the switching loss can be reduced.

[0109] Example 3

[0110] Reference Fig.11 , a power conversion device according to a third embodiment of the present invention is described. Fig.11 It is a block diagram showing the circuit configuration of the power conversion device of this embodiment.

[0111] exist Fig.11 , an example of a three-phase AC motor driving an axle of an electric vehicle composed of a battery pack 250, a power conversion device 260, and a motor 270 serving as a load is shown.

[0112] The power conversion device 260 of this embodiment includes three one-phase branch circuits composed of two-in-one (2in1) power semiconductor modules 200 or power semiconductor modules 202, a capacitor 240, and a control circuit 230. In addition, the power conversion device 260 includes gate drive circuits 210 (210a to 210c) equal in number to the phases of the AC.

[0113] The power conversion device 260 maintains the main voltage (Vcc) by the capacitor 240, and the gate drive signal of the semiconductor switch element in each power semiconductor module 200 (202) generated by the control circuit 230 is input to each power semiconductor module 200 (202) via the gate drive circuits 210a, 210b, 210c.

[0114] The branch circuits 220 a , 220 b , and 220 c constitute a first-phase inverter branch, a second-phase inverter branch, and a third-phase inverter branch, respectively. The output of each inverter branch is connected to the motor 270 .

[0115] In this embodiment, the branch circuits 220a, 220b, and 220c have the same circuit structure. Therefore, the circuit structure is described by taking the branch circuit 220a as an example.

[0116] The branch circuit 220a includes a pair of upper and lower branches constituted by the power semiconductor module 200a (202a), and a gate drive circuit 210a that performs on / off control of the power semiconductor module 200a (202a).

[0117] According to this embodiment, by using the power semiconductor module described in either Embodiment 1 or Embodiment 2 in the power semiconductor module 200 or the power semiconductor module 202 mounted on the power conversion device 260, the cost of the power conversion device 260 and the electric vehicle motor drive system including the power semiconductor module 200 and the power semiconductor module 202 can be reduced.

[0118] Furthermore, by using the power semiconductor module 202 described in the second embodiment, the main circuit inductance can be reduced, and thus the switching loss can be reduced compared to the conventional module structure.

[0119] Therefore, the power conversion device 260 and the electric vehicle motor drive system including the power conversion device 260 can be made low-cost and low-loss.

[0120] In addition, the present invention is not limited to the above-mentioned embodiments, and includes various modified examples. For example, the above-mentioned embodiments are described in detail in order to explain the present invention in an easy-to-understand manner, and are not necessarily limited to having all the structures described. In addition, a part of the structure of a certain embodiment can be replaced with the structure of another embodiment, and in addition, the structure of another embodiment can be added to the structure of a certain embodiment. In addition, other structures can be added, deleted, or replaced with a part of the structure of each embodiment.

[0121] For example, the sizes and insulation distances of the components constituting the power semiconductor modules 200 and 202 may be arbitrary depending on the application.

[0122] Furthermore, the chip arrangement of the semiconductor switch elements constituting the power semiconductor module 200 and the power semiconductor module 202 is not limited to the illustrated arrangement.

[0123] As the power semiconductor module 200 or the power semiconductor module 202, in addition to the parallel connection of the IGBT and the diode described in each embodiment, it can also be a parallel connection structure of multiple MOSFET chips, a unipolar device such as a JFET (Junction Field Effect Transistor), or a bipolar device such as a BJT (Bipolar Junction Transistor). In addition, depending on the device, the names of the main terminal and the sensing terminal are called "drain" and "source" in addition to the above-mentioned "collector" and "emitter".

[0124] Furthermore, the power conversion device 260 using the power semiconductor module 200 or the power semiconductor module 202 can be applied to a PCS (Power Conditioning System) in a solar power generation device, a railway vehicle electrical system, and the like in addition to a motor drive system for an electric vehicle.

[0125] Explanation of symbols

[0126] 1, 1A—external main terminal (high voltage power supply terminal), 2—external main terminal (AC voltage terminal), 3, 3A—external main terminal (low voltage power supply terminal), 5, 7—signal terminal (gate control terminal), 6, 8—signal terminal (emitter sense terminal), 11—conductor layer pattern (potential of high voltage power supply terminal), 12—conductor layer pattern (potential of AC voltage terminal), 13—conductor layer pattern (potential of low voltage power supply terminal), 14—conductor layer pattern, 15, 18—conductor layer pattern (potential of gate voltage terminal), 16, 19—conductor layer pattern (potential of emitter sense voltage terminal), 21, 22, 22A—lead frame, 25, 27—bonding lead (for gate wiring), 26, 28—bonding lead (for emitter sense wiring) , 31, 33—IGBT chip, 32, 34—diode chip, 50—insulating substrate (ceramic substrate), 60—sealing resin, 61—recess shape (of sealing resin), 71, 72—slit (between conductor layer patterns), 200, 201, 202—power semiconductor module, 210, 210a~210c—gate drive circuit, 220, 220a~220c—branch circuit, 230—control circuit, 240—capacitor, 250—battery pack, 260—power conversion device, 270—motor, 301—collector electrode, 302—emitter electrode, 303—gate electrode, 304—anode electrode, 305—cathode electrode, X1, X4, Y1, Y2, Y3, Y4—distance, T—thickness of sealing resin.

Claims

1. A power semiconductor module, which is a resin-sealed power semiconductor module having no supporting member of an insulating substrate, characterized in that: have: Insulating substrate; A first conductor layer pattern, which is arranged on the insulating substrate; a second conductor layer pattern, which is disposed on the insulating substrate and is electrically insulated from the first conductor layer pattern; a third conductor layer pattern, which is disposed on the insulating substrate and is electrically insulated from the first conductor layer pattern and the second conductor layer pattern; A first semiconductor chip group having one or more semiconductor chips bonded to the first conductor layer pattern; a second semiconductor chip group having one or more semiconductor chips bonded to the second conductor layer pattern; a first lead frame electrically connecting the second conductor layer pattern to the opposite side of the first semiconductor chip group to the bonding surface of the first conductor layer pattern; as well as a second lead frame electrically connecting the side of the second semiconductor chip group opposite to the bonding surface with the second conductor layer pattern and the third conductor layer pattern, The first lead frame and the second lead frame are respectively arranged across a gap between the first conductor layer pattern and the second conductor layer pattern, and are arranged in a layer in a direction perpendicular to a surface of the insulating substrate on which the conductor layer patterns are arranged.

2. The power semiconductor module according to claim 1, characterized in that: The first lead frame and the second lead frame do not overlap each other in a direction perpendicular to a surface of the insulating substrate on which the conductor layer patterns are arranged.

3. The power semiconductor module according to claim 1, characterized in that: The slit is arranged in the central portion of the insulating substrate. The length of the slit is the longest among the plurality of slits formed between the conductor layer patterns on the insulating substrate.

4. The power semiconductor module according to claim 3, characterized in that: A sealing resin is provided, wherein the sealing resin seals the insulating substrate, the first semiconductor chip group, the second semiconductor chip group, the first lead frame, and the second lead frame. The thickness of the sealing resin in a region including at least a portion of the slit is thinner than the thickness of the sealing resin in other regions.

5. The power semiconductor module according to claim 1, characterized in that: Only the sealing resin is arranged on the first lead frame and the second lead frame in a direction perpendicular to the arrangement surface of the insulating substrate on which the conductor layer patterns are arranged.

6. The power semiconductor module according to claim 4, characterized in that: The sealing resin has a concave portion on the surface. The recessed portion is a region where the sealing resin is thin, and has a depth of 2 mm or more.

7. The power semiconductor module according to claim 4, characterized in that: The sealing resin has a concave portion on the surface. The recessed portion is a region where the sealing resin is relatively thin, and has a rectangular shape with a short side of 4 mm or more when the power semiconductor module is viewed from above.

8. The power semiconductor module according to claim 1, characterized in that: having an external terminal electrically connected to the first conductor layer pattern, A part of the external terminal faces the second lead frame via a sealing resin on the arrangement surface of the conductor layer patterns of the insulating substrate, and faces the third conductor layer pattern via a sealing resin.

9. The power semiconductor module according to claim 1, characterized in that: The insulating substrate is a ceramic substrate having aluminum oxide Al2O3 as a main component.

10. The power semiconductor module according to claim 1, characterized in that: At least any one of the joining of the first semiconductor chip group and the first conductor layer pattern, the connection of the first semiconductor chip group and the first lead frame, the joining of the second semiconductor chip group and the second conductor layer pattern, and the connection of the second semiconductor chip group and the second lead frame utilizes the joining or connection of sintered copper.

11. The power semiconductor module according to claim 1, characterized in that: have: A first external terminal electrically connected to the first conductor layer pattern; and a second external terminal electrically connected to the third conductor layer pattern; The second external terminal is formed integrally with the second lead frame.

12. A power conversion device, characterized in that: have: A main circuit having one or more upper and lower branches; and A driving circuit drives the upper and lower branches. The power semiconductor module according to any one of claims 1 to 11 is used in the upper and lower branches.

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