Method for evaluating thermal stability of power MOSFET chip

Abstract

The invention provides a method for evaluating the thermal stability of a power MOSFET chip. The method comprises the following steps: packaging a to-be-evaluated MOSFET chip into a DUT (Device Under Test); calibrating the TSP of the DUT by using semiconductor thermal analysis equipment to obtain calibration parameters; a 10ms current is selected as an evaluation current for heating the DUT, 80% of V (br) dss is selected as an evaluation position, thermal stability evaluation measurement is performed on the DUT, and V (br) dss is a maximum rated value of drain-source voltage; and S103, analyzing the measurement data in the step S103 to obtain a characteristic junction temperature point # imgabs0 # to evaluate the thermal stability of the DUT chip. According to the invention, thermal parameters Tj corresponding to different electrical parameters Vds and Id can be obtained through the in-situ test of the MOSFET, and the height of each characteristic junction temperature point # imgabs1 # on the evaluation position line can be visually seen, so that the thermal stability evaluation of the MOSFET chip becomes simple and clear, the product reliability is improved, and the use risk of a user is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of MOSFET (metal oxide semiconductor field effect transistor) reliability evaluation, and in particular to a method for evaluating the thermal stability of a power MOSFET chip. Background Art

[0002] The statements in this section merely provide background technical information related to the present application and do not necessarily constitute prior art.

[0003] Since the 21st century, with the rapid development of China's economy and society, power MOSFET devices are being widely used in inverters, converters, grid protectors in the field of smart grids, as well as motor drives and power management modules in the field of new energy vehicles due to their excellent performance. However, in these applications, MOSFET devices will experience various natural ambient temperatures, and the thermal stability of the devices becomes very important, especially in high temperature environments.

[0004] At present, the problems faced by domestic power MOSFET manufacturers are: ① When evaluating chip design solutions or facing multiple chip suppliers, they do not know how to optimize or (and) select due to the lack of chip thermal stability evaluation methods; ② my country's current standards and specifications lack evaluation methods for the thermal stability of MOSFET chips.

[0005] Therefore, a method for evaluating the thermal stability of a power MOSFET chip is a technical problem that needs to be solved urgently by technicians in this field. Summary of the invention

[0006] In order to solve or partially solve the problems in the background technology, the present application proposes a method for evaluating thermal stability of a power MOSFET chip.

[0007] The thermal stability evaluation method of a power MOSFET chip provided in the present application comprises the following steps:

[0008] Step S101: packaging the MOSFET chip to be evaluated into a device under test (DUT);

[0009] Step S102: using semiconductor thermal analysis equipment to calibrate the temperature sensitive parameter TSP of the DUT chip junction to obtain calibration parameters;

[0010] Step S103: Select 10ms current as the evaluation current for heating the DUT, and select 80% of V (br)dss As the evaluation position, the DUT is subjected to thermal stability evaluation measurement, V (br)dss is the maximum rated value of drain-source voltage;

[0011] Step S104: Analyze the measurement data of step S103 to obtain the characteristic junction temperature point Evaluate the thermal stability of the DUT chip.

[0012] Preferably, in step S102, the calibration parameters include test current, junction calibration slope and intercept.

[0013] Preferably, in step S103, the method for performing thermal stability evaluation measurement on the DUT is as follows:

[0014] Step (1): Install the DUT into the thermal stability evaluation measurement circuit and set its case temperature T c Adjusted to 25°C and cooled by a cooling device;

[0015] Step (2): Use a 10ms electrical signal to control the on and off of the DUT and monitor the junction temperature T of the DUT j and drain-source voltage V ds , monitoring at different gate voltages V gs and T j The current I flowing through the DUT d ;

[0016] V ds Maintained at 80% of V (br)dss No change, adjust V from zero to large gs Make I d Start from zero and gradually increase until the DUT fails due to thermal breakdown. Record each I d The corresponding T j data;

[0017] During this period, the electrical method was used to measure T j , each time the heating circuit is cut off, T is connected j Measuring circuit, measuring current I sense Equal to the junction calibration current in step S102, used to calculate T j The slope and intercept of are equal to the slope and intercept of the knot calibration in step S102.

[0018] Step (3): Plot the measurement data recorded in step (2) on the evaluation position line, which is the evaluation measurement point of thermal stability.

[0019] Compared with the prior art, the beneficial effects of this application are:

[0020] This application can obtain different electrical parameters V by in-situ testing of MOSFET ds ,I d The corresponding thermal parameter T j , you can intuitively see each characteristic junction temperature point The height above the evaluation position line makes the thermal stability evaluation of MOSFET chips simple and clear, improves product reliability and reduces user risks. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings in the specification, which constitute a part of the present application, are used to provide further understanding of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application.

[0022] Figure 1 This is a schematic diagram of the thermal stability evaluation process of an embodiment of the present application.

[0023] Figure 2 This is a schematic diagram of the measurement circuit principle of an embodiment of the present application.

[0024] Figure 3 The power MOSFET safety interval T of one embodiment of the present application is j Schematic diagram,

[0025] Figure 4 The power MOSFET risk interval T of one embodiment of the present application is j Schematic diagram,

[0026] Figure 5 The power MOSFET out-of-control interval T of one embodiment of the present application j Schematic diagram,

[0027] Figure 6 This is a schematic diagram of an implementation of an embodiment of the present application.

[0028] Figure 7 A schematic diagram of the “bull’s eye” thermal breakdown morphology of a power MOSFET according to an embodiment of the present application.

[0029] The test sample used in the figure is the TO-254 packaged silicon-based enhancement mode MOSFET LYPM4905. DETAILED DESCRIPTION

[0030] The present application is further described below in conjunction with the accompanying drawings and embodiments.

[0031] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0032] In the present disclosure, terms such as "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", "side", "bottom" and the like indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings. They are relational words determined only for the convenience of describing the structural relationships of the various parts or elements of the present disclosure, and do not specifically refer to any part or element in the present disclosure and should not be understood as limitations on the present disclosure.

[0033] Example 1

[0034] like Figures 1 to 7 As shown, the present application provides a method for evaluating thermal stability of a power MOSFET chip, comprising the following steps:

[0035] Step S101: packaging the MOSFET chip to be evaluated into a device under test (DUT);

[0036] Step S102: using semiconductor thermal analysis equipment to calibrate the temperature sensitive parameter TSP of the DUT, and obtaining various calibration parameters, including test current, junction calibration slope and intercept.

[0037] Step S103: Select 10ms current as the evaluation current for heating the DUT chip, and select 80% of V (br)dss As an evaluation position, thermal stability evaluation measurements are performed on the DUT, such as Figure 6 shown.

[0038] Electrical rationality of 10ms current: MOSFET is prone to self-excitation in DC state, making it difficult to achieve T c =25℃, (absolute maximum temperature) test conditions; when the current pulse width is short, the applied power is too high and easily exceeds the detection capability of the MOSFET manufacturer's inspection equipment. Therefore, it is more electrically reasonable to choose a 10ms current for thermal stability evaluation.

[0039] Thermal rationality of 10ms current: For most power MOSFETs, the heat generated in the chip junction by a current not exceeding 10ms generally does not cause a large case temperature rise. Therefore, it is more thermally rational to choose a 10ms current for evaluation.

[0040] The Spirito-Effect states that a higher V ds It has a higher tendency of thermal instability, but the industry does not recommend MOSFET to work at V (br)dss , therefore, choose 80% of V (br)dss It is more reasonable as an "evaluation position".

[0041] The thermal stability evaluation measurement of the DUT includes the following steps:

[0042] Step (1), such as Figure 2 As shown in the figure, install the DUT into the thermal stability evaluation measurement circuit and c Adjust to 25℃ and cool by water (or oil) cooling device.

[0043] Step (2), such as Figure 2 As shown in the figure, a 10ms electrical signal is used to control the on and off of the DUT and monitor the junction temperature T of the DUT. j and drain-source voltage V ds , monitoring at different gate voltages V gs and T j The heating current I flowing through the DUT d .

[0044] According to the Spirito-Effect, V ds Maintained at 80% of V (br)ds No change, adjust V from zero to large gs , so that I d Start from zero and gradually increase until the DUT fails due to thermal breakdown. Record each I d The corresponding T j data;

[0045] During this period, the electrical method was used to measure T j , each time the heating circuit is cut off, T is connected j Measuring circuit, measuring current I sense Equal to the test current in step S102, used to calculate T j The slope and intercept of the calibration are equal to the calibration slope and intercept in step S102, T j The calculation method is as follows:

[0046] T j =m·V j +T0

[0047] Where m is the slope, V j is TSP, T0 is the intercept;

[0048] Step (3), draw the evaluation measurement data points recorded in step (2) on the evaluation position line, that is, the thermal stability evaluation measurement points, such as Figure 6 shown.

[0049] Step S104: Figure 6 As shown, the evaluation measurement data of step S103 is analyzed to find the characteristic junction temperature point of the DUT chip (by adjusting the heating power). Evaluate the thermal stability of MOSFET chips.

[0050] The characteristic junction temperature points of MOSFET chips include but are not limited to the following three:

[0051] (or 175℃)(absolute maximum temperature point);

[0052] (Thermal runaway point);

[0053] (Diffusion point).

[0054] For MOSFET chips, manufacturers usually As the absolute maximum temperature of the entire device That is, the maximum temperature at which the entire device can operate safely.

[0055] Safety interval: When When MOSFET has thermal instability, its junction temperature is less than And it is still controllable, so this range is considered to be the safe range of the device, such as Figure 3 shown.

[0056] Risk range: When the MOSFET's T j tend The risk of thermal runaway is increasing, and the probability is related to T j Therefore, this interval is considered to be a risk interval. In actual tests, it is found that the I d exist When the speed is about 2000, it becomes uncontrollable and the DUT may fail at any time. Figure 4 shown.

[0057] Out of control range: When the MOSFET enters the thermal runaway zone, some areas of the chip surface will heat up faster than other areas, and one of the areas will become a hot spot. The hot spot will spread from the adjacent cells (all with the same V ds and V gs ) where they "grab" the current, causing it to accelerate beyond neighboring cells and reach dangerous speeds. At high temperature, there is enough mutual diffusion between Al (aluminum) and Si (silicon) on the chip surface to form an Al-Si low-resistance interface. In actual testing, it will become more difficult to capture the junction temperature in this range, such as Figure 5 shown.

[0058] when When the chip is melted quickly, it means that the temperature inside the chip must have exceeded like Figure 7 shown.

[0059] In actual testing, it was found that a certain domestic MOSFET chip The following entered the risk range and out-of-control range and eventually failed, showing poor thermal stability.

[0060] It can be seen that for MOSFET chips with the same specifications (mechanical dimensions and electrical parameters), The higher the position of the dot, the better the thermal stability of the chip, the higher its actual power handling capability, and the higher the reliability of the product. Figure 6 As shown in chip B.

[0061] The methods and devices not described in detail in the present invention are all prior art and will not be described in detail.

[0062] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0063] Although the above describes the specific implementation methods of the present application in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present application. Technical personnel in the relevant field should understand that on the basis of the technical solution of the present application, various modifications or deformations that can be made by technical personnel in this field without creative work are still within the scope of protection of the present application.

Claims

1. A method for evaluating thermal stability of a power MOSFET chip, characterized in that: The steps include: Step S101: packaging the MOSFET chip to be evaluated into a device under test (DUT); Step S102: using semiconductor thermal analysis equipment to calibrate the temperature sensitive parameter TSP of the DUT chip junction to obtain calibration parameters; Step S103: Select 10ms current as the evaluation current for heating the DUT, and select 80% of V (br)dss As the evaluation position, the DUT is subjected to thermal stability evaluation measurement, V (br)dss is the maximum rated value of drain-source voltage; Step S104: Analyze the measurement data of step S103 to obtain the characteristic junction temperature point T j Char , evaluate the thermal stability of the DUT chip.

2. The method for evaluating thermal stability of a power MOSFET chip according to claim 1, wherein: In the step S102, the calibration parameters include a test current, a junction calibration slope and an intercept.

3. The method for evaluating thermal stability of a power MOSFET chip according to claim 2, wherein: In step S103, the method for evaluating the thermal stability of the DUT is as follows: Step (1): Install the DUT into the thermal stability evaluation measurement circuit and set the case temperature T c Adjusted to 25°C and cooled by a cooling device; Step (2): Use a 10ms electrical signal to control the on and off of the DUT and monitor the junction temperature T of the DUT j and drain-source voltage V ds , monitoring at different gate voltages V gs and T j The current I flowing through the DUT d ; V ds Maintained at 80% of V (br)dss No change, adjust V from zero to large gs , so that I d Start from zero and gradually increase until the DUT fails due to thermal breakdown. Record each I d The corresponding T j data; During this period, the electrical method was used to measure T j , each time the heating circuit is cut off, T is connected j Measuring circuit, measuring current I sense Equal to the junction calibration current in step S102, used to calculate T j The slope and intercept of are equal to the slope and intercept of the knot calibration in step S102. Step (3): Plot the measurement data recorded in step (2) on the evaluation position line, which is the evaluation measurement point of thermal stability.

Images