Measurement error correction device and method and calibration method
By designing a measurement error correction device in a digital power meter, the delay start control module is used to provide delay data, eliminating the delay difference between voltage and current signals, solving the problem of reduced accuracy of measurement results and achieving higher measurement accuracy.
Patent Information
- Application Number
- CN202411662869.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-20
- Publication Date
- 2025-03-21
AI Technical Summary
The delay difference generated by the voltage and current signals in the digital power meter after passing through the measurement circuit leads to a decrease in the accuracy of the measurement results, affecting the measurement accuracy of active power, reactive power, power factor and phase difference.
A measurement error correction device is designed, including a first data processing module, a second data processing module, a delay start control module and a data reading module. The delay data is provided by the delay start control module to eliminate the delay difference between the voltage signal and the current signal.
By eliminating the delay difference between the voltage signal and the current signal, the accuracy of the measurement results is ensured and the measurement accuracy of active power, reactive power, power factor and phase difference is improved.
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Figure CN119667578A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of power meters, and in particular to a measurement error correction device, method and calibration method. Background Art
[0002] The digital power meter includes voltage and current measurement circuits, ADC, FPGA and CPU. The voltage or current signal is input into the digital power meter, and after being formatted by the measurement circuit, it is sent to the ADC. The ADC reads the voltage and current signals and converts them into digital values, which are then input into the FPGA. The FPGA converts the digital values into measurement values and then sends them to the CPU. The CPU obtains each measurement result based on the measurement value, and the CPU can display the measurement results on the display screen.
[0003] In the related art, the voltage and current measurement circuit includes a frequency measurement circuit, a protection circuit and a multi-stage amplifier circuit. The amplifier circuit includes an operational amplifier, a resistor, a capacitor and an analog switch. The voltage and current signals will produce different degrees of delay after passing through the measurement circuit. There are two reasons for this phenomenon. One is that there is an objective deviation in the resistance and capacitance values; the other is that under different measurement ranges, the operational amplifier has different amplification factors, resulting in inconsistent bandwidth of the amplifier circuit. The delay generated after the voltage signal passes through the voltage measurement circuit is t V The delay caused by the current signal after passing through the current measurement circuit is t I , the delay difference between the voltage and current signals before the measurement circuit is 0, then the delay difference between the voltage and current signals after passing through the measurement circuit is Δt = t V -t I Assuming that the frequency of the voltage and current signals is F, the error caused by Δt on the phase difference measurement is Δθ=Δt*F, the error caused by Δt on the active power measurement is ΔP=U*I*(COS(θ)-COS(θ+Δθ)), and the error caused by Δt on the power factor measurement is Δλ=ΔP / (U*I). According to the reactive power formula Δt will also affect the reactive power measurement. It can be seen that the delay difference between the voltage signal and the current signal after passing through the measurement circuit will reduce the measurement accuracy of active power, reactive power, power factor and phase difference.
[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0005] In view of at least one of the above technical problems, the present application provides a measurement error correction device, method and calibration method.
[0006] In a first aspect, a measurement error correction device is provided, comprising: a first data processing module, a second data processing module, a delay start control module and a data reading module;
[0007] The delayed start control module provides delay data;
[0008] The delayed start control module sends a first start signal to the first data processing module, and sends a second start signal to the second data processing module after the delay data; or the delayed start control module sends a first start signal to the second data processing module, and sends a second start signal to the second data processing module after the delay data;
[0009] The first data processing module obtains a voltage signal according to a signal sent by the delayed start control module; the second data processing module obtains a current signal according to a signal sent by the delayed start control module; the data reading module reads the voltage signal in the first data processing module and reads the current signal in the second data processing module.
[0010] One of the above technical solutions has at least one of the following advantages or beneficial effects: the device is provided with a delayed start control module, and the delayed start control module provides delay data, thereby eliminating the delay difference between the voltage signal and the current signal, thereby ensuring the accuracy of the measurement result.
[0011] In some possible implementations, when the first data processing module acquires the voltage signal, the first data processing module generates a first non-empty flag; when the second data processing module acquires the current signal, the second data processing module generates a second non-empty flag; the data reading module reads the voltage signal and the current signal respectively according to the first non-empty flag and the second non-empty flag.
[0012] In some possible implementations, when the data reading module simultaneously acquires the first non-empty flag and the second non-empty flag, the data reading module reads one data point of the voltage signal and one data point of the current signal.
[0013] In some possible implementations, when the data reading module obtains only the first non-empty flag or the second non-empty flag, the data reading module suspends reading data.
[0014] In some possible implementations, the delayed start control module includes a delay register, and the delay register is used to provide delay data.
[0015] In some possible implementations, when the delay data is a positive value, the delay start control module sends a first start signal to the first data processing module, and sends a second start signal to the second data processing module after the delay data; when the delay data is a negative value, the delay start control module sends a first start signal to the second data processing module, and sends a second start signal to the third data processing module after the delay data.
[0016] In some possible implementations, the first data processing module includes a first sampling module and a first buffer module. The first sampling module obtains the voltage signal according to the signal sent by the delay start control module, and stores the voltage signal in the first buffer module.
[0017] In some possible implementations, the second data processing module includes a second sampling module and a second cache module. The second sampling module obtains the current signal according to the signal sent by the delay start control module, and stores the current signal in the second cache module.
[0018] In a second aspect, a measurement error correction method is provided, which is implemented by a measurement error correction device, the measurement error correction device includes a first data processing module and a second data processing module, and the measurement error correction method includes the following steps:
[0019] Provide delayed data;
[0020] Sending a first start signal to the first data processing module according to the delayed data, and sending a second start signal to the second data processing module after the delayed data; or sending a first start signal to the second data processing module according to the delayed data, and sending a second start signal to the second data processing module after the delayed data;
[0021] The first data processing module is used to obtain a voltage signal according to a signal sent by the delay start control module;
[0022] The second data processing module is used to obtain the current signal according to the signal sent by the delay start control module.
[0023] In a third aspect, a method for calibrating delay data is provided. The calibration method is implemented by a calibration device, the calibration device includes a computer, a calibrator, a power analyzer and a power meter to be calibrated, and the calibration method includes the following steps:
[0024] Step 1: The computer controls the output voltage and current waveform of the calibrator according to the power range of the power meter, and the frequency is F 信号 , the phase angle is Φ;
[0025] Step 2: The computer reads the power factor PF of the power analyzer 分析仪 And the power factor PF of the power meter to be calibrated 功率计, calculate the delay data N of the current power range, the formula is as follows:
[0026]
[0027] Among them, F FPGA is the system frequency of FPGA;
[0028] Step 3: The computer sends the delayed data N to the power meter to be calibrated, and the power meter to be calibrated stores the delayed data N in the internal memory.
[0029] The present application is further described below in conjunction with the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0031] Figure 1 A schematic diagram of the structure of a measurement error correction device provided in an embodiment of the present application; DETAILED DESCRIPTION
[0032] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.
[0033] like Figure 1 As shown, this embodiment provides a measurement error correction device, including: a first data processing module 100, a second data processing module 200, a delay start control module 300 and a data reading module 400. This device is provided with a delay start control module 300, and the delay start control module 300 provides delay data, thereby eliminating the delay difference between the voltage signal and the current signal, thereby ensuring the accuracy of the measurement result.
[0034] The specific structure of the measurement error correction device is introduced below.
[0035] The delayed start control module 300 provides delay data. The delayed start control module 300 includes a delay register, which is used to provide delay data.
[0036] The delayed start control module 300 sends a first start signal to the first data processing module 100, and sends a second start signal to the second data processing module 200 after the delay data; or the delayed start control module 300 sends a first start signal to the second data processing module 200, and sends a second start signal to the second data processing module 200 after the delay data;
[0037] The first data processing module 100 obtains a voltage signal according to a signal sent by the delayed start control module 300; the second data processing module 200 obtains a current signal according to a signal sent by the delayed start control module 300; the data reading module 400 reads the voltage signal in the first data processing module 100, and reads the current signal in the second data processing module 200.
[0038] When acquiring signals, the first data processing module 100 continuously samples the voltage signal at a set sampling rate when acquiring the voltage signal. Similarly, the second data processing module 200 continuously samples the current signal at a set sampling rate when acquiring the current signal.
[0039] like Figure 1 As shown, the first data processing module 100 may include a first sampling module 110 and a first buffer module 120 . The first sampling module 110 acquires a voltage signal according to a signal sent by the delay start control module 300 , and stores the voltage signal in the first buffer module 120 .
[0040] The second data processing module 200 may include a second sampling module 210 and a second buffer module 220 . The second sampling module 210 acquires a current signal according to a signal sent by the delay start control module 300 , and stores the current signal in the second buffer module 220 .
[0041] like Figure 1 As shown, when the first data processing module 100 obtains the voltage signal, the first data processing module 100 generates a first non-empty flag; when the second data processing module 200 obtains the current signal, the second data processing module 200 generates a second non-empty flag; the data reading module 400 reads the voltage signal and the current signal respectively according to the first non-empty flag and the second non-empty flag.
[0042] In the first data processing module 100 , the first sampling module 110 samples the voltage signal and stores the sampled voltage signal in the first cache module 120 . At this time, the first cache module 120 generates a first non-empty flag, which means that there is data in the first cache module 120 .
[0043] Similarly, in the second data processing module 200 , the second sampling module 210 samples the current signal and stores the sampled current signal in the second cache module 220 . At this time, the second cache module 220 generates a second non-empty flag, which means that the second cache module 220 has data.
[0044] When the data reading module 400 obtains the first non-empty flag and the second non-empty flag at the same time, the data reading module 400 reads a data point of the voltage signal and a data point of the current signal. It is worth noting that when the first non-empty flag and the second non-empty flag are valid at the same time, the data reading module 400 will read a data point of the voltage signal and a data point of the current signal at the same time.
[0045] When the data reading module 400 obtains only the first non-empty flag or the second non-empty flag, the data reading module 400 suspends reading data. That is, after the data reading module 400 simultaneously reads a data point of a voltage signal and a data point of a current signal, there is no data in the second cache module 220, the second non-empty flag is invalid, and the data reading module 400 suspends reading data.
[0046] When the second sampling module 210 collects the next data point of the current signal and stores it in the second buffer module 220 , the second non-empty flag becomes effective, and the data reading module 400 restarts reading data.
[0047] In addition, the delay data can determine the order of the first data processing module 100 and the second data processing module 200. When the delay data is a positive value, the delay start control module 300 sends a first start signal to the first data processing module 100, and sends a second start signal to the second data processing module 200 after the delay data; when the delay data is a negative value, the delay start control module 300 sends a first start signal to the second data processing module 200, and sends a second start signal to the second data processing module after the delay data.
[0048] The measurement error correction device implements a measurement error correction method. The measurement error correction device includes a first data processing module 100 and a second data processing module 200. The measurement error correction method includes the following steps:
[0049] Provide delayed data;
[0050] Sending a first start signal to the first data processing module 100 according to the delayed data, and sending a second start signal to the second data processing module 200 after the delayed data; or sending a first start signal to the second data processing module 200 according to the delayed data, and sending a second start signal to the second data processing module 200 after the delayed data;
[0051] The first data processing module 100 is used to obtain a voltage signal according to a signal sent by the delay start control module 300;
[0052] The second data processing module 200 is used to obtain a current signal according to the signal sent by the delay start control module 300.
[0053] In addition, this embodiment also provides a calibration method for delay data, the calibration method is implemented by a calibration device, the calibration device includes a computer, a calibrator, a power analyzer and a power meter to be calibrated, and the calibration method includes the following steps:
[0054] Step 1: The computer controls the output voltage and current waveform of the calibrator according to the power range of the power meter, and the frequency is F 信号 , the phase angle is Φ;
[0055] Step 2: The computer reads the power factor PF of the power analyzer 分析仪 And the power factor PF of the power meter to be calibrated 功率计 , calculate the delay data N of the current power range, the formula is as follows:
[0056]
[0057] Among them, F FPGA is the system frequency of FPGA;
[0058] Step 3: The computer sends the delayed data N to the power meter to be calibrated, and the power meter to be calibrated stores the delayed data N in the internal memory.
[0059] In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.
[0060] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features.
[0061] In addition, various aspects or features of the present application can be implemented as methods, devices or products using standard programming and / or engineering techniques. The term "product" used in this application covers computer programs that can be accessed from any computer-readable device, carrier or medium. For example, computer-readable media may include, but are not limited to: magnetic storage devices (e.g., hard disks, floppy disks or tapes, etc.), optical disks (e.g., compact discs (CDs), digital versatile discs (DVDs), etc.), smart cards and flash memory devices (e.g., erasable programmable read-only memory (EPROM), cards, sticks or key drives, etc.). In addition, the various storage media described herein may represent one or more devices and / or other machine-readable media for storing information. The term "machine-readable medium" may include, but is not limited to, wireless channels and various other media capable of storing, containing and / or carrying instructions and / or data.
[0062] It should also be understood that in the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.
[0063] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.
[0064] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.
[0065] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described below are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, or can be electrical, mechanical or other forms of connection.
[0066] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of the present application.
[0067] The above are only preferred embodiments of the present application, and do not constitute any formal limitation on the present application. Any technician familiar with the art can use the above disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment of equivalent changes. Therefore, all equivalent changes made according to the shape, structure and principle of the present application without departing from the content of the technical solution of the present application should be included in the protection scope of the present application.
Claims
1. A measurement error correction device, characterized in that: include: A first data processing module, a second data processing module, a delayed start control module and a data reading module; The delayed start control module provides delay data; The delayed start control module sends a first start signal to the first data processing module, and sends a second start signal to the second data processing module after the delay data; or the delayed start control module sends a first start signal to the second data processing module, and sends a second start signal to the second data processing module after the delay data; The first data processing module obtains a voltage signal according to the signal sent by the delayed start control module; the second data processing module obtains a current signal according to the signal sent by the delayed start control module; the data reading module reads the voltage signal in the first data processing module, and reads the current signal in the second data processing module.
2. The measurement error correction device according to claim 1, characterized in that: When the first data processing module acquires the voltage signal, the first data processing module generates a first non-empty flag; when the second data processing module acquires the current signal, the second data processing module generates a second non-empty flag; The data reading module reads the voltage signal and the current signal respectively according to the first non-empty flag and the second non-empty flag.
3. The measurement error correction device according to claim 2, characterized in that: When the data reading module simultaneously acquires the first non-empty flag and the second non-empty flag, the data reading module reads one data point of the voltage signal and reads one data point of the current signal.
4. The measurement error correction device according to claim 3, characterized in that: When the data reading module obtains only the first non-empty flag or the second non-empty flag, the data reading module suspends reading data.
5. The measurement error correction device according to claim 1, characterized in that: The delayed start control module includes a delay register, and the delay register is used to provide the delay data.
6. The measurement error correction device according to claim 5, characterized in that: When the delay data is a positive value, the delay start control module sends a first start signal to the first data processing module, and sends a second start signal to the second data processing module after the delay data; when the delay data is a negative value, the delay start control module sends a first start signal to the second data processing module, and sends a second start signal to the second data processing module after the delay data.
7. The measurement error correction device according to claim 1, characterized in that: The first data processing module includes a first sampling module and a first buffer module. The first sampling module obtains a voltage signal according to a signal sent by the delay start control module, and stores the voltage signal in the first buffer module.
8. The measurement error correction device according to claim 1, characterized in that: The second data processing module includes a second sampling module and a second buffer module. The second sampling module obtains a current signal according to a signal sent by the delay start control module, and stores the current signal in the second buffer module.
9. A measurement error correction method, implemented by the measurement error correction device according to claim 1, characterized in that: The measurement error correction device comprises a first data processing module and a second data processing module, and the measurement error correction method comprises the following steps: Provide delayed data; Sending a first start signal to the first data processing module according to the delayed data, and sending a second start signal to the second data processing module after the delayed data; or sending a first start signal to the second data processing module according to the delayed data, and sending a second start signal to the second data processing module after the delayed data; The first data processing module is used to obtain a voltage signal according to the signal sent by the delay start control module; The second data processing module is used to obtain a current signal according to the signal sent by the delay start control module.
10. A method for calibrating the delay data of claim 1, wherein the method is implemented by a calibration device, the calibration device comprising a computer, a calibrator, a power analyzer and a power meter to be calibrated, characterized in that: The calibration method comprises the following steps: Step 1: The computer controls the output voltage and current waveform of the calibrator according to the power range of the power meter, and the frequency is F 信号 , the phase angle is Φ; Step 2: The computer reads the power factor PF of the power analyzer 分析仪 And the power factor PF of the power meter to be calibrated 功率计 , calculate the delay data N of the current power range, the formula is as follows: Among them, F FPGA is the system frequency of FPGA; Step 3: The computer sends the delayed data N to the power meter to be calibrated, and the power meter to be calibrated stores the delayed data N in the internal memory.