Online updating method and device based on PCIe rescanning

Abstract

The embodiment of the invention relates to the technical field of electronic engineering and computer science, and discloses an online updating method and device based on PCIe rescanning, and the method comprises the steps: carrying out the initialization of FPGA equipment, so as to enable the FPGA equipment to prepare to receive to-be-updated data; sending to-be-updated data to the FPGA equipment, so that the FPGA equipment loads the to-be-updated data to a configuration memory of the FPGA equipment; closing an FPGA equipment file, carrying out reverse initialization on the FPGA equipment, and releasing resources applied in the initialization process of the FPGA equipment; the rescanning PCIe equipment is used for reidentifying and configuring the FPGA equipment; and the FPGA equipment file is reopened, and access to the FPGA equipment is recovered, so that the problems of long downtime, complex operation, poor system stability and the like in the existing FPGA upgrading technology are solved.

Description

Technical Field

[0001] The embodiments of the present application relate to the fields of electronic engineering and computer science technology, and in particular to an online update method and device based on PCIe rescanning. Background Art

[0002] With the rapid development of information technology, Field-Programmable Gate Array (FPGA) is widely used in many fields such as communication, automation, aerospace, medical equipment, etc. due to its high flexibility and reconfigurability. The application of FPGA enables complex hardware design to flexibly respond to changing requirements and standards. However, as the application evolves, FPGA program upgrades become particularly important to ensure that it can meet new functional requirements and performance standards.

[0003] PCIe (Peripheral Component Interconnect Express, PCI-Express) is a high-speed serial computer expansion bus standard. PCIe belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission. The connected devices are allocated exclusive channel bandwidth and do not share bus bandwidth. It mainly supports active power management, error reporting, end-to-end reliable transmission, hot plugging, and quality of service (QOS) and other functions.

[0004] The traditional method of upgrading FPGA programs is usually through the JTAG (Joint Test Action Group) interface. Connect the JTAG programmer to the JTAG interface of the FPGA, connect the programmer to the PC or development equipment, run the FPGA development tool on the PC, and load the new FPGA configuration file. The main disadvantages of this method are:

[0005] 1. Slow update speed: The JTAG interface has a low transmission rate, and data is transmitted bit by bit. For larger configuration files, the transmission time may be longer, especially on large-capacity FPGAs, and the upgrade process may be time-consuming.

[0006] 2. Difficult to achieve remote upgrade: The JTAG interface is usually a local connection and it is difficult to support remote operation, which limits the flexibility and maintainability of the device after field deployment.

[0007] 3. Long system downtime: JTAG programming requires the system to be completely suspended, and the device is in a downtime state during the upgrade. Especially in scenarios where high availability needs to be maintained, long downtime will affect the stability and continuity of the system.

[0008] 4. Lack of redundancy mechanism: JTAG programming directly overwrites the FPGA configuration. Once an error occurs during the programming process (such as data transmission error or power failure), the FPGA may not start normally, and the device needs to be reprogrammed or even restored to normal operation by other means.

[0009] In response to these problems, a variety of online upgrade solutions have been proposed in recent years to reduce downtime and operational complexity. Among them, FPGA partial reconfiguration is a method that allows dynamic updates in certain areas of the FPGA without affecting the entire design. Partial reconfiguration requires special planning and management of FPGA design, which increases the complexity of the design. Designers need to consider the boundaries, interfaces, and data flows of the reconfigured area, which makes the design process more cumbersome. Although FPGA partial reconfiguration provides a certain degree of flexibility and resource utilization efficiency, its complexity, stability, performance, debugging, and compatibility issues during the online upgrade process may limit its effectiveness and wide application in certain application scenarios.

[0010] Therefore, developing an efficient, stable and easy-to-operate online FPGA program upgrade method has become a technical problem that needs to be solved urgently. Summary of the invention

[0011] The purpose of the embodiments of the present application is to provide an online update method and device based on PCIe rescanning to solve the problems of long downtime, complex operation and poor system stability in the existing FPGA upgrade technology. It is suitable for scenarios with high requirements for system real-time performance, such as embedded systems, communication equipment and industrial automation control systems, and significantly improves the system availability and maintenance efficiency.

[0012] According to some embodiments of the present application, a first aspect of the embodiments of the present application provides an online update method based on PCIe rescanning, which initializes an FPGA device to prepare the FPGA device for receiving data to be updated; sends the data to be updated to the FPGA device so that the FPGA device loads the data to be updated into the configuration memory of the FPGA device; closes the FPGA device file, deinitializes the FPGA device, and releases the resources applied for during the initialization of the FPGA device; rescans the PCIe device to re-identify and configure the FPGA device; reopens the FPGA device file to restore access to the FPGA device.

[0013] According to some embodiments of the present application, the second aspect of the embodiments of the present application also provides an online update device based on PCIe rescanning, including: an initialization module: used to initialize the FPGA device so that the FPGA device is ready to receive the data to be updated; a receiving module, used to send the data to be updated to the FPGA device, so that the FPGA device loads the data to be updated into the configuration memory of the FPGA device, and the data to be updated is a bin file to be upgraded; a de-initialization module: used to close the FPGA device file, de-initialize the FPGA device, and release the resources applied for during the initialization process of the FPGA device; a rescan module: used to rescan the PCIe device, and to re-identify and configure the FPGA device; a recovery module: used to reopen the FPGA device file and restore access to the FPGA device.

[0014] According to some embodiments of the present application, a third aspect of the embodiments of the present application also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the online update method based on PCIe rescanning as described above.

[0015] According to some embodiments of the present application, a fourth aspect of the embodiments of the present application further provides a computer-readable storage medium, which, when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, performs the online update method based on PCIe rescanning as described above.

[0016] According to some embodiments of the present application, a fifth aspect of the embodiments of the present application further provides a computer program product, including a computer program, which implements the above-mentioned online update method based on PCIe rescanning when executed by a processor.

[0017] The technical solution provided in the embodiment of the present application has at least the following advantages:

[0018] After the FPGA device is initialized, the data to be updated is sent to the FPGA device so that the FPGA device loads the data to be updated into the configuration memory of the FPGA device to complete the data update. The updated FPGA device is re-identified and configured through the rescan of the PCIe bus to adapt to the updated device characteristics, thereby updating the FPGA online without restarting the system, avoiding the downtime caused by completely restarting the device in the traditional method, enabling the system to continue to provide services, thereby improving the user experience and enhancing the availability of the system; through a reasonable management process for FPGA device files, including opening, closing, and reopening of device files, the system is ensured to have stable access and control of the FPGA device at all stages of the firmware update, reducing dependence on manual operations and reducing the risk of system failures caused by human errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0020] Figure 1 It is a flow chart of an online update method based on PCIe rescanning according to an embodiment of the present application;

[0021] Figure 2 is a schematic diagram of an online update device based on PCIe rescanning according to an embodiment of the present application;

[0022] Figure 3 is a schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0023] In the related art, the FPGA program upgrade method is usually carried out through the JTAG interface, connecting the JTAG programmer to the JTAG interface of the FPGA, and connecting the programmer to the PC or development equipment, running the FPGA development tool on the PC, and loading the new FPGA configuration file. The main disadvantages of this method include: slow update speed: the JTAG interface has a low transmission rate, and the data is transmitted bit by bit. For larger configuration files, the transmission time may be longer, especially on large-capacity FPGAs, the upgrade process may be time-consuming; it is difficult to achieve remote upgrades: the JTAG interface is usually a local connection, and it is difficult to support remote operation, which limits the flexibility and maintainability of the equipment after field deployment; the system downtime is long: JTAG programming requires the system to be completely suspended, and the equipment is in a downtime state during the upgrade. Especially in scenarios where high availability needs to be maintained, long downtime will affect the stability and continuity of the system; lack of redundancy mechanism: JTAG programming directly overwrites the FPGA configuration. Once an error occurs during the programming process (such as data transmission error or power failure), the FPGA may not start normally, and the device needs to be reprogrammed or even restored to normal operation by other means.

[0024] In the related technology, online upgrade can be achieved through FPGA partial reconfiguration (PR), which allows dynamic reconfiguration of specific areas of the FPGA without stopping the operation of the entire FPGA. PR technology supports the reconstruction of part of the FPGA's logic resources without interfering with other running logic modules. However, partial reconstruction requires special planning and management of FPGA design, which increases the complexity of the design. Designers need to consider the boundaries, interfaces and data flows of the reconstruction area, which makes the design process more cumbersome. Although FPGA partial reconstruction provides a certain degree of flexibility and resource utilization efficiency, its complexity, stability, performance, debugging and compatibility issues during the online upgrade process limit its effectiveness and wide application in certain application scenarios.

[0025] Based on this, an embodiment of the present application provides an online update method based on PCIe rescanning, which initializes the FPGA device, sends the data to be updated to the FPGA device, so that the FPGA device loads the data to be updated into the configuration memory of the FPGA device, closes the FPGA device file, and releases resources; rescans the PCIe device; reopens the FPGA device file to restore access to the FPGA device; reads the updated version and verifies the updated version to implement an online update method for the FPGA program, so as to solve the problems of long downtime, complex operation and poor system stability existing in the existing FPGA upgrade technology.

[0026] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in the present application, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can also be implemented. The division of the following embodiments is for the convenience of description, and the specific implementation of the present application should not be construed as any limitation, and the various embodiments can be combined and referenced with each other under the premise of no contradiction.

[0027] An embodiment of the present application relates to an online update method based on PCIe rescanning, which is applied to a device including a PCIe bus. The method includes: initializing an FPGA device so that the FPGA device is ready to receive data to be updated; sending the data to be updated to the FPGA device so that the FPGA device loads the data to be updated into the configuration memory of the FPGA device; closing the FPGA device file, deinitializing the FPGA device, and releasing the resources applied for during the initialization of the FPGA device; rescanning the PCIe device to re-identify and configure the FPGA device; reopening the FPGA device file to restore access to the FPGA device. The implementation details of the online update method based on PCIe rescanning of an embodiment of the present invention are described in detail below. The following content is only the implementation details provided for easy understanding and is not necessary for the implementation of this solution. Figure 1 As shown, the following steps are included:

[0028] Step S11, initializing the FPGA device so that the FPGA device is ready to receive data to be updated.

[0029] Before initializing the FPGA device, the process also includes: opening the FPGA device file to ensure that the FPGA device can be read and written; and accessing the status and configuration information of the FPGA device to prepare for subsequent initialization and data transmission operations.

[0030] The FPGA device file is a device file created by the driver of the FPGA device when it recognizes the FPGA hardware device. The application can access the FPGA hardware device through this file. The system first opens the file interface of the FPGA device to ensure that it can read and write to the FPGA device. After opening the file, the system can access the FPGA device to prepare for subsequent initialization and data transmission operations.

[0031] After the device file is opened, the system initializes the FPGA device to ensure that the device can receive update data. The system initializes the FPGA device by obtaining and mapping the register base address of the FPGA device, applying for DMA memory, and sending the DMA memory address to the FPGA device through the register, resetting the FPGA device, and reading the current state of the FPGA device through the register to see if it is abnormal. The above steps ensure that the FPGA can receive new firmware data.

[0032] Direct Memory Access (DMA) is a technology for efficient data transfer that allows data to be exchanged directly between peripherals and memory without CPU intervention. DMA can significantly reduce CPU load and improve data transfer efficiency.

[0033] In an embodiment of the present application, the data to be updated is a bin file to be upgraded. The bin file is a binary file containing FPGA configuration data and is used to program and configure the FPGA.

[0034] The order of initializing the FPGA device is: get the mapping register -> reset the FPGA -> check the FPGA status -> apply for DMA and write the address. The details are as follows:

[0035] Acquiring and mapping the register base address of the FPGA device are both implemented through the interface provided by the system. The interface under the Linux system includes obtaining the starting position and length of the PCI resource (pci_resource_start, pci_resource_len) and address mapping (pci_iomap).

[0036] Reset the FPGA device: Tell the FPGA to reset by writing registers, so as to restore the FPGA to its initial state. After the FPGA reset is completed, the reset completion state (ie, the initial state) will be written into the corresponding register.

[0037] The program checks whether the current state of the FPGA device is abnormal by reading the corresponding registers: the purpose is to check whether the FPGA is in the initial state.

[0038] Applying for DMA memory and sending the DMA memory address to the FPGA device through a register is because the transmission of the bin file is carried out through the DMA memory, so the FPGA device must know the address of the DMA memory to read the contents of the bin file from the DMA.

[0039] Step S12: sending the data to be updated to the FPGA device, so that the FPGA device loads the data to be updated into the configuration memory of the FPGA device.

[0040] The manner in which the FPGA device loads the data to be updated into the configuration memory of the FPGA device includes:

[0041] A bin file to be upgraded is received, where the bin file to be upgraded is data transmitted from the CPU to the FPGA device through the DMA memory.

[0042] The DMA transmission method can efficiently transfer data to the FPGA device in a short time, ensuring data integrity and transmission speed. The bin file containing the FPGA program is transferred to the FPGA device through DMA.

[0043] The bin file to be upgraded is written into the non-volatile memory (FLASH) of the FPGA device for storage. After the FPGA device receives the bin file, it writes the bin file in blocks into a specific location of the FLASH through an interface such as a serial peripheral interface (SPI) or QSPI (Quad SPI), so that a new program can be loaded after the device is restarted or reset.

[0044] The bin file to be upgraded is loaded from the FLASH storage of the FPGA device to the configuration memory of the FPGA device to complete the program update.

[0045] After the bin file is written, the controller triggers a soft reset instruction, and the FPGA device enters the reconfiguration mode without powering off. The FPGA reads the new configuration file (bin file) from the specific address of the Flash, and loads its data into the FPGA's configuration memory through the ICAP interface, thereby completing the dynamic reconfiguration of the logic and completing the program update. This process ensures that the FPGA loads a new bin file without powering off to meet new business needs or function update requirements.

[0046] Step S13, closing the FPGA device file, deinitializing the FPGA device, and releasing the resources applied for during the initialization process of the FPGA device.

[0047] After the firmware update is completed, the FPGA has new business features. The FPGA device can no longer be accessed through the previously opened device file handle. At this time, the system needs to close the FPGA device file. Some resources are applied for during initialization, such as DMA memory and mapping register addresses. After closing the FPGA device file, these resources are released to prepare for rescanning the device.

[0048] Step S14, rescanning the PCIe device to re-identify and reconfigure the FPGA device.

[0049] Since the FPGA device has loaded a new bin file, the resource allocation, device ID, and functional characteristics of the PCIe endpoint may change. From the system perspective, it looks like a "new device". Therefore, after closing the device file, rescan the PCIe bus to re-identify and reconfigure the FPGA device to adapt to the new device characteristics.

[0050] The PCIe endpoint (PCI Express Endpoint) is a device in the PCI Express bus architecture. It is a peripheral device that communicates with the host system (Root Complex) through the PCIe bus. The endpoint device is usually the implementer of the functional module, such as the network interface card (NIC), storage controller, graphics processing unit (GPU), and FPGA.

[0051] The receiving system initiates a request to rescan the PCIe bus, the purpose of which is to allow the system to re-identify the devices on the PCIe bus, including the FPGA device; the rescan process is triggered by a software instruction, and the driver of the FPGA device is automatically detected and reloaded. After rescanning the PCIe bus, it is detected whether the FPGA device is successfully identified. If the identification is successful, the system will proceed to the next step; if the FPGA device is not identified, the rescan operation is repeated until the updated FPGA device is successfully identified.

[0052] Step S15, reopening the FPGA device file to restore access to the FPGA device.

[0053] After successfully identifying the FPGA device, the system reopens the FPGA device file and restores access to the FPGA device. This step ensures that the FPGA device can be re-identified and accessed by the system so that new business operations can be performed.

[0054] In an embodiment of the present application, the method further includes reading an updated version and verifying the updated version.

[0055] After reopening the FPGA device file, read the updated version of the firmware from the FPGA register for verification. This step is used to ensure that the FPGA firmware has been updated successfully.

[0056] Finally, the system starts to perform a series of business operations on the FPGA device, such as data processing, control signal output, etc., to meet the business needs of the device. Through this method, the system successfully completes the online update of the FPGA program without the need for a complete restart, realizing the real-time upgrade and function expansion of the FPGA.

[0057] In an embodiment of the present invention, the data to be updated is sent to the FPGA device so that the FPGA device loads the data to be updated into the configuration memory of the FPGA device to complete the data update. The updated FPGA device is re-identified and configured by rescanning the PCIe bus to adapt to the updated device characteristics, thereby performing online update on the FPGA without restarting the system, avoiding the downtime caused by completely restarting the device in traditional methods, enabling the system to continue to provide services, thereby improving the user experience and enhancing the availability of the system; by performing a reasonable management process for FPGA device files, including opening, closing, and reopening of device files, the system is ensured to have stable access and control of the FPGA device at each stage of the firmware update, thereby reducing dependence on manual operations and reducing the risk of system failures due to human errors.

[0058] The steps of the above method are divided only for the purpose of clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent; adding insignificant modifications to the algorithm or process or introducing insignificant designs without changing the core design of the algorithm and process are all within the scope of protection of this patent.

[0059] In addition, the examples mentioned in the above embodiments can be freely combined, and any combination can be understood as an embodiment. The "embodiment" or "example" appearing in various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It can be understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0060] Another embodiment of the present invention relates to an online update device 200 based on PCIe rescanning, such as Figure 2 As shown, including:

[0061] Initialization module 201: used to initialize the FPGA device so that the FPGA device is ready to receive data to be updated.

[0062] The receiving module 202 is used to send the data to be updated to the FPGA device, so that the FPGA device loads the data to be updated into the configuration memory of the FPGA device.

[0063] Deinitialization module 203: used to close the FPGA device file, deinitialize the FPGA device, and release the resources applied during the initialization process of the FPGA device.

[0064] Rescan module 204: used to rescan PCIe devices to re-identify and reconfigure the FPGA device;

[0065] Restoration module 205: used to reopen the FPGA device file and restore access to the FPGA device.

[0066] In some embodiments, before initializing the FPGA device, the method further includes: opening the FPGA device file to perform read and write operations on the FPGA device; and accessing the status and configuration information of the FPGA.

[0067] In some embodiments, the initialization of the FPGA device to prepare the FPGA device to receive data to be updated includes: obtaining and mapping the register base address of the FPGA device; applying for DMA memory, and sending the DMA memory address to the FPGA device via a register; resetting the FPGA device; and reading via a register whether the current state of the FPGA device is abnormal.

[0068] In some embodiments, the data to be updated is a bin file to be upgraded, and the way in which the FPGA device loads the data to be updated into the configuration memory of the FPGA device includes: receiving the bin file to be upgraded, and the bin file to be upgraded is data transmitted to the FPGA device by the CPU through the DMA memory; writing the bin file to be upgraded into the FLASH storage of the FPGA device; loading the bin file to be upgraded from the FLASH storage of the FPGA device to the configuration memory of the FPGA device.

[0069] In some embodiments, rescanning the PCIe device to re-identify and configure the FPGA device includes: receiving a request initiated by the system to rescan the PCIe bus; automatically detecting and reloading the driver of the FPGA device; detecting whether the FPGA device is successfully identified, and if the FPGA device is not identified, repeating the rescan operation until the FPGA device is successfully identified.

[0070] In some embodiments, the online update method based on PCIe rescanning further includes: reading an updated version, and verifying the updated version.

[0071] In an embodiment of the present invention, after the FPGA device is initialized, the data to be updated is sent to the FPGA device so that the FPGA device loads the data to be updated into the configuration memory of the FPGA device to complete the data update. The updated FPGA device is re-identified and configured by rescanning the PCIe bus to adapt to the updated device characteristics, thereby performing an online update on the FPGA without restarting the system, avoiding the downtime caused by completely restarting the device in traditional methods, enabling the system to continue to provide services, thereby improving the user experience and enhancing the availability of the system; by performing a reasonable management process for FPGA device files, including opening, closing, and reopening of device files, the system is ensured to have stable access and control of the FPGA device at each stage of the firmware update, thereby reducing dependence on manual operations and reducing the risk of system failures caused by human errors.

[0072] It is not difficult to find that this embodiment is a device embodiment corresponding to the above method embodiment, and this embodiment can be implemented in conjunction with the above method embodiment. The relevant technical details mentioned in the above method embodiment are still valid in this embodiment, and in order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the above method embodiment.

[0073] It is worth mentioning that all modules involved in this embodiment are logic modules. In practical applications, a logic unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of the present invention, this embodiment does not introduce units that are not closely related to solving the technical problem proposed by the present invention, but this does not mean that there are no other units in this embodiment.

[0074] Another embodiment of the present application relates to an electronic device 300, see Figure 3 , including: a processor 301, a memory 302, and a computer program stored in the memory 302 and executable on the processor 301, such as a data processing program. When the processor 301 executes the computer program, the steps in the above-mentioned embodiments of the online update method based on PCIe rescanning are implemented, such as Figure 1 Steps S11-S15 are shown.

[0075] Exemplarily, the computer program may be divided into one or more modules / units, which are stored in the memory 302 and executed by the processor 301 to complete the present application. The one or more modules / units may be a series of computer program instruction segments capable of completing specific functions, which are used to describe the execution process of the computer program in the electronic device.

[0076] The electronic device may be a computing device such as a desktop computer, a notebook, a PDA, and a cloud server. The electronic device may include, but is not limited to, a processor 301 and a memory 302. Those skilled in the art will appreciate that the schematic diagram is merely an example of an electronic device and does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the diagram, or may combine certain components, or different components. For example, the electronic device may also include an input / output device, a network access device, a bus, etc.

[0077] The processor 301 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor 301 may also be any conventional processor, etc. The processor 301 is the control center of the electronic device, and uses various interfaces and lines to connect various parts of the entire electronic device.

[0078] The memory 302 can be used to store the computer program and / or module, and the processor 301 realizes various functions of the electronic device by running or executing the computer program and / or module stored in the memory 302, and calling the data stored in the memory 302. The memory 302 can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the mobile phone (such as audio data, a phone book, etc.), etc. In addition, the memory 302 can include a high-speed random access memory, and can also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (SecureDigital, SD) card, a flash card (Flash Card), at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0079] Wherein, if the module / unit integrated in the electronic device is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor 301. Wherein, the computer program includes a computer program code, and the computer program code can be in the form of source code, object code, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a U disk, a mobile hard disk, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), an electrical carrier signal, a telecommunication signal, and a software distribution medium.

[0080] Another embodiment of the present application provides a computer-readable storage medium, on which programs or instructions are stored. When the programs or instructions are executed by a processor, the various processes of an embodiment of an online update method based on PCIe rescanning such as any of the above are implemented, and the same technical effect can be achieved. To avoid repetition, they are not repeated here.

[0081] Computer readable media include permanent and non-permanent, removable and non-removable media, and can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0082] Another embodiment of the present application further provides a computer program product, including computer instructions, which, when executed by a processor, implement the above Figure 1 The various processes of any of the embodiments of the online update method based on PCIe rescanning shown in the figure can achieve the same technical effect. To avoid repetition, they will not be described again here.

[0083] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0084] It should be noted that the collection, collection, updating, analysis, processing, use, transmission, storage and other aspects of user personal information involved in the technical solution of this disclosure are in compliance with the provisions of relevant laws and regulations, are used for legitimate purposes, and do not violate public order and good morals. Necessary measures are taken for user personal information to prevent illegal access to user personal information data and maintain the security of user personal information and network security.

[0085] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0086] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a service classification device (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0087] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. An online update method based on PCIe rescanning, characterized in that: include: Initializing the FPGA device so that the FPGA device is ready to receive data to be updated; Sending the data to be updated to the FPGA device, so that the FPGA device loads the data to be updated into the configuration memory of the FPGA device; Close the FPGA device file, deinitialize the FPGA device, and release the resources applied for during the initialization of the FPGA device; Rescanning PCIe devices to re-identify and reconfigure the FPGA device; Reopen the FPGA device file to restore access to the FPGA device.

2. The online update method based on PCIe rescanning as claimed in claim 1, characterized in that: Before initializing the FPGA device, the method further includes: Open the FPGA device file and perform read and write operations on the FPGA device; Access FPGA status and configuration information.

3. The online update method based on PCIe rescanning as claimed in claim 1, characterized in that: Initializing the FPGA device so that the FPGA device is ready to receive the data to be updated includes: Obtain and map the register base address of the FPGA device; Apply for DMA memory, and send the DMA memory address to the FPGA device via a register; Resetting the FPGA device; Read through the register whether the current state of the FPGA device is abnormal.

4. The online update method based on PCIe rescanning according to claim 3, wherein the data to be updated is a bin file to be upgraded, wherein: The manner in which the FPGA device loads the data to be updated into the configuration memory of the FPGA device includes: Receive a bin file to be upgraded, where the bin file to be upgraded is data transmitted from the CPU to the FPGA device through the DMA memory; Writing the bin file to be upgraded into the FLASH storage of the FPGA device; The bin file to be upgraded is loaded from the FLASH storage of the FPGA device to the configuration memory of the FPGA device.

5. The online update method based on PCIe rescanning as claimed in claim 1, characterized in that: The rescanning of the PCIe device to re-identify and reconfigure the FPGA device includes: A request for rescanning the PCIe bus initiated by a receiving system; Automatically detect and reload the driver of the FPGA device; Detect whether the FPGA device is successfully identified. If the FPGA device is not identified, repeat the rescan operation until the FPGA device is successfully identified.

6. The online update method based on PCIe rescanning as claimed in claim 1, characterized in that: Also includes: The updated version is read and verified.

7. An online update device based on PCIe rescanning, characterized in that: The online update device based on PCIe rescanning includes: Initialization module: used to initialize the FPGA device so that the FPGA device is ready to receive the data to be updated; A receiving module, used for sending the data to be updated to the FPGA device, so that the FPGA device loads the data to be updated into the configuration memory of the FPGA device; Deinitialization module: used to close the FPGA device file, deinitialize the FPGA device, and release the resources applied during the initialization process of the FPGA device; Rescan module: used to rescan PCIe devices, and to re-identify and configure the FPGA device; Restoration module: used for reopening the FPGA device file and restoring access to the FPGA device.

8. An electronic device, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: When the instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the method as claimed in any one of claims 1 to 6.

10. A computer program product, characterized in that The method comprises a computer program, which implements the method according to any one of claims 1 to 6 when being executed by a processor.

Images