FPGA-based circuit automatic generation method and system

Abstract

The present invention relates to the technical field of automatic circuit generation, and is a method and system for automatic circuit generation based on FPGA, comprising: inputting circuit design requirements into the module generation model to obtain an initial circuit function module set, normalizing the initial module characteristic parameter set to obtain a standard module characteristic parameter set, inputting the standard module characteristic parameter set into a module splicing model to obtain a module splicing circuit, performing simulation test according to an HDL file to obtain a simulation test result, judging whether the simulation test result meets the simulation test standard, if not, performing model tuning, if yes, performing performance test according to the HDL file to obtain a performance test result, judging whether the performance test result meets the performance test standard, if not, performing model tuning on the module splicing model, if yes, constructing an FPGA configuration file according to the HDL file. The present invention can solve the problems of long circuit design cycle and low efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of automatic circuit generation, and in particular to an automatic circuit generation method and system based on FPGA. Background Art

[0002] Current FPGA (Field Programmable Gate Array) tools and EDA (Electronic Design Automation) tools mainly rely on engineers to manually input design codes or construct logic through a graphical interface for circuit design. This process requires engineers to have a deep understanding of the FPGA hardware architecture and HDL (Hardware Description Language). In addition, it often takes a lot of time to debug and optimize complex circuits, resulting in long design cycles and low efficiency. Summary of the invention

[0003] The present invention provides a method and system for automatically generating a circuit based on FPGA, the main purpose of which is to solve the problems of long circuit design cycle and low efficiency.

[0004] To achieve the above object, the present invention provides a method for automatically generating a circuit based on FPGA, comprising:

[0005] Receiving circuit design requirements input by a user, wherein the circuit design requirements refer to circuit functions, performance indicators, and design constraints, and receiving a module generation model selected by the user;

[0006] Inputting the circuit design requirements into the module generation model to obtain an initial circuit function module set;

[0007] Acquire an initial module characteristic parameter set corresponding to the initial circuit function module set, and normalize the initial module characteristic parameter set to obtain a standard module characteristic parameter set;

[0008] Inputting the standard module characteristic parameter set into a pre-trained module splicing model to obtain a module splicing circuit;

[0009] Constructing an HDL file according to the module splicing circuit, performing simulation test according to the HDL file, and obtaining simulation test results;

[0010] Determining whether the simulation test result meets the preset simulation test standard;

[0011] If the simulation test result does not meet the simulation test standard, the module generation model and the module splicing model are optimized, and the process returns to the step of inputting the circuit design requirements into the module generation model;

[0012] If the simulation test result meets the simulation test standard, a performance test is performed according to the HDL file to obtain a performance test result;

[0013] Determine whether the performance test result meets the preset performance test standard;

[0014] If the performance test result does not meet the performance test standard, the module splicing model is optimized, and the step of inputting the standard module characteristic parameter set into the pre-trained module splicing model is returned to the above step;

[0015] If the performance test results meet the preset performance test standards, the FPGA configuration file is constructed according to the HDL file to complete the automatic generation of the circuit based on FPGA.

[0016] Optionally, the obtaining of an initial module characteristic parameter set corresponding to the initial circuit function module set includes:

[0017] Extracting initial circuit function modules in sequence from the initial circuit function module set, and obtaining communication protocols, data flows, topological structures and timing relationships of the initial circuit function modules;

[0018] The communication protocol, data flow, topology and timing relationship are used as initial module characteristic parameters of the initial circuit function module, and the initial module characteristic parameters of each initial circuit function module are collected to obtain an initial module characteristic parameter set.

[0019] Optionally, the normalizing the initial module characteristic parameter set to obtain a standard module characteristic parameter set includes:

[0020] Unifying the representation form of the communication protocol and data flow direction of each initial module characteristic parameter in the initial module characteristic parameter set to obtain a standard communication protocol and a standard data flow direction;

[0021] quantifying the timing relationship in the initial module characteristic parameters to obtain a standard timing relationship;

[0022] The standard communication protocol, standard data flow, standard timing relationship and topological structure corresponding to the initial module characteristic parameters are used as the standard module characteristic parameters, and the characteristic parameters of each standard module are collected to obtain a standard module characteristic parameter set.

[0023] Optionally, the training process of the module splicing model includes:

[0024] Acquire a training circuit functional module set and a training module characteristic parameter set corresponding to the training circuit functional module set;

[0025] Normalizing the training module characteristic parameter set to obtain a normalized training module characteristic parameter set, wherein the normalized training module characteristic parameter set includes: a training communication protocol, a training data flow, a training topology structure, and a training timing relationship corresponding to each normalized training module characteristic parameter;

[0026] Modeling is performed according to the training topology structure to obtain a module node relationship graph, wherein the nodes in the module node relationship graph represent training circuit function modules;

[0027] Extracting module nodes in the module node relationship diagram in sequence, obtaining performance parameters of training circuit function modules corresponding to the module nodes, and extracting training communication protocols corresponding to the module nodes from the normalized training module characteristic parameter set;

[0028] Using the performance parameters of the training circuit function module and the training communication protocol corresponding to the module node as the node characteristics of the module node;

[0029] Extracting the training data flow direction and training timing relationship of the training function module corresponding to the module node from the normalized training module characteristic parameter set, and using the training data flow direction and training timing relationship as the edge features of the module node;

[0030] Construct a GNN model according to the module node relationship graph, node features and edge features;

[0031] Iterate the GNN model using the preset global delay, power consumption and resource occupancy to obtain an iterative GNN model;

[0032] Identifying model performance of the iterative GNN model using a pre-built EDA tool;

[0033] Determining whether the model performance meets the preset splicing performance;

[0034] If the model performance does not meet the splicing performance, return to the above step of iterating the GNN model using the preset global delay, power consumption and resource occupancy;

[0035] If the model performance meets the splicing performance, a module splicing model is obtained.

[0036] Optionally, performing simulation testing according to the HDL file to obtain simulation test results includes:

[0037] Loading the HDL file into a simulation environment and loading a test vector;

[0038] A simulation response under the stimulus of the test vector is obtained, and the simulation response is used as a simulation test result.

[0039] Optionally, before performing model tuning on the module generation model and the module splicing model, the method further includes:

[0040] Performing error analysis on the simulation test results to obtain an error analysis log and error-related data;

[0041] The model to be tuned is determined according to the error analysis log and error-related data, wherein the model to be tuned is a module generation model or a module splicing model.

[0042] Optionally, the performing model tuning on the module splicing model includes:

[0043] Obtaining a performance test analysis report, wherein the performance test analysis report includes: a timing report, a power consumption report, and a resource occupancy report;

[0044] The module splicing model is optimized according to the performance test analysis report.

[0045] Optionally, constructing an FPGA configuration file according to the HDL file includes:

[0046] Adding necessary comments to the HDL file to obtain an annotated HDL file;

[0047] Construct an FPGA configuration file based on the annotated HDL file.

[0048] Optionally, the module generation model is a convolutional neural network, wherein the convolutional neural network can input the logical structure characteristics, input and output characteristics, performance characteristics, power consumption characteristics, delay time, and resource utilization characteristics of the initial circuit function module, and can output the circuit structure of the initial circuit function module. The module generation model includes: a computing module generation model, a storage module generation model, a control module generation model, a communication module generation model, an encryption module generation model, and a digital signal processing module generation model.

[0049] To achieve the above object, the present invention further provides a circuit automatic generation system based on FPGA, comprising:

[0050] A circuit function module set generation module is used to receive circuit design requirements input by a user, wherein the circuit design requirements refer to circuit functions, performance indicators and design constraints, and receive a module generation model selected by the user; input the circuit design requirements into the module generation model to obtain an initial circuit function module set;

[0051] A circuit function module set splicing module is used to obtain an initial module characteristic parameter set corresponding to the initial circuit function module set, normalize the initial module characteristic parameter set to obtain a standard module characteristic parameter set; input the standard module characteristic parameter set into a pre-trained module splicing model to obtain a module splicing circuit;

[0052] A module splicing circuit verification and optimization module is used to construct an HDL file according to the module splicing circuit, perform simulation testing according to the HDL file, and obtain simulation test results; determine whether the simulation test results meet the preset simulation test standards; if the simulation test results do not meet the simulation test standards, perform model tuning on the module generation model and the module splicing model, and return to the above step of inputting the circuit design requirements into the module generation model; if the simulation test results meet the simulation test standards, perform performance testing according to the HDL file to obtain performance test results; determine whether the performance test results meet the preset performance test standards; if the performance test results do not meet the performance test standards, perform model tuning on the module splicing model, and return to the above step of inputting the standard module characteristic parameter set into the pre-trained module splicing model;

[0053] The FPGA configuration file generation module is used to construct an FPGA configuration file according to the HDL file if the performance test result meets the preset performance test standard.

[0054] In order to solve the above problem, the present invention further provides an electronic device, the electronic device comprising:

[0055] A memory storing at least one instruction; and a processor executing the instruction stored in the memory to implement the above-mentioned FPGA-based automatic circuit generation method.

[0056] In order to solve the above problem, the present invention also provides a computer-readable storage medium, in which at least one instruction is stored. The at least one instruction is executed by a processor in an electronic device to implement the above-mentioned FPGA-based circuit automatic generation method.

[0057] The present invention is to solve the problem described in the background technology. The present invention first generates an initial circuit function module set, then splices the initial circuit function module set to obtain a module splicing circuit, and finally verifies and optimizes the module splicing circuit. In the process of generating the initial circuit function module set, it is necessary to first receive the circuit design requirements input by the user, wherein the circuit design requirements refer to circuit functions, performance indicators and design constraints. At this time, it is necessary to receive the module generation model selected by the user, and then input the circuit design requirements into the module generation model to obtain the initial circuit function module set. Since the initial circuit function module set needs to be spliced ​​according to the initial module characteristic parameter set, it is necessary to obtain the initial module characteristic parameter set corresponding to the initial circuit function module set, and then normalize the initial module characteristic parameter set to obtain a standard module characteristic parameter set. At this time, the standard module characteristic parameter set is input into the module splicing model that has been trained in advance to obtain the module splicing circuit. After obtaining the module splicing circuit, it is necessary to verify and optimize the module splicing circuit. Therefore, firstly, an HDL file is constructed according to the module splicing circuit, and then a simulation test is performed according to the HDL file to obtain a simulation test result. At this time, it is determined whether the simulation test result meets the preset simulation test standard. If the simulation test result does not meet the simulation test standard, the module generation model and the module splicing model are model tuned, and the standard module characteristic parameter set is re-input into the module generation model. If the simulation test result meets the simulation test standard, a performance test is performed according to the HDL file to obtain a performance test result. After completing the simulation test, a performance test is required. First, it is determined whether the performance test result meets the preset performance test standard. If the performance test result does not meet the performance test standard, the module splicing model is model tuned, and the standard module characteristic parameter set is re-input into the module splicing model that has been trained in advance. If the performance test result meets the preset performance test standard, an FPGA configuration file is constructed according to the HDL file to complete the automatic generation of the circuit based on FPGA. Therefore, the present invention can solve the problems of long circuit design cycle and low efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 A schematic diagram of a flow chart of a method for automatically generating a circuit based on FPGA provided by an embodiment of the present invention;

[0059] Figure 2 A functional module diagram of an FPGA-based circuit automation generation system provided by an embodiment of the present invention;

[0060] Figure 3 A schematic diagram of the structure of an electronic device for implementing the FPGA-based automatic circuit generation method provided by an embodiment of the present invention.

[0061] Description of reference numerals:

[0062] 1. Electronic device; 10. Processor; 11. Memory; 12. Bus.

[0063] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0064] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0065] The embodiment of the present application provides a method for automatically generating circuits based on FPGA. The execution subject of the method for automatically generating circuits based on FPGA includes but is not limited to at least one of the electronic devices such as a server and a terminal that can be configured to execute the method provided by the embodiment of the present application. In other words, the method for automatically generating circuits based on FPGA can be executed by software or hardware installed on a terminal device or a server device, and the software can be a blockchain platform. The server includes but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, etc.

[0066] Reference Figure 1 FIG. 1 is a flow chart of an FPGA-based circuit automatic generation method provided by an embodiment of the present invention. In this embodiment, the FPGA-based circuit automatic generation method includes:

[0067] S1. Receive circuit design requirements input by a user, wherein the circuit design requirements refer to circuit functions, performance indicators, and design constraints, and receive a module generation model selected by the user.

[0068] It can be understood that the circuit design requirements refer to the requirements of FPGA circuit design, including: expected circuit functions (for example: specific algorithms, specific communication protocols, etc.), performance indicators (for example: clock frequency, power consumption requirements, etc.), and design constraints (for example: chip resource limitations, pin allocation, etc.).

[0069] Furthermore, the circuit design requirements may be input through a graphical user interface (GUI), which includes a function selection menu, a performance parameter input box, and a design constraint setting area.

[0070] In detail, in the function selection menu, detailed circuit function module type options (such as computing modules with different precisions, storage modules with various capacities and access speeds, interface modules for multiple communication protocols, etc.) and customized function input boxes can be provided. Users can generally check or enter descriptions to specify the required circuit function module types and overall functional requirements. In the performance parameter input box, users are allowed to enter performance indicators such as clock frequency range, power consumption budget, and signal delay requirements. These performance parameter input boxes can set reasonable default values ​​and provide prompt information to help users enter correctly. In the design constraint setting area, users can specify constraints such as FPGA chip models (so that the tool can generate appropriate designs based on chip resource limitations), pin allocation requirements (such as specific signals must be assigned to specific pins). When receiving the circuit design requirements, it is necessary to determine whether the circuit design requirements are complete and clear. If not, the user is prompted to supplement.

[0071] In an embodiment of the present invention, the module generation model is a convolutional neural network, wherein the convolutional neural network can input the logical structure characteristics, input and output characteristics, performance characteristics, power consumption characteristics, delay time, and resource utilization characteristics of the initial circuit function module, and can output the circuit structure of the initial circuit function module. The module generation model includes: a computing module generation model, a storage module generation model, a control module generation model, a communication module generation model, an encryption module generation model, and a digital signal processing module generation model.

[0072] Furthermore, the training process of the module generation model includes:

[0073] Acquire a training module characteristic parameter set, wherein the training module characteristic parameter set includes: training logic structure characteristics, training input and output characteristics, training performance characteristics, training power consumption characteristics, training delay time, training resource utilization characteristics and training circuit structure;

[0074] Input the training logic structure features, training input and output features, training performance features, training power consumption features, training delay time, and training resource utilization features into a pre-constructed original generation model to obtain an iterative circuit structure;

[0075] Identifying iterative timing performance, iterative power consumption, and iterative resource utilization of the iterative circuit structure;

[0076] Identifying training timing performance, training power consumption, and training resource utilization of the training circuit structure;

[0077] Calculating a multi-objective loss function value of the iteration timing performance, iteration power consumption, and iteration resource utilization and the training timing performance, training power consumption, and training resource utilization;

[0078] According to the multi-objective loss function value, the parameters of the original generation model are adjusted using a pre-constructed gradient descent algorithm until the multi-objective loss function value meets a preset loss function threshold, thereby obtaining a module generation model.

[0079] It can be explained that the training logic structure characteristics, training input and output characteristics, training performance characteristics, training power consumption characteristics, training delay time, training resource utilization characteristics and training circuit structure respectively refer to the logic structure characteristics, input and output characteristics, performance characteristics, power consumption characteristics, delay time, resource utilization characteristics and circuit structure used for training. The iterative circuit structure refers to the circuit structure output during the training process. The iterative timing performance, iterative power consumption and iterative resource utilization rate respectively refer to the timing performance, power consumption and resource utilization rate of the iterative circuit structure. The training timing performance, training power consumption and training resource utilization rate respectively refer to the timing performance, power consumption and resource utilization rate of the training circuit structure. The multi-objective loss function value refers to the performance parameter difference between the iterative circuit structure and the training circuit structure.

[0080] Furthermore, the circuit structure is represented in the form of a hardware description language or a logical topology diagram, including information such as the connection relationship between the initial circuit function modules, resource allocation and timing information. The training timing performance, training power consumption, training resource utilization, iteration timing performance, iteration power consumption, and iteration resource utilization can be monitored using EDA tools. First, the error between the iteration timing performance and the training timing performance, the error between the iteration power consumption and the training power consumption, and the error between the iteration resource utilization and the training resource utilization are calculated, and then the above errors are integrated into a multi-objective loss function.

[0081] It can be understood that the parameter adjustment includes the adjustment of parameters such as convolution kernel weights and bias terms. Dynamic adjustment of hyperparameters can accelerate the convergence of the original generation model.

[0082] S2. Input the circuit design requirements into the module generation model to obtain an initial circuit function module set.

[0083] It is understandable that the initial circuit function module set refers to a set of circuit function modules that meet the circuit design requirements. The module generation model can generate corresponding circuit function module design schemes according to the circuit design requirements input by the user, and each circuit function module design scheme meets the circuit function, performance indicators and design constraints in the circuit design requirements. For example: when generating a high-speed computing module, the module generation model generates a design module with appropriate computing power, power consumption and delay requirements, including: the selection and connection method of logic gates.

[0084] S3. Acquire an initial module characteristic parameter set corresponding to the initial circuit function module set, and normalize the initial module characteristic parameter set to obtain a standard module characteristic parameter set.

[0085] It is understandable that the initial module characteristic parameter set refers to the characteristic parameter set of each initial circuit function module. The normalization process refers to converting the initial module characteristic parameter set into a unified standardized representation form. The standard module characteristic parameter set refers to a standardized initial module characteristic parameter set.

[0086] In the embodiment of the present invention, the step of obtaining an initial module characteristic parameter set corresponding to the initial circuit function module set includes:

[0087] Extracting initial circuit function modules in sequence from the initial circuit function module set, and obtaining communication protocols, data flows, topological structures and timing relationships of the initial circuit function modules;

[0088] The communication protocol, data flow, topology and timing relationship are used as initial module characteristic parameters of the initial circuit function module, and the initial module characteristic parameters of each initial circuit function module are collected to obtain an initial module characteristic parameter set.

[0089] Furthermore, the communication protocol refers to a data transmission protocol between the initial circuit function modules, such as UART, SPI or a custom protocol. The data flow direction refers to the data flow path between the initial circuit function modules, including input-output relationships and multi-module cascade relationships. The topology structure refers to a global topology relationship diagram of the initial circuit function modules, which is used to describe the connection mode and dependency relationship between the initial circuit function modules. The timing relationship refers to the timing dependency between the initial circuit function modules, for example: a clock synchronization mechanism for cross-module data transmission.

[0090] In the embodiment of the present invention, the normalization process of the initial module characteristic parameter set to obtain the standard module characteristic parameter set includes:

[0091] Unifying the representation form of the communication protocol and data flow direction of each initial module characteristic parameter in the initial module characteristic parameter set to obtain a standard communication protocol and a standard data flow direction;

[0092] quantifying the timing relationship in the initial module characteristic parameters to obtain a standard timing relationship;

[0093] The standard communication protocol, standard data flow, standard timing relationship and topological structure corresponding to the initial module characteristic parameters are used as the standard module characteristic parameters, and the characteristic parameters of each standard module are collected to obtain a standard module characteristic parameter set.

[0094] S4. Input the standard module characteristic parameter set into a pre-trained module splicing model to obtain a module splicing circuit.

[0095] Furthermore, the module splicing model refers to a model for splicing the initial circuit function module set according to the standard module characteristic parameter set. The module splicing model can connect the generated initial circuit function module set according to the optimal splicing rules learned by it to form a complete FPGA circuit design, and the generated FPGA circuit design is output in a standard hardware description language (such as Verilog or VHDL) or a specific FPGA configuration file format. The module splicing circuit refers to the splicing circuit obtained after the module splicing model splices the initial circuit function module set.

[0096] In the embodiment of the present invention, the training process of the module splicing model includes:

[0097] Acquire a training circuit functional module set and a training module characteristic parameter set corresponding to the training circuit functional module set;

[0098] Normalizing the training module characteristic parameter set to obtain a normalized training module characteristic parameter set, wherein the normalized training module characteristic parameter set includes: a training communication protocol, a training data flow, a training topology structure, and a training timing relationship corresponding to each normalized training module characteristic parameter;

[0099] Modeling is performed according to the training topology structure to obtain a module node relationship graph, wherein the nodes in the module node relationship graph represent training circuit function modules;

[0100] Extracting module nodes in the module node relationship diagram in sequence, obtaining performance parameters of training circuit function modules corresponding to the module nodes, and extracting training communication protocols corresponding to the module nodes from the normalized training module characteristic parameter set;

[0101] Using the performance parameters of the training circuit function module and the training communication protocol corresponding to the module node as the node characteristics of the module node;

[0102] Extracting the training data flow direction and training timing relationship of the training function module corresponding to the module node from the normalized training module characteristic parameter set, and using the training data flow direction and training timing relationship as the edge features of the module node;

[0103] Construct a GNN model according to the module node relationship graph, node features and edge features;

[0104] Iterate the GNN model using the preset global delay, power consumption and resource occupancy to obtain an iterative GNN model;

[0105] Identifying model performance of the iterative GNN model using a pre-built EDA tool;

[0106] Determining whether the model performance meets the preset splicing performance;

[0107] If the model performance does not meet the splicing performance, return to the above step of iterating the GNN model using the preset global delay, power consumption and resource occupancy;

[0108] If the model performance meets the splicing performance, a module splicing model is obtained.

[0109] It is understandable that the training circuit function module set refers to the circuit function module used to train the module splicing model, and the training module characteristic parameter set refers to the characteristic parameter set of each training circuit function module. The training communication protocol, training data flow, training topology and training timing relationship respectively refer to the communication protocol, data flow, topology and timing relationship of the training circuit function module. The module node relationship diagram refers to the node relationship diagram representing the training topology. The performance parameters can be the delay and power consumption of the training circuit function module. The GNN model refers to a graph neural network model, which is a deep learning model specifically used to process graph structure data. It learns the optimal circuit splicing method by minimizing the loss function (such as the loss function based on the performance of the circuit after splicing). At the same time, the verification set can be used to adjust the GNN model parameters to improve the generalization ability of the GNN model for module splicing in different circuit design scenarios. The splicing performance refers to the expected global delay, power consumption and resource occupancy of the GNN model.

[0110] S5. Construct an HDL file according to the module splicing circuit, perform simulation test according to the HDL file, and obtain simulation test results.

[0111] It can be understood that the HDL (Hardware Description Language) file refers to a file that describes the structure, function and behavior of the module splicing circuit. The HDL file can be used to design and verify the electronic system more efficiently and accurately.

[0112] Furthermore, the module splicing circuit is output through a standardized hardware description language (HDL), and an FPGA configuration file is generated at the same time, which is then verified and optimized using simulation tools and performance analysis tools, ultimately generating a complete FPGA design and verification report that meets the requirements.

[0113] In the embodiment of the present invention, performing simulation test according to the HDL file to obtain simulation test results includes:

[0114] Loading the HDL file into a simulation environment and loading a test vector;

[0115] A simulation response under the stimulus of the test vector is obtained, and the simulation response is used as a simulation test result.

[0116] It can be understood that the simulation response refers to the output signal and state change of the module splicing circuit under the stimulation of the test vector, such as: output digital signal, output analog signal, timing information, error and warning information, etc.

[0117] S6. Determine whether the simulation test result meets the preset simulation test standard.

[0118] It can be understood that the simulation test standard refers to the preset simulation response standard of the module splicing circuit.

[0119] If the simulation test result does not meet the simulation test standard, execute S7 to perform model tuning on the module generation model and the module splicing model.

[0120] In the embodiment of the present invention, before the module generation model and the module splicing model are optimized, the method further includes:

[0121] Performing error analysis on the simulation test results to obtain an error analysis log and error-related data;

[0122] The model to be tuned is determined according to the error analysis log and error-related data, wherein the model to be tuned is a module generation model or a module splicing model.

[0123] It is understandable that the error analysis log refers to a detailed document that records the errors, anomalies or behaviors that do not meet expected expectations found in the simulation test results, such as: the manifestation of the error, the time point when the error occurs, the possible error type, the location of the error, the cause of the error, suggestions for error repair, etc. The error-related data refers to the data and information directly related to the error during the simulation test, such as: simulation test data, signal waveform diagram, resource usage data, timing analysis report, etc. By analyzing the error analysis log and error-related data, it can be determined whether the module generation model needs to be further tuned or the module splicing model needs to be further tuned.

[0124] Return to the above step of inputting the circuit design requirements into the module generation model.

[0125] It is understandable that after the module generation model and the module splicing model are tuned, it is necessary to reuse the module generation model to generate an initial circuit function module set and to use the module splicing model to generate a module splicing circuit.

[0126] If the simulation test result meets the simulation test standard, S8 is executed to perform a performance test according to the HDL file to obtain a performance test result.

[0127] It is understandable that the performance test results include the timing test results, power consumption test results and resource occupancy test results of the module splicing circuit.

[0128] S9. Determine whether the performance test result meets the preset performance test standard.

[0129] It should be understood that the performance test standard refers to the timing, power consumption and resource occupation standard set for the module splicing circuit. The comprehensive tool provided by the FPGA manufacturer can be used to conduct a comprehensive analysis of the module splicing circuit to obtain the timing information, power consumption information and other performance data of the module splicing circuit. If the performance requirements input by the user are not met, the circuit design is adjusted using an optimization algorithm (such as a layout and routing optimization algorithm, a logic optimization algorithm, etc.). For example, the timing performance can be improved by adjusting the number of logic gate levels on the critical path in the circuit or by optimizing the use of storage units to reduce power consumption, etc. The optimization process can be repeated until the circuit design meets all performance indicators and design constraints.

[0130] If the performance test result does not meet the performance test standard, execute S10, perform model tuning on the module splicing model, and return to the above step of inputting the standard module characteristic parameter set into the pre-trained module splicing model.

[0131] Furthermore, when the performance test results do not meet the performance test standards, the module splicing model can be directly tuned. Since only the module splicing model is tuned, it is sufficient to directly return to the step of inputting the standard module characteristic parameter set into the pre-trained module splicing model.

[0132] In the embodiment of the present invention, the step of optimizing the module splicing model includes:

[0133] Obtaining a performance test analysis report, wherein the performance test analysis report includes: a timing report, a power consumption report, and a resource occupancy report;

[0134] The module splicing model is optimized according to the performance test analysis report.

[0135] It is understandable that the timing report, power consumption report and resource occupancy report can be used as optimization consideration dimensions to iteratively tune the module splicing model.

[0136] If the performance test result meets the preset performance test standard, S11 is executed to construct an FPGA configuration file according to the HDL file to complete the automatic generation of the circuit based on FPGA.

[0137] In an embodiment of the present invention, the step of constructing an FPGA configuration file according to the HDL file includes:

[0138] Adding necessary comments to the HDL file to obtain an annotated HDL file;

[0139] Construct an FPGA configuration file based on the annotated HDL file.

[0140] The present invention is to solve the problem described in the background technology. The present invention first generates an initial circuit function module set, then splices the initial circuit function module set to obtain a module splicing circuit, and finally verifies and optimizes the module splicing circuit. In the process of generating the initial circuit function module set, it is necessary to first receive the circuit design requirements input by the user, wherein the circuit design requirements refer to circuit functions, performance indicators and design constraints. At this time, it is necessary to receive the module generation model selected by the user, and then input the circuit design requirements into the module generation model to obtain the initial circuit function module set. Since the initial circuit function module set needs to be spliced ​​according to the initial module characteristic parameter set, it is necessary to obtain the initial module characteristic parameter set corresponding to the initial circuit function module set, and then normalize the initial module characteristic parameter set to obtain a standard module characteristic parameter set. At this time, the standard module characteristic parameter set is input into the module splicing model that has been trained in advance to obtain the module splicing circuit. After obtaining the module splicing circuit, it is necessary to verify and optimize the module splicing circuit. Therefore, firstly, an HDL file is constructed according to the module splicing circuit, and then a simulation test is performed according to the HDL file to obtain a simulation test result. At this time, it is determined whether the simulation test result meets the preset simulation test standard. If the simulation test result does not meet the simulation test standard, the module generation model and the module splicing model are model tuned, and the standard module characteristic parameter set is re-input into the module generation model. If the simulation test result meets the simulation test standard, a performance test is performed according to the HDL file to obtain a performance test result. After completing the simulation test, a performance test is required. First, it is determined whether the performance test result meets the preset performance test standard. If the performance test result does not meet the performance test standard, the module splicing model is model tuned, and the standard module characteristic parameter set is re-input into the module splicing model that has been trained in advance. If the performance test result meets the preset performance test standard, an FPGA configuration file is constructed according to the HDL file to complete the automatic generation of the circuit based on FPGA. Therefore, the present invention can solve the problems of long circuit design cycle and low efficiency.

[0141] like Figure 2 , which is a functional module diagram of an FPGA-based circuit automatic generation system provided in one embodiment of the present invention.

[0142] The FPGA-based circuit automatic generation system 100 of the present invention can be installed in an electronic device. According to the functions to be implemented, the FPGA-based circuit automatic generation system 100 can include a circuit function module set generation module 101, a circuit function module set splicing module 102, a module splicing circuit verification optimization module 103 and an FPGA configuration file generation module 104. The module of the present invention can also be called a unit, which refers to a series of computer program segments that can be executed by an electronic device processor and can complete fixed functions, which are stored in the memory of the electronic device.

[0143] The circuit function module set generation module 101 is used to receive the circuit design requirements input by the user, wherein the circuit design requirements refer to circuit functions, performance indicators and design constraints, and receive the module generation model selected by the user; input the circuit design requirements into the module generation model to obtain an initial circuit function module set;

[0144] The circuit function module set splicing module 102 is used to obtain an initial module characteristic parameter set corresponding to the initial circuit function module set, normalize the initial module characteristic parameter set to obtain a standard module characteristic parameter set; input the standard module characteristic parameter set into a pre-trained module splicing model to obtain a module splicing circuit;

[0145] The module splicing circuit verification and optimization module 103 is used to construct an HDL file according to the module splicing circuit, perform simulation testing according to the HDL file, and obtain simulation test results; determine whether the simulation test results meet the preset simulation test standards; if the simulation test results do not meet the simulation test standards, perform model tuning on the module generation model and the module splicing model, and return to the above step of inputting the circuit design requirements into the module generation model; if the simulation test results meet the simulation test standards, perform performance testing according to the HDL file to obtain performance test results; determine whether the performance test results meet the preset performance test standards; if the performance test results do not meet the performance test standards, perform model tuning on the module splicing model, and return to the above step of inputting the standard module characteristic parameter set into the pre-trained module splicing model;

[0146] The FPGA configuration file generating module 104 is used to construct an FPGA configuration file according to the HDL file if the performance test result meets the preset performance test standard.

[0147] In detail, each module in the FPGA-based circuit automatic generation system 100 in the embodiment of the present invention is used in the same manner as described above. Figure 1The same technical means as the FPGA-based circuit automatic generation method described in the previous section can produce the same technical effects, which will not be repeated here.

[0148] like Figure 3 , is a schematic diagram of the structure of an electronic device for implementing an FPGA-based circuit automatic generation method provided by an embodiment of the present invention.

[0149] The electronic device 1 may include a processor 10, a memory 11 and a bus 12, and may also include a computer program stored in the memory 11 and executable on the processor 10, such as an FPGA-based circuit automatic generation method program.

[0150] The memory 11 includes at least one type of readable storage medium, and the readable storage medium includes a flash memory, a mobile hard disk, a multimedia card, a card-type memory (e.g., SD or DX memory, etc.), a magnetic memory, a disk, an optical disk, etc. In some embodiments, the memory 11 may be an internal storage unit of the electronic device 1, such as a mobile hard disk of the electronic device 1. In other embodiments, the memory 11 may also be an external storage device of the electronic device 1, such as a plug-in mobile hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (SecureDigital, SD) card, a flash card (Flash Card), etc. equipped on the electronic device 1. Further, the memory 11 also includes an internal storage unit of the electronic device 1 and an external storage device. The memory 11 can not only be used to store application software and various types of data installed in the electronic device 1, such as the code of the circuit automation generation method program based on FPGA, but also can be used to temporarily store data that has been output or is to be output.

[0151] The processor 10 may be composed of an integrated circuit in some embodiments, for example, a single packaged integrated circuit, or a plurality of packaged integrated circuits with the same or different functions, including one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and combinations of various control chips, etc. The processor 10 is the control core (Control Unit) of the electronic device, and uses various interfaces and lines to connect various components of the entire electronic device, and executes or executes programs or modules (such as FPGA-based circuit automation generation method programs, etc.) stored in the memory 11, and calls data stored in the memory 11 to execute various functions of the electronic device 1 and process data.

[0152] The bus 12 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus 12 may be divided into an address bus, a data bus, a control bus, etc. The bus 12 is configured to realize connection and communication between the memory 11 and at least one processor 10, etc.

[0153] Figure 3 Only an electronic device with components is shown, and those skilled in the art will understand that Figure 3 The structure shown does not constitute a limitation on the electronic device 1, and may include fewer or more components than shown in the figure, or combine certain components, or arrange the components differently.

[0154] For example, although not shown, the electronic device 1 may also include a power source (such as a battery) for supplying power to various components. Preferably, the power source may be logically connected to the at least one processor 10 through a power management device, so that the power management device can realize functions such as charging management, discharging management, and power consumption management. The power source may also include one or more DC or AC power sources, recharging devices, power failure detection circuits, power converters or inverters, power status indicators, and other arbitrary components. The electronic device 1 may also include a variety of sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be repeated here.

[0155] Furthermore, the electronic device 1 may also include a network interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a WI-FI interface, a Bluetooth interface, etc.), which is generally used to establish a communication connection between the electronic device 1 and other electronic devices.

[0156] Optionally, the electronic device 1 may further include a user interface, which may be a display, an input unit (such as a keyboard), or a standard wired interface or a wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, and an OLED (Organic Light-Emitting Diode) touch device. The display may also be appropriately referred to as a display screen or a display unit, which is used to display information processed in the electronic device 1 and to display a visual user interface.

[0157] The FPGA-based circuit automatic generation method program stored in the memory 11 in the electronic device 1 is a combination of multiple instructions. When running in the processor 10, it can achieve:

[0158] Receiving circuit design requirements input by a user, wherein the circuit design requirements refer to circuit functions, performance indicators, and design constraints, and receiving a module generation model selected by the user;

[0159] Inputting the circuit design requirements into the module generation model to obtain an initial circuit function module set;

[0160] Acquire an initial module characteristic parameter set corresponding to the initial circuit function module set, and normalize the initial module characteristic parameter set to obtain a standard module characteristic parameter set;

[0161] Inputting the standard module characteristic parameter set into a pre-trained module splicing model to obtain a module splicing circuit;

[0162] Constructing an HDL file according to the module splicing circuit, performing simulation test according to the HDL file, and obtaining simulation test results;

[0163] Determining whether the simulation test result meets the preset simulation test standard;

[0164] If the simulation test result does not meet the simulation test standard, the module generation model and the module splicing model are optimized, and the process returns to the step of inputting the circuit design requirements into the module generation model;

[0165] If the simulation test result meets the simulation test standard, a performance test is performed according to the HDL file to obtain a performance test result;

[0166] Determine whether the performance test result meets the preset performance test standard;

[0167] If the performance test result does not meet the performance test standard, the module splicing model is optimized, and the step of inputting the standard module characteristic parameter set into the pre-trained module splicing model is returned to the above step;

[0168] If the performance test result meets the preset performance test standard, an FPGA configuration file is constructed according to the HDL file to complete the automatic generation of the FPGA-based circuit.

[0169] Specifically, the specific implementation method of the processor 10 for the above instructions can refer to Figures 1 to 3 The description of the relevant steps in the corresponding embodiments will not be repeated here.

[0170] Furthermore, if the module / unit integrated in the electronic device 1 is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. The computer-readable storage medium can be volatile or non-volatile. For example, the computer-readable medium can include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a mobile hard disk, a magnetic disk, an optical disk, a computer memory, and a read-only memory (ROM).

[0171] The present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor of an electronic device, the computer program can implement:

[0172] Receiving circuit design requirements input by a user, wherein the circuit design requirements refer to circuit functions, performance indicators, and design constraints, and receiving a module generation model selected by the user;

[0173] Inputting the circuit design requirements into the module generation model to obtain an initial circuit function module set;

[0174] Acquire an initial module characteristic parameter set corresponding to the initial circuit function module set, and normalize the initial module characteristic parameter set to obtain a standard module characteristic parameter set;

[0175] Inputting the standard module characteristic parameter set into a pre-trained module splicing model to obtain a module splicing circuit;

[0176] Constructing an HDL file according to the module splicing circuit, performing simulation test according to the HDL file, and obtaining simulation test results;

[0177] Determining whether the simulation test result meets the preset simulation test standard;

[0178] If the simulation test result does not meet the simulation test standard, the module generation model and the module splicing model are optimized, and the process returns to the step of inputting the circuit design requirements into the module generation model;

[0179] If the simulation test result meets the simulation test standard, a performance test is performed according to the HDL file to obtain a performance test result;

[0180] Determine whether the performance test result meets the preset performance test standard;

[0181] If the performance test result does not meet the performance test standard, the module splicing model is optimized, and the step of inputting the standard module characteristic parameter set into the pre-trained module splicing model is returned to the above step;

[0182] If the performance test result meets the preset performance test standard, an FPGA configuration file is constructed according to the HDL file to complete the automatic generation of the FPGA-based circuit.

[0183] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, systems and methods can be implemented in other ways. For example, the system embodiments described above are only illustrative, and actual implementation may have other division methods.

[0184] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0185] In addition, each functional module in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0186] It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0187] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.

Claims

1. A method for automatic circuit generation based on FPGA, characterized in that: The method comprises: Receiving circuit design requirements input by a user, wherein the circuit design requirements refer to circuit functions, performance indicators, and design constraints, and receiving a module generation model selected by the user; Inputting the circuit design requirements into the module generation model to obtain an initial circuit function module set; Acquire an initial module characteristic parameter set corresponding to the initial circuit function module set, and normalize the initial module characteristic parameter set to obtain a standard module characteristic parameter set; Inputting the standard module characteristic parameter set into a pre-trained module splicing model to obtain a module splicing circuit; Constructing an HDL file according to the module splicing circuit, performing simulation test according to the HDL file, and obtaining simulation test results; Determining whether the simulation test result meets the preset simulation test standard; If the simulation test result does not meet the simulation test standard, the module generation model and the module splicing model are optimized, and the process returns to the step of inputting the circuit design requirements into the module generation model; If the simulation test result meets the simulation test standard, a performance test is performed according to the HDL file to obtain a performance test result; Determine whether the performance test result meets the preset performance test standard; If the performance test result does not meet the performance test standard, the module splicing model is optimized, and the step of inputting the standard module characteristic parameter set into the pre-trained module splicing model is returned to the above step; If the performance test result meets the preset performance test standard, an FPGA configuration file is constructed according to the HDL file to complete the automatic generation of the FPGA-based circuit.

2. The FPGA-based circuit automatic generation method according to claim 1, characterized in that: The obtaining of the initial module characteristic parameter set corresponding to the initial circuit function module set includes: Extracting initial circuit function modules in sequence from the initial circuit function module set, and obtaining communication protocols, data flows, topological structures and timing relationships of the initial circuit function modules; The communication protocol, data flow, topology and timing relationship are used as initial module characteristic parameters of the initial circuit function module, and the initial module characteristic parameters of each initial circuit function module are collected to obtain an initial module characteristic parameter set.

3. The FPGA-based circuit automatic generation method according to claim 2, characterized in that: The normalizing of the initial module characteristic parameter set to obtain a standard module characteristic parameter set includes: Unifying the representation form of the communication protocol and data flow direction of each initial module characteristic parameter in the initial module characteristic parameter set to obtain a standard communication protocol and a standard data flow direction; quantifying the timing relationship in the initial module characteristic parameters to obtain a standard timing relationship; The standard communication protocol, standard data flow, standard timing relationship and topological structure corresponding to the initial module characteristic parameters are used as the standard module characteristic parameters, and the characteristic parameters of each standard module are collected to obtain a standard module characteristic parameter set.

4. The FPGA-based circuit automatic generation method according to claim 1, characterized in that: The training process of the module splicing model includes: Acquire a training circuit functional module set and a training module characteristic parameter set corresponding to the training circuit functional module set; Normalizing the training module characteristic parameter set to obtain a normalized training module characteristic parameter set, wherein the normalized training module characteristic parameter set includes: a training communication protocol, a training data flow, a training topology structure, and a training timing relationship corresponding to each normalized training module characteristic parameter; Modeling is performed according to the training topology structure to obtain a module node relationship graph, wherein the nodes in the module node relationship graph represent training circuit function modules; Extracting module nodes in the module node relationship diagram in sequence, obtaining performance parameters of training circuit function modules corresponding to the module nodes, and extracting training communication protocols corresponding to the module nodes from the normalized training module characteristic parameter set; Using the performance parameters of the training circuit function module and the training communication protocol corresponding to the module node as the node characteristics of the module node; Extracting the training data flow direction and training timing relationship of the training function module corresponding to the module node from the normalized training module characteristic parameter set, and using the training data flow direction and training timing relationship as the edge features of the module node; Construct a GNN model according to the module node relationship graph, node features and edge features; Iterate the GNN model using the preset global delay, power consumption and resource occupancy to obtain an iterative GNN model; Identifying model performance of the iterative GNN model using a pre-built EDA tool; Determining whether the model performance meets the preset splicing performance; If the model performance does not meet the splicing performance, return to the above step of iterating the GNN model using the preset global delay, power consumption and resource occupancy; If the model performance meets the splicing performance, a module splicing model is obtained.

5. The FPGA-based circuit automatic generation method according to claim 1, characterized in that: The performing simulation test according to the HDL file to obtain the simulation test result includes: Loading the HDL file into a simulation environment and loading a test vector; A simulation response under the stimulus of the test vector is obtained, and the simulation response is used as a simulation test result.

6. The FPGA-based circuit automatic generation method according to claim 5, characterized in that: Before performing model tuning on the module generation model and the module splicing model, the method further includes: Performing error analysis on the simulation test results to obtain an error analysis log and error-related data; The model to be tuned is determined according to the error analysis log and error-related data, wherein the model to be tuned is a module generation model or a module splicing model.

7. The FPGA-based circuit automatic generation method according to claim 6, characterized in that: The step of optimizing the module splicing model includes: Obtaining a performance test analysis report, wherein the performance test analysis report includes: a timing report, a power consumption report, and a resource occupancy report; The module splicing model is optimized according to the performance test analysis report.

8. The FPGA-based circuit automatic generation method according to claim 7, characterized in that: The step of constructing an FPGA configuration file according to the HDL file includes: Adding necessary comments to the HDL file to obtain an annotated HDL file; Construct an FPGA configuration file based on the annotated HDL file.

9. The FPGA-based circuit automatic generation method according to claim 8, characterized in that: The module generation model is a convolutional neural network, wherein the convolutional neural network can input the logical structure characteristics, input and output characteristics, performance characteristics, power consumption characteristics, delay time, and resource utilization characteristics of the initial circuit function module, and can output the circuit structure of the initial circuit function module. The module generation model includes: a computing module generation model, a storage module generation model, a control module generation model, a communication module generation model, an encryption module generation model, and a digital signal processing module generation model.

10. An FPGA-based circuit automatic generation system, characterized in that: The system comprises: A circuit function module set generation module is used to receive circuit design requirements input by a user, wherein the circuit design requirements refer to circuit functions, performance indicators and design constraints, and receive a module generation model selected by the user; input the circuit design requirements into the module generation model to obtain an initial circuit function module set; A circuit function module set splicing module is used to obtain an initial module characteristic parameter set corresponding to the initial circuit function module set, normalize the initial module characteristic parameter set to obtain a standard module characteristic parameter set; input the standard module characteristic parameter set into a pre-trained module splicing model to obtain a module splicing circuit; A module splicing circuit verification and optimization module is used to construct an HDL file according to the module splicing circuit, perform simulation testing according to the HDL file, and obtain simulation test results; determine whether the simulation test results meet the preset simulation test standards; if the simulation test results do not meet the simulation test standards, perform model tuning on the module generation model and the module splicing model, and return to the above step of inputting the circuit design requirements into the module generation model; if the simulation test results meet the simulation test standards, perform performance testing according to the HDL file to obtain performance test results; determine whether the performance test results meet the preset performance test standards; if the performance test results do not meet the performance test standards, perform model tuning on the module splicing model, and return to the above step of inputting the standard module characteristic parameter set into the pre-trained module splicing model; The FPGA configuration file generation module is used to construct an FPGA configuration file according to the HDL file if the performance test result meets the preset performance test standard.

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