Storage and calculation integrated processor, data processing method and computer equipment

Abstract

The invention relates to a storage and calculation integrated processor, a data processing method and computer equipment, the storage and calculation integrated processor comprises a control module and a data module, and the control module is connected with the data module; the data module comprises a storage unit and a storage and calculation integrated processing engine, and the storage and calculation integrated processing engine is connected with the storage unit; the storage and calculation integrated processing engine comprises N storage and calculation integrated processing units and a first calculator group, and the storage and calculation integrated processing units are connected with the first calculator group; each storage and calculation integrated processing unit comprises M storage and calculation integrated array units and a second calculator group, and the storage and calculation integrated array units are connected with the second calculator group; each storage and calculation integrated array unit comprises a storage and calculation integrated array, an array control unit and a reading circuit, and the storage and calculation integrated array comprises a plurality of storage and calculation devices which are arranged in a crossed manner; the control module is used for controlling the storage and calculation integrated processing engine to obtain the data from the storage unit and instructing the storage and calculation integrated processing engine to calculate the obtained data. Data parallel computing is supported, and the computing efficiency is improved.

Description

Technical Field

[0001] The present application relates to a novel computing field, and in particular to a storage-computing integrated processor, a data processing method and a computer device. Background Art

[0002] In recent years, with the rise of artificial intelligence and large-scale model applications, the demand for processor computing power has continued to increase. Although most processors are still based on the von Neumann architecture to meet the demand for growing computing power, in order to develop accelerated computing chips with higher computing power and higher energy efficiency, it is necessary to solve the "storage wall" problem in the traditional von Neumann architecture. This problem requires a new architecture system that solves the problem of storage and computing separation by integrating storage and computing.

[0003] Computing-in-Memory (CiM) is an emerging computing architecture paradigm that aims to integrate computing functions with storage functions in the same processing unit or module. In traditional computer architecture, data usually needs to be transferred from memory to processor for calculation, and this data transfer consumes a lot of energy and time. Computing-in-Memory avoids this data movement by performing computing tasks on new types of memory, thereby improving computing efficiency and energy efficiency. However, most of the current computing-in-Memory architectures use a serial pipeline mode to process data, and the computing efficiency needs to be improved. Summary of the invention

[0004] Based on this, it is necessary to provide a storage and computing integrated processor, data processing method and computer equipment that can improve computing efficiency in response to the above technical problems.

[0005] In a first aspect, the present application provides a storage-computing integrated processor, comprising: a control module and a data module, wherein the control module is connected to the data module; wherein the data module comprises a storage unit and a storage-computing integrated processing engine, wherein the storage-computing integrated processing engine is connected to the storage unit; The storage-computation integrated processing engine includes N storage-computation integrated processing units and a first calculator group, and the storage-computation integrated processing unit is connected to the first calculator group; each of the storage-computation integrated processing units includes M storage-computation integrated array units and a second calculator group, and the storage-computation integrated array unit is connected to the second calculator group; N and M are both natural numbers greater than 1; each of the storage-computation integrated array units includes a storage-computation integrated array, an array control unit and a readout circuit, and the storage-computation integrated array includes a plurality of storage-computation devices arranged crosswise; The control module is used to control the storage-computing integrated processing engine to obtain data from the storage unit, and to instruct the storage-computing integrated processing engine to calculate the obtained data.

[0006] In one embodiment, the first calculator group includes a first accumulator group and / or a first quantizer group; wherein the first accumulator group includes N accumulators, and the accumulators are connected to the storage-computation integrated processing unit one by one; the first quantizer group includes N quantizers, and the quantizers are connected to the storage-computation integrated processing unit one by one; The second calculator group includes a second accumulator group and / or a second quantizer group; wherein, the second accumulator group includes M accumulators, and the accumulators are connected one-to-one with the storage and computing array units; the second quantizer group includes M quantizers, and the quantizers are connected one-to-one with the storage and computing array units.

[0007] In one embodiment, the data module further includes: a data preloading unit, a channel selection unit and a data preprocessing unit; wherein, The input end of the data preloading unit is connected to the storage unit, the output end of the data preloading unit is connected to the input end of the channel selection unit, and the data preloading unit is used to preload data from the storage unit; The input end of the channel selection unit is also connected to the storage unit, the output end of the channel selection unit is connected to the input end of the data preprocessing unit, and the channel selection unit is used to select the data to be calculated from the storage unit and the data preloading unit; The output end of the data preprocessing unit is connected to the storage-computation integrated processing engine, and the data preprocessing unit is used to preprocess the data output by the channel selection unit.

[0008] In one embodiment, the data preloading unit includes N register groups, and the register groups are connected to the data preprocessing unit; the data preprocessing unit is used to preprocess the data output by the channel selection unit, including: The data preprocessing unit preprocesses the data of each register group and transmits the preprocessing result to the corresponding storage-computation integrated processing unit; or, The data preprocessing unit aggregates the data of the plurality of register groups and transmits the aggregation result to one of the preset storage-computation integrated processing units.

[0009] In one embodiment, the data module further includes: a data post-processing unit, the input end of the data post-processing unit is connected to the storage-computing integrated processing engine, and the output end of the data post-processing unit is connected to the storage unit; wherein, The data post-processing unit is used to post-process the calculation results of the storage and computing integrated processing engine and transmit the post-processing results to the storage unit.

[0010] In one embodiment, the data module further includes: a write verification unit, the write verification unit is connected to the storage-computation integrated processing engine and the storage unit respectively; wherein, The write verification unit is used to configure the write verification programming mode of the storage-computation integrated processing engine, and the write verification programming mode includes a first mode and a second mode; wherein, In the first mode, write verification programming is performed on the storage computing device at a single address by writing an immediate unit value instruction; In the second mode, write verification is performed on the storage and computing devices at the same row address after taking values ​​from the storage cells according to address write instructions.

[0011] In one embodiment, the data module further includes: a data write-back unit, the data write-back unit is connected to the storage-computing integrated processing engine and the storage unit respectively; wherein, The data write-back unit is used to return the calculation results of the integrated storage and computing processing engine to the storage unit in sequence according to the order of writing back data.

[0012] In one embodiment, the data write-back unit includes: N first write-back FIFOs, W second write-back FIFOs, a data path switch, and an arbiter; W is a natural number greater than or equal to 1; The first write-back FIFO is used to temporarily store the write-back data and write-back address generated by the storage-computation integrated processing engine, and send a request to the arbitrator based on the write-back address; The arbiter is used to feed back a confirmation signal to the highest priority request according to the priority of the request; The data path switch is used to select the target write-back data that obtains the confirmation signal, so that the target write-back data is transmitted to the second write-back FIFO; The second write-back FIFO is used to temporarily store the target write-back data and the corresponding write-back address, and when the storage unit is available, write the target write-back data into the storage unit based on the corresponding write-back address.

[0013] In one embodiment, the control module includes: a control unit, a register unit and an instruction unit, and the control unit is connected to the register unit, the instruction unit and the data module respectively; wherein, The register unit is used to configure the operation mode and operation address of the data module, and record the operation status of the data module; The control unit is used to generate a control signal and control the register unit and the data module based on the control signal; The instruction unit is used to define an instruction set, which includes control instructions for execution by the control unit and calculation instructions for execution by the storage-computation integrated processing engine.

[0014] In one of the embodiments, the control instruction includes at least one of the following: a load data instruction, an align load data instruction, a storage instruction, a register configuration instruction, a write storage computing device instruction according to an immediate number, a write storage computing device instruction according to data, a data sending instruction, and a module control instruction; The calculation instructions include at least one of the following: vector-matrix multiplication instructions that are written back immediately with data preloaded, vector-matrix multiplication instructions that are not written back with data preloaded, vector-matrix multiplication instructions that are written back immediately with data immediately fetched, vector-matrix multiplication instructions that are not written back with data immediately fetched, matrix multiplication instructions that are written back immediately with data preloaded, matrix multiplication instructions that are not written back with data preloaded, matrix multiplication instructions that are written back immediately after data preprocessing, and matrix multiplication instructions that are not written back after data preprocessing.

[0015] In a second aspect, the present application provides a data processing method. Applied to the storage-computing integrated processor described in the first aspect, the method comprises: The control module generates a control signal and sends the control signal to the data module; The data module performs a data access operation and a data calculation operation based on the control signal.

[0016] In one embodiment, the data module performs data access operations and data calculation operations based on the control signal, including: The first l The feature vectors of the layer nodes are loaded into the data preloading unit and aggregated by the data preprocessing unit to obtain the aggregated result; l is a positive integer; The aggregation result is input into the storage and computing integrated processing engine for vector matrix calculation, and the vector matrix calculation result is calculated by the data post-processing unit for nonlinear activation function calculation to obtain the first l The feature vector of the +1 layer.

[0017] In one embodiment, the l The feature vectors of the layer nodes are loaded into the data preloading unit and aggregated by the data preprocessing unit to obtain the aggregation results, including: Take n adjacent periods as a group and l The current batch of data in the feature vectors of the target node and its neighboring nodes in the layer are sequentially loaded into the data preloading unit according to the cycle; n is a natural number greater than 1; In the n+1th cycle, the next batch of data in the feature vector of the target node of the lth layer is loaded into the data preloading unit, and the previous batch of data loaded into the data preloading unit is aggregated by the data preprocessing unit to obtain an aggregated point embedding vector; The aggregated point embedding vector is input into the storage-computation integrated processing engine to perform the vector matrix calculation.

[0018] In a third aspect, the present application provides a computer device in which the storage-computing integrated processor described in the first aspect is deployed.

[0019] The above-mentioned storage-computing integrated processor, data processing method and computer device, by integrating the storage unit and the storage-computing integrated processing engine into the processor, and setting multiple storage-computing integrated processing units in the storage-computing integrated processing engine, thus, on the basis of realizing storage-computing integration, a single storage-computing integrated processing unit is used as the minimum computing unit to process data, supporting data parallel computing and improving computing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of the structure of a storage-computing integrated processor in one embodiment; Figure 2 for Figure 1 A schematic diagram of the structure of the integrated storage and computing processing engine; Figure 3 for Figure 2 A schematic diagram of the structure of the integrated storage and computing array unit; Figure 4 A schematic diagram of the structure of a storage-computation integrated processing engine in one embodiment; Figure 5 is a schematic diagram of the structure of a data module in one embodiment; Figure 6 is a structural schematic diagram of a data preloading unit in one embodiment; Figure 7 is a schematic diagram of the structure of a data module in one embodiment; Figure 8 A schematic diagram of data flow in a data module in one embodiment; Fig. 9 is a schematic diagram of the structure of a data module in one embodiment; Fig.10 A schematic diagram of a state machine for a writing verification unit in one embodiment; Fig.11 is a schematic diagram of the structure of a data module in one embodiment; Fig.12 A schematic diagram of the structure of a data write-back unit in one embodiment; Fig.13A schematic diagram of data flow in a data module in one embodiment; Fig.14 is a schematic diagram of the structure of a control module in one embodiment; Fig.15 is a schematic diagram of a control instruction set in one embodiment; Fig.16 is a schematic diagram of a computing instruction set in an embodiment; Fig.17 A schematic diagram of the structure of a storage-computing integrated processor in one embodiment; Fig.18 is a flow chart of a data processing method in one embodiment; Fig.19 A schematic diagram of a flow chart of graph convolution calculation in one embodiment; Fig. 20 A schematic diagram of a graph convolution calculation process in one embodiment; Fig.21 A schematic diagram of a process of data aggregation processing in one embodiment; Fig. 22 A schematic diagram of node feature aggregation in one embodiment; Fig.23 A schematic diagram of parallel computing of a storage-computation integrated processing unit in one embodiment; Fig.24 FIG. 1 is a schematic diagram of the structure of a computer device in an embodiment. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0022] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with general skills in the technical field to which this application belongs. The words "one", "a", "the", "these" and the like in this application do not indicate a quantitative limitation, and they may be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" may mean: A exists alone, A and B exist at the same time, and B exists alone. Generally, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0023] In one embodiment, a storage and computing integrated processor is provided. Figure 1 Schematic diagram of the structure of the integrated processor in the embodiment of the present application. Figure 1 As shown, the storage-computing integrated processor includes: a control module and a data module, and the control module is connected to the data module; wherein the data module includes a storage unit and a storage-computing integrated processing engine, and the storage-computing integrated processing engine is connected to the storage unit; the control module is used to control the storage-computing integrated processing engine to obtain data from the storage unit, and instruct the storage-computing integrated processing engine to calculate the obtained data.

[0024] In this embodiment, the storage unit and the storage-computing integrated processing engine are integrated in the data module, and the data module can be regarded as an integral structure that supports access, storage, and calculation of data. Among them, the storage unit is used to store data, and the storage-computing integrated processing engine is used to perform calculation operations. Under the control of the control module, it obtains data from the storage unit and performs calculations, and the calculation results can be returned to the storage unit for storage. The control module is used to control the data module. In addition to controlling the storage-computing integrated processing engine to obtain data from the storage unit and instructing the storage-computing integrated processing engine to calculate the obtained data, it can also realize the switching of different operating modes of the entire storage-computing integrated processor and data flow control.

[0025] Figure 2 and Figure 3 The schematic diagrams of the structure of the storage and computing integrated processing engine in this embodiment are shown respectively. Figure 2 As shown, the storage-computing integrated processing engine includes N storage-computing integrated processing units and a first calculator group, and the storage-computing integrated processing unit is connected to the first calculator group; each storage-computing integrated processing unit includes M storage-computing integrated array units and a second calculator group, and the storage-computing integrated array unit is connected to the second calculator group; N and M are both natural numbers greater than 1; Figure 3 As shown, each integrated storage and computing array unit includes an integrated storage and computing array, an array control unit and a readout circuit, and the integrated storage and computing array includes a plurality of cross-arranged storage and computing devices.

[0026] In the storage-computing integrated processing engine, a single storage-computing integrated processing unit is used as the minimum computing unit to perform data calculations, and multiple calculation results of each storage-computing integrated processing unit are accumulated and / or quantified through the first calculator group.

[0027] In the storage-computation integrated processing unit, each storage-computation integrated array unit performs data calculation, and the second calculator group accumulates and / or quantifies multiple calculation results of each storage-computation integrated array unit.

[0028] In the storage-computing integrated array unit, multiple storage-computing devices are cross-arranged to form an array. Assume that the array size is A×B, A is the number of rows, B is the number of columns, and each storage-computing device corresponds to a different value. The array control unit is used to control the input voltage value, and the readout circuit is used to read the output current value. Voltage can be input on different rows, such as inputting voltage 1 on the 1st row, inputting voltage 2 on the 2nd row, ..., inputting voltage A on the Athletics row, and each storage-computing device will output current. According to Kirchhoff's current law, the total current output of each column is the sum of the output currents of each storage-computing device in a column, such as outputting current 1 on the 1st column, outputting current 2 on the 2nd column, ..., and outputting current B on the Bth column. Among them, the storage-computing device can be any memory, such as FLASH (Flash Memory), RRAM (Resistive Random Access Memory), MRAM (Magnetoresistive RandomAccess Memory) or FeFET (Ferroelectric Field-Effect Transistor).

[0029] The storage-computing integrated processor of this embodiment integrates a storage unit and a storage-computing integrated processing engine into the processor, and sets multiple storage-computing integrated processing units in the storage-computing integrated processing engine. In this way, on the basis of realizing storage-computing integration, a single storage-computing integrated processing unit is used as the minimum computing unit to process data, support data parallel computing, and improve computing efficiency.

[0030] In one embodiment, Figure 4 A schematic diagram of the structure of a storage and computing integrated processing engine is provided, such as Figure 4 As shown, the first calculator group includes a first accumulator group and / or a first quantizer group. Wherein, the first accumulator group includes N accumulators, and the accumulators are connected to the storage-computation integrated processing units one by one, and are used to accumulate multiple calculation results of the corresponding storage-computation integrated processing units. The first quantizer group includes N quantizers, and the quantizers are connected to the storage-computation integrated processing units one by one, and are used to quantize the multiple calculation results of the corresponding storage-computation integrated processing units. The second calculator group includes a second accumulator group and / or a second quantizer group. Wherein, the second accumulator group includes M accumulators, and the accumulators are connected to the storage-computation integrated array units one by one, and are used to accumulate multiple calculation results of the corresponding storage-computation integrated array units. The second quantizer group includes M quantizers, and the quantizers are connected to the storage-computation integrated array units one by one, and are used to quantize the multiple calculation results of the corresponding storage-computation integrated array units.

[0031] In some of the embodiments, the first calculator group may further include a data buffer group, the data buffer group includes N data buffers, the data buffers are connected one by one to the storage and computing integrated processing unit, and are used to temporarily store data after passing through the quantizer to provide data input for subsequent data processing.

[0032] In one embodiment, Figure 5 A structural diagram of a data module is provided, such as Figure 5 As shown, the data module also includes: a data preloading unit, a channel selection unit and a data preprocessing unit. Among them, the input end of the data preloading unit is connected to the storage unit, the output end of the data preloading unit is connected to the input end of the channel selection unit, and the data preloading unit is used to preload data from the storage unit. The input end of the channel selection unit is also connected to the storage unit, and the output end of the channel selection unit is connected to the input end of the data preprocessing unit. The channel selection unit can be switched by different instructions to select data to be calculated from the storage unit and the data preloading unit. The output end of the data preprocessing unit is connected to the storage and computing integrated processing engine, and the data preprocessing unit is used to preprocess the data output by the channel selection unit.

[0033] In this embodiment, if the data preloading unit receives an enable signal, the channel selection unit selects to read data from the data preloading unit to the data preprocessing unit; if the data preloading unit does not receive an enable signal, the channel selection unit selects to directly read data from the storage unit to the data preprocessing unit.

[0034] Figure 6 A structural diagram of a data preloading unit is provided, such as Figure 6 As shown, the data preloading unit includes N register groups, and the register groups are connected to the data preprocessing unit. Among them, the data bit width of a single group of register groups is consistent with the amount of data that can be stored in a single address in the storage unit, that is, the maximum amount of data that the data preloading unit inputs from the storage unit at a time. After executing data preloading, the data preloading unit pre-inputs the data into the data preprocessing unit based on the register unit in the control module for data preprocessing operations.

[0035] In some embodiments, the data preprocessing unit will maintain the output to the corresponding storage-computation integrated processing unit during the preprocessing process. For example, after the data preprocessing unit preprocesses the data of each register group by performing a nonlinear activation function operation or a quantization operation, the preprocessing result is transmitted to the corresponding storage-computation integrated processing unit.

[0036] In some embodiments, the data preprocessing unit changes the output corresponding to the storage-computation integrated processing unit during the preprocessing process. For example, after the data preprocessing unit aggregates the data of multiple register groups, the aggregation result is transmitted to one of the preset storage-computation integrated processing units. Data aggregation includes summing, averaging, maximizing, or minimizing the data. In some embodiments, the preprocessing unit may not perform preprocessing and directly output the data to the storage-computation integrated processing unit.

[0037] In one embodiment, Figure 7 A structural diagram of a data module is provided, such as Figure 7 As shown, the data module also includes: a data post-processing unit, the input end of the data post-processing unit is connected to the storage and computing integrated processing engine, and the output end of the data post-processing unit is connected to the storage unit; wherein the data post-processing unit is used to post-process the calculation results of the storage and computing integrated processing engine, such as numerical accumulation, quantization, and nonlinear activation function operations, and transmit the post-processing results to the storage unit.

[0038] Figure 8 A data flow diagram within a data module is provided, such as Figure 8As shown, during the calculation process, the data flow starts from the storage unit and is pre-loaded into the data preloading unit according to different calculation instruction types. If the data preloading unit receives an enable signal, the channel selection unit chooses to read data from the data preloading unit to the data preprocessing unit. If the data preloading unit does not receive an enable signal, the channel selection unit chooses to read data directly from the storage unit to the data preprocessing unit. The data preprocessing unit preprocesses the data and transmits the preprocessing results to the storage-computation integrated processing engine for calculation. In the storage-computation integrated processing engine, each storage-computation integrated processing unit calculates data in parallel, accumulates and quantizes multiple calculation results, and temporarily stores the calculation results in the data buffer. The data buffer then hands the calculation results to the data post-processing unit for further processing, and the final calculated data will be transmitted back to the storage unit.

[0039] In one embodiment, Fig. 9 A structural diagram of a data module is provided, such as Fig. 9 As shown, the data module also includes: a write verification unit, which is connected to the integrated storage and computing processing engine and the storage unit respectively; wherein the write verification unit is used to configure the write verification programming mode of the integrated storage and computing processing engine, and the write verification programming mode includes a first mode and a second mode; wherein, in the first mode, write verification programming is performed on the storage and computing device of a single address by writing instructions according to unit immediate values; in the second mode, write verification is performed on the storage and computing devices of the same row address after taking values ​​from the storage unit by writing instructions according to the address.

[0040] In this embodiment, the write verification unit is used for programming and post-programming verification operations of the storage and computing devices in the storage and computing integrated array, including two write verification programming modes, the first mode is manual (MANUAL) mode, and the second mode is automatic (AUTO) mode. Parameters related to the operation mode, write pulse time, and write verification times can be set through the register unit. Among them, the operation mode can be a data preprocessing mode, a data post-processing mode, a storage and computing integrated engine operation mode, an accumulation mode, and a quantization mode.

[0041] Fig.10 A state machine diagram of a write verification unit is provided, such as Fig.10As shown, the two write verification programming modes can be controlled by a state machine. Both modes include four stages, namely, IDLE, WRITE, VERIFY, and DONE. Among them, in the idle stage, the write verification unit is in a dormant state and does not perform any operation. In the write stage, the write verification unit performs a write operation on the storage and computing device based on the configuration register pulse width configuration. By setting the time parameters, the operation timeout is considered completed and enters the verification stage. In the verification stage, the current stage mainly reads the data of the storage and computing device and compares it with the target data. For example, if the read data matches the target data, the current write operation is completed, otherwise it returns to the write stage and restarts writing. The end stage is used to reply to the state after the write verification operation is completed, output the end signal, and prepare for the next write verification.

[0042] Among them, condition 1 is: (verification successful == 1 && verification number != Ncell) || (verification successful == 0 && verification times exceeded == 0) || (verification successful == 0 && verification times exceeded == 1 && verification number != Ncell).

[0043] Condition 2 is: (verification success == 1 || verification success == 0 && verification times exceeded == 1) && verification number != Ncell.

[0044] Condition 3 is: verification success == 1||verification times exceeded == 1.

[0045] Condition 4 is: verification success == 0 && number of times exceeded == 0.

[0046] The mode control can be used to switch between the manual and automatic state machines. The automatic mode adds automatic jump of the write device address and multiple write data loading operations on the basis of the manual mode. In addition to the normal write operation, the maximum number of attempts can be set through the register unit. When the number of attempts of the storage device exceeds the maximum value, it will be automatically skipped.

[0047] In one embodiment, Fig.11 A structural diagram of a data module is provided, such as Fig.11 As shown, the data module also includes: a data write back unit, which is connected to the integrated storage and computing processing engine and the storage unit respectively; wherein the data write back unit is used to return the calculation results of the integrated storage and computing processing engine to the storage unit in sequence according to the order of write back data.

[0048] In one embodiment, Fig.12 A structural diagram of a data write-back unit is provided, such as Fig.12As shown, the data write back unit includes: N first write back FIFOs, W second write back FIFOs, a data path switch and an arbitrator; W is a natural number greater than or equal to 1; the first write back FIFO is used to temporarily store the write back data and write back address generated by the storage and computing integrated processing engine, and send a request to the arbitrator based on the write back address; the arbitrator is used to feedback a confirmation signal to the highest priority request according to the priority of the request; the data path switch is used to select the target write back data that obtains the confirmation signal, so that the target write back data is transmitted to the second write back FIFO; the second write back FIFO is used to temporarily store the target write back data and the corresponding write back address, and when the storage unit is available, the target write back data is written to the storage unit based on the corresponding write back address.

[0049] In this embodiment, the first write-back FIFO serves as the write-back FIFO of the input channel, and the second write-back FIFO serves as the write-back FIFO of the output channel. N is the number of storage-computing integrated processing units, and W is consistent with the number of write-back channels that the storage unit can support. The minimum value requirement of W is 1.

[0050] Fig.13 A data flow diagram within a data module is provided, such as Fig.13 As shown, during the calculation process, the data flow starts from the storage unit and is pre-loaded into the data preloading unit according to different calculation instruction types. If the data preloading unit receives an enable signal, the channel selection unit chooses to read data from the data preloading unit to the data preprocessing unit. If the data preloading unit does not receive an enable signal, the channel selection unit chooses to read data directly from the storage unit to the data preprocessing unit. The data preprocessing unit preprocesses the data, and transmits the preprocessing results to the storage and computing integrated processing engine for calculation, and temporarily stores the calculation results in the data buffer. If it is an immediate write-back instruction type, the data will be immediately output to the data write-back unit after entering the data buffer, otherwise the data will continue to be stored in the data buffer, waiting for the STORE instruction. The starting and ending positions of the flow calculation data are both in the storage unit, and the data related to the network weight is stored in the storage and computing integrated array unit.

[0051] In one embodiment, Fig.14 A structural diagram of a control module is provided, such as Fig.14 As shown, the control module includes: a control unit, a register unit and an instruction unit, and the control unit is connected to the register unit, the instruction unit and the data module respectively; wherein the register unit is used to configure the operation mode and operation address of the data module, and to record the operation status of the data module; the control unit is used to generate a control signal, and control the register unit and the data module based on the control signal; the instruction unit is used to define an instruction set, and the instruction set includes control instructions for execution by the control unit, and calculation instructions for execution by the storage-computation integrated processing engine.

[0052] In this embodiment, the control unit is respectively connected to each component in the storage-computing integrated processor, and is used to control instructions, data scheduling, and calculation-related operations. The control unit may specifically include an instruction control unit, a data control unit, and a data processing control unit. In addition to controlling each component in the storage-computing integrated processor, the control unit is also responsible for controlling the data communication protocol between the storage-computing integrated processor and the external system bus, adapting the communication between the external data and the system bus to various communication protocols through the interface module, and controlling the data flow. The register unit may specifically include a state controller and a configuration register, which are used for parameter configuration of the mode and operation address and recording of the operating status, and can be configured through instructions or bus data access. The instruction unit is used to customize various operations related to the reduced instruction set, including a program counter, an instruction memory, instruction decoding, and distribution.

[0053] The control unit and the register unit jointly realize the switching of different operating modes of the storage and computing processor and the control of data flow. Among them, the status register and configuration register in the register unit can be configured in advance with interrupt enable, operating status, node enable, clock enable, data base address, data source address, data target address, PC jump base address, data preprocessing mode, data post-processing mode, storage and computing integrated processing engine operating mode, storage and computing integrated calculation address, accumulation mode, and quantization mode. The control unit can generate corresponding control signals based on the configuration in the register unit.

[0054] The control module of this embodiment has a built-in custom reduced instruction set and configuration registers, which makes the storage-computing integrated processor reconfigurable and programmable. By providing a combination of different computing instructions, multiple storage-computing integrated processing units can enter pipeline parallel computing, thereby improving the throughput of the entire storage-computing integrated processor.

[0055] Fig.15 is a schematic diagram of a control instruction set in this embodiment, Fig.16 FIG. 1 is a schematic diagram of a computing instruction set in this embodiment. Fig.15 and Fig.16As shown, this embodiment adopts a 32-bit custom instruction set, including control instructions related to data scheduling and computing instructions related to storage-computation integration processing. The opcode is 4 bits, used to represent the operation instruction; the buffer index is used to index the specified buffer; the byte mask is used to select the value taken from the storage address to load into the buffer; the start address is used to specify the starting address loaded into the data buffer; the storage address is used for direct data access of the storage unit; the storage address offset is used to calculate the address by adding it to the base address in the configuration register, so as to access the data; the type parameter is 4 bits, and the operation is adjusted for different instructions; the unit index is used to specify the storage-computation integration processing unit corresponding to the instruction; the storage-computation array index is used to specify the storage-computation integration array corresponding to the instruction; the storage-computation device address is used to index the storage-computation integration device; the storage-computation device write address is used to specify the target starting address of the data write storage-computation device instruction.

[0056] Table 1 is a 32-bit custom instruction set of this embodiment.

[0057] Table 1 Among them, control instructions can be used for data access, weight reading and writing, and data flow processing, including data loading (LOAD), data loading by byte (LOADB), data storage (STORE), register configuration (CONFIG), storage and computing device immediate data writing by unit (WRITEB), storage and computing device writing by address (WRITED), reading data to the outside (READ), and control-related instructions (CTRL), such as accumulator clearing, cache shifting, PC jump, and inserting useless instructions. The following introduces each control instruction.

[0058] LOAD: loads the data at the storage unit address into a preload buffer (i.e., data preload unit) with a specified index; LOADB: Loads data from a storage unit address into a preload buffer at a specified index; STORE: Write back the calculation results stored in the data buffer to the direct storage address. Type 4'b0000 means writing back the buffer data, and type 4'b0001 means writing back the accumulated data. CONFIG: Set data to the configuration register by directly addressing the register. Operation type [2], 1 indicates the first half of the 64-bit register, and 0 indicates the second half. Operation type [1:0] indicates the byte selection signal, 11 indicates half word, 01 and 10 indicate the first and second half bytes respectively. WRITEB: Write to a storage device at a specific location. Operation type 0000 is write 0, which is equal to reset. Operation type 0001 is write 1, which is equal to set. WRITED: write data on a specific RAM half-row from the calculated data storage address (storage address offset + address register); SEND: reads data from the storage or storage array through a direct address and sends it to the bus; CTRL: All operations are defined by different operation types: 0000 is to clear the accumulation, 0001 is to shift the data preload register; 0010 is used for PC jump; 0011 is used for instruction skipping and inserting bubbles.

[0059] Among them, the calculation instructions can be used for calculations in the storage-computation integrated processing engine, including data preloaded immediate write-back vector and matrix multiplication operations (vMUL, mvMUL), data immediate write-back vector and matrix multiplication operations (vMULI, mvMULI), data immediate non-write-back vector and matrix multiplication operations (vMULA, mvMULA), data preprocessed non-write-back vector and matrix multiplication operations (mvaMUL, mvaMULA). The following is an introduction to each calculation instruction.

[0060] vMUL: Send the data preloaded into a single preload register group (the register group in the data preload unit) to the specified storage and calculation integrated processing unit to calculate the multiplication and accumulation, and then store the result directly into the storage unit (destination data storage address = storage address offset + address register); vMULA: Sends the preloaded data in a single preload register group to the specified storage-computation integrated processing unit for multiplication and accumulation. Multiple rounds of accumulation can be performed without direct storage. vMULI: Send the data stored in the storage unit (source data storage address = storage address offset + address register 0) to the specified storage and calculation integrated processing unit to calculate the multiplication and accumulation, and then store the result directly into the storage unit (destination data storage address = storage address offset + address register); vMULAI: Sends the data stored in the storage unit (source data storage address = storage address offset + address register 0) to the specified storage-computation integrated processing unit for multiplication and accumulation. Multiple rounds of accumulation can be performed without direct storage. mvMUL: Send the data stored in multiple data buffers to the integrated storage and calculation processing unit enabled by the mask to calculate the multiplication and accumulation, and then store the result directly into the storage unit (destination data storage address = storage address offset + address register); mvULA: Sends data stored in multiple data buffers to the integrated storage and calculation processing unit enabled by the mask to calculate multiplication and accumulation. Multiple rounds of accumulation can be performed without direct storage. mvaMUL: Sends the preprocessed data to the specified storage and calculation integrated processing unit to calculate the multiplication and accumulation, and then stores the result directly into the storage unit (destination data storage address = storage address offset + address register); mvaMULA: Sends the preprocessed data to the specified integrated storage and computation processing unit to calculate multiplication and accumulation. Multiple rounds of accumulation can be performed without direct storage.

[0061] In one embodiment, Fig.17 A schematic diagram of the structure of a storage and computing integrated processor is provided. Fig.17 As shown, the storage-computing integrated processor includes: a control module and a data module; the control module includes a control unit, a register unit and an instruction unit, and the control unit is respectively connected to the register unit, the instruction unit and the data module; the data module includes a storage unit, a storage-computing integrated processing engine, a data preloading unit, a channel selection unit, a data preprocessing unit, a data post-processing unit, a write verification unit and a data write back unit, wherein the storage unit, the data preloading unit, the channel selection unit, the data preprocessing unit, the storage-computing integrated processing engine and the data post-processing unit are connected in sequence, the write verification unit is respectively connected to the storage-computing integrated processing engine and the storage unit, and the data write back unit is respectively connected to the data post-processing unit and the storage unit.

[0062] In this embodiment, after the instruction unit performs instruction fetching and decoding, the data module receives a control signal issued by the control unit, performs data access and data processing operations, and passes the data to each component in sequence through the pipeline. Among them, the storage unit is used to store initial data and calculation result data, and the data can be passed to the storage and calculation integrated processing engine or sent to the system bus via the data preloading unit. For the calculation of the internal data flow of the data module, please refer to the above embodiment, and the embodiment will not be repeated.

[0063] The storage-computing integrated processor provided in this embodiment is suitable for data processing, including neural network acceleration and matrix calculation acceleration. It adopts a custom reduced instruction set (refer to Table 1 above) and a pipeline structure (refer to the connection relationship between the components inside the data module in the above embodiment). It has programmability, high versatility and flexibility, can realize the combination of different computing instructions, support pipeline parallel computing of different storage-computing integrated processing units, and improve the throughput of the storage-computing integrated processor. The storage-computing integrated processor is reconfigurable and programmable. With the combination of programming instructions and configuration registers, it can be flexibly used in different application scenarios and optimized in different storage-computing integrated technology application scenarios.

[0064] In one embodiment, a data processing method is provided. Fig.18 The flowchart of the data processing method is as follows. Taking the method applied to the storage-computing integrated processor of any of the above embodiments as an example, the method includes the following steps: Step S101, the control module generates a control signal and sends the control signal to the data module; Step S102: the data module performs data access operations and data calculation operations based on the control signal.

[0065] In this embodiment, after the control signal sends the control signal to the data module, the data module takes and decodes the control signal, performs data access and data processing operations, and passes the data to each component in sequence through the pipeline. Among them, the data module can specifically include a storage unit and a storage and calculation integrated processing engine. The storage unit is used to store initial data and calculation result data, and the storage and calculation integrated processing engine is used to perform calculations and return the calculation results to the storage unit. For the calculation of the internal data flow of the data module, please refer to the above embodiment, and the embodiments will not be repeated here. Among them, In one embodiment, the application of a storage-computation integrated processor to graph convolution calculation is taken as an example. In the graph convolution calculation process, it is necessary to find neighboring nodes based on the target node to extract node embedding features, including point embedding aggregation, activation function, and vector-matrix multiplication. Assume that for the target node v, there is a set of u neighboring nodes, and the current l+1 The layer node feature aggregation formula is: ; in l+1 The embedding features of the target node v of the layer need to be based on the previous layer l The point embedding features of the layer are calculated, N(v) represents the number of neighboring nodes of the target node v participating in feature extraction, and L is the total number of calculation layers. Fig.19 This is a schematic diagram of the flow of graph convolution calculation in this embodiment, as shown in Fig.19 As shown, the process includes the following steps: Step S201, loading the feature vector of the node in the first layer into the data preloading unit, and performing aggregation processing through the data preprocessing unit to obtain an aggregation result; l Is a positive integer.

[0066] Fig. 20 Schematic diagram of the graph convolution calculation process in this embodiment. Fig. 20 As shown, the target node v has 2 neighboring nodes , respectively l Layer has feature vector . l The feature vector of the layer It will be preloaded into the data preloading unit and then aggregated through the data preprocessing unit.

[0067] Step S202, input the aggregation result into the storage and computing integrated processing engine for vector matrix calculation, and perform nonlinear activation function calculation on the obtained vector matrix calculation result through the data post-processing unit to obtain the feature vector of the l+1th layer.

[0068] The output results of the data preprocessing unit will be input into the storage and computing integrated processing engine for vector matrix calculation, and then the calculation results will be processed by the data post-processing unit to complete the nonlinear activation function calculation to obtain l+1 The feature vector of the layer .

[0069] Fig.21 This is a flow chart of data aggregation processing in this implementation. Fig.21 As shown, l The feature vectors of the layer nodes are loaded into the data preloading unit and aggregated by the data preprocessing unit to obtain the aggregated results, including the following steps: Step S301, taking n adjacent periods as a group, l The current batch of data in the feature vectors of the target node and its neighboring nodes in the layer are sequentially loaded into the data preloading unit according to the cycle; n is a natural number greater than 1.

[0070] Fig. 22 This is a schematic diagram of node feature aggregation in this embodiment. Fig. 22 As shown in , the cycle interval n depends on the number of data that need to be aggregated in each batch of preprocessing. Since each batch needs to aggregate the feature vector of 1 target node and the feature vectors of 2 neighboring nodes, n=3. At cycle 0, The i-th to i+7-th data are preloaded into the data preload unit; in cycle 1, The i-th to i+7-th data are preloaded into the preload unit; in cycle 2, The i-th to i+7-th data are preloaded into the preload unit. The variable i represents the position of the first data in the current batch in the point embedding vector, 0≤i≤I, and I is the length of the point embedding vector.

[0071] Step S302, in the n+1th cycle, the next batch of data in the feature vector of the target node of the lth layer is loaded into the data preloading unit, and the previous batch of data loaded into the data preloading unit is aggregated through the data preprocessing unit to obtain the aggregated point embedding vector.

[0072] In cycle 3, The i+8th to i+15th data are preloaded into the preload unit. The i-th to i+7-th data are aggregated.

[0073] Step S303, input the aggregated point embedding vector into the storage and computing integrated processing engine for vector matrix calculation.

[0074] Output the point embedding vector after aggregation The i+8th to i+15th data are sent to the storage and computing integrated processing engine for calculation; the data is preloaded based on each cycle after the cycle, and the aggregated point embedding vector is output every n cycle intervals The data in the storage and computing engine is calculated. This setting realizes data parallel computing and improves computing efficiency.

[0075] Fig.23 Schematic diagram of parallel computing of the storage and computing integrated processing unit in this embodiment. Fig.23 As shown in the figure, when multiple storage-computation integrated processing units are processed in parallel, Ndata represents the number of data that need to be aggregated during preprocessing, and Npe represents the number of storage-computation integrated processing units used. When the calculation operation of the storage-computation integrated processing unit takes 8 cycles: When Ndata=8 and Npe=1, each task takes an average of 8 cycles to complete the processing in the pipeline processing case; When Ndata=6 and Npe=2, each task takes an average of 6 cycles to complete the processing in the pipeline processing case; When Ndata=3 and Npe=3, each task takes an average of 3 cycles to complete the processing in the case of pipeline processing.

[0076] This embodiment can achieve a better throughput rate by adjusting the parallelism of the storage and computing integrated processing unit in different application scenarios by combining different programming solutions.

[0077] In one embodiment, a computer device is provided. Fig.24 It is a schematic diagram of the structure of computer equipment, such as Fig.24 As shown, a storage-computing integrated processor of any of the above-mentioned embodiments is deployed in a computer device. The computer device may also include a memory and a communication interface, and the storage-computing integrated processor is connected to the memory and the communication interface via a system bus. Among them, the storage-computing integrated processor is used to provide computing and control capabilities. The memory of the computer device may be a non-volatile storage medium and an internal memory, wherein the non-volatile storage medium stores an operating system, a computer program and a database, the internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium, and the database is used to store data. The communication interface of the computer device is used to communicate with an external terminal through a network connection.

[0078] It should be noted that, in this embodiment, specific examples of the storage-computing integrated processor can refer to the examples described in the above embodiments and optional implementation modes, and will not be repeated in this embodiment.

[0079] Those skilled in the art will understand that Fig.24 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0080] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0081] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0082] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0083] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A storage and computing integrated processor, characterized in that: include: A control module and a data module, wherein the control module is connected to the data module; wherein the data module includes a storage unit and a storage-computing integrated processing engine, and the storage-computing integrated processing engine is connected to the storage unit; The storage-computation integrated processing engine includes N storage-computation integrated processing units and a first calculator group, and the storage-computation integrated processing unit is connected to the first calculator group; each of the storage-computation integrated processing units includes M storage-computation integrated array units and a second calculator group, and the storage-computation integrated array unit is connected to the second calculator group; N and M are both natural numbers greater than 1; each of the storage-computation integrated array units includes a storage-computation integrated array, an array control unit and a readout circuit, and the storage-computation integrated array includes a plurality of storage-computation devices arranged crosswise; The control module is used to control the storage-computing integrated processing engine to obtain data from the storage unit, and to instruct the storage-computing integrated processing engine to calculate the obtained data.

2. The integrated storage and computing processor according to claim 1, characterized in that: The first calculator group includes a first accumulator group and / or a first quantizer group; wherein the first accumulator group includes N accumulators, and the accumulators are connected to the storage-computation integrated processing unit one by one; the first quantizer group includes N quantizers, and the quantizers are connected to the storage-computation integrated processing unit one by one; The second calculator group includes a second accumulator group and / or a second quantizer group; wherein, the second accumulator group includes M accumulators, and the accumulators are connected one-to-one with the storage and computing array units; the second quantizer group includes M quantizers, and the quantizers are connected one-to-one with the storage and computing array units.

3. The integrated storage and computing processor according to claim 1, characterized in that: The data module also includes: a data preloading unit, a channel selection unit and a data preprocessing unit; wherein, The input end of the data preloading unit is connected to the storage unit, the output end of the data preloading unit is connected to the input end of the channel selection unit, and the data preloading unit is used to preload data from the storage unit; The input end of the channel selection unit is also connected to the storage unit, the output end of the channel selection unit is connected to the input end of the data preprocessing unit, and the channel selection unit is used to select the data to be calculated from the storage unit and the data preloading unit; The output end of the data preprocessing unit is connected to the storage-computation integrated processing engine, and the data preprocessing unit is used to preprocess the data output by the channel selection unit.

4. The integrated storage and computing processor according to claim 3, characterized in that: The data preloading unit includes N register groups, and the register groups are connected to the data preprocessing unit; the data preprocessing unit is used to preprocess the data output by the channel selection unit, including: The data preprocessing unit preprocesses the data of each register group and transmits the preprocessing result to the corresponding storage-computation integrated processing unit; or The data preprocessing unit aggregates the data of the plurality of register groups and transmits the aggregation result to one of the preset storage-computation integrated processing units.

5. The integrated storage and computing processor according to claim 1, characterized in that: The data module further includes: a data post-processing unit, the input end of the data post-processing unit is connected to the storage and computing integrated processing engine, and the output end of the data post-processing unit is connected to the storage unit; wherein, The data post-processing unit is used to post-process the calculation results of the storage and computing integrated processing engine and transmit the post-processing results to the storage unit.

6. The integrated storage and computing processor according to claim 1, characterized in that: The data module further includes: a write verification unit, which is connected to the storage-computation integrated processing engine and the storage unit respectively; wherein, The write verification unit is used to configure the write verification programming mode of the storage-computation integrated processing engine, and the write verification programming mode includes a first mode and a second mode; wherein, In the first mode, write verification programming is performed on the storage computing device at a single address by writing an immediate unit value instruction; In the second mode, write verification is performed on the storage and computing devices at the same row address after taking values ​​from the storage cells according to address write instructions.

7. The integrated storage and computing processor according to claim 1, characterized in that: The data module further includes: a data write-back unit, which is connected to the storage-computation integrated processing engine and the storage unit respectively; wherein, The data write-back unit is used to return the calculation results of the storage-computation integrated processing engine to the storage unit in sequence according to the order of writing back data.

8. The integrated storage and computing processor according to claim 7, characterized in that: The data write-back unit includes: N first write-back FIFOs, W second write-back FIFOs, a data path switch and an arbiter; W is a natural number greater than or equal to 1; The first write-back FIFO is used to temporarily store the write-back data and write-back address generated by the storage-computation integrated processing engine, and send a request to the arbitrator based on the write-back address; The arbiter is used to feed back a confirmation signal to the highest priority request according to the priority of the request; The data path switch is used to select the target write-back data that obtains the confirmation signal, so that the target write-back data is transmitted to the second write-back FIFO; The second write-back FIFO is used to temporarily store the target write-back data and the corresponding write-back address, and when the storage unit is available, write the target write-back data into the storage unit based on the corresponding write-back address.

9. The integrated storage and computing processor according to claim 1, characterized in that: The control module includes: a control unit, a register unit and an instruction unit, and the control unit is connected to the register unit, the instruction unit and the data module respectively; wherein, The register unit is used to configure the operation mode and operation address of the data module, and record the operation status of the data module; The control unit is used to generate a control signal and control the register unit and the data module based on the control signal; The instruction unit is used to define an instruction set, which includes control instructions for execution by the control unit and calculation instructions for execution by the storage-computation integrated processing engine.

10. The integrated storage and computing processor according to claim 9, characterized in that: The control instruction includes at least one of the following: a load data instruction, an align load data instruction, a storage instruction, a register configuration instruction, a write storage computing device instruction according to an immediate number, a write storage computing device instruction according to data, a data sending instruction, and a module control instruction; The calculation instructions include at least one of the following: vector-matrix multiplication instructions that are written back immediately with data preloaded, vector-matrix multiplication instructions that are not written back with data preloaded, vector-matrix multiplication instructions that are written back immediately with data immediately fetched, vector-matrix multiplication instructions that are not written back with data immediately fetched, matrix multiplication instructions that are written back immediately with data preloaded, matrix multiplication instructions that are not written back with data preloaded, matrix multiplication instructions that are written back immediately after data preprocessing, and matrix multiplication instructions that are not written back after data preprocessing.

11. A data processing method, characterized in that: Applied to the storage-computing integrated processor according to any one of claims 1 to 10, the method comprising: The control module generates a control signal and sends the control signal to the data module; The data module performs a data access operation and a data calculation operation based on the control signal.

12. The data processing method according to claim 11, characterized in that: The data module performs a data access operation and a data calculation operation based on the control signal, including: The first l The feature vectors of the layer nodes are loaded into the data preloading unit and aggregated by the data preprocessing unit to obtain the aggregated result; l is a positive integer; The aggregation result is input into the storage and computing integrated processing engine for vector matrix calculation, and the obtained vector matrix calculation result is calculated by the data post-processing unit for nonlinear activation function calculation to obtain the first l The feature vector of the +1 layer.

13. The data processing method according to claim 12, characterized in that: The first l The feature vectors of the layer nodes are loaded into the data preloading unit and aggregated by the data preprocessing unit to obtain the aggregation results, including: Take n adjacent periods as a group and l The current batch of data in the feature vectors of the target node and its neighboring nodes in the layer are sequentially loaded into the data preloading unit according to the period; n is a natural number greater than 1; In the n+1th cycle, the l The next batch of data in the feature vector of the target node of the layer is loaded into the data preloading unit, and the data preprocessing unit aggregates the previous batch of data loaded into the data preloading unit to obtain an aggregated point embedding vector; The aggregated point embedding vector is input into the storage-computation integrated processing engine to perform the vector matrix calculation.

14. A computer device, characterized in that: The computer device is deployed with a storage-computing integrated processor as described in any one of claims 1 to 10.

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