Memory, operating method thereof, memory system, and electronic device

Abstract

The embodiment of the invention discloses a memory, an operation method of the memory, a memory system and electronic equipment. The memory includes a peripheral circuit; the peripheral circuit includes: a first register circuit configured to store a plurality of initial refresh rates; the plurality of initial refresh rates are in one-to-one correspondence with the plurality of initial temperature sections; a temperature sensing circuit configured to generate a temperature signal based on the sensed temperature; a control logic circuit configured to determine a target configuration refresh rate based on the temperature signal and the configuration mapping table, and adjust a target initial refresh rate in the plurality of initial refresh rates to the target configuration refresh rate; the configuration mapping table comprises a plurality of configuration temperature sections and a plurality of configuration refresh rates, and the plurality of configuration temperature sections and the plurality of configuration refresh rates are in one-to-one correspondence.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to semiconductor technology, and relate to but are not limited to a memory and an operating method thereof, a memory system, and an electronic device. Background Art

[0002] Semiconductor memories are divided into volatile memories and non-volatile memories according to whether the stored data is retained when power is off, among which volatile memories whose data is lost when power is off may include static random-access memory (SRAM) and dynamic random access memory (DRAM).

[0003] Volatile memory needs to be refreshed periodically to maintain the data stored in the memory cell. As the temperature rises, the data retention characteristics of the memory cell deteriorate. Therefore, how to adjust the refresh frequency (also known as the refresh rate) of the volatile memory based on the temperature change has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a memory and an operating method thereof, a memory system, and an electronic device.

[0005] In a first aspect, an embodiment of the present disclosure provides a memory, wherein the memory includes a peripheral circuit; the peripheral circuit includes:

[0006] A first register circuit, wherein the first register circuit is configured to: store a plurality of initial refresh rates; wherein the plurality of initial refresh rates correspond to a plurality of initial temperature sections one by one;

[0007] a temperature sensing circuit, the temperature sensing circuit being configured to: sense a temperature of the memory and generate a temperature signal based on the sensed temperature;

[0008] A control logic circuit, wherein the control logic circuit is configured to: determine a target configuration refresh rate based on the temperature signal and a configuration mapping table, and adjust the target initial refresh rate among the multiple initial refresh rates to the target configuration refresh rate; wherein the configuration mapping table includes multiple configuration temperature segments and multiple configuration refresh rates, and the multiple configuration temperature segments and the multiple configuration refresh rates correspond one to one.

[0009] In some embodiments, the peripheral circuit further includes:

[0010] a second register circuit, the second register circuit being configured to store the configuration mapping table;

[0011] The control logic circuit is specifically configured to: read the second register circuit based on the temperature signal to determine the target configuration refresh rate.

[0012] In some embodiments, the configuration mapping table includes a plurality of sub-configuration mapping tables, and the sub-configuration mapping tables are used to record the corresponding relationship between the configuration temperature segments and the configuration refresh rates; the peripheral circuit further includes:

[0013] An address decoding circuit, the address decoding circuit being configured to: decode and generate a target address based on the temperature signal; wherein the target address is used to indicate a physical address of a target sub-configuration mapping table among the multiple sub-configuration mapping tables;

[0014] The control logic circuit is specifically configured to: based on the target address, obtain the target sub-configuration mapping table and determine the target configuration refresh rate.

[0015] In some embodiments, the first register circuit is further configured to:

[0016] Updating the target initial refresh rate to the target configuration refresh rate;

[0017] The target configuration refresh rate is sent to a memory controller.

[0018] In some embodiments, the peripheral circuit further includes:

[0019] an electric fuse circuit, the electric fuse circuit being configured to store the configuration mapping table;

[0020] The control logic circuit is specifically configured to: read the configuration mapping table in the electrical fuse circuit, and save the read configuration mapping table into the second register circuit.

[0021] In some embodiments, the initial refresh rate includes a basic refresh rate and an initial multiple value, and the initial multiple values ​​of any two of the multiple initial refresh rates are different; the configured refresh rate includes the basic refresh rate and a configured multiple value, and the configured multiple values ​​of any two of the multiple configured refresh rates are different;

[0022] The control logic circuit is specifically configured to: determine a configuration multiple value of the target configuration refresh rate based on the temperature signal and the configuration mapping table;

[0023] The first register circuit is further configured to update the initial multiple value of the target initial refresh rate to the configured multiple value of the target configured refresh rate.

[0024] In some embodiments, the multiple initial temperature segments include N initial temperature segments, N is an integer greater than 1; the configuration mapping table includes N configured temperature segments; wherein the minimum temperature of the i-th initial temperature segment is different from the minimum temperature of the i-th configured temperature segment; and / or the maximum temperature of the i-th initial temperature segment is different from the maximum temperature of the i-th configured temperature segment; i is an integer greater than or equal to 1 and less than or equal to N.

[0025] In some embodiments, the control logic circuit is further configured to:

[0026] Entering a refresh mode based on a current refresh command sent by the memory controller;

[0027] Entering the refresh mode based on a next refresh command sent by the memory controller; wherein the target configuration refresh rate is used to indicate a time interval between the next refresh command and the current refresh command.

[0028] In some embodiments, the memory is further configured to:

[0029] After the usage time of the memory is greater than or equal to the preset time, at least one of the configuration temperature sections in the configuration mapping table is updated.

[0030] In a second aspect, an embodiment of the present disclosure further provides a method for operating a memory, wherein the memory peripheral circuit comprises a first register circuit, and the first register circuit is configured to store a plurality of initial refresh rates; wherein the plurality of initial refresh rates correspond to a plurality of initial temperature sections one by one; and the operating method comprises:

[0031] sensing a temperature of the memory, and generating a temperature signal based on the sensed temperature;

[0032] Determining a target configuration refresh rate based on the temperature signal and a configuration mapping table; wherein the configuration mapping table includes a plurality of configuration temperature segments and a plurality of configuration refresh rates, and the plurality of configuration temperature segments and the plurality of configuration refresh rates correspond one to one;

[0033] A target initial refresh rate among the multiple initial refresh rates is adjusted to the target configuration refresh rate.

[0034] In some embodiments, the peripheral circuit further includes a second register circuit configured to store the configuration mapping table;

[0035] The determining the target configuration refresh rate based on the temperature signal and the configuration mapping table includes:

[0036] Based on the temperature signal, the second register circuit is read to determine the target configuration refresh rate.

[0037] In some embodiments, the configuration mapping table includes a plurality of sub-configuration mapping tables, and the sub-configuration mapping tables are used to record the corresponding relationship between the configuration temperature segments and the configuration refresh rates;

[0038] The step of reading the second register circuit based on the temperature signal to determine the target configuration refresh rate includes:

[0039] Based on the temperature signal, decoding generates a target address; wherein the target address is used to indicate a physical address of a target sub-configuration mapping table among the multiple sub-configuration mapping tables;

[0040] Based on the target address, the target sub-configuration mapping table is obtained to determine the target configuration refresh rate.

[0041] In some embodiments, the operating method further includes:

[0042] Updating the target initial refresh rate to the target configuration refresh rate;

[0043] The target configuration refresh rate is sent to a memory controller.

[0044] In some embodiments, the peripheral circuit further includes an electric fuse circuit, and the electric fuse circuit is configured to store the configuration mapping table; the operation method further includes:

[0045] The configuration mapping table in the electrical fuse circuit is read, and the read configuration mapping table is stored in the second register circuit.

[0046] In some embodiments, the initial refresh rate includes a basic refresh rate and an initial multiple value, and the initial multiple values ​​of any two of the multiple initial refresh rates are different; the configured refresh rate includes the basic refresh rate and a configured multiple value, and the configured multiple values ​​of any two of the multiple configured refresh rates are different;

[0047] The determining the target configuration refresh rate based on the temperature signal and the configuration mapping table includes:

[0048] Determine a configuration multiple value of the target configuration refresh rate based on the temperature signal and the configuration mapping table;

[0049] The step of adjusting the target initial refresh rate to the target configuration refresh rate includes:

[0050] The initial multiple value of the target initial refresh rate is updated to the configuration multiple value of the target configuration refresh rate.

[0051] In some embodiments, the multiple initial temperature segments include N initial temperature segments, N is an integer greater than 1; the configuration mapping table includes N configured temperature segments; wherein the minimum temperature of the i-th initial temperature segment is different from the minimum temperature of the i-th configured temperature segment; and / or the maximum temperature of the i-th initial temperature segment is different from the maximum temperature of the i-th configured temperature segment; i is an integer greater than or equal to 1 and less than or equal to N.

[0052] In some embodiments, the operating method further includes:

[0053] Entering a refresh mode based on a current refresh command sent by the memory controller;

[0054] Entering the refresh mode based on a next refresh command sent by the memory controller; wherein the target configuration refresh rate is used to indicate a time interval between the next refresh command and the current refresh command.

[0055] In some embodiments, the operating method further includes:

[0056] After the usage time of the memory is greater than or equal to the preset time, at least one of the configuration temperature sections in the configuration mapping table is updated.

[0057] In a third aspect, an embodiment of the present disclosure further provides a memory system, the memory system comprising:

[0058] One or more memories as described in any one of the embodiments of the first aspect of the present disclosure;

[0059] A memory controller is coupled to the memory and configured to control the memory.

[0060] In a fourth aspect, an embodiment of the present disclosure further provides an electronic device, comprising the memory system as described in the above embodiment.

[0061] In the disclosed embodiment, the temperature of the memory is sensed by a temperature sensing circuit and a temperature signal is generated based on the sensed temperature. The control logic circuit determines the target configuration refresh rate based on the temperature signal and the configuration mapping table, and adjusts the target initial refresh rate to the target configuration refresh rate. In this way, on the one hand, the expected refresh rate can be generated based on the data retention characteristics of the memory to avoid data loss and ensure data reliability; on the other hand, the refresh rate can be flexibly adjusted based on the data retention characteristics of the memory to avoid frequent refresh operations, thereby reducing power consumption and increasing the service life of the memory; on the third hand, without changing the circuit design, the range of the temperature segment can be flexibly configured and the configuration mapping table can be customized to meet the data retention requirements of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 is a schematic diagram of a system according to an embodiment of the present disclosure;

[0063] Figure 2 is a schematic diagram of a dynamic random access memory according to an embodiment of the present disclosure;

[0064] Figure 3 is a schematic diagram showing the variation of leakage current with temperature according to an embodiment of the present disclosure;

[0065] Figure 4 is a schematic diagram showing the variation of data retention time with temperature according to an embodiment of the present disclosure;

[0066] Figure 5 is a schematic diagram showing the change of the initial refresh rate with the initial temperature section according to an embodiment of the present disclosure;

[0067] Figure 6 is a schematic diagram of a mode register according to an embodiment of the present disclosure;

[0068] Figure 7a and Figure 7b is a schematic diagram of a memory according to an embodiment of the present disclosure;

[0069] Figure 8 is a schematic diagram showing changes in configuration refresh rate with configuration temperature range according to an embodiment of the present disclosure;

[0070] Fig. 9 is a flow chart of a method for operating a memory according to an embodiment of the present disclosure;

[0071] Fig.10 is a schematic diagram showing a method of adjusting a refresh rate according to an embodiment of the present disclosure;

[0072] Fig.11 The present invention is a flowchart showing a method of generating a configuration mapping table through an algorithm according to an embodiment of the present invention. DETAILED DESCRIPTION

[0073] In order to facilitate the understanding of the present disclosure, the exemplary embodiments of the present disclosure will be described in more detail below with reference to the relevant drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0074] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In some embodiments, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0075] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, terms such as "one" or "the" can also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0076] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0077] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0078] Figure 1 1 is a schematic diagram of a system 1 according to an embodiment of the present disclosure. The system 1 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein.

[0079] like Figure 1As shown in , system 1 may include a host HOST and a memory system 30, the memory system 30 having one or more memories 20 and a memory controller 10. The host HOST may be a processor (e.g., a central processing unit (CPU) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host HOST may be configured to send data to the memory 20 or receive data from the memory 20. The memory controller 10 is coupled to the memory 20 and the host HOST, and is configured to control the memory 20. The memory controller 10 may manage data stored in the memory 20 and communicate with the host HOST.

[0080] The memory controller 10 may be configured to control operations of the memory 20, such as read, erase, write and refresh operations. In some embodiments, the memory controller 10 is also configured to process error correction codes (ECC) on data read from or written to the memory 20. The memory controller 10 may also perform any other suitable functions, such as formatting the memory 20.

[0081] In some specific embodiments, the memory controller 10 and one or more memories 20 can be integrated into various types of storage devices. For example, the memory controller 10 can be integrated into the north bridge of the computer motherboard or directly integrated into the computer CPU, and multiple memories 20 can be integrated into a memory stick. In other words, the memory system 30 can be implemented and packaged into different types of terminal electronic products.

[0082] The memory controller 10 may send data to or receive data from the host HOST, and may send a command CMD and an address ADDR to the memory 20. The memory controller 10 may include a command generator 110, an address generator 120, a device interface 130, and a host interface 140. The host interface 140 may receive a command CMD and an address ADDR from the host HOST, and the command generator 110 may generate an access command, a refresh command, etc. by decoding the command CMD received from the host HOST, and may provide the access command and the refresh command to the memory 20 through the device interface 130. The access command may be a signal instructing the memory 20 to write or read data by accessing a row of the memory cell array 220 corresponding to the address ADDR. The refresh command may be a signal instructing the memory 20 to read out and rewrite data by accessing a row of the memory cell array 220 corresponding to the refresh address ADDR.

[0083] The address generator 120 in the memory controller 10 can generate a row address and a column address to be accessed in the memory cell array 220 by decoding the address ADDR received from the host interface 140. In addition, the memory 20 can generate an address of a memory bank to be accessed when the memory cell array 220 includes a plurality of memory banks.

[0084] In addition, the memory controller 10 can control memory operations such as writing and reading by providing various signals to the memory 20 via the device interface 130. For example, the memory controller 10 can provide a write command to the memory 20. The write command is used to instruct the memory 20 to perform a write operation to store data in the memory 20. In some embodiments, the memory 20 includes a memory cell array 220 and a peripheral circuit 210; wherein the memory cell array 220 includes a plurality of memory banks, each memory bank includes a plurality of memory blocks (Block), each memory block includes a plurality of memory cell rows and a plurality of memory cell columns, each memory cell row is coupled to a corresponding word line, and each memory cell column is coupled to a corresponding bit line. The peripheral circuit 210 can write data to the memory cell array 220 or read data from the memory cell array 220 based on the command CMD and the address ADDR received from the memory controller 10, or can provide a control signal CTRL for refreshing the memory cells included in the memory cell array 220 to the row decoder and the column decoder. In other words, the peripheral circuit 210 can perform all operations to process the data in the memory cell array 220. The peripheral circuit 210 may include: a control circuit corresponding to each storage block, for example, a sensing amplifier circuit (SA) and a word-line driver circuit (WLD), etc., a control circuit corresponding to each storage body, for example, a row decoder, a column decoder, etc., and a control circuit corresponding to all storage bodies, for example, a command buffer, a command decoder, an address buffer, a data input / output buffer, a mode register, etc.

[0085] The memory 20 may be a random access memory (RAM), such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a static RAM (SRAM), a double data rate SDRAM (DDR SDRAM), a DDR2 SDRAM, a DDR3 SDRAM, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), etc. The following description only takes DRAM as an example.

[0086] Figure 2is a schematic diagram of a dynamic random access memory according to an embodiment of the present disclosure. Figure 2 As shown, the dynamic random access memory includes at least one DRAM chip (Die), each DRAM chip includes a memory cell array, the memory cell array includes a plurality of memory cells 201 arranged in an array, each memory cell 201 includes a transistor T (Transistor) and a capacitor C (Capacitor), and the main working principle of the memory cell is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. The memory cells are arranged in an array, which can be regarded as a typical mesh structure. The mesh structure can be specifically referred to in the following Figure 7b The memory cell array uses rows and columns to specify addresses. By specifying the intersection of rows and columns (by specifying the row address and column address of DRAM), the memory controller can independently access each memory cell in the DRAM chip and read, write or refresh the data stored in it.

[0087] The leakage current of a DRAM memory cell is proportional to the temperature, that is, the leakage current increases with the increase of temperature. Figure 3 As shown. Since the charge stored in the memory cell is limited, the data retention time of the memory cell is inversely proportional to the temperature. For example, the data retention time at 40°C is t1, and the data retention time at 80°C is t2, and t2 is less than t1, as shown in Figure 4 In order to ensure data reliability, DRAM needs to perform periodic refresh operations to maintain the data stored in the storage unit.

[0088] There are two ways of periodic refresh operation: one is that the memory controller periodically issues a refresh command, and the memory controller is responsible for maintaining the data (also known as automatic refresh); the other way is that the memory generates a refresh signal internally (also known as self-refresh). In the automatic refresh operation, the time interval between two refresh commands issued by the memory controller is usually related to the temperature to ensure that the data remains unchanged. If the time interval between two refresh commands is short, the refresh command will take too much time, thereby reducing the time for normal read and write operations. Therefore, the time interval should be updated according to the temperature, which can not only retain the data, but also provide more time for normal read and write operations. In addition, it also reduces the refresh frequency by temperature changes (for example, temperature reduction) to reduce power consumption.

[0089] The memory controller updates the time interval between two refresh commands according to the refresh rate stored in the mode register in the memory. Specifically, the memory updates the refresh rate according to the change in temperature, the mode register sends the updated refresh rate to the memory controller, and the memory controller sends a refresh command to the memory based on the updated refresh rate. It can be understood that the time interval between two refresh commands is notified to the memory controller by the mode register.

[0090] The mode register stores multiple initial refresh rates, which correspond to multiple initial temperature segments. For example, the operating temperature range of the memory is -25°C ≤ T ≤ 80°C. Based on multiple initial temperature values, -25°C ≤ T ≤ 80°C can be divided into multiple initial temperature segments, each of which corresponds to an initial refresh rate, and different initial temperature segments correspond to different initial refresh rates. For example, refer to Figure 5 As shown, 16 initial temperature values ​​are selected according to the operating temperature range of the memory, for example, the initial temperature value T e1 , T e2 ,……,T e16 , it can be divided into 17 initial temperature sections.

[0091] According to the JEDEC (Joint Electron Device Engineering Council) protocol, the mode register stores 17 initial refresh rates, for example, low temperature limit refresh rate, refresh rate 8x, ..., high temperature limit refresh rate, such as Figure 6 As shown, each initial refresh rate corresponds to a refresh rate code, and different initial refresh rates correspond to different refresh rate codes. Exemplarily, when the temperature of the memory changes to the second initial temperature segment, the mode register sends the refresh rate code 5'b00001 corresponding to the initial refresh rate 8x to the memory controller, and the memory controller performs an automatic refresh operation on the memory at the initial refresh rate of 8x.

[0092] Since multiple initial temperature segments are fixed and it is difficult to adjust the range of the initial temperature segments, the initial refresh rates corresponding to all temperatures in the same initial temperature segment are also fixed. However, for different memories, the data retention characteristics of their storage units at a certain temperature may be different, and it will be difficult to produce the expected refresh rate using a fixed initial temperature segment.

[0093] Figure 7a and Figure 7b is a schematic diagram of a memory 300 according to an embodiment of the present disclosure. Figure 7a and Figure 7bAs shown, the memory 300 includes a peripheral circuit 310; the peripheral circuit 310 includes:

[0094] A first register circuit 350, wherein the first register circuit 350 is configured to: store a plurality of initial refresh rates; wherein the plurality of initial refresh rates correspond to the plurality of initial temperature sections one by one;

[0095] The temperature sensing circuit 330 is configured to: sense the temperature of the memory 300 and generate a temperature signal based on the sensed temperature;

[0096] The control logic circuit 340 is configured to: determine the target configuration refresh rate based on the temperature signal and the configuration mapping table, and adjust the target initial refresh rate among the multiple initial refresh rates to the target configuration refresh rate; wherein the configuration mapping table includes multiple configuration temperature segments and multiple configuration refresh rates, and the multiple configuration temperature segments and the multiple configuration refresh rates correspond one to one.

[0097] In the disclosed embodiment, the memory 300 includes but is not limited to DRAM, double data rate synchronous dynamic random access memory (Double Data Rate, DDR), low power double data rate dynamic random access memory (Low Power Double Data Rate, LPDDR), graphics double data rate dynamic random access memory (Graphics Double Data Rate, GDDR) and high bandwidth memory (High Bandwidth Memory, HBM), etc.

[0098] Reference Figure 7b As shown, the memory 300 includes a plurality of word lines 322 and a plurality of bit lines 323, and the peripheral circuit 310 is coupled to the memory cell array 320 through the plurality of word lines 322 and the plurality of bit lines 323. The memory cell array 320 includes a plurality of memory cells 321 arranged in an array, and the memory cell 321 includes a transistor 324 and an energy storage element 325 coupled to the transistor 324. The transistor 324 includes a semiconductor column 326, a gate dielectric layer 327 and a gate 328, the semiconductor column includes a source, a drain and a channel between the source and the drain, the gate dielectric layer 327 covers the sidewall of the channel, and the gate 328 contacts at least one sidewall of the gate dielectric layer 327; wherein the word line 322 is coupled to the gate of the memory cell 321 in the same row, and the bit line 323 is coupled to the semiconductor column (for example, the drain of the semiconductor column) of the memory cell 321 in the same column.

[0099] In a specific embodiment, the storage unit 321 may be a volatile storage unit. For example, a DRAM storage unit, and the energy storage element 325 may be a capacitor. Of course, in other embodiments, the storage unit 321 may be a phase change storage unit, and the energy storage element 325 may be a phase change storage layer; or, the storage unit 321 may also be a ferroelectric storage unit, and the energy storage element 325 may be a ferroelectric storage layer; the present disclosure does not limit this.

[0100] The first register circuit 350 may store multiple initial refresh rates, each of which corresponds to multiple initial temperature segments, which are divided based on at least one initial temperature value, wherein each initial temperature segment corresponds to an initial refresh rate, and different initial temperature segments correspond to different initial refresh rates. The first register circuit 350 includes but is not limited to a mode register.

[0101] Exemplarily, 17 initial refresh rates are stored in the first register circuit 350, for example, a low temperature limit refresh rate, a refresh rate of 8x, ..., a high temperature limit refresh rate, such as Figure 6 The 17 initial refresh rates correspond to 17 initial temperature segments, and the 17 initial temperature segments are divided based on 16 initial temperature values. For example, the initial temperature value T e1 , T e2 ,……,T e16 Each initial refresh rate corresponds to a refresh rate code, and different initial refresh rates correspond to different refresh rate codes.

[0102] The refresh rate indicates how often the data stored in the memory is read out and rewritten. Periodically reading out and rewriting the data stored in the memory can keep the leakage of the energy storage element (e.g., capacitor) used to store data in the memory small, thereby avoiding the problem of being unable to distinguish between logical values ​​"0" and "1" due to large leakage, and ensuring the reliability of the data stored in the memory. Generally speaking, the higher the temperature of the memory operating environment, the faster the leakage speed of the energy storage element used to store data. Therefore, the higher the temperature of the memory, the higher the corresponding refresh rate.

[0103] It should be noted that the multiple initial refresh rates stored in the first register circuit 350 are based on the JEDEC protocol, and are usually written into each die (ultimately packaged as a memory) during packaging. The multiple initial refresh rates and the initial temperature segments corresponding to the multiple initial refresh rates are fixed, and it is difficult to adapt to the data retention characteristics of different memories. Therefore, the configuration mapping table set in the embodiment of the present disclosure can generate an expected refresh rate based on the data retention characteristics of the memory to meet the data retention requirements of the memory. The configuration mapping table will be described in detail below, and for the sake of brevity, it will not be repeated here.

[0104] The temperature sensing circuit 330 can sense the temperature of the memory 300 and output a temperature signal based on the sensed temperature. In a specific embodiment, the temperature sensing circuit 330 includes a temperature sensor, which can convert an analog temperature signal into a digital temperature signal and send the digital temperature signal to the control logic circuit 340. The temperature signal output by the temperature sensor can be a voltage signal corresponding to the sensed temperature, and the number of temperature sensors can be one or more. Although the present embodiment describes the case where the temperature sensing circuit 330 is located in the memory 300, the temperature sensing circuit 330 can be outside the memory 300 and sense the temperature of the memory 300.

[0105] It should be noted that a plurality of temperature sections can be divided according to the operating temperature range of the memory, and the temperature signals corresponding to different temperatures can be the same or different. For example, if the first temperature and the second temperature belong to the same temperature section, the temperature signals corresponding to the first temperature and the second temperature can be the same; for another example, if the first temperature and the second temperature belong to different temperature sections, the temperature signals corresponding to the first temperature and the second temperature can be different.

[0106] In practical applications, at least one configuration temperature value may be selected according to the operating temperature range of the memory, and multiple configuration temperature sections may be divided based on the configuration temperature value, and the multiple configuration temperature sections may correspond to multiple configuration refresh rates. Here, the selection of the configuration temperature value may be determined based on the data retention characteristics of the memory itself; when multiple configuration temperature values ​​are selected, at least one of the multiple configuration temperature values ​​may be different from the above initial temperature value.

[0107] For example, 16 configuration temperature values ​​may be selected to divide 17 configuration temperature sections, for example, the configuration temperature sections T in Table 1 c1 , T c2 ,……,T c9 ,……,T c16 and T c17 ; The 17 configuration temperature segments correspond to 17 configuration refresh rates, for example, the configuration refresh rates RM1, RM2, ..., RM9, ..., RM 16 and RM 17 .

[0108] In a specific example, the 16 configuration temperature values ​​are 25°C, 30°C, 35°C, 40°C, 42°C, 45°C, 48°C, 50°C, 52°C, 55°C, 60°C, 65°C, 70°C, 75°C, 80°C and 85°C. It should be noted that the selection of the configuration temperature value can be determined based on the temperature variation characteristics of the memory leakage current. For example, if the memory leakage current changes dramatically at a certain temperature, the temperature can be determined as the configuration temperature value. The above numerical values ​​are only examples for conveying the present disclosure to those skilled in the art, and the selection of the configuration temperature value is not limited thereto.

[0109] The control logic circuit 340 can receive the temperature signal, determine the target configuration refresh rate based on the received temperature signal and the configuration mapping table, and adjust the initial refresh rate corresponding to the temperature signal (i.e., the target initial refresh rate) to the target configuration refresh rate, and the mode register sends the refresh rate code corresponding to the target configuration refresh rate to the memory controller, and the memory controller performs an automatic refresh operation on the memory at the target configuration refresh rate. Here, the target configuration refresh rate and the target initial refresh rate can be the same or different.

[0110] For example, refer to Figure 6 and Figure 8 As shown, when the temperature sensing circuit 330 senses that the temperature of the memory 300 is greater than the configured temperature value T e2x And less than or equal to the initial temperature value T e2 (i.e., in the second initial temperature section), if the configuration mapping table is not set, the control logic circuit 340 determines the target initial refresh rate to be 8x based on the temperature, and the first register circuit 350 sends the refresh rate code 5'b00001 corresponding to the refresh rate 8x to the memory controller, and the memory controller performs an automatic refresh operation on the memory 300 at a refresh rate of 8x. However, the refresh rate 8x corresponding to the temperature may not be sufficient to maintain the data stored in the memory 300, resulting in data loss and reduced reliability of the memory 300.

[0111] For example, refer to Figure 6 and Figure 8 As shown, when the temperature sensing circuit 330 senses that the temperature of the memory 300 is greater than the configured temperature value T e2x And less than or equal to the configured temperature value T e3x(i.e., located in the third configuration temperature zone), if a configuration mapping table is set, the control logic circuit 340 determines that the configuration refresh rate is RM3 based on the temperature and the configuration mapping table. For example, RM3 can be a refresh rate of 6x. The first register circuit 350 sends the refresh rate code 5'b00010 corresponding to the refresh rate 6x to the memory controller, and the memory controller performs an automatic refresh operation on the memory 300 at a refresh rate of 6x. In this example, the target configuration refresh rate is different from the target initial refresh rate, which can avoid data loss and improve the reliability of the memory 300.

[0112] For example, when the temperature sensing circuit 330 senses that the temperature of the memory 300 is greater than the initial temperature value T e1 And less than or equal to the configured temperature value T e2x When a configuration mapping table is set, the control logic circuit 340 determines that the configuration refresh rate is RM2 based on the temperature and the configuration mapping table. For example, RM2 can be a refresh rate of 8x. The first register circuit 350 sends the refresh rate code 5'b00001 corresponding to the refresh rate 8x to the memory controller, and the memory controller performs an automatic refresh operation on the memory 300 at the configuration refresh rate of 8x. In this example, the target configuration refresh rate and the target initial refresh rate can be the same.

[0113] It is understandable that the temperature value T is configured in the above example. e2x Compared with the initial temperature T e2 Left shift (e.g., T e1 <T e2x <T e2 ), when the temperature of the memory 300 changes to a value greater than the configured temperature value T e2x And less than or equal to the initial temperature value T e2 When the temperature value T is set to 0, the automatic refresh operation can be performed at an increased refresh rate based on the configuration mapping table to avoid data loss and improve the reliability of the memory 300. e2x Can be compared to the initial temperature value T e2 Shift right (for example, T e2 <T e2x <T e3 ), when the temperature of the memory 300 changes to a value greater than the initial temperature value T e2 And less than or equal to the configured temperature value T e2x When the automatic refresh operation can be performed at a reduced refresh rate based on the configuration mapping table, it can not only avoid data loss, but also provide more time for normal read and write operations, and avoid increased power consumption due to frequent refreshes, that is, reduce power consumption. The selection of the configuration temperature value can be determined based on the data retention characteristics of the memory itself to produce an expected refresh rate, thereby meeting the data retention requirements of the memory, and the present disclosure is not limited to this.

[0114] Table 1 Configuration mapping table

[0115]

[0116] It should be noted that the peripheral circuit 310 in the embodiment of the present disclosure may also include other circuits known in the art, such as a sense amplifier circuit, a word line driver circuit, a row decoder, a column decoder, a data input / output buffer, etc. For the sake of simplicity, Figure 7a Not shown.

[0117] In actual applications, different configuration mapping tables can be customized for different memories, increasing the flexibility of adjusting the refresh rate. For example, before the memory leaves the factory, the R&D personnel develop and design different configuration mapping tables for different memories, and write (also called program) the configuration mapping tables into the memory.

[0118] In the disclosed embodiment, the temperature of the memory is sensed by a temperature sensing circuit and a temperature signal is generated based on the sensed temperature. The control logic circuit determines the target configuration refresh rate based on the temperature signal and the configuration mapping table, and adjusts the target initial refresh rate to the target configuration refresh rate. In this way, on the one hand, the expected refresh rate can be generated based on the data retention characteristics of the memory to avoid data loss and ensure data reliability; on the other hand, the refresh rate can be flexibly adjusted based on the data retention characteristics of the memory to avoid frequent refresh operations, thereby reducing power consumption and increasing the service life of the memory; on the third hand, without changing the circuit design, the range of the temperature segment can be flexibly configured and the configuration mapping table can be customized to meet the data retention requirements of the memory.

[0119] In some embodiments, the peripheral circuit 310 further includes: a second register circuit 360 , the second register circuit 360 being configured to store a configuration mapping table;

[0120] The control logic circuit 340 is specifically configured to read the second register circuit 360 based on the temperature signal to determine the target configuration refresh rate.

[0121] In the embodiment of the present disclosure, the configuration mapping table can be stored in the second register circuit 360, and the control logic circuit 340 reads the second register circuit 360 based on the received temperature signal to determine the target configuration refresh rate. The second register circuit 360 includes but is not limited to a mode register, and the mode register can store various operating parameters and control parameters of the operating memory 300, etc. The mode register can be programmed to set multiple operating parameters and control parameters, and the mode register can store parameter codes. For example, the mode register can store parameter codes (i.e., a configuration mapping table) for multiple configuration refresh rates related to temperature, and the mode register can be read to determine the target configuration refresh rate. In a specific embodiment, the mode register can store data temporarily or permanently.

[0122] In some embodiments, the configuration mapping table includes a plurality of sub-configuration mapping tables, and the sub-configuration mapping tables are used to record the corresponding relationship between the configuration temperature segments and the configuration refresh rates; the peripheral circuit 310 further includes:

[0123] An address decoding circuit 370, the address decoding circuit 370 is configured to: decode and generate a target address based on the temperature signal; wherein the target address is used to indicate a physical address of a target sub-configuration mapping table in the plurality of sub-configuration mapping tables;

[0124] The control logic circuit 340 is specifically configured to: based on the target address, obtain the target sub-configuration mapping table and determine the target configuration refresh rate.

[0125] In the embodiment of the present disclosure, the configuration mapping table includes multiple sub-configuration mapping tables, and different sub-configuration mapping tables record the corresponding relationship between different configuration temperature segments and configuration refresh rates. For example, referring to Table 1, the configuration mapping table includes 17 sub-configuration mapping tables, and the first sub-configuration mapping table records the configuration temperature segment T c1 and the mapping relationship between the configuration refresh rate RM1, and the second sub-configuration mapping table records the configuration temperature segment T c2 and the mapping relationship between the configuration refresh rate RM2, ..., the 17th sub-configuration mapping table records the configuration temperature segment T c17 and configure refresh rate RM 17 The mapping relationship between them, the number of sub-configuration mapping tables in the configuration mapping table is not limited to 17, and the number of sub-configuration mapping tables can be less than or greater than 17.

[0126] The address decoding circuit 370 receives the temperature signal, decodes the temperature signal to generate a target address, and sends the target address to the control logic circuit 340; the control logic circuit 340 reads the sub-configuration mapping table in the second register circuit 360 based on the target address to determine the target configuration refresh rate. It can be understood that the multiple sub-configuration mapping tables are stored in different locations in the second register circuit 360, corresponding to multiple different physical addresses, the target sub-configuration mapping table is a sub-configuration mapping table among the multiple sub-configuration mapping tables, and the target address is the physical address corresponding to the sub-configuration mapping table.

[0127] Exemplarily, at the first moment, the temperature sensing circuit 330 senses that the temperature of the memory 300 is 25°C and outputs a first temperature signal; the address decoding circuit 370 receives the first temperature signal and decodes the first temperature signal to generate a first target address; the control logic circuit 340 reads the first sub-configuration mapping table in the second register circuit 360 based on the first target address, determines the target configuration refresh rate RM1, and the memory controller performs an automatic refresh operation on the memory 300 at the refresh rate of RM1. In this example, the target sub-configuration mapping table is the first sub-configuration mapping table, and the target address is the physical address of the first sub-configuration mapping table, that is, the first target address.

[0128] Exemplarily, at the second moment, the temperature sensing circuit 330 senses that the temperature of the memory 300 is 30°C and outputs a second temperature signal, the address decoding circuit 370 receives the second temperature signal, and decodes the second temperature signal to generate a second target address, the control logic circuit 340 reads the second sub-configuration mapping table in the second register circuit 360 based on the second target address, determines the target configuration refresh rate RM2, and the memory controller performs an automatic refresh operation on the memory 300 at the refresh rate of RM2. In this example, the target sub-configuration mapping table is the second sub-configuration mapping table, and the target address is the physical address of the second sub-configuration mapping table, that is, the second target address. The second moment can be before or after the first moment, so that the refresh rate of the memory can be adjusted in time when the temperature changes.

[0129] In some embodiments, the first register circuit 350 is further configured to: update the target initial refresh rate to the target configuration refresh rate; and send the target configuration refresh rate to the memory controller.

[0130] For example, when the sensed temperature is greater than the configured temperature value T e2x And less than or equal to the initial temperature value T e2The control logic circuit 340 determines the configuration refresh rate as RM3 based on the temperature and the configuration mapping table, for example, RM3 may be a refresh rate of 6x; the first register circuit 350 updates the target initial refresh rate 8x corresponding to the temperature to the target configuration refresh rate 6x, and sends the refresh rate code 5'b00010 corresponding to the refresh rate 6x to the memory controller, and the memory controller performs an automatic refresh operation on the memory 300 at a configuration refresh rate of 6x.

[0131] In some embodiments, the peripheral circuit 310 also includes: an electric fuse circuit 380, which is configured to store a configuration mapping table; the control logic circuit 340 is specifically configured to: read the configuration mapping table in the electric fuse circuit 380, and save the read configuration mapping table to the second register circuit 360.

[0132] The electric fuse circuit 380 is used to save the configuration mapping table. The electric fuse circuit 380 includes a programmable logic device, such as a one-time programmable (OTP) register, a few-time programmable (FTP) register, or a multi-time programmable (MTP) register. OTP includes a fuse OTP or an anti-fuse OTP. Before the memory 300 leaves the factory, the configuration mapping table can be written into the electric fuse circuit 380. Since OTP, FTP, MTP, etc. are non-volatile, the configuration mapping table can still be saved when the memory 300 is powered off to avoid the loss of the configuration mapping table.

[0133] The control logic circuit 340 can first read the configuration mapping table in the electric fuse circuit 380, and cache the read configuration mapping table in the second register circuit 360, so that when the temperature changes (for example, increases or decreases), the target configuration refresh rate is determined based on the temperature signal output by the temperature sensing circuit 330 and the configuration mapping table cached in the second register circuit 360, and the refresh rate of the memory 300 is adjusted to the target configuration refresh rate in a timely manner.

[0134] In the disclosed embodiment, an electric fuse circuit is provided to store the configuration mapping table. Due to the non-volatility of the electric fuse circuit, the configuration mapping table can still be saved when the memory is powered off, thereby avoiding the loss of the configuration mapping table.

[0135] In some embodiments, the initial refresh rate includes a basic refresh rate and an initial multiple value, and the initial multiple values ​​of any two of the multiple initial refresh rates are different; the configuration refresh rate includes a basic refresh rate and a configuration multiple value, and the configuration multiple values ​​of any two of the multiple configuration refresh rates are different;

[0136] The control logic circuit 340 is specifically configured to: determine a configuration multiple value of a target configuration refresh rate based on the temperature signal and the configuration mapping table;

[0137] The first register circuit 350 is further configured to update the initial multiple value of the target initial refresh rate to the configured multiple value of the target configured refresh rate.

[0138] For example, refer to Figure 6 As shown, the 17 initial refresh rates can be expressed as multiples of the basic refresh rate x, and the initial multiple values ​​of any two initial refresh rates are different. For example, the initial multiple value of the refresh rate 8x is 8, and the initial multiple value of the refresh rate 6x is 6. The representation method of multiple configured refresh rates is similar to the representation method of multiple initial refresh rates, which will not be repeated here.

[0139] Exemplarily, the control logic circuit 340 determines the configuration multiple value 6 of the target configuration refresh rate 6x based on the temperature signal and the configuration mapping table; the first register circuit 350 updates the initial multiple value 8 of the target initial refresh rate 8x to the configuration multiple value 6, thereby updating the target initial refresh rate 8x to the target configuration refresh rate 6x. It can be understood that in this example, by updating the multiple value of the basic refresh rate, the target initial refresh rate can be updated to the target configuration refresh rate.

[0140] In some embodiments, the multiple initial temperature segments include N initial temperature segments, N is an integer greater than 1; the configuration mapping table includes N configured temperature segments; wherein the minimum temperature of the i-th initial temperature segment is different from the minimum temperature of the i-th configured temperature segment; and / or the maximum temperature of the i-th initial temperature segment is different from the maximum temperature of the i-th configured temperature segment; i is an integer greater than or equal to 1 and less than or equal to N.

[0141] For example, refer to Figure 8 As shown, the minimum temperature of the second initial temperature section and the minimum temperature of the second configuration temperature section are both T e1 , the maximum temperature of the second initial temperature section is T e2 , the maximum temperature of the second configuration temperature section is T e2x , where T e1 <T e2x <T e2 In this example, the minimum temperature of the second initial temperature section is the same as the minimum temperature of the second configuration temperature section, and the maximum temperature of the second initial temperature section is different from the maximum temperature of the second configuration temperature section. Of course, in other embodiments, the minimum temperature of the second initial temperature section and the minimum temperature of the second configuration temperature section may be different. For example, the minimum temperature of the second initial temperature section is T e1 , the minimum temperature of the second configuration temperature section is T e1x , Te1x Can be less than or greater than T e1 .

[0142] In practical applications, the range of each configured temperature segment can be flexibly adjusted according to the characteristics of the memory's leakage current changing with temperature. For example, if the leakage current changes dramatically, the configured temperature segment is adjusted to a shorter range; if the leakage current changes less, the configured temperature segment is adjusted to a wider range to adapt to the memory's data retention characteristics, thereby generating an expected refresh rate at a specific temperature.

[0143] It can be understood that by shifting the minimum temperature and / or maximum temperature of at least one of the multiple initial temperature sections, a configured temperature section with a range different from that of the initial temperature section can be obtained, thereby meeting the data retention requirements of the memory.

[0144] In some embodiments, the control logic circuit 340 is further configured to:

[0145] Entering a refresh mode based on a current refresh command sent by the memory controller;

[0146] Entering a refresh mode based on a next refresh command sent by the memory controller; wherein the target configuration refresh rate is used to indicate a time interval between a next refresh command and a current refresh command.

[0147] The memory controller is coupled to the memory 300 and is used to control the logical operations of the memory 300, such as writing, reading or refreshing. The memory controller refreshes the storage cells in the memory by periodically sending refresh commands to the memory 300. Operations such as writing and reading are usually performed after the automatic refresh operation is completed.

[0148] Exemplarily, the first register circuit 350 sends the refresh rate code 5'b00010 to the memory controller, and the memory controller performs an automatic refresh operation on the memory 300 at a refresh rate of 6x, and the refresh rate 6x is used to indicate the time interval between the next refresh command and the current refresh command. It can be understood that when the refresh rate changes, the time interval between the next refresh command and the current refresh command also changes. For example, when the refresh rate becomes higher, the time interval between the next refresh command and the current refresh command becomes shorter; for another example, when the refresh rate becomes lower, the time interval between the next refresh command and the current refresh command becomes longer.

[0149] In some embodiments, the memory 300 is further configured to: update at least one configuration temperature section in the configuration mapping table after the usage time of the memory 300 is greater than or equal to a preset time.

[0150] Compared to when the memory is just leaving the factory, the performance of the memory may degrade after being used for a period of time. For example, the data retention time of the storage unit may be reduced at a certain temperature. Therefore, after the usage time of the memory is greater than or equal to the preset time, the minimum temperature and / or maximum temperature of the configuration temperature section may be adjusted so that the configuration refresh rate corresponding to the temperature is adjusted to a larger value, thereby reducing the time interval of the refresh command. The preset time period includes one month, half a year, one year or other longer time. It should be noted that after the usage time of the memory is greater than or equal to the preset time, the configuration refresh rate corresponding to one or more configuration temperature sections in the configuration mapping table may be updated, and the present disclosure has no special restrictions on this.

[0151] In practical applications, multiple configuration temperature values ​​can be written after chip testing, more specifically, written into the second register circuit 360, and multiple configuration temperature sections can be divided based on the multiple configuration temperature values. The multiple configuration temperature values ​​can also be updated after chip packaging, thereby updating at least one configuration temperature section in the configuration mapping table.

[0152] In the embodiment of the present disclosure, after the usage time of the memory is greater than or equal to the preset time, at least one configuration temperature section in the configuration mapping table is updated, thereby updating the configuration refresh rate corresponding to the configuration temperature section. In this way, the refresh rate of the memory can be adjusted in time according to the usage time of the memory, which can further avoid data loss and increase the service life of the memory.

[0153] Based on the above memory, an embodiment of the present disclosure further provides a method for operating the memory.

[0154] Fig. 9 The present invention is a flowchart of a method for operating a memory according to an embodiment of the present invention, wherein the memory includes a peripheral circuit; the peripheral circuit includes a first register circuit, and the first register circuit is configured to store a plurality of initial refresh rates; wherein the plurality of initial refresh rates correspond to a plurality of initial temperature zones one by one. Fig. 9 As shown, the operation method at least includes the following steps:

[0155] Step S410: sensing the temperature of the memory, and generating a temperature signal based on the sensed temperature;

[0156] Step S420: determining a target configuration refresh rate based on the temperature signal and the configuration mapping table; wherein the configuration mapping table includes a plurality of configuration temperature segments and a plurality of configuration refresh rates, and the plurality of configuration temperature segments and the plurality of configuration refresh rates correspond one to one;

[0157] Step S430: adjusting a target initial refresh rate among the multiple initial refresh rates to a target configuration refresh rate.

[0158] In some embodiments, the peripheral circuit further includes a second register circuit, and the second register circuit is configured to store a configuration mapping table; the above step S420 includes: based on the temperature signal, reading the second register circuit to determine the target configuration refresh rate.

[0159] In some embodiments, the configuration mapping table includes a plurality of sub-configuration mapping tables, and the sub-configuration mapping tables are used to record the corresponding relationship between the configuration temperature segments and the configuration refresh rates; the above-mentioned reading the second register circuit based on the temperature signal to determine the target configuration refresh rate includes:

[0160] Based on the temperature signal, decoding generates a target address; wherein the target address is used to indicate a physical address of a target sub-configuration mapping table in the plurality of sub-configuration mapping tables;

[0161] Based on the target address, obtain the target sub-configuration mapping table and determine the target configuration refresh rate.

[0162] In some embodiments, the above operation method further includes:

[0163] Update the target initial refresh rate to the target configured refresh rate;

[0164] Sends the target configuration refresh rate to the memory controller.

[0165] In some embodiments, the peripheral circuit further includes an electric fuse circuit, and the electric fuse circuit is configured to store a configuration mapping table; the above operation method further includes:

[0166] The configuration mapping table in the electrical fuse circuit is read, and the read configuration mapping table is stored in the second register circuit.

[0167] In some embodiments, the initial refresh rate includes a basic refresh rate and an initial multiple value, and the initial multiple values ​​of any two of the multiple initial refresh rates are different; the configuration refresh rate includes a basic refresh rate and a configuration multiple value, and the configuration multiple values ​​of any two of the multiple configuration refresh rates are different;

[0168] The above step S420 includes: determining a configuration multiple value of a target configuration refresh rate based on the temperature signal and the configuration mapping table;

[0169] The above step S430 includes: updating the initial multiple value of the target initial refresh rate to the configured multiple value of the target configured refresh rate.

[0170] In some embodiments, the multiple initial temperature segments include N initial temperature segments, N is an integer greater than 1; the configuration mapping table includes N configured temperature segments; wherein the minimum temperature of the i-th initial temperature segment is different from the minimum temperature of the i-th configured temperature segment; and / or the maximum temperature of the i-th initial temperature segment is different from the maximum temperature of the i-th configured temperature segment; i is an integer greater than or equal to 1 and less than or equal to N.

[0171] In some embodiments, the above operation method further includes:

[0172] Entering a refresh mode based on a current refresh command sent by the memory controller;

[0173] Entering a refresh mode based on a next refresh command sent by the memory controller; wherein the target configuration refresh rate is used to indicate a time interval between a next refresh command and a current refresh command.

[0174] In some embodiments, the above operation method further includes:

[0175] After the usage time of the memory is greater than or equal to the preset time, at least one configuration temperature section in the configuration mapping table is updated.

[0176] The above operation method has been introduced in detail on the memory side and will not be repeated here for the sake of brevity.

[0177] Fig.10 This is a schematic diagram of adjusting the refresh rate according to an embodiment of the present disclosure. Fig.10 As shown, the temperature sensing circuit senses the temperature of the memory and generates a temperature signal based on the sensed temperature; the control logic circuit receives the temperature signal, determines the target configuration refresh rate based on the temperature signal and the configuration mapping table, and adjusts the target initial refresh rate to the target configuration refresh rate. Here, the configuration mapping table is used to store the results of the computer algorithm, and the algorithm can be developed in parallel with the circuit design of the memory; it is written after the chip is tested. Of course, in other circuit design and chip testing processes, the algorithm can be optimized according to the circuit design and test results.

[0178] In a specific embodiment, referring to Fig.10 As shown, the address decoding circuit receives a temperature signal, decodes the temperature signal to generate a target address; the control logic circuit reads the target sub-configuration mapping table in the second register circuit based on the target address, and outputs the reading result (i.e., the reading value), and the output reading result is used to indicate the target configuration refresh rate.

[0179] Fig.11 This is a schematic diagram of a process of generating a configuration mapping table by an algorithm according to an embodiment of the present disclosure. Fig.11 The above embodiments illustrate the process of generating a configuration mapping table in the embodiment of the present disclosure.

[0180] Execute step S510: set the initial multiple value. For example, write the product of multiple initial multiple values ​​specified by the JEDEC protocol and the basic refresh rate x into the first register circuit respectively, so that the first register circuit stores multiple initial refresh rates, each initial refresh rate corresponds to an initial temperature segment, and different initial refresh rates correspond to different initial temperature segments.

[0181] Execute step S520: calculate the configuration temperature value. For example, calculate multiple configuration temperature values ​​related to temperature according to the data retention characteristics of the memory. For example, 16 configuration temperature values ​​are calculated, namely 25°C, 30°C, 35°C, 40°C, 42°C, 45°C, 48°C, 50°C, 52°C, 55°C, 60°C, 65°C, 70°C, 75°C, 80°C and 85°C.

[0182] Execute step S530: save the configuration temperature value. Based on the multiple configuration temperature values, multiple configuration temperature sections can be divided, and the corresponding relationship between the multiple configuration temperature sections and the multiple configuration refresh rates, that is, the configuration mapping table, is established; and the configuration mapping table is saved in the second register circuit.

[0183] Execute step S540: test the configured temperature value. For example, provide a test temperature to test the memory.

[0184] Execute step S550: determine whether the configuration temperature value meets the requirements based on the test results; if so, complete; if not, return to step S520, recalculate the configuration temperature value by adjusting the algorithm, generate a new configuration temperature segment based on the newly calculated configuration temperature value, and write the new configuration temperature segment into the second register circuit until the requirements are met. Here, at the test temperature, when the configuration refresh rate corresponding to the test temperature is the refresh rate, the memory is sufficient to hold the data, and it can be determined that the configuration temperature value meets the requirements.

[0185] The present disclosure also provides a memory system. Figure 1 As shown, the memory system 30 includes:

[0186] One or more memories 300 according to any of the above embodiments;

[0187] The memory controller 10 is coupled to the memory 300 and is configured to control the memory 300 .

[0188] The memory 300 may correspond to the reference Figure 1 The memory 20 in the illustrated embodiment, the functions, applications and interaction between the memory 300 and the memory controller 10 are not described in detail here.

[0189] An embodiment of the present disclosure further provides an electronic device, including the memory system as described in the above embodiment.

[0190] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0191] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0192] The above is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory, characterized in that: The memory includes a peripheral circuit; the peripheral circuit includes: A first register circuit, wherein the first register circuit is configured to: store a plurality of initial refresh rates; wherein the plurality of initial refresh rates correspond to a plurality of initial temperature sections one by one; a temperature sensing circuit, the temperature sensing circuit being configured to: sense a temperature of the memory and generate a temperature signal based on the sensed temperature; A control logic circuit, wherein the control logic circuit is configured to: determine a target configuration refresh rate based on the temperature signal and a configuration mapping table, and adjust the target initial refresh rate among the multiple initial refresh rates to the target configuration refresh rate; wherein the configuration mapping table includes multiple configuration temperature segments and multiple configuration refresh rates, and the multiple configuration temperature segments and the multiple configuration refresh rates correspond one to one.

2. The memory according to claim 1, characterized in that: The peripheral circuit also includes: a second register circuit, the second register circuit being configured to store the configuration mapping table; The control logic circuit is specifically configured to: read the second register circuit based on the temperature signal to determine the target configuration refresh rate.

3. The memory according to claim 2, characterized in that: The configuration mapping table includes a plurality of sub-configuration mapping tables, and the sub-configuration mapping tables are used to record the corresponding relationship between the configuration temperature segments and the configuration refresh rates; the peripheral circuit also includes: An address decoding circuit, the address decoding circuit being configured to: decode and generate a target address based on the temperature signal; wherein the target address is used to indicate a physical address of a target sub-configuration mapping table among the multiple sub-configuration mapping tables; The control logic circuit is specifically configured to: based on the target address, obtain the target sub-configuration mapping table and determine the target configuration refresh rate.

4. The memory according to claim 2, characterized in that: The first register circuit is further configured as: Updating the target initial refresh rate to the target configuration refresh rate; The target configuration refresh rate is sent to a memory controller.

5. The memory according to claim 2, characterized in that: The peripheral circuit also includes: an electric fuse circuit, the electric fuse circuit being configured to store the configuration mapping table; The control logic circuit is specifically configured to: read the configuration mapping table in the electrical fuse circuit, and save the read configuration mapping table into the second register circuit.

6. The memory according to claim 1, characterized in that: The initial refresh rate includes a basic refresh rate and an initial multiple value, and the initial multiple values ​​of any two of the multiple initial refresh rates are different; the configured refresh rate includes the basic refresh rate and a configured multiple value, and the configured multiple values ​​of any two of the multiple configured refresh rates are different; The control logic circuit is specifically configured to: determine a configuration multiple value of the target configuration refresh rate based on the temperature signal and the configuration mapping table; The first register circuit is further configured to update the initial multiple value of the target initial refresh rate to the configured multiple value of the target configured refresh rate.

7. The memory according to claim 1, characterized in that: The multiple initial temperature segments include N initial temperature segments, N is an integer greater than 1; the configuration mapping table includes N configured temperature segments; wherein the minimum temperature of the i-th initial temperature segment is different from the minimum temperature of the i-th configured temperature segment; and / or the maximum temperature of the i-th initial temperature segment is different from the maximum temperature of the i-th configured temperature segment; i is an integer greater than or equal to 1 and less than or equal to N.

8. The memory according to claim 1, characterized in that: The control logic circuit is further configured to: Entering a refresh mode based on a current refresh command sent by the memory controller; Entering the refresh mode based on a next refresh command sent by the memory controller; wherein the target configuration refresh rate is used to indicate a time interval between the next refresh command and the current refresh command.

9. The memory according to claim 1, characterized in that: The memory is further configured to: After the usage time of the memory is greater than or equal to the preset time, at least one of the configuration temperature sections in the configuration mapping table is updated.

10. A method for operating a memory, characterized in that: The memory includes a peripheral circuit; the peripheral circuit includes a first register circuit, and the first register circuit is configured to store a plurality of initial refresh rates; wherein the plurality of initial refresh rates correspond to a plurality of initial temperature sections one by one; and the operating method includes: sensing a temperature of the memory, and generating a temperature signal based on the sensed temperature; Determining a target configuration refresh rate based on the temperature signal and a configuration mapping table; wherein the configuration mapping table includes a plurality of configuration temperature segments and a plurality of configuration refresh rates, and the plurality of configuration temperature segments and the plurality of configuration refresh rates correspond one to one; A target initial refresh rate among the multiple initial refresh rates is adjusted to the target configuration refresh rate.

11. The operating method according to claim 10, characterized in that: The peripheral circuit further includes a second register circuit configured to store the configuration mapping table; The determining the target configuration refresh rate based on the temperature signal and the configuration mapping table includes: Based on the temperature signal, the second register circuit is read to determine the target configuration refresh rate.

12. The operating method according to claim 11, characterized in that: The configuration mapping table includes a plurality of sub-configuration mapping tables, and the sub-configuration mapping tables are used to record the corresponding relationship between the configuration temperature segments and the configuration refresh rates; The step of reading the second register circuit based on the temperature signal to determine the target configuration refresh rate includes: Based on the temperature signal, decoding generates a target address; wherein the target address is used to indicate a physical address of a target sub-configuration mapping table among the multiple sub-configuration mapping tables; Based on the target address, the target sub-configuration mapping table is obtained to determine the target configuration refresh rate.

13. The operating method according to claim 11, characterized in that: The operation method also includes: Updating the target initial refresh rate to the target configuration refresh rate; The target configuration refresh rate is sent to a memory controller.

14. The operating method according to claim 11, characterized in that: The peripheral circuit further includes an electric fuse circuit, and the electric fuse circuit is configured to store the configuration mapping table; the operation method further includes: The configuration mapping table in the electrical fuse circuit is read, and the read configuration mapping table is stored in the second register circuit.

15. The operating method according to claim 10, characterized in that: The initial refresh rate includes a basic refresh rate and an initial multiple value, and the initial multiple values ​​of any two of the multiple initial refresh rates are different; the configured refresh rate includes the basic refresh rate and a configured multiple value, and the configured multiple values ​​of any two of the multiple configured refresh rates are different; The determining the target configuration refresh rate based on the temperature signal and the configuration mapping table includes: Determine a configuration multiple value of the target configuration refresh rate based on the temperature signal and the configuration mapping table; The step of adjusting the target initial refresh rate to the target configuration refresh rate includes: The initial multiple value of the target initial refresh rate is updated to the configuration multiple value of the target configuration refresh rate.

16. The operating method according to claim 10, characterized in that: The multiple initial temperature segments include N initial temperature segments, N is an integer greater than 1; the configuration mapping table includes N configured temperature segments; wherein the minimum temperature of the i-th initial temperature segment is different from the minimum temperature of the i-th configured temperature segment; and / or the maximum temperature of the i-th initial temperature segment is different from the maximum temperature of the i-th configured temperature segment; i is an integer greater than or equal to 1 and less than or equal to N.

17. The operating method according to claim 10, characterized in that: The operation method also includes: Entering a refresh mode based on a current refresh command sent by the memory controller; Entering the refresh mode based on a next refresh command sent by the memory controller; wherein the target configuration refresh rate is used to indicate a time interval between the next refresh command and the current refresh command.

18. The operating method according to claim 10, characterized in that: The operation method also includes: After the usage time of the memory is greater than or equal to the preset time, at least one of the configuration temperature sections in the configuration mapping table is updated.

19. A memory system, characterized in that: include: One or more memories as claimed in any one of claims 1 to 9; A memory controller is coupled to the memory and is configured to control the memory.

20. An electronic device, characterized in that: include: The memory system of claim 19.

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