Closed-loop multi-output radio frequency matching device, method and processing chamber

Abstract

An apparatus and method for closed loop multi-output control for radio frequency (RF) matching of semiconductor wafer manufacturing processes is provided. An apparatus for providing a signal to a station of a process chamber performs a semiconductor manufacturing process. A plurality of signal generators generate signals having first and second frequencies. The measurement circuit measures a voltage standing wave ratio (VSWR). The matched reflection optimizer has a reactance component configured to be adjusted in response to an output signal from the measurement circuit.

Description

This application is a divisional application of the application with application number 202080034447.4, application date April 30, 2020, and invention name “Closed-loop multi-output RF matching device, method and processing chamber”. Background Art

[0001] The descriptions of background and context contained herein are provided only for the purpose of presenting the context of the disclosure as a whole. Many of the present inventions are the work of the inventors, and simply because such work is described in the background section or presented as context elsewhere in this article, it does not mean that it will be considered as prior art.

[0002] The processing of semiconductor wafers for forming integrated circuits may include a large number and variety of processing steps. In certain processing steps (which may be performed after depositing various materials on the semiconductor wafer), materials may be etched away to allow deposition of other materials (such as metals). Such deposition processes may involve the formation of conductive lines, transistor gates, vias, circuit components, etc. However, in at least some cases, in semiconductor processing (e.g., processes involving plasma-based etching and / or plasma-enhanced atomic layer deposition), uncontrollable process variations may result in lower yields, increased costs, unnecessary redesign of semiconductor layouts and masks, etc. Therefore, techniques to increase control over plasma-based wafer etching and / or plasma-enhanced atomic layer deposition continue to be an active area of ​​research. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1A A substrate processing apparatus is shown for depositing films on semiconductor substrates using any number of processes.

[0004] Figure 1B is a block diagram showing various components of a system for performing a semiconductor processing process according to one embodiment.

[0005] Figure 2 is a block diagram showing various components of a closed-loop multi-output radio frequency (RF) matching procedure used in performing a semiconductor manufacturing process according to one embodiment.

[0006] Figure 3 is a diagram showing various circuit components utilized in a closed-loop multi-output RF matching procedure used in performing semiconductor processing according to one embodiment.

[0007] Figure 4 is a diagram showing circuit elements used to perform matching reflection optimization in a closed-loop multi-output RF matching procedure used in performing semiconductor processing according to one embodiment.

[0008] Figure 5is a diagram showing circuit components for performing RF power control in a closed-loop multi-output RF matching procedure according to one embodiment.

[0009] Figure 6 is a diagram showing circuit elements for RF isolation and filtering in a closed loop multi-output RF matching procedure used in performing semiconductor processing according to one embodiment.

[0010] Figure 7 is a diagram showing circuit components for matching and / or impedance conversion in a closed-loop multi-output RF matching procedure used in performing semiconductor processing according to one embodiment.

[0011] Figure 8 FIG. 1 is a flow chart of a closed-loop RF matching method according to an embodiment.

[0012] Fig. 9 A schematic diagram of an embodiment of a multi-station processing tool is depicted. DETAILED DESCRIPTION

[0013] In certain embodiments, closed-loop multi-output radio frequency (RF) matching may be utilized in various semiconductor processing processes, such as plasma-based wafer processing. Closed-loop multi-output RF matching may facilitate the ability to deliver RF power to one or more stations of a processing chamber in a manner that allows for dynamic adjustment to varying loads presented by the stations of the processing chamber. Such dynamic adjustment provides a real-time capability to closely match the impedance of the load presented by the plasma within the station to the source impedance of one or more RF power generators, even if such loads drift during the processing process. Thus, the RF delivered from individual stations may be dynamically increased while simultaneously reducing and / or minimizing the RF power reflected from the RF power generator. Certain embodiments may be used with some wafer processing processes, such as various plasma-enhanced atomic layer deposition (ALD) processes, various plasma-enhanced chemical vapor deposition (CVD) processes, or may be used in real time during a single deposition process. In certain embodiments, the RF power matching network utilizes a simplified circuit topology to accommodate load variations at any signal frequency, such as 400 kHz and 27.12 MHz. However, in other embodiments, the RF power matching network can operate at any signal frequency, such as relatively low frequencies (eg, between about 50 kHz and about 1 MHz), as well as higher signal frequencies (eg, between about 10 MHz and about 100 MHz).

[0014] It should be noted that while the specific embodiments described herein may show and / or describe a closed-loop multi-output RF match for use with 4 stations of a process chamber, in other embodiments, a smaller number of process chamber stations may be used, such as 1 station, 2 stations, or 3 stations. In other embodiments, the closed-loop multi-output RF match may be used with a larger number of process chamber stations, such as 5 stations, 6 stations, 7 stations, 8 stations, 10 stations, 12 stations, or any other number of process chamber stations.

[0015] The manufacture of semiconductor devices generally involves depositing one or more thin films on a planar or non-planar substrate in an integrated processing process. In certain aspects of the integrated processing, it may be useful to deposit a thin film that follows the substrate morphology. One type of reaction that is useful in some cases includes chemical vapor deposition (CVD). In a typical CVD process, gas phase reactants are simultaneously introduced into a station of a reaction chamber and undergo a gas phase reaction. The reaction products are deposited on the surface of the substrate. The reaction may be driven by a plasma, in which case the process may be referred to as a plasma enhanced chemical vapor deposition (PECVD) reaction. As used herein, unless otherwise indicated, the term "CVD" is intended to include PECVD. CVD processing has certain disadvantages that make it less suitable in some cases. For example, mass transport limitations of CVD gas phase reactions may result in a "bread-loafing" deposition effect, which shows a thicker deposition at the top surface (e.g., the top surface of the gate stack) and a thinner deposition at the recessed surface (e.g., the bottom corner of the gate stack). Furthermore, because some dies may have areas of different device density, mass transport effects across the substrate surface may result in thickness differences within the die and within the wafer. These thickness differences may result in over-etching in some areas and under-etching in other areas, which may reduce device performance and die yield. Another problem associated with CVD processing is its general inability to form conformal films within high aspect ratio features. This issue becomes increasingly problematic as device dimensions continue to shrink. These and other disadvantages in certain aspects of wafer fabrication processes are combined with Figure 1A and Figure 1B and discuss it.

[0016] In another example, certain deposition processes involve multiple film deposition cycles, each of which produces a separate film thickness. For example, in atomic layer deposition (ALD), thin layers of film are applied in a repeated sequential manner and can be considered to involve multiple cycles of deposition. As device and feature sizes continue to shrink in the semiconductor industry, and 3D device structures become more prevalent in integrated circuit (IC) design, the ability to deposit thin conformal films (films of material having uniform thickness relative to the shape of the underlying structure, even if non-planar) continues to become more important. ALD is a film formation technique that is well suited for the deposition of conformal films, due to the fact that a single cycle of ALD deposits only a single thin layer of material, the thickness of which is limited by the amount of one or more film precursor reactants that can be adsorbed on the substrate surface (i.e., forming an adsorption limiting layer) prior to the film forming chemical reaction itself. Multiple ALD cycles can then be used to build up a film of desired thickness, and because each layer is thin and conformal, the resulting film substantially conforms to the shape of the underlying device structure. In certain embodiments, each ALD cycle comprises the following steps:

[0017] The substrate surface is exposed to a first precursor.

[0018] A reaction chamber in which the substrate is located is purged.

[0019] The reaction on the substrate surface is activated, typically using a plasma and / or a second precursor.

[0020] A reaction chamber in which the substrate is located is purged.

[0021] The duration of each ALD cycle may typically be less than 25 seconds, or less than 10 seconds, or less than 5 seconds. One or more plasma exposure steps of an ALD cycle may have a short duration, such as a duration of less than 1 second.

[0022] Figure 1A A substrate processing apparatus is shown for depositing films on semiconductor substrates using any number of processes. Figure 1A The apparatus 100 of the present invention utilizes a single processing station 102 of a processing chamber having a single substrate holder 108 (e.g., a susceptor) within an interior volume that can be maintained under vacuum by a vacuum pump 118. A gas delivery system 101 and a showerhead 106 are also fluidly connected to the processing chamber to deliver, for example, film precursors, carrier and / or purge gases and / or process gases, auxiliary reactants, etc. Apparatus for generating a plasma within the processing chamber is also shown. Figure 1A In. Figure 1A The apparatus schematically described therein is particularly suitable for performing plasma enhanced CVD.

[0023] For simplicity, the processing apparatus 100 is depicted as an independent processing station (102) for a processing chamber that maintains a low pressure environment. However, it should be understood that, as described herein, multiple processing stations may be included in a common processing tool environment (e.g., in a common reaction chamber). For example, Figure 1B Embodiments of multi-station processing tools are depicted and discussed in further detail below.In addition, it should be understood that in certain embodiments, one or more hardware parameters of the processing apparatus 100 (including those discussed in detail herein) may be programmatically adjusted via one or more system controllers.

[0024] The station 102 of the processing chamber is in fluid communication with the gas delivery system 101 to deliver the processing gas (which may include liquid and / or gas) to the distribution showerhead 106. The gas delivery system 101 includes a mixing vessel 104, which is used to mix and / or regulate the processing gas for delivery to the showerhead 106. One or more mixing vessel inlet valves 120 can control the introduction of the processing gas into the mixing vessel 104.

[0025] Certain reactants may be stored in liquid form prior to vaporization and subsequent delivery to station 102 of the processing chamber. Figure 1A Embodiments include a vaporization point 103 for vaporizing liquid reactants to be supplied to the mixing vessel 104. In certain embodiments, the vaporization point 103 can be a heated liquid injection module. In certain embodiments, the vaporization point 103 can be a heated vaporizer. In yet other embodiments, the vaporization point 103 can be omitted from the processing station. In certain embodiments, a liquid flow controller (LFC) upstream of the vaporization point 103 can be provided to control the mass flow rate of the liquid used for vaporization and delivery to the processing station 102.

[0026] The showerhead 106 distributes process gases and / or reactants (e.g., film precursors) toward the substrate 112 at the processing station, and the flow of the process gases and / or reactants is controlled by one or more valves (e.g., valves 120, 120A, 105) upstream of the showerhead. Figure 1A In the illustrated embodiment, substrate 112 is positioned below showerhead 106 and is shown as resting on pedestal 108. Showerhead 106 may have any suitable shape and may have any suitable number and configuration of ports for distributing process gases to substrate 112. In certain embodiments having two or more stations, gas delivery system 101 includes valves or other flow control structures upstream of the showerhead that can independently control the flow of process gases and / or reactants to each station, such that gases can flow to one station but not to another. In addition, gas delivery system 101 can be configured to independently control the process gases and / or reactants delivered to each station in a multi-station apparatus so that the gas composition provided to different stations is different; for example, the partial pressures of gas components may vary between multiple stations at the same time.

[0027] Volume 107 is located below showerhead 106. In certain embodiments, pedestal 108 may be raised or lowered to expose substrate 112 to volume 107 and / or to change the volume of volume 107. Optionally, pedestal 108 may be lowered and / or raised during portions of a deposition process to modulate process pressure, reactant concentrations, etc. within volume 107.

[0028] exist Figure 1A In the embodiment, the showerhead 106 and the base 108 are electrically coupled to the RF power supply 114 and the matching network 116, which are used to power the plasma generator. In some embodiments, the plasma energy can be controlled by controlling one or more of the following (e.g., via a system controller with appropriate machine-readable instructions and / or control logic): processing station pressure, gas concentration, source of RF power, etc. For example, the RF power supply 114 and the matching network 116 can be operated at any appropriate power to form a plasma with a desired radical species composition. Similarly, the RF power supply 114 can provide RF power of any appropriate frequency or frequency group, as well as power.

[0029] In some embodiments, the plasma ignition and maintenance conditions are controlled using appropriate hardware and / or appropriate machine-readable instructions in a system controller, which may provide control instructions via a sequence of input / output control (IOC) instructions. In one example, instructions for setting plasma conditions for plasma ignition or maintenance are provided in the form of a plasma activation recipe of a process recipe. In some cases, the process recipe may be configured sequentially so that all instructions for a process are executed simultaneously with the process. In some embodiments, instructions for setting one or more plasma parameters may be included in a recipe prior to the plasma process. For example, a first recipe may include: instructions for setting the flow rate of an inert gas (e.g., helium) and / or a reactant gas, instructions for setting a plasma generator to a power set point, and a time delay instruction for the first recipe. A subsequent second recipe may include instructions for starting a plasma generator, and a time delay instruction for a second recipe. A third recipe may include instructions for stopping a plasma generator, and a time delay instruction for a third recipe. It should be understood that these recipes may be further subdivided and / or iterated in any appropriate manner within the scope of the present invention.

[0030] In some deposition processes, plasma strikes last for a duration of about several seconds or more. In certain embodiments described herein, much shorter plasma strikes may be applied during a process cycle. These may be about less than 50 milliseconds, such as 25 milliseconds.

[0031] According to implementation scheme 151, Figure 1Bis a block diagram showing various components of a system for performing semiconductor processing. Figure 1B In the embodiment, RF signal generators 155 and 160 are used to generate excitation signals that can cause plasma to form in stations 102A, 102B, 102C, and 102D of the processing chamber. Stations 102A, 102B, 102C, and 102D can correspond to stations of a semiconductor processing chamber, as described above with reference to Figure 1A Therefore, in Figure 1B In an embodiment of the present invention, the RF signal generator 155 may generate a relatively low frequency signal (e.g., a signal of approximately 400 kHz), while the RF signal generator 160 generates a relatively high frequency signal (e.g., a signal of approximately 27.12 MHz). However, it should be noted that these frequencies represent only exemplary frequencies. In other embodiments, different radio frequencies may be generated, and the embodiments are not limited to signals of 400 kHz and 27.12 MHz. For example, in certain cases, the relatively low frequency may correspond to a frequency between 360 kHz and 440 kHz. In another case, the relatively high frequency may correspond to a frequency between 26.5 MHz and 27.5 MHz.

[0032] exist Figure 1B In the embodiment, the RF transmission line coupling the signal generator 155 to the low frequency matching network 158 and the RF transmission line coupling the signal generator 160 to the high frequency matching network 163 may have a characteristic impedance of 50 ohms. However, other embodiments may utilize transmission lines with different characteristic impedances, such as 70 ohms, 300 ohms, etc. Figure 1B In an embodiment of the present invention, a low frequency matching network 158 and a high frequency matching network 163 are used to match the load presented by the power divider 170 to the output impedance of the signal generator 155 and the signal generator 160 (respectively). These matching steps facilitate the ability to couple maximum power transfer from the RF signal generators 155 and 160 to the power divider 170. Thus, even when the power divider 170 presents a highly reactive load (e.g., a complex impedance having a relatively small real portion and a large reactive portion), maximum power can be transferred from the signal generators 155 and 160 to the power divider 170. The matching networks 158 and 163 may utilize various reactive components such as inductors and / or capacitors that operate to compensate for the highly reactive load that may be presented by the power divider 170.

[0033] In certain embodiments, the components of the matching network 158 / 163 may be configured to match the specific loads presented by the low-frequency and high-frequency input ports of the power divider 170, which may be used to provide plasma generation power via output ports 171, 172, 173, and 174. However, during a plasma-based etching operation or other plasma-based processing (for example), the load (e.g., the reactive load presented by the plasma formation within the stations 102A, 102B, 102C, and 102D of the processing chamber) may begin to change or drift. Thus, for example, during the initial moments of plasma generation (e.g., the initial 30-60 seconds), the output signal amplitudes from ports 171-174 may correspond to substantially equal amounts. However, as plasma generation proceeds, the output signal amplitudes from ports 171-174 may begin to differ. Such differences may be caused by changes in the reactive loads presented by the stations 102A-102D of the processing chamber. Thus, in some cases, the value of the actual power coupled from ports 171-174 of the power divider may vary within a range of 0.0% to 25.0% in response to the varying reactive loads presented by stations 102A-102D of the processing chamber. Additionally, the RF power flow to the stations may be set to 0.0, or other negligible amount, by inputting 0.0 Watts as a set point. Alternatively, the capacitance of the variable capacitor may be adjusted to a value that results in a current approaching or approximating 0.0 amps.

[0034] therefore, Figure 1B The configuration may be classified as an "open loop" plasma generation system because it may be difficult to ensure constant, uniform power delivery from the power divider 170 to the stations 102A-102D during plasma generation operations. Thus, without additional control measures (e.g., control measures for providing real-time closed loop tuning of reactive components within the low frequency matching network 158 and the high frequency matching network 163 in response to changes in the reactive load presented by the stations 102A-102D), undesirable consequences may result. Such consequences may include, for example, under-etching, in which case insufficient material is removed from the semiconductor wafer; and over-etching, in which case excessive amounts of material are removed from the semiconductor wafer. In some cases, such under-etching and / or over-etching may result in the need to scrap the etched semiconductor wafer, which results in increased costs, schedule delays, etc.

[0035] Figure 2 is a block diagram showing various components of a closed-loop multi-output radio frequency (RF) matching process used in performing a semiconductor manufacturing process according to an embodiment 200 . Figure 2Embodiments of the present invention may facilitate increased control over the power delivered to the processing chamber from the low frequency and high frequency signal generators. Such increased control may be achieved through power flow sensing, which may tune or adjust the values ​​of the reactive elements of the matching network in a manner that allows real-time compensation for changes in the reactive impedance presented by the processing chamber. In response, changes in the reactive impedance presented by the processing chamber (which may change during plasma enhanced processing) may be compensated to allow for maximum power transfer from the signal generator to the processing chamber. In addition, power flow sensing (e.g., which may be achieved through the use of one or more phase sensitive voltmeters) may be used in a multi-channel environment, such as Figure 1B 171, 172, 173, and 174 of the power divider. Furthermore, this technique can be extended to a power divider having 6 output ports, 8 output ports, 10 output ports, or any other number of output ports (practically unlimited), which can be coupled to stations of a processing chamber, such as 6 stations, 8 stations, 10 stations, or any number of stations. Of course, 4 output ports (e.g. Figure 1B The impedance presented by the output ports 171, 172, 173 and 174) of the present invention is increased to present a parallel combination of about 50 ohms. For example, for a power divider comprising 4 output ports, each output port can be matched to a load of 200 ohms to present a load of 50 ohms at a single input port. In another example, for a power divider comprising 8 output ports, each output port can be matched to a load of 400 ohms to present a load of 50 ohms at a single input port.

[0036] exist Figure 2 In an embodiment, plasma enhanced processing can be performed at stations 102A, 102B, 102C, and 102N of a processing chamber. Thus, while only four stations (102A-102N) are depicted, the claimed subject matter is not limited to any particular number of stations of a processing chamber. An embodiment may include 2 stations, 3 stations, 5 stations, 8 stations, etc.

[0037] exist Figure 2, signal generator 205 may represent a hybrid signal generator, such as a signal generator that generates two different frequencies, such as a low frequency (e.g., 400.0 kHz) and a high frequency (e.g., 27.12 MHz). Thus, two or more signal generators may be utilized to implement signal generator 205, and the outputs of the two or more signal generators may be combined in a power combiner (e.g., a two-way Wilkinson power combiner). Signal generator 205 may include an output impedance of 50 ohms, which may be coupled to transmission line 210, which may include a characteristic impedance of 50 ohms. Transmission line 210 may be coupled to phase / voltage / current sensing circuit 215, which may be used to provide a feedback signal in response to an impedance mismatch between transmission line 210 and matching reflection optimizer 220. For example, if the voltage standing wave ratio (VSWR) increases beyond a threshold, the phase / voltage / current sensing circuit 215 may provide a signal to match matching reflection optimizer 220 to approximately 50 ohms. Thus, in certain embodiments, if the phase / voltage / current sensing circuit 215 measures an increase in VSWR from, for example, 1.0:1 to 1.15:1, the reactive components of the matching reflection optimizer 220 may be modified to reduce the measured VSWR to a smaller value, such as 1.10:1 or less. However, it should be noted that the threshold of the measured VSWR at which the reactive elements of the matching reflection optimizer 220 should be modified may be determined based on the desired application, and embodiments are not limited to any particular VSWR threshold or range of VSWR thresholds. Thus, in certain embodiments, for example, if a VSWR greater than 1.10:1 is measured, the reactive components of the matching reflection optimizer 220 may be adjusted to reduce the measured VSWR to, for example, 1.10:1. However, it should be noted that in some embodiments, tuning the reactive components of the matched reflectance optimizer 220 in response to relatively small changes in the measured VSWR (e.g., to make the VSWR less than 1.05:1) may result in over-tuning of the reactive components of the matched reflectance optimizer 220, which may reduce the useful life of the reactive components. Figure 3 As shown in , various circuit topologies may be utilized in the matched reflection optimizer 220 .

[0038] exist Figure 2, a plurality of RF power control circuits 225A-225N are shown coupled to the output port of the matching reflection optimizer 220 and to the input ports of the isolation RF filters 230A-230N. In a particular embodiment, the RF power control circuits 225 operate to achieve maximum power transfer between the matching reflection optimizer 220 and the various stations 102A-102N of the processing chamber. In a particular embodiment, the RF power control circuits 225A include adjustable reactive components (e.g., capacitors) in a manner similar to the matching reflection optimizer 220 that achieve maximum power transfer from the output port of the matching reflection optimizer 220 to the input ports of the stations 102A-102N of the processing chamber. Figure 2 In some embodiments, such adjustment of one or more reactive components of RF power control circuits 225A-225N may be facilitated in response to a second measurement of the phase-sensitive voltage (e.g., by phase / voltage / current sensing circuit 235A). Thus, in certain embodiments, in response to, for example, an increase in VSWR at the input port of station 102 measured by phase / voltage / current sensing circuit 235A, sensing circuit 235A may adjust the reactive components of RF power control circuit 225A to reduce the VSWR, thereby improving power transfer between RF power control circuit 225A and station 102A. In a similar manner, phase / voltage / current sensing circuit 235B may be operable to adjust one or more reactive components of RF power control circuit 225B. Similarly, phase / voltage / current sensing circuit 235C may be operable to adjust one or more reactive resistors of RF power control circuit 225C. Similarly, phase / voltage / current sensing circuit 235N may be operable to adjust one or more reactive components of RF power control circuit 225N.

[0039] The isolation RF filters 230A-230N are used to provide decoupling between the low frequency source (e.g., 400 kHz source) and the high frequency source (e.g., 27.12 MHz) while allowing both signals to appear at sufficient amplitude at the stations 102A-102N. Figure 7 It can be seen that while both low frequencies (e.g., 400 kHz) and high frequencies (e.g., 27.12 MHz) may be allowed to interact within a particular station, RF notch filters are utilized to substantially isolate low frequency signals from high frequency signals, while high pass filters may be used to substantially isolate high frequency signals from low frequency signals.

[0040] Figure 3 300 is a diagram showing various circuit components utilized in a closed loop multi-output RF matching process used in performing a plasma enhanced process. Note that for clarity of illustration, Figure 3 Only Figure 2However, it should be understood that any number of, for example, RF power control circuits (e.g., 225A, 225B), isolation RF filters (e.g., 230A, 230B), phase / voltage / current sensing circuits (e.g., 235A, 235B), and stations (e.g., 102A, 102B) may be utilized.

[0041] exist Figure 3 In FIG. 1 , the matching reflection optimizer 220 includes a variable capacitor C220 and an inductor L220. Figure 3 In an embodiment of the invention, inductor L220 represents a static component whose value is selected to provide a range of admittances that can be presented by the series combination of C220 and L220. In a specific embodiment, C220 represents a variable capacitor whose value can be controlled via a remote signal (e.g., a signal from the phase / voltage / current sensing circuit 215). Therefore, in response to the phase / voltage / current sensing circuit 215 measuring an increase in inductance presented by the combination of RF power control circuits 225A-225N (e.g., through a measurement of VSWR), the capacitance value presented by C220 can be adjusted to present sufficient admittance to return the measured VSWR to a value less than a predetermined threshold (e.g., 1.15:1, 1.10:1, etc.). Such adjustment of capacitor C220 can increase power transfer from signal generator 205 to the RF power control circuit (e.g., 225A).

[0042] RF power control circuit 225A may additionally include a series impedance represented by C225A and inductor L225A. Inductor L225A may represent a static component whose value is selected to provide a range of impedances that may be presented by the combination of C225A and L225A. In a particular embodiment, C225A may represent a variable capacitor whose value may be controlled via a remote signal (e.g., a signal from phase / voltage / current sensing circuit 235A). Thus, in response to changes in the impedance of station 102A measured by phase / voltage / current sensing circuit 235A, capacitor C225A may be adjusted to achieve maximum power transfer between matching reflection optimizer 220 and stations 102A and 102B.

[0043] Figure 4 FIG. 4 is a diagram showing circuit components for performing matching reflection optimization in a closed-loop multi-output RF matching process used in performing semiconductor processing according to an embodiment 400. Figure 3As described, the matching circuit reflection optimizer 220 may include a shunt circuit that utilizes relatively fixed values ​​of inductance and a variable capacitor to provide an admittance that can be used to maximize power transfer from the signal generator 205 to the RF power control circuit 225A. However, it should be understood that while a matching reflection optimizer circuit (e.g., circuit 220) may be particularly suitable for matching at high frequencies (e.g., 27.12 MHz), other circuit topologies such as pi-matching circuit 420 may also be used to match at lower frequencies (e.g., 400 kHz). In addition, in other cases (e.g., when a series impedance can be used to reduce VSWR), a T-matching circuit such as circuit 320 may be used.

[0044] Figure 5 is a diagram showing circuit components for performing RF power control in a closed-loop multi-output RF matching process according to an embodiment 500. Figure 5 The implementation scheme can be Figure 4 , where various circuit topologies can be utilized depending on the frequency (e.g., 400kHz or 27.12MHz) at which impedance matching is to be achieved. It is expected that in many cases, a series circuit (e.g., series circuit 225) with adjustable capacitance C225A can be operated to bring the VSWR measured by the phase / voltage / current sensing circuit 235A to a value less than a threshold. However, in other cases, it may be advantageous to utilize a parallel circuit (e.g., parallel circuit 325) to reduce or modify the VSWR measured by the phase / voltage / current sensing circuit 235A. In still other cases, it may be advantageous to utilize a shunt circuit (e.g., shunt circuit 425) to reduce or modify the VSWR measured by the phase / voltage / current sensing circuit 235A.

[0045] Figure 6 600 is a diagram showing circuit elements for RF isolation and filtering in a closed loop multi-output RF matching process used in performing semiconductor processing. Figure 4 and Figure 5 Similarly, various circuit topologies may exist to provide decoupling between a low frequency source (e.g., a 400 kHz source) and a high frequency source (e.g., 27.12 MHz) while allowing both signals and sufficient amplitude to appear at stations 102A-102N of the processing chamber. Thus, circuit designers may utilize high pass filter 230, low pass filter 330, notch filter 435, and / or band pass filter 535 to achieve sufficient isolation (e.g., isolation between 25.0 dB and 35.0 dB).

[0046] Figure 7700 is a diagram showing circuit components for matching and / or impedance conversion in a closed-loop multi-output RF matching process used in performing semiconductor processing. It should be understood that Figure 7 The goal of the circuit components of may be to couple signals from the high frequency generator 160 and the low frequency generator 155 to a station (e.g., station 102A). As previously described, a station for performing a plasma-based wafer processing process (or other type of semiconductor processing process) may present an impedance having only a small real portion and a relatively high reactive (or imaginary) portion. Thus, in certain embodiments, one purpose of the low frequency matching network 158 and the high frequency matching network 163 is to transform the impedance of a processing station (e.g., stations 102-102N of a processing chamber) so that such impedance presents a load at least similar to 50 ohms. In embodiments, such impedance transformation facilitates power transfer between a signal generator and a transmission line (having a characteristic impedance of 50 ohms) to a highly reactive (e.g., inductive / capacitive) load.

[0047] However, it is also understood that, at least in certain embodiments, separating high frequency signals from low frequency signals may be problematic. In certain embodiments, if such signals are not isolated (or at least decoupled by, for example, 25 dB to 40 dB), such cross coupling may interfere with the ability of the signal generator to generate an appropriate RF signal.

[0048] Therefore, in Figure 7 , the shunt network 710 may be used to filter low frequency components from the output signal port of the HF signal generator 160. Thus, the values ​​of HF_L1 and HF_L2 shown in parallel at the shunt network 710 may be selected so that the low frequency signal (e.g., a 400 kHz signal) is shunted to the local ground. In addition, the capacitor HF_C1 may also be selected to present an open loop (or at least a relatively high impedance) to the low frequency signal 730 that may be coupled from the low frequency matching network 158. Thus, in one embodiment, the signal 730 may be only weakly coupled (as indicated by the low amplitude signal 735) by the filtering action of the capacitor HF_C1. However, as Figure 7 As shown, signal 730 may be coupled via the VI probe and enter station 102A before impinging on capacitor HF_C1.

[0049] In addition, the high frequency signal (e.g., as shown in waveform 720) from the high frequency matching network 163 can be significantly attenuated by, for example, between 25 and 40 dB, by notch filter (NF) 715. Therefore, as shown in waveform 725, the high frequency waveform 720 can be significantly attenuated. However, the high frequency component may be able to couple through VI probe 717 and enter station 102A. Therefore, as shown in waveform 725, Figure 7As shown, at node 728, the high frequency waveform 720 and the low frequency signal 730 may be allowed to couple via the VI probe 717 and into the station 102A.

[0050] Although Figure 7 A single signal path associated with station 102A is depicted (including HF_C1, notch filter (NF) 715, and VI probe 717), but it is contemplated that in certain embodiments, additional processing stations (e.g., Figure 2 102B, 102C, and 102D) together with duplicating additional signal paths (including additional notch filters and additional VI probes). Similarly, although Figure 7 Only a single signal path of the low frequency matching network 158 is depicted (which includes signal coupling through a low pass filter and impedance transformation network 740), but it is contemplated that certain implementations include additional signal paths, such as a signal path for each of the processing stations 102A, 102B, 102C, and 102D.

[0051] Figure 8 FIG. 1 is a flow chart of a closed-loop RF matching method according to an embodiment. Figure 8 The method begins at 810, and includes measuring a voltage standing wave ratio (VSWR) at an input port of a power divider. The method continues at 820, and includes: in response to the measured VSWR, adjusting a value of a reactive component of a matching reflection optimizer, wherein the step of adjusting the reactive component results in a second VSWR below a first threshold.

[0052] At 820, the reactive component may correspond to a variable capacitor or may correspond to a variable inductor. The step of adjusting the reactive component may result in a second VSWR of less than 1.15:1. However, in certain embodiments, it may be desirable to reduce the second VSWR to a value other than less than 1.15:1, such as less than 1.25:1, less than 1.20:1, less than 1.10:1, or less than 1.05:1. The VSWR may be measured at a signal frequency of any value, such as about 400kHz (between 360kHz and 440kHz), or at another frequency between about 50kHz and 1MHz. The VSWR may also be measured at any other signal frequency between about 27.12MHz and 50MHz. The operation of measuring the VSWR may be performed at an input port of one or more input ports corresponding to a station of the processing chamber.

[0053] One or more processing stations may be included in a multi-station processing tool. Fig. 9A schematic diagram of an embodiment of a multi-station processing tool 900 is depicted. The tool 900 employs a single substrate processing chamber 914 that houses a plurality of substrate processing stations, each of which can be used to perform processing operations on a substrate held in a substrate holder (e.g., a pedestal) at the processing station. In this particular embodiment, the multi-station substrate processing apparatus 900 is shown as having four processing stations 102A, 102B, 102C, and 102D. Other similar multi-station processing apparatuses may have more or fewer processing stations depending on the embodiment and, for example, the desired degree of parallel wafer processing, size / space constraints, cost constraints, etc. In Fig. 9 Also shown are a substrate handling robot 906 and a controller 950.

[0054] like Fig. 9 As shown in FIG. , the multi-station processing tool 900 has a substrate loading port 920, and the robot 906 is configured to move substrates from a box loaded by a wafer boat 908 into a processing chamber 914 and to one of the four stations 102A, 102B, 102C and 102D via the loading port 920.

[0055] Fig. 9 The processing chamber 914 shown in Figure 1 provides four processing stations 102A, 102B, 102C and 102D. RF power is generated at RF power system 913 and distributed to each of stations 102A, 102B, 102C and 102D. The RF power system may include one or more RF power sources, such as high frequency (HFRF) and low frequency (LFRF) sources, impedance matching modules and filters. In certain embodiments, the power source may be limited to only high frequency or low frequency sources. The distribution system of the RF power system will be symmetrical relative to the reactor and may have high impedance. This symmetry and impedance cause approximately equal amounts of power to be delivered to each station. In certain embodiments, the RF power system may be configured to independently deliver power to each station.

[0056] Fig. 9 Also depicted is an embodiment of a substrate transfer device 990 within the processing chamber 914 for transferring substrates between the processing stations 102A, 102B, 102C, and 102D. It should be understood that any suitable substrate transfer device may be employed. Non-limiting examples include a wafer turntable and a wafer handling robot. System Controller

[0057] Fig. 9Also depicted is an embodiment of a system controller 950 for controlling processing conditions and hardware states of the processing tool 900. The system controller 950 may include one or more memory devices 956, one or more mass storage devices 954, and one or more processors 952. The processor 952 may include a CPU or computer, analog, and / or digital input / output connections, a stepper motor controller board, etc.

[0058] In some embodiments, the system controller 950 controls all actions of the processing tool 900. The system controller 950 executes system control software 958, which is stored in the mass storage device 954, loaded into the memory device 956, and executed on the processor 952. The system control software 958 may include instructions for controlling the timing, the mixing of gases, the pressure of the chamber and / or station, the temperature of the chamber and / or station, the temperature of the wafer, the target power level, the RF power level, the RF exposure time, the position of the substrate pedestal, chuck and / or pedestal, the number of cycles performed at one or more stations, and other parameters of the specific process performed by the processing tool 900. These programmed processes may include various types of processes, including (but not limited to) processes related to determining the accumulation on the surface inside the chamber, processes related to thin film deposition on the substrate (including the number of cycles, determining and obtaining the compensation cycle number), and processes related to the clean room. The system control software 958 can be configured in any suitable manner. For example, subroutines or control objects for various process tool components may be written to control the operation of the process tool components required to perform the processes of the various process tools.The system control software 958 may be coded in any suitable computer readable programming language.

[0059] In some embodiments, the system control software 958 may include input / output control (IOC) sequencing instructions to control the various parameters described above. For example, deposition on a substrate and each phase of a deposition cycle may include one or more instructions executed by the system controller 950. Instructions for setting process conditions for an ALD / CFD deposition process may be included in a corresponding ALD / CFD deposition recipe phase. In certain embodiments, the recipe phases may be configured sequentially so that all instructions for a process phase are executed simultaneously with that process phase.

[0060] In some embodiments, other computer software and / or programs may be employed that are stored on the mass storage device 954 and / or the memory device 956 associated with the system controller 950. Examples of programs or portions of programs for this purpose include substrate positioning programs, process gas control programs, pressure control programs, heater control programs, and plasma control programs.

[0061] The substrate positioning program may include code for processing tool components for loading a substrate onto the pedestal 918 and for controlling the spacing between the substrate and other components of the processing tool 900. The positioning program may include instructions for appropriately moving the substrate into and out of reaction chambers to deposit films on the substrate and cleaning chambers as needed.

[0062] The process gas control program may include code for controlling gas composition and flow rates and optionally for flowing gas into one or more process stations to stabilize pressure in the process stations prior to deposition. In certain embodiments, the process gas control program includes instructions for introducing gas during film formation on a substrate in a reaction chamber. This may include introducing gas for different number of cycles for one or more substrates in a batch of substrates.

[0063] The pressure control program may include code for controlling the pressure within the process station by adjusting, for example, a throttle valve in an exhaust system of the process station, a gas flow into the process station, etc. The pressure control program may include instructions for maintaining the same pressure during different numbers of deposition cycles performed on one or more substrates during batch processing.

[0064] The heater control program may contain code for controlling the current of a heating unit used to heat the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas (eg, helium) to the substrate.

[0065] The plasma control program may include code for setting RF power levels, frequencies, and exposure times in one or more processing stations according to embodiments herein. In some embodiments, the plasma control program may include instructions for using the same RF power level and / or frequency and / or exposure time during deposition processes of different numbers of cycles on one or more substrates during batch processing.

[0066] In some embodiments, there may be a user interface associated with the system controller 950. The user interface may include a display screen, graphical software display of the device and / or processing station, and user input devices (e.g., pointing device, keyboard, touch screen, microphone, etc.).

[0067] In some embodiments, the parameters adjusted via the system controller 950 may relate to processing conditions. Non-limiting examples include process gas composition and flow rates, temperature, pressure, plasma conditions (e.g., RF bias power level and exposure time), etc. These parameters may be provided to the user in the form of a recipe, which may be entered using a user interface. A recipe for an entire batch of substrates may include a compensated cycle count for one or more substrates in the batch to account for thickness trends during batch processing.

[0068] Signals to monitor the process may be provided via analog and / or digital input connections of the system controller 950 from various process tool sensors. Signals to control the process may be output on analog and digital output connections of the process tool 900. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (e.g., manometers), thermocouples, etc. Sensors may also be included and used to monitor and determine accumulation on one or more surfaces within the chamber, and / or thickness of material layers on substrates in the chamber. Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain process conditions.

[0069] The system controller 950 may provide program instructions for carrying out the deposition process described above. These program instructions may control various process parameters, such as DC power level, RF bias power level, pressure, temperature, number of cycles for the substrate, accumulation on at least one surface within the chamber, etc. The instructions may control the parameters to operate the in-situ deposition of the film stack according to the various embodiments described herein.

[0070] For example, the system controller may include control logic for performing the techniques described herein, such as (a) determining the cumulative amount of deposited material currently on at least one internal region within the deposition chamber; (b) applying the cumulative amount of deposited material determined in (a) or a parameter derived therefrom to the relationship between (i) the number of ALD cycles required to achieve a target deposition thickness and (ii) a variable representing the cumulative amount of deposited material to obtain a compensated number of ALD cycles to produce the target deposition thickness given the cumulative amount of deposited material currently on the internal region within the deposition chamber; and (c) performing the compensated number of ALD cycles on one or more substrates in a batch of substrates. The system may also include control logic for performing the following operations: determining that the cumulative amount in the chamber has reached a cumulative limit and stopping processing of the batch of substrates in response to the determination; and causing cleaning of the chamber interior.

[0071] The system controller will typically include one or more memory devices and one or more processors configured to execute instructions so that the apparatus performs methods according to the present invention. A machine-readable non-transitory medium containing instructions for controlling process operations according to the present invention may be connected to the system controller.

[0072] In some embodiments, the controller is part of a system, which may be part of the above examples. Such a system may include a semiconductor processing device, which includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems can be integrated with electronic devices for controlling their operations before, during, and after the processing of semiconductor wafers or substrates. The electronic device can be referred to as a "controller", which can control various components or subcomponents of one or more systems. Depending on the processing requirements and / or system type, the controller can be programmed to control any processing disclosed herein, including the number of cycles performed on the substrate, the delivery of the processing gas, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer in and out of tools and other transfer tools and / or load locks connected to or connected to a specific system through an interface.

[0073] In general, a controller can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuit can include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or one or more microprocessors, or a microcontroller that executes program instructions (e.g., software). The program instructions can be instructions sent to the controller in the form of various individual settings (or program files) that define operating parameters for performing specific processing on or for a semiconductor wafer or system. In some embodiments, the operating parameters can be part of a recipe defined by a process engineer to complete one or more processing steps during the manufacture of one or more (kinds of) layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0074] In some implementations, the controller may be part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the "cloud" or may be all or part of a wafer fab host system that may allow remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of a manufacturing operation, check the history of past manufacturing operations, check trends or performance criteria for multiple manufacturing operations, change parameters of a current process, set processing steps to follow the current process, or start a new process. In some examples, a remote computer (e.g., a server) may provide a processing recipe to the system via a network (which may include a local network or the Internet). The remote computer may include a user interface that enables input or programming of parameters and / or settings, which are then sent from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify parameters for each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus, as described above, the controller may be distributed, for example, by including one or more discrete controllers networked together and working toward a common purpose (e.g., processing and control as described herein). An example of a distributed controller for such a purpose is one or more integrated circuits on a chamber that communicate with one or more integrated circuits remotely (e.g., at a platform level or as part of a remote computer), which combine to control processing on the chamber.

[0075] In the above detailed description, a large number of specific details are described to provide a thorough understanding of the proposed embodiments or implementations. The disclosed embodiments or implementations can be implemented without some or all of these specific details. In other examples, in order not to make the disclosed embodiments or implementations difficult to understand, conventional processing operations will not be described in detail. Although the disclosed embodiments or implementations are described in conjunction with specific embodiments or implementations, it should be understood that this description is not intended to limit the disclosed embodiments or implementations.

[0076] For the purpose of describing the disclosed aspects, the above detailed description is for certain embodiments or implementations. However, the teachings of this article can be applied and implemented in many different ways. In the above detailed description, reference is made to the accompanying drawings. Although the disclosed embodiments or implementations are described in sufficient detail to enable those skilled in the art to practice these embodiments or implementations, it should be understood that these examples are not restrictive; other implementations can be used, and they can be changed without departing from the spirit and scope of the disclosed embodiments or implementations. In addition, it should be understood that, unless otherwise indicated, the conjunction "or" is intended to be inclusive in this article in appropriate circumstances; for example, the term "A, B, or C" is intended to include the possibility of "A", "B", "C", "A and B", "B and C", "A and C", and "A, B, and C".

[0077] In this application, the terms "semiconductor wafer", "wafer", "substrate", "wafer substrate", and "partially processed integrated circuit" are used interchangeably. It should be understood by those skilled in the art that the term "partially processed integrated circuit" can refer to a silicon wafer during any of many stages of integrated circuit processing. Wafers or substrates used in the semiconductor device industry typically include a diameter of 200 mm, or 300 mm, or 450 mm. The above detailed description assumes that the implementation scheme or implementation scheme is implemented on the wafer, or in conjunction with the processing associated with forming or manufacturing the wafer. However, the claimed subject matter is not so limited. The workpiece can be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that can utilize the claimed subject matter can include various objects, such as printed circuit boards, or the manufacture of printed circuit boards, etc.

[0078] Unless the context of the present disclosure clearly requires otherwise, throughout the specification and claims, the terms "comprising," "including," and the like are to be interpreted in an inclusive sense rather than an exclusive or comprehensive sense; that is, in the sense of "including, but not limited to." The use of singular or plural terms also generally includes the plural or singular, respectively. When the term "or" is used with reference to a list of two or more items, the term encompasses all of the following interpretations of the term: any one of the items in the list, all of the items in the list, and any combination of the items in the list. The term "implementation" means an implementation of the techniques and methods described herein, as well as a physical object that implements the structure and includes the techniques and / or methods described herein.

Claims

1. An apparatus for providing signals to a plurality of stations of a processing chamber, the processing chamber being configured to perform a plasma-based semiconductor processing process, the apparatus comprising: a measurement circuit configured to measure a voltage standing wave ratio; and A matched reflection optimizer having a plurality of output ports each corresponding to one of the plurality of stations of the process chamber, the matched reflection optimizer comprising a reactive component configured to be adjusted in response to an output signal from the measurement circuit.

2. The apparatus of claim 1, wherein the reactive component is configured to be adjusted to modify the measured voltage standing wave ratio from a first value to a second value.

3. The apparatus of claim 1, wherein the measurement circuit for measuring the voltage standing wave ratio corresponds to a phase-sensitive voltage / current measurement circuit.

4. The apparatus of claim 1, wherein the reactive component corresponds to a variable capacitor.

5. The apparatus of claim 1, further comprising a second measurement circuit for measuring a second voltage standing wave ratio at one or more input ports of one of the plurality of stations.

6. The apparatus of claim 1 further comprising an isolation RF filter for providing between 25 and 40 dB of isolation between high frequency and low frequency portions of the apparatus. 7 . The apparatus of claim 1 , wherein the matched reflection optimizer is configured to reduce the voltage standing wave ratio to a value less than a threshold value.

8. The apparatus of claim 7, wherein the threshold value of the voltage standing wave ratio corresponds to 1.15:

1.

9. The apparatus of claim 7, wherein the threshold value of the voltage standing wave ratio corresponds to 1.10:

1.

10. A method of coupling a plurality of signals to a plurality of stations of a processing chamber configured to perform a plasma-based semiconductor processing process, the method comprising: measuring the voltage standing wave ratio at the input port of the power divider; and In response to the measured VSWR, a value of a reactive component of a matched reflection optimizer is adjusted, the matched reflection optimizer having a plurality of output ports, the output ports each corresponding to one of the plurality of stations of the process chamber. The method of claim 10 , wherein the reactive component comprises a variable capacitor.

12. The method of claim 10, wherein adjusting the value of the reactive component reduces the voltage standing wave ratio to a value less than 1.15:

1.

13. The method of claim 10, wherein the measuring comprises measuring the voltage standing wave ratio of a first signal having a first frequency of approximately 400 kHz and a second signal having a second frequency of approximately 27.12 MHz.

14. The method of claim 13, further comprising attenuating the signal having the second frequency by an amount between 25 and 40 dB at a signal generator of the first frequency.

15. The method according to claim 10, further comprising: measuring a voltage standing wave ratio at an input port of one or more of the plurality of stations of the process chamber; and The value of a reactive component of an RF power control circuit is adjusted, and the reactive component of the RF power control circuit is adjusted to produce a voltage standing wave ratio below a second threshold.

16. The method of claim 10, further comprising adjusting a value of a reactive component of a pi-matching circuit such that the voltage standing wave ratio of a signal at a first frequency between 360 kHz and 440 kHz is reduced.

17. The method of claim 10, further comprising adjusting the value of a reactive component of an L-matching circuit to reduce the voltage standing wave ratio at a second frequency between about 26.5 MHz and about 27.5 MHz.

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