An isolated gate drive circuit using a package lid parasitic element

Abstract

The application relates to an isolated gate drive circuit using a packaging cover plate parasitic element, which is combined with a power module and comprises a coreless transformer, a DSP control chip, a transmitter, a primary side capacitor, a secondary side capacitor, a receiver and a gate drive controller; wherein the coreless transformer is arranged on the power module shell, the DSP control chip and the gate drive controller are located on the packaging cover plate; the coreless transformer is connected with the primary side capacitor and the secondary side capacitor respectively, the DSP control chip is connected with the primary side capacitor through the transmitter, and the gate drive controller is connected with the secondary side capacitor through the receiver. The circuit can be equivalent to isolation, is suitable for high power density power module scenes, has low transmission delay, and simultaneously realizes absolute insulation. Since the PCB circuit board and the transformer have a relative distance in the physical space, the circuit conduction interference of components on the transformer is reduced.

Description

Technical Field

[0001] This application relates to the field of switching power supply technology, and in particular to an isolated gate drive circuit utilizing parasitic elements of a package cover. Background Technology

[0002] In power modules, the PWM (Pulse Width Modulation) control signal generated by the control chip cannot be directly connected to the power transistor. It needs to pass through an isolation barrier and a gate driver chip to generate a drive signal to control the power transistor in the power module. To improve the isolation voltage level of the gate driver chip, a traditional solution is to use a transformer to isolate the gate driver chip from the power transistor. The low-side non-isolated gate driver chip applies pulses to the transformer to control the power transistor's on and off states. Although this solution has low propagation delay, the transformer is large and expensive, making it unsuitable for high power density applications. Furthermore, in high power density power modules, current research is increasingly focused on smaller size and higher integration, leading to a gradual increase in the number of PCB (Printed Circuit Board) layers and a decrease in board area. The close bonding of components in multi-layer PCBs greatly limits the difficulty of routing and PCB layout.

[0003] Transformers are widely used in power modules to convert voltage from one amplitude to another. A traditional transformer consists of a pair of conductive windings around a magnetic core. This configuration is easy to manufacture, but it has disadvantages in terms of the size, weight, and brittleness of the magnetic materials. Summary of the Invention

[0004] Therefore, it is necessary to provide an isolated gate drive circuit that utilizes parasitic elements of the package cover plate to address the above-mentioned technical problems. This circuit can achieve high power density of the power module by providing strong anti-interference capability, low loss, saving board area, and high power density of the power module.

[0005] This application provides an isolated gate drive circuit utilizing parasitic elements of a package cover. This circuit is integrated with a power module and includes a coreless transformer, a DSP (Digital Signal Processor) control chip, a transmitter, a primary capacitor, a secondary capacitor, a receiver, and a gate drive controller. The coreless transformer is located on the power module housing, while the DSP control chip and the gate drive controller are located on the package cover. The coreless transformer is connected to both the primary and secondary capacitors. The DSP control chip is connected to the primary capacitor via the transmitter, and the gate drive controller is connected to the secondary capacitor via the receiver.

[0006] In one embodiment, the package cover includes a PCB board, with a DSP control chip and a gate drive controller respectively disposed on a first side and a second side of the PCB board.

[0007] In one embodiment, the PCB board is connected to signal ground, and the power module casing is connected to earth ground.

[0008] In one embodiment, both the primary-side capacitor and the secondary-side capacitor include parasitic capacitance between the PCB board and the power module housing, as well as parasitic capacitance of the coreless transformer.

[0009] In one embodiment, the DSP control chip sends a PWM control signal, which is modulated by the transmitter and the primary capacitor. After coupling through a coreless transformer, the coupled PWM control signal is transmitted to the gate drive controller for demodulation through the receiver and the secondary capacitor to generate the drive signal for the power module.

[0010] In one embodiment, the output of the DSP control chip is connected to the input of the transmitter, the output of the transmitter is connected to the primary capacitor, the input of the receiver is connected to the secondary capacitor, and the output of the receiver is connected to the input of the gate drive controller. When the PWM control signal switches from low to high, the transmitter and the primary capacitor encode the rising edge as a positive narrow pulse. When the PWM control signal switches from high to low, the transmitter and the primary capacitor encode the falling edge as a negative narrow pulse. The pulse signal modulated by the transmitter and the primary capacitor is coupled to the secondary side through a coreless transformer. The receiver and the secondary capacitor restore the positive narrow pulse to a rising edge and the negative narrow pulse to a falling edge according to the polarity of the received pulse.

[0011] In one embodiment, the coreless transformer includes a square metal coil in which the primary winding and the secondary winding are located on the same layer.

[0012] In one embodiment, the tap of the metal coil is provided with a contact pad.

[0013] The aforementioned isolated gate drive circuit utilizing parasitic elements in the encapsulated cover plate abandons the traditional scheme of transmitting signals using a transformer core. It employs a coreless transformer coupling method, using a transformer composed of a metal coil and silicon oxide insulating medium to transmit control signals modulated in the form of current pulses. This achieves high anti-interference capability. The circuit improves the voltage change rate dv / dt while exhibiting low losses and good stability. In this application, the coreless transformer is fitted into the power module housing, avoiding the occupation of PCB bare board area inside the power module. It cleverly transmits the gate drive control signal through the power module housing, saving PCB bare board space and increasing the power density of the power module. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a traditional isolated gate drive circuit;

[0015] Figure 2 Simulation waveform diagram of a traditional isolated gate drive circuit;

[0016] Figure 3 This is a schematic diagram of an isolated gate drive circuit utilizing parasitic elements of a package cover in one embodiment;

[0017] Figure 4 This is a schematic diagram of a coreless transformer in one embodiment;

[0018] Figure 5 Here is an equivalent circuit diagram of a coreless transformer in one embodiment;

[0019] Figure 6 This is a schematic diagram of an isolated gate-driven brick-type power module utilizing parasitic elements of a package cover in one embodiment.

[0020] Figure 7 This is a waveform diagram of an isolated gate drive circuit utilizing parasitic elements of a package cover in one embodiment. Detailed Implementation

[0021] In the power module, the PWM control signal generated by the control chip cannot be directly connected to the power transistor. It needs to pass through the isolation barrier and the gate driver chip to generate a drive signal to control the power transistor in the power module.

[0022] In gate drive control circuits, half-bridge gate drives are widely used in various applications. However, due to the need for isolation and the requirement to provide an isolated power supply for the high-side gate driver, their design is quite challenging. Based on the medium used for the isolation barrier and the physical quantities transmitted through it, isolation methods can be categorized into optocoupler isolation, magnetic coupling isolation, and capacitive isolation.

[0023] Different applications have different isolation requirements, which can be divided into four levels: functional, basic, dual, and enhanced. In commercial products, enhanced isolation is the highest available isolation level. Although it consists of a single isolation barrier, this barrier typically performs dual-level equivalent isolation.

[0024] To improve the isolation voltage level of gate driver chips, a traditional solution is to use a transformer to isolate the gate driver chip from the power transistor. The low-side non-isolated gate driver chip applies pulses to the transformer, thereby controlling the power transistor's on and off states. While this solution offers low propagation delay, the transformer is bulky and unsuitable for high power density applications.

[0025] Magnetic isolation utilizes the changing magnetic field between inductively coupled coils to transmit signals. The preceding circuit generates a changing current signal that flows through the primary coil, generating a changing magnetic field on the primary coil. Due to the magnetic field coupling between the primary and secondary coils, the secondary coil will induce a changing current. The rate of change of the current is proportional to the rate of change of the current in the primary coil, thereby achieving signal transmission.

[0026] Magnetic coupling isolation offers faster transmission speeds, longer lifespans, and a wider operating temperature range, and can transmit both data and energy. However, the on-chip transformer used in magnetic coupling isolation lacks a magnetic core, making it susceptible to external magnetic field (noise) interference and exhibiting low magnetic field immunity. Furthermore, the on-chip transformer itself is a radiation source, posing EMI (Electromagnetic Interference) problems. In humid environments, the polyimide used in magnetic coupling isolation is easily affected. On-chip transformers require MEMS (Micro-Electro-Mechanical Systems) technology, occupy a large area, and are technically challenging and costly to manufacture.

[0027] Transformers are widely used in power modules to convert voltage from one amplitude to another. Traditional transformers consist of a pair of conductive windings surrounding a magnetic core. This configuration is easy to manufacture, but it has drawbacks in terms of the size, weight, and brittleness of the magnetic materials. To improve the power density of power modules, coreless transformers are becoming increasingly popular and are widely used in highly integrated isolated gate drive circuits. However, high integration means that components in the circuit can generate conducted interference to the transformer. Therefore, how to reduce conducted interference in isolated gate drive circuits while using coreless transformers remains a problem that urgently needs to be solved.

[0028] A schematic diagram of a traditional isolated gate drive circuit is shown below. Figure 1 As shown, the traditional magnetically isolated gate drive circuit mainly consists of capacitor Cp, transformer parasitic resistance Rp, transformer primary inductance Lp and secondary inductance Ls, capacitor Cs and load Rd. The input terminal is the high-frequency PWM control signal generated by DSP (Digital Signal Processing) connected to capacitor Cp. Due to the high-frequency signal at the edge of the PWM control signal, the inductor and capacitor in the circuit are in high-frequency resonance, generating a high-frequency current pulse signal. The signal modulation function of the primary side is realized by edge detection, as shown in the following formula (1), where VIN is the input voltage, I s For secondary current:

[0029]

[0030] Figure 2This is a simulation waveform diagram of a traditional magnetically isolated gate drive circuit, where VIN is the input signal, Ip is the primary current, and Is is the secondary current. When the input signal rises, the capacitor detects the signal and generates a corresponding positive current pulse. Due to magnetic coupling isolation, a corresponding signal is induced in the power module transformer and transmitted to the secondary side, generating a positive or negative pulse based on the transformer windings. When the input signal falls, the capacitor detects the signal and generates a corresponding negative current pulse. This, in turn, induces a corresponding signal in the power module transformer and transmits it to the secondary side, generating a positive or negative current pulse based on the transformer windings, thus achieving signal modulation. The transformer transmits the modulated signal to the receiver, where the gate drive chip performs the corresponding demodulation function to obtain the control signal corresponding to the PWM signal, completing the signal transmission.

[0031] In traditional isolated gate drive circuits, the resonant period of the magnetically coupled isolation circuit is affected by parasitic parameters during the high-frequency rising edge of the PWM control signal. The effects of primary capacitor Cp, transformer inductance Lp and Ls, transformer parasitic resistance Rs, and secondary capacitor Cs should be reasonably adjusted. Therefore, if the resonant time of the magnetically coupled gate drive circuit is too long during high-frequency PWM signals, the values ​​of parasitic parameters such as primary capacitor Cp and Cs can be appropriately reduced to keep the resonant time within a suitable range.

[0032] This application proposes an isolated gate drive scheme based on a coreless transformer. The scheme includes an isolated gate drive circuit that utilizes parasitic elements of the package cover. This structure adopts a coreless transformer coupling method, which has strong anti-interference ability, low loss, saves board area, and achieves high power density of the power module.

[0033] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0034] In one exemplary embodiment, such as Figure 3 As shown, an isolated gate drive circuit utilizing parasitic elements of a package cover is provided. This circuit is integrated with a power supply module and includes a coreless transformer, a DSP control chip, a primary capacitor, a secondary capacitor, a transmitter, a receiver, and a gate drive controller. The coreless transformer is located on the power supply module housing, while the DSP control chip and the gate drive controller are located on the package cover. The coreless transformer is connected to both the primary and secondary capacitors. The DSP control chip is connected to the primary capacitor via the transmitter, and the gate drive controller is connected to the secondary capacitor via the receiver. The transmitter is located within the DSP control chip, and the receiver is located within the gate drive controller (IC).

[0035] Specifically, the isolated gate drive circuit utilizing parasitic elements of the package cover plate, implemented without a core transformer in this application, mainly includes a DSP control chip, a transmitter, a primary-side capacitor, a coreless transformer, a secondary-side capacitor, a receiver, and a gate drive controller. In the isolated gate drive circuit utilizing parasitic elements of the package cover plate, the DSP control chip located on the package cover plate sends a PWM control signal. The transmitter and the primary-side capacitor modulate the PWM wave, which is then coupled through the coreless transformer located on the power module casing and transmitted to the gate drive controller on the other side of the package cover plate for demodulation, generating drive signals for the power module's power transistors. The package cover plate includes a bare PCB board.

[0036] In one exemplary embodiment, it remains as follows Figure 3 As shown, the package cover includes a PCB board, a DSP control chip, and a gate drive controller, which are respectively located on the first and second sides of the PCB board.

[0037] Specifically, the isolated resonant gate drive circuit implements the corresponding function in the packaged power module, wherein the DSP control chip and the gate drive controller are located on both sides of the PCB board, and the coreless converter is located in the power module housing.

[0038] In one exemplary embodiment, it remains as follows Figure 3 As shown, the PCB board is connected to signal ground, and the power module casing is connected to earth ground.

[0039] Specifically, in the magnetically isolated gate drive power module solution provided in the embodiments of this application, the DSP module and the gate drive control chip are located on the bare PCB board inside the power module. The gate drive control chip is the gate drive controller. The PCB board and the power module shell are respectively connected to signal ground GND and earth ground EGND. The power module shell uses a coreless transformer to achieve magnetic coupling and realize the transmission of the modulated PWM control signal.

[0040] In one exemplary embodiment, it remains as follows Figure 3 As shown, both the primary and secondary capacitors include the parasitic capacitance between the PCB board and the power module housing, as well as the parasitic capacitance of the coreless transformer.

[0041] Specifically, Figure 3 The dashed line represents parasitic capacitance. The primary and secondary capacitors include parasitic capacitances of the PCB board and power module casing, as well as parasitic capacitances of the coreless transformer, achieving coreless magnetic coupling isolation technology.

[0042] In an exemplary embodiment, the DSP control chip sends a PWM control signal, modulates the PWM control signal through the transmitter and primary-side capacitor, couples it through a coreless transformer, and transmits the coupled PWM control signal to the gate drive controller for demodulation through the receiver and secondary-side capacitor to generate the drive signal for the power module.

[0043] In an exemplary embodiment, the output of the DSP control chip is connected to the input of the transmitter, the output of the transmitter is connected to the primary capacitor, the input of the receiver is connected to the secondary capacitor, and the output of the receiver is connected to the input of the gate drive controller. When the PWM control signal switches from low to high, the transmitter and the primary capacitor encode the rising edge as a positive narrow pulse. When the PWM control signal switches from high to low, the transmitter and the primary capacitor encode the falling edge as a negative narrow pulse. The pulse signal modulated by the transmitter and the primary capacitor is coupled to the secondary side through a coreless transformer. The receiver and the secondary capacitor restore the positive narrow pulse to a rising edge and the negative narrow pulse to a falling edge according to the polarity of the received pulse.

[0044] Specifically, in the isolated resonant gate drive system-level circuit, which utilizes the parasitic elements of the package cover, the output of the DSP control chip is connected to the input of the transmitter, and the output of the transmitter is connected to the primary-side capacitor. When the PWM control signal switches from low to high, the primary-side transmitter and parasitic capacitor encode the rising edge as a positive narrow pulse; when the control signal switches from high to low, the primary-side transmitter and parasitic capacitor encode the falling edge as a negative narrow pulse. The modulated pulse signal is coupled to the secondary side through a coreless transformer in the power module housing. The secondary-side receiver, based on the received pulse polarity (i.e., the receiver and secondary-side capacitor), restores the positive narrow pulse to a rising edge and the negative narrow pulse to a falling edge, thus restoring the carrier signal to a square wave signal, achieving a magnetically coupled isolated gate drive scheme.

[0045] In the magnetically isolated gate drive power module described in the above embodiment, which utilizes the parasitic elements of the package cover plate in an isolated gate drive circuit, the DSP module and the gate drive control chip IC are located on the bare PCB board within the power module. The gate drive control chip IC is the gate drive controller. The PCB board and the power module casing are connected to signal ground GND and earth ground EGND, respectively. The power module casing uses a coreless transformer to achieve magnetic coupling, enabling the transmission of the modulated PWM control signal. The parasitic capacitance between the power module casing and the PCB ground also affects the modulation of the PWM control signal. Therefore, it is necessary to reasonably adjust the values ​​of the primary-side capacitor Cp and the secondary-side capacitor Cs to reduce the influence of the parasitic capacitance between the power module casing and the PCB ground. In the figure, when the DSP controller sends the PWM control signal through the primary-side capacitor Cp to the power module casing, it has been modulated into a current pulse signal and coupled to the gate drive controller through the transformer.

[0046] In one exemplary embodiment, the coreless transformer includes a square metal coil in which the primary winding and the secondary winding are located on the same layer.

[0047] Specifically, the coreless magnetic coupling transformer structure in this application, i.e., the coreless transformer, is as follows: Figure 4 As shown, the coreless magnetic coupling transformer structure in this application consists of a square metal coil, achieving isolation between the primary and secondary sides, avoiding the use of a large magnetic core in the power module space, and improving the space utilization of the power module. The input ports of the primary and secondary coils of the transformer are Pa and Pb, and the output ports are Sa and Sb. The width of the inner loop of the square coil is d. in The width of the outer ring is d out In a coreless metal coil, the primary and secondary windings are designed to be located on the same layer to avoid the introduction of planar parasitic capacitances in the primary and secondary coils due to their being on different layers.

[0048] In one exemplary embodiment, the tap of the metal coil is provided with a contact pad.

[0049] Specifically, because the primary and secondary metal coils of the transformer are on the same layer and wound side-by-side, line-to-line parasitic capacitance is generated. The coils at the power module package casing in this application also interact with the package casing, generating eddy current fields that affect the magnetic field of the transformer's metal coils, thus affecting the transmitted pulse current signal. To ensure the insulation of the package, contact pads are designed at the coil taps. To ensure better transmission of the modulated signal, low-resistance coils are used to increase the current.

[0050]

[0051] As shown in formulas (2) and (3), the inductance of the square metal coil can be obtained based on the dimensions and winding resistance of the square metal coil in this application, where μ0 is the permeability of free space, K1 and K2 are the primary and secondary inductance coefficients of the square metal coil, n is the turns ratio of the transformer coil, and f r d is the ratio of the difference in the width of the metal coils to the sum of the values. avg The width of the primary and secondary metal coils is the average value, and the width of the inner loop of the square coil is d. in The width of the outer ring is d out .

[0052] Furthermore, in the isolated gate drive circuit utilizing parasitic elements of the package cover in this application, the upper limit of the coil self-resonant frequency fsr at the power module package shell is determined by the parasitic capacitance and the inductance of the coil; the coupling coefficient k is mainly determined by the inductance Loc measured by the secondary open circuit and the inductance Lsc measured by the secondary short circuit, as shown in formula (4):

[0053]

[0054] The winding capacitance is determined by the transformer's self-resonant frequency. Shortening the insulation between the primary and secondary coils can suppress the influence of the winding capacitance.

[0055] Furthermore, the equivalent circuit diagram of the coreless transformer in this application is as follows: Figure 5 As shown, the equivalent circuit consists of two coupled inductors (i.e., inductance Leq) connected in parallel with capacitor C. By using symmetry in the coreless transformer, inductors L1 and L2 are identical. Capacitor C is the equivalent capacitance of capacitors C3 and C4 connected in parallel. Capacitors C1 and C2 determine the self-resonant frequency, and resistors R1 and R2 are parasitic resistances determined by the transformer coils. Based on the equivalent circuit of the coreless transformer, the corresponding parasitic parameters such as capacitance and resistance can be measured. This allows for the design of corresponding inductance values ​​based on the control signal frequency of the power module, thereby reducing the impact of various parasitic parameters within the power module on the modulated signal and achieving high-performance signal transmission.

[0056] In this embodiment, based on the equivalent circuit of the coreless transformer, the corresponding parasitic parameters such as resistance and capacitance can be measured, and then the corresponding values ​​can be designed according to the control signal frequency of the power module, thereby reducing the influence of various parasites inside the power module on the modulated signal and realizing high-performance signal transmission.

[0057] In one embodiment, such as Figure 6As shown, a schematic diagram of an isolated gate-driven brick-type power module utilizing parasitic elements of a package cover is provided. The coreless transformer coil 601 is located on the cover plate 602 and connected to EGND. The DSP control chip 603 and the gate drive controller IC 604 are located on the bare PCB board 605 within the power module and connected to GND. A parasitic capacitance Cp exists between the transformer coil 601 and the DSP control chip 603, and a parasitic capacitance Cs exists between the transformer coil 601 and the gate drive controller IC 604. Further, the waveform of this circuit is shown below. Figure 7 As shown in the figure, VIN is the input signal, VOUT is the output signal, Ip is the primary current, and Is is the secondary current. From the waveform diagram, it can be seen that after adding the transformer coil to the cover plate 602, due to parasitic resistance and parasitic capacitance, the primary current Ip and the secondary current Is exhibit obvious oscillations, but ultimately the drive voltage VOUT waveform can be output normally, realizing the correct gate drive function. This scheme reduces transmission delay and also reduces interference from components.

[0058] Unlike traditional magnetically isolated gate drive circuits, the magnetically isolated gate drive circuit in the above embodiments is combined with the power module, cleverly utilizing the power module housing to achieve magnetic coupling of the PWM control signal. This significantly reduces the area of ​​the bare power module board and increases the power module's power density. By mounting the coreless transformer on the package housing, fewer components are added to the PCB motherboard, achieving equivalent isolation. This makes it suitable for high-power-density power module scenarios, offering low transmission latency and absolute insulation. Furthermore, the physical distance between the PCB and the transformer reduces conducted interference from components to the transformer.

[0059] For those skilled in the art, various modifications and improvements can be made without departing from the concept of this application, and these all fall within the scope of protection of this application. Therefore, the scope of protection of this application shall be determined by the appended claims.

Claims

1. An isolated gate drive circuit using a package lid parasitic element, characterized by, The circuit is combined with a power module, and comprises a coreless transformer, a DSP control chip, a transmitter, a primary capacitor, a secondary capacitor, a receiver and a gate drive controller; the coreless transformer is arranged on a power module shell, and the DSP control chip and the gate drive controller are located on an encapsulation cover plate; the coreless transformer is connected with the primary capacitor and the secondary capacitor respectively, the DSP control chip is connected with the primary capacitor through the transmitter, and the gate drive controller is connected with the secondary capacitor through the receiver. The DSP control chip sends a PWM control signal, modulates the PWM control signal through the transmitter and the primary capacitor, couples the modulated PWM control signal through the coreless transformer, transmits the coupled PWM control signal to the gate drive controller through the receiver and the secondary capacitor, and demodulates the PWM control signal to generate a driving signal of the power module. The coreless transformer comprises a square metal coil, and a primary winding and a secondary winding in the metal coil are located on the same layer to avoid introducing a planar stray capacitor of the primary and secondary windings due to not being on the same layer. The contact pad is arranged at the tap of the metal coil, low resistance coil is used to increase current, and the inductance value of the square coil is obtained according to the size of the square metal coil and the winding resistance : ； ； wherein, is the vacuum permeability, and is the primary and secondary inductance coefficient of square metal coil, is the turns ratio of transformer coil, is the ratio of the difference and the sum of the width of metal coil, is the average of the width of primary and secondary metal coil; the width of inner ring of square coil is , and the width of outer ring is . The upper limit of the coil self-resonant frequency fsr at the power module package shell is determined by the parasitic capacitance and the inductance of the coil, and the coupling coefficient k is determined by the open-circuit inductance of the secondary side and the short-circuit inductance of the secondary side determination: ； A winding capacitor is determined by a self-resonant frequency of the transformer, and the influence of the winding capacitor is suppressed by shortening insulation between the primary coil and the secondary coil.

2. The circuit of claim 1, wherein, The encapsulation cover plate comprises a PCB plate, and the DSP control chip and the gate drive controller are arranged on a first side and a second side of the PCB plate respectively.

3. The circuit of claim 2, wherein, The PCB plate is connected with a signal ground, and the power module shell is connected with a ground.

4. The circuit of claim 3, wherein, The primary capacitor and the secondary capacitor each comprise a stray capacitor between a PCB plate and a power module shell and a stray capacitor of the coreless transformer.

5. The circuit of claim 4, wherein, An input end of the transmitter is connected with an output end of the DSP control chip, an output end of the transmitter is connected with the primary capacitor, an input end of the receiver is connected with the secondary capacitor, and an input end of the gate drive controller is connected with an output end of the receiver; when the PWM control signal is switched from a low level to a high level, the transmitter and the primary capacitor encode a rising edge as a positive narrow pulse; when the PWM control signal is switched from the high level to the low level, the transmitter and the primary capacitor encode a falling edge as a negative narrow pulse; the pulse signal modulated by the transmitter and the primary capacitor is coupled to the secondary through the coreless transformer, and the receiver and the secondary capacitor restore the positive narrow pulse to a rising edge and restore the negative narrow pulse to a falling edge according to the received pulse polarity.

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